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Ben Dooksb6d64542007-02-20 13:58:01 -08001/* sm501-regs.h
2 *
3 * Copyright 2006 Simtec Electronics
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Silicon Motion SM501 register definitions
10*/
11
12/* System Configuration area */
13/* System config base */
14#define SM501_SYS_CONFIG (0x000000)
15
16/* config 1 */
17#define SM501_SYSTEM_CONTROL (0x000000)
18#define SM501_MISC_CONTROL (0x000004)
19
20#define SM501_MISC_BUS_SH (0x0)
21#define SM501_MISC_BUS_PCI (0x1)
22#define SM501_MISC_BUS_XSCALE (0x2)
23#define SM501_MISC_BUS_NEC (0x6)
24#define SM501_MISC_BUS_MASK (0x7)
25
26#define SM501_MISC_VR_62MB (1<<3)
27#define SM501_MISC_CDR_RESET (1<<7)
28#define SM501_MISC_USB_LB (1<<8)
29#define SM501_MISC_USB_SLAVE (1<<9)
30#define SM501_MISC_BL_1 (1<<10)
31#define SM501_MISC_MC (1<<11)
32#define SM501_MISC_DAC_POWER (1<<12)
33#define SM501_MISC_IRQ_INVERT (1<<16)
34#define SM501_MISC_SH (1<<17)
35
36#define SM501_MISC_HOLD_EMPTY (0<<18)
37#define SM501_MISC_HOLD_8 (1<<18)
38#define SM501_MISC_HOLD_16 (2<<18)
39#define SM501_MISC_HOLD_24 (3<<18)
40#define SM501_MISC_HOLD_32 (4<<18)
41#define SM501_MISC_HOLD_MASK (7<<18)
42
43#define SM501_MISC_FREQ_12 (1<<24)
44#define SM501_MISC_PNL_24BIT (1<<25)
45#define SM501_MISC_8051_LE (1<<26)
46
47
48
49#define SM501_GPIO31_0_CONTROL (0x000008)
50#define SM501_GPIO63_32_CONTROL (0x00000C)
51#define SM501_DRAM_CONTROL (0x000010)
52
53/* command list */
54#define SM501_ARBTRTN_CONTROL (0x000014)
55
56/* command list */
57#define SM501_COMMAND_LIST_STATUS (0x000024)
58
59/* interrupt debug */
60#define SM501_RAW_IRQ_STATUS (0x000028)
61#define SM501_RAW_IRQ_CLEAR (0x000028)
62#define SM501_IRQ_STATUS (0x00002C)
63#define SM501_IRQ_MASK (0x000030)
64#define SM501_DEBUG_CONTROL (0x000034)
65
66/* power management */
Ben Dooks81906222007-06-23 17:16:30 -070067#define SM501_POWERMODE_P2X_SRC (1<<29)
68#define SM501_POWERMODE_V2X_SRC (1<<20)
69#define SM501_POWERMODE_M_SRC (1<<12)
70#define SM501_POWERMODE_M1_SRC (1<<4)
71
Ben Dooksb6d64542007-02-20 13:58:01 -080072#define SM501_CURRENT_GATE (0x000038)
73#define SM501_CURRENT_CLOCK (0x00003C)
74#define SM501_POWER_MODE_0_GATE (0x000040)
75#define SM501_POWER_MODE_0_CLOCK (0x000044)
76#define SM501_POWER_MODE_1_GATE (0x000048)
77#define SM501_POWER_MODE_1_CLOCK (0x00004C)
78#define SM501_SLEEP_MODE_GATE (0x000050)
79#define SM501_POWER_MODE_CONTROL (0x000054)
80
81/* power gates for units within the 501 */
82#define SM501_GATE_HOST (0)
83#define SM501_GATE_MEMORY (1)
84#define SM501_GATE_DISPLAY (2)
85#define SM501_GATE_2D_ENGINE (3)
86#define SM501_GATE_CSC (4)
87#define SM501_GATE_ZVPORT (5)
88#define SM501_GATE_GPIO (6)
89#define SM501_GATE_UART0 (7)
90#define SM501_GATE_UART1 (8)
91#define SM501_GATE_SSP (10)
92#define SM501_GATE_USB_HOST (11)
93#define SM501_GATE_USB_GADGET (12)
94#define SM501_GATE_UCONTROLLER (17)
95#define SM501_GATE_AC97 (18)
96
97/* panel clock */
98#define SM501_CLOCK_P2XCLK (24)
99/* crt clock */
100#define SM501_CLOCK_V2XCLK (16)
101/* main clock */
102#define SM501_CLOCK_MCLK (8)
103/* SDRAM controller clock */
104#define SM501_CLOCK_M1XCLK (0)
105
106/* config 2 */
107#define SM501_PCI_MASTER_BASE (0x000058)
108#define SM501_ENDIAN_CONTROL (0x00005C)
109#define SM501_DEVICEID (0x000060)
110/* 0x050100A0 */
111
Ben Dooks1e27dbe2007-06-23 17:16:31 -0700112#define SM501_DEVICEID_SM501 (0x05010000)
113#define SM501_DEVICEID_IDMASK (0xffff0000)
114
Ben Dooksb6d64542007-02-20 13:58:01 -0800115#define SM501_PLLCLOCK_COUNT (0x000064)
116#define SM501_MISC_TIMING (0x000068)
117#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
118
119/* GPIO base */
120#define SM501_GPIO (0x010000)
121#define SM501_GPIO_DATA_LOW (0x00)
122#define SM501_GPIO_DATA_HIGH (0x04)
123#define SM501_GPIO_DDR_LOW (0x08)
124#define SM501_GPIO_DDR_HIGH (0x0C)
125#define SM501_GPIO_IRQ_SETUP (0x10)
126#define SM501_GPIO_IRQ_STATUS (0x14)
127#define SM501_GPIO_IRQ_RESET (0x14)
128
129/* I2C controller base */
130#define SM501_I2C (0x010040)
131#define SM501_I2C_BYTE_COUNT (0x00)
132#define SM501_I2C_CONTROL (0x01)
133#define SM501_I2C_STATUS (0x02)
134#define SM501_I2C_RESET (0x02)
135#define SM501_I2C_SLAVE_ADDRESS (0x03)
136#define SM501_I2C_DATA (0x04)
137
138/* SSP base */
139#define SM501_SSP (0x020000)
140
141/* Uart 0 base */
142#define SM501_UART0 (0x030000)
143
144/* Uart 1 base */
145#define SM501_UART1 (0x030020)
146
147/* USB host port base */
148#define SM501_USB_HOST (0x040000)
149
150/* USB slave/gadget base */
151#define SM501_USB_GADGET (0x060000)
152
153/* USB slave/gadget data port base */
154#define SM501_USB_GADGET_DATA (0x070000)
155
156/* Display contoller/video engine base */
157#define SM501_DC (0x080000)
158
159/* common defines for the SM501 address registers */
160#define SM501_ADDR_FLIP (1<<31)
161#define SM501_ADDR_EXT (1<<27)
162#define SM501_ADDR_CS1 (1<<26)
163#define SM501_ADDR_MASK (0x3f << 26)
164
165#define SM501_FIFO_MASK (0x3 << 16)
166#define SM501_FIFO_1 (0x0 << 16)
167#define SM501_FIFO_3 (0x1 << 16)
168#define SM501_FIFO_7 (0x2 << 16)
169#define SM501_FIFO_11 (0x3 << 16)
170
171/* common registers for panel and the crt */
172#define SM501_OFF_DC_H_TOT (0x000)
173#define SM501_OFF_DC_V_TOT (0x008)
174#define SM501_OFF_DC_H_SYNC (0x004)
175#define SM501_OFF_DC_V_SYNC (0x00C)
176
177#define SM501_DC_PANEL_CONTROL (0x000)
178
179#define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
180#define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
181#define SM501_DC_PANEL_CONTROL_DATA (1<<25)
182#define SM501_DC_PANEL_CONTROL_VDD (1<<24)
183#define SM501_DC_PANEL_CONTROL_DP (1<<23)
184
185#define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
186#define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
187#define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
188
189#define SM501_DC_PANEL_CONTROL_DE (1<<20)
190
191#define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
192#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
193#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
194
195#define SM501_DC_PANEL_CONTROL_CP (1<<14)
196#define SM501_DC_PANEL_CONTROL_VSP (1<<13)
197#define SM501_DC_PANEL_CONTROL_HSP (1<<12)
198#define SM501_DC_PANEL_CONTROL_CK (1<<9)
199#define SM501_DC_PANEL_CONTROL_TE (1<<8)
200#define SM501_DC_PANEL_CONTROL_VPD (1<<7)
201#define SM501_DC_PANEL_CONTROL_VP (1<<6)
202#define SM501_DC_PANEL_CONTROL_HPD (1<<5)
203#define SM501_DC_PANEL_CONTROL_HP (1<<4)
204#define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
205#define SM501_DC_PANEL_CONTROL_EN (1<<2)
206
207#define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
208#define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
209#define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
210
211
212#define SM501_DC_PANEL_PANNING_CONTROL (0x004)
213#define SM501_DC_PANEL_COLOR_KEY (0x008)
214#define SM501_DC_PANEL_FB_ADDR (0x00C)
215#define SM501_DC_PANEL_FB_OFFSET (0x010)
216#define SM501_DC_PANEL_FB_WIDTH (0x014)
217#define SM501_DC_PANEL_FB_HEIGHT (0x018)
218#define SM501_DC_PANEL_TL_LOC (0x01C)
219#define SM501_DC_PANEL_BR_LOC (0x020)
220#define SM501_DC_PANEL_H_TOT (0x024)
221#define SM501_DC_PANEL_H_SYNC (0x028)
222#define SM501_DC_PANEL_V_TOT (0x02C)
223#define SM501_DC_PANEL_V_SYNC (0x030)
224#define SM501_DC_PANEL_CUR_LINE (0x034)
225
226#define SM501_DC_VIDEO_CONTROL (0x040)
227#define SM501_DC_VIDEO_FB0_ADDR (0x044)
228#define SM501_DC_VIDEO_FB_WIDTH (0x048)
229#define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
230#define SM501_DC_VIDEO_TL_LOC (0x050)
231#define SM501_DC_VIDEO_BR_LOC (0x054)
232#define SM501_DC_VIDEO_SCALE (0x058)
233#define SM501_DC_VIDEO_INIT_SCALE (0x05C)
234#define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
235#define SM501_DC_VIDEO_FB1_ADDR (0x064)
236#define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
237
238#define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
239#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
240#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
241#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
242#define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
243#define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
244#define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
245#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
246#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
247#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
248
249#define SM501_DC_PANEL_HWC_BASE (0x0F0)
250#define SM501_DC_PANEL_HWC_ADDR (0x0F0)
251#define SM501_DC_PANEL_HWC_LOC (0x0F4)
252#define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
253#define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
254
255#define SM501_HWC_EN (1<<31)
256
257#define SM501_OFF_HWC_ADDR (0x00)
258#define SM501_OFF_HWC_LOC (0x04)
259#define SM501_OFF_HWC_COLOR_1_2 (0x08)
260#define SM501_OFF_HWC_COLOR_3 (0x0C)
261
262#define SM501_DC_ALPHA_CONTROL (0x100)
263#define SM501_DC_ALPHA_FB_ADDR (0x104)
264#define SM501_DC_ALPHA_FB_OFFSET (0x108)
265#define SM501_DC_ALPHA_TL_LOC (0x10C)
266#define SM501_DC_ALPHA_BR_LOC (0x110)
267#define SM501_DC_ALPHA_CHROMA_KEY (0x114)
268#define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
269
270#define SM501_DC_CRT_CONTROL (0x200)
271
272#define SM501_DC_CRT_CONTROL_TVP (1<<15)
273#define SM501_DC_CRT_CONTROL_CP (1<<14)
274#define SM501_DC_CRT_CONTROL_VSP (1<<13)
275#define SM501_DC_CRT_CONTROL_HSP (1<<12)
276#define SM501_DC_CRT_CONTROL_VS (1<<11)
277#define SM501_DC_CRT_CONTROL_BLANK (1<<10)
278#define SM501_DC_CRT_CONTROL_SEL (1<<9)
279#define SM501_DC_CRT_CONTROL_TE (1<<8)
280#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
281#define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
282#define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
283
284#define SM501_DC_CRT_CONTROL_8BPP (0<<0)
285#define SM501_DC_CRT_CONTROL_16BPP (1<<0)
286#define SM501_DC_CRT_CONTROL_32BPP (2<<0)
287
288#define SM501_DC_CRT_FB_ADDR (0x204)
289#define SM501_DC_CRT_FB_OFFSET (0x208)
290#define SM501_DC_CRT_H_TOT (0x20C)
291#define SM501_DC_CRT_H_SYNC (0x210)
292#define SM501_DC_CRT_V_TOT (0x214)
293#define SM501_DC_CRT_V_SYNC (0x218)
294#define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
295#define SM501_DC_CRT_CUR_LINE (0x220)
296#define SM501_DC_CRT_MONITOR_DETECT (0x224)
297
298#define SM501_DC_CRT_HWC_BASE (0x230)
299#define SM501_DC_CRT_HWC_ADDR (0x230)
300#define SM501_DC_CRT_HWC_LOC (0x234)
301#define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
302#define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
303
304#define SM501_DC_PANEL_PALETTE (0x400)
305
306#define SM501_DC_VIDEO_PALETTE (0x800)
307
308#define SM501_DC_CRT_PALETTE (0xC00)
309
310/* Zoom Video port base */
311#define SM501_ZVPORT (0x090000)
312
313/* AC97/I2S base */
314#define SM501_AC97 (0x0A0000)
315
316/* 8051 micro controller base */
317#define SM501_UCONTROLLER (0x0B0000)
318
319/* 8051 micro controller SRAM base */
320#define SM501_UCONTROLLER_SRAM (0x0C0000)
321
322/* DMA base */
323#define SM501_DMA (0x0D0000)
324
325/* 2d engine base */
326#define SM501_2D_ENGINE (0x100000)
327#define SM501_2D_SOURCE (0x00)
328#define SM501_2D_DESTINATION (0x04)
329#define SM501_2D_DIMENSION (0x08)
330#define SM501_2D_CONTROL (0x0C)
331#define SM501_2D_PITCH (0x10)
332#define SM501_2D_FOREGROUND (0x14)
333#define SM501_2D_BACKGROUND (0x18)
334#define SM501_2D_STRETCH (0x1C)
335#define SM501_2D_COLOR_COMPARE (0x20)
336#define SM501_2D_COLOR_COMPARE_MASK (0x24)
337#define SM501_2D_MASK (0x28)
338#define SM501_2D_CLIP_TL (0x2C)
339#define SM501_2D_CLIP_BR (0x30)
340#define SM501_2D_MONO_PATTERN_LOW (0x34)
341#define SM501_2D_MONO_PATTERN_HIGH (0x38)
342#define SM501_2D_WINDOW_WIDTH (0x3C)
343#define SM501_2D_SOURCE_BASE (0x40)
344#define SM501_2D_DESTINATION_BASE (0x44)
345#define SM501_2D_ALPHA (0x48)
346#define SM501_2D_WRAP (0x4C)
347#define SM501_2D_STATUS (0x50)
348
349#define SM501_CSC_Y_SOURCE_BASE (0xC8)
350#define SM501_CSC_CONSTANTS (0xCC)
351#define SM501_CSC_Y_SOURCE_X (0xD0)
352#define SM501_CSC_Y_SOURCE_Y (0xD4)
353#define SM501_CSC_U_SOURCE_BASE (0xD8)
354#define SM501_CSC_V_SOURCE_BASE (0xDC)
355#define SM501_CSC_SOURCE_DIMENSION (0xE0)
356#define SM501_CSC_SOURCE_PITCH (0xE4)
357#define SM501_CSC_DESTINATION (0xE8)
358#define SM501_CSC_DESTINATION_DIMENSION (0xEC)
359#define SM501_CSC_DESTINATION_PITCH (0xF0)
360#define SM501_CSC_SCALE_FACTOR (0xF4)
361#define SM501_CSC_DESTINATION_BASE (0xF8)
362#define SM501_CSC_CONTROL (0xFC)
363
364/* 2d engine data port base */
365#define SM501_2D_ENGINE_DATA (0x110000)