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gerrit-public.fairphone.software / kernel / msm-4.9 / 75850d0bcece42416ba81bd38e4c719f101c832d / . / include / linux / mlx5 / mlx5_ifc.h
blob: 4633b88b0c3b615d4d9936ae4c06fbf21dff456c [file] [log] [blame]
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]1/*
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]31*/
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
35enum {
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
69enum {
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
74enum {
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]169 MLX5_CMD_OP_CREATE_TIR = 0x900,
170 MLX5_CMD_OP_MODIFY_TIR = 0x901,
171 MLX5_CMD_OP_DESTROY_TIR = 0x902,
172 MLX5_CMD_OP_QUERY_TIR = 0x903,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]173 MLX5_CMD_OP_CREATE_SQ = 0x904,
174 MLX5_CMD_OP_MODIFY_SQ = 0x905,
175 MLX5_CMD_OP_DESTROY_SQ = 0x906,
176 MLX5_CMD_OP_QUERY_SQ = 0x907,
177 MLX5_CMD_OP_CREATE_RQ = 0x908,
178 MLX5_CMD_OP_MODIFY_RQ = 0x909,
179 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
180 MLX5_CMD_OP_QUERY_RQ = 0x90b,
181 MLX5_CMD_OP_CREATE_RMP = 0x90c,
182 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
183 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
184 MLX5_CMD_OP_QUERY_RMP = 0x90f,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]185 MLX5_CMD_OP_CREATE_TIS = 0x912,
186 MLX5_CMD_OP_MODIFY_TIS = 0x913,
187 MLX5_CMD_OP_DESTROY_TIS = 0x914,
188 MLX5_CMD_OP_QUERY_TIS = 0x915,
189 MLX5_CMD_OP_CREATE_RQT = 0x916,
190 MLX5_CMD_OP_MODIFY_RQT = 0x917,
191 MLX5_CMD_OP_DESTROY_RQT = 0x918,
192 MLX5_CMD_OP_QUERY_RQT = 0x919,
193 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
194 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
196 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
197 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
198 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
199 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
200 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
201 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
202};
203
204struct mlx5_ifc_flow_table_fields_supported_bits {
205 u8 outer_dmac[0x1];
206 u8 outer_smac[0x1];
207 u8 outer_ether_type[0x1];
208 u8 reserved_0[0x1];
209 u8 outer_first_prio[0x1];
210 u8 outer_first_cfi[0x1];
211 u8 outer_first_vid[0x1];
212 u8 reserved_1[0x1];
213 u8 outer_second_prio[0x1];
214 u8 outer_second_cfi[0x1];
215 u8 outer_second_vid[0x1];
216 u8 reserved_2[0x1];
217 u8 outer_sip[0x1];
218 u8 outer_dip[0x1];
219 u8 outer_frag[0x1];
220 u8 outer_ip_protocol[0x1];
221 u8 outer_ip_ecn[0x1];
222 u8 outer_ip_dscp[0x1];
223 u8 outer_udp_sport[0x1];
224 u8 outer_udp_dport[0x1];
225 u8 outer_tcp_sport[0x1];
226 u8 outer_tcp_dport[0x1];
227 u8 outer_tcp_flags[0x1];
228 u8 outer_gre_protocol[0x1];
229 u8 outer_gre_key[0x1];
230 u8 outer_vxlan_vni[0x1];
231 u8 reserved_3[0x5];
232 u8 source_eswitch_port[0x1];
233
234 u8 inner_dmac[0x1];
235 u8 inner_smac[0x1];
236 u8 inner_ether_type[0x1];
237 u8 reserved_4[0x1];
238 u8 inner_first_prio[0x1];
239 u8 inner_first_cfi[0x1];
240 u8 inner_first_vid[0x1];
241 u8 reserved_5[0x1];
242 u8 inner_second_prio[0x1];
243 u8 inner_second_cfi[0x1];
244 u8 inner_second_vid[0x1];
245 u8 reserved_6[0x1];
246 u8 inner_sip[0x1];
247 u8 inner_dip[0x1];
248 u8 inner_frag[0x1];
249 u8 inner_ip_protocol[0x1];
250 u8 inner_ip_ecn[0x1];
251 u8 inner_ip_dscp[0x1];
252 u8 inner_udp_sport[0x1];
253 u8 inner_udp_dport[0x1];
254 u8 inner_tcp_sport[0x1];
255 u8 inner_tcp_dport[0x1];
256 u8 inner_tcp_flags[0x1];
257 u8 reserved_7[0x9];
258
259 u8 reserved_8[0x40];
260};
261
262struct mlx5_ifc_flow_table_prop_layout_bits {
263 u8 ft_support[0x1];
264 u8 reserved_0[0x1f];
265
266 u8 reserved_1[0x2];
267 u8 log_max_ft_size[0x6];
268 u8 reserved_2[0x10];
269 u8 max_ft_level[0x8];
270
271 u8 reserved_3[0x20];
272
273 u8 reserved_4[0x18];
274 u8 log_max_ft_num[0x8];
275
276 u8 reserved_5[0x18];
277 u8 log_max_destination[0x8];
278
279 u8 reserved_6[0x18];
280 u8 log_max_flow[0x8];
281
282 u8 reserved_7[0x40];
283
284 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
285
286 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
287};
288
289struct mlx5_ifc_odp_per_transport_service_cap_bits {
290 u8 send[0x1];
291 u8 receive[0x1];
292 u8 write[0x1];
293 u8 read[0x1];
294 u8 reserved_0[0x1];
295 u8 srq_receive[0x1];
296 u8 reserved_1[0x1a];
297};
298
299struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
300 u8 smac_47_16[0x20];
301
302 u8 smac_15_0[0x10];
303 u8 ethertype[0x10];
304
305 u8 dmac_47_16[0x20];
306
307 u8 dmac_15_0[0x10];
308 u8 first_prio[0x3];
309 u8 first_cfi[0x1];
310 u8 first_vid[0xc];
311
312 u8 ip_protocol[0x8];
313 u8 ip_dscp[0x6];
314 u8 ip_ecn[0x2];
315 u8 vlan_tag[0x1];
316 u8 reserved_0[0x1];
317 u8 frag[0x1];
318 u8 reserved_1[0x4];
319 u8 tcp_flags[0x9];
320
321 u8 tcp_sport[0x10];
322 u8 tcp_dport[0x10];
323
324 u8 reserved_2[0x20];
325
326 u8 udp_sport[0x10];
327 u8 udp_dport[0x10];
328
329 u8 src_ip[4][0x20];
330
331 u8 dst_ip[4][0x20];
332};
333
334struct mlx5_ifc_fte_match_set_misc_bits {
335 u8 reserved_0[0x20];
336
337 u8 reserved_1[0x10];
338 u8 source_port[0x10];
339
340 u8 outer_second_prio[0x3];
341 u8 outer_second_cfi[0x1];
342 u8 outer_second_vid[0xc];
343 u8 inner_second_prio[0x3];
344 u8 inner_second_cfi[0x1];
345 u8 inner_second_vid[0xc];
346
347 u8 outer_second_vlan_tag[0x1];
348 u8 inner_second_vlan_tag[0x1];
349 u8 reserved_2[0xe];
350 u8 gre_protocol[0x10];
351
352 u8 gre_key_h[0x18];
353 u8 gre_key_l[0x8];
354
355 u8 vxlan_vni[0x18];
356 u8 reserved_3[0x8];
357
358 u8 reserved_4[0x20];
359
360 u8 reserved_5[0xc];
361 u8 outer_ipv6_flow_label[0x14];
362
363 u8 reserved_6[0xc];
364 u8 inner_ipv6_flow_label[0x14];
365
366 u8 reserved_7[0xe0];
367};
368
369struct mlx5_ifc_cmd_pas_bits {
370 u8 pa_h[0x20];
371
372 u8 pa_l[0x14];
373 u8 reserved_0[0xc];
374};
375
376struct mlx5_ifc_uint64_bits {
377 u8 hi[0x20];
378
379 u8 lo[0x20];
380};
381
382enum {
383 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
384 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
385 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
386 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
387 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
388 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
389 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
390 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
391 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
392 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
393};
394
395struct mlx5_ifc_ads_bits {
396 u8 fl[0x1];
397 u8 free_ar[0x1];
398 u8 reserved_0[0xe];
399 u8 pkey_index[0x10];
400
401 u8 reserved_1[0x8];
402 u8 grh[0x1];
403 u8 mlid[0x7];
404 u8 rlid[0x10];
405
406 u8 ack_timeout[0x5];
407 u8 reserved_2[0x3];
408 u8 src_addr_index[0x8];
409 u8 reserved_3[0x4];
410 u8 stat_rate[0x4];
411 u8 hop_limit[0x8];
412
413 u8 reserved_4[0x4];
414 u8 tclass[0x8];
415 u8 flow_label[0x14];
416
417 u8 rgid_rip[16][0x8];
418
419 u8 reserved_5[0x4];
420 u8 f_dscp[0x1];
421 u8 f_ecn[0x1];
422 u8 reserved_6[0x1];
423 u8 f_eth_prio[0x1];
424 u8 ecn[0x2];
425 u8 dscp[0x6];
426 u8 udp_sport[0x10];
427
428 u8 dei_cfi[0x1];
429 u8 eth_prio[0x3];
430 u8 sl[0x4];
431 u8 port[0x8];
432 u8 rmac_47_32[0x10];
433
434 u8 rmac_31_0[0x20];
435};
436
437struct mlx5_ifc_flow_table_nic_cap_bits {
438 u8 reserved_0[0x200];
439
440 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
441
442 u8 reserved_1[0x200];
443
444 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
445
446 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
447
448 u8 reserved_2[0x200];
449
450 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
451
452 u8 reserved_3[0x7200];
453};
454
455struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
456 u8 csum_cap[0x1];
457 u8 vlan_cap[0x1];
458 u8 lro_cap[0x1];
459 u8 lro_psh_flag[0x1];
460 u8 lro_time_stamp[0x1];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]461 u8 reserved_0[0x3];
462 u8 self_lb_en_modifiable[0x1];
463 u8 reserved_1[0x2];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]464 u8 max_lso_cap[0x5];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]465 u8 reserved_2[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]466 u8 rss_ind_tbl_cap[0x4];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]467 u8 reserved_3[0x3];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]468 u8 tunnel_lso_const_out_ip_id[0x1];
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]469 u8 reserved_4[0x2];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]470 u8 tunnel_statless_gre[0x1];
471 u8 tunnel_stateless_vxlan[0x1];
472
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]473 u8 reserved_5[0x20];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]474
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]475 u8 reserved_6[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]476 u8 lro_min_mss_size[0x10];
477
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]478 u8 reserved_7[0x120];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]479
480 u8 lro_timer_supported_periods[4][0x20];
481
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]482 u8 reserved_8[0x600];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]483};
484
485struct mlx5_ifc_roce_cap_bits {
486 u8 roce_apm[0x1];
487 u8 reserved_0[0x1f];
488
489 u8 reserved_1[0x60];
490
491 u8 reserved_2[0xc];
492 u8 l3_type[0x4];
493 u8 reserved_3[0x8];
494 u8 roce_version[0x8];
495
496 u8 reserved_4[0x10];
497 u8 r_roce_dest_udp_port[0x10];
498
499 u8 r_roce_max_src_udp_port[0x10];
500 u8 r_roce_min_src_udp_port[0x10];
501
502 u8 reserved_5[0x10];
503 u8 roce_address_table_size[0x10];
504
505 u8 reserved_6[0x700];
506};
507
508enum {
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
513 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
514 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
515 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
518};
519
520enum {
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
525 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
526 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
527 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
528 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
529 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
530};
531
532struct mlx5_ifc_atomic_caps_bits {
533 u8 reserved_0[0x40];
534
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]535 u8 atomic_req_8B_endianess_mode[0x2];
536 u8 reserved_1[0x4];
537 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]538
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]539 u8 reserved_2[0x19];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]540
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]541 u8 reserved_3[0x20];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]542
543 u8 reserved_4[0x10];
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]544 u8 atomic_operations[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]545
546 u8 reserved_5[0x10];
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]547 u8 atomic_size_qp[0x10];
548
549 u8 reserved_6[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]550 u8 atomic_size_dc[0x10];
551
Eran Ben Elishaf91e6d82015-12-14 16:34:09 +0200[diff] [blame]552 u8 reserved_7[0x720];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]553};
554
555struct mlx5_ifc_odp_cap_bits {
556 u8 reserved_0[0x40];
557
558 u8 sig[0x1];
559 u8 reserved_1[0x1f];
560
561 u8 reserved_2[0x20];
562
563 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
564
565 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
566
567 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
568
569 u8 reserved_3[0x720];
570};
571
572enum {
573 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
574 MLX5_WQ_TYPE_CYCLIC = 0x1,
575 MLX5_WQ_TYPE_STRQ = 0x2,
576};
577
578enum {
579 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
580 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
581};
582
583enum {
584 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
585 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
586 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
587 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
588 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
589};
590
591enum {
592 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
593 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
594 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
595 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
596 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
597 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
598};
599
600enum {
601 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
602 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
603};
604
605enum {
606 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
607 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
608 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
609};
610
611enum {
612 MLX5_CAP_PORT_TYPE_IB = 0x0,
613 MLX5_CAP_PORT_TYPE_ETH = 0x1,
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]614};
615
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]616struct mlx5_ifc_cmd_hca_cap_bits {
617 u8 reserved_0[0x80];
618
619 u8 log_max_srq_sz[0x8];
620 u8 log_max_qp_sz[0x8];
621 u8 reserved_1[0xb];
622 u8 log_max_qp[0x5];
623
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]624 u8 reserved_2[0xb];
625 u8 log_max_srq[0x5];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]626 u8 reserved_3[0x10];
627
628 u8 reserved_4[0x8];
629 u8 log_max_cq_sz[0x8];
630 u8 reserved_5[0xb];
631 u8 log_max_cq[0x5];
632
633 u8 log_max_eq_sz[0x8];
634 u8 reserved_6[0x2];
635 u8 log_max_mkey[0x6];
636 u8 reserved_7[0xc];
637 u8 log_max_eq[0x4];
638
639 u8 max_indirection[0x8];
640 u8 reserved_8[0x1];
641 u8 log_max_mrw_sz[0x7];
642 u8 reserved_9[0x2];
643 u8 log_max_bsf_list_size[0x6];
644 u8 reserved_10[0x2];
645 u8 log_max_klm_list_size[0x6];
646
647 u8 reserved_11[0xa];
648 u8 log_max_ra_req_dc[0x6];
649 u8 reserved_12[0xa];
650 u8 log_max_ra_res_dc[0x6];
651
652 u8 reserved_13[0xa];
653 u8 log_max_ra_req_qp[0x6];
654 u8 reserved_14[0xa];
655 u8 log_max_ra_res_qp[0x6];
656
657 u8 pad_cap[0x1];
658 u8 cc_query_allowed[0x1];
659 u8 cc_modify_allowed[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]660 u8 reserved_15[0xd];
661 u8 gid_table_size[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]662
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]663 u8 out_of_seq_cnt[0x1];
664 u8 vport_counters[0x1];
665 u8 reserved_16[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]666 u8 max_qp_cnt[0xa];
667 u8 pkey_table_size[0x10];
668
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]669 u8 vport_group_manager[0x1];
670 u8 vhca_group_manager[0x1];
671 u8 ib_virt[0x1];
672 u8 eth_virt[0x1];
673 u8 reserved_17[0x1];
674 u8 ets[0x1];
675 u8 nic_flow_table[0x1];
676 u8 reserved_18[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]677 u8 local_ca_ack_delay[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]678 u8 reserved_19[0x6];
679 u8 port_type[0x2];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]680 u8 num_ports[0x8];
681
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]682 u8 reserved_20[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]683 u8 log_max_msg[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]684 u8 reserved_21[0x18];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]685
686 u8 stat_rate_support[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]687 u8 reserved_22[0xc];
688 u8 cqe_version[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]689
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]690 u8 compact_address_vector[0x1];
691 u8 reserved_23[0xe];
692 u8 drain_sigerr[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]693 u8 cmdif_checksum[0x2];
694 u8 sigerr_cqe[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]695 u8 reserved_24[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]696 u8 wq_signature[0x1];
697 u8 sctr_data_cqe[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]698 u8 reserved_25[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]699 u8 sho[0x1];
700 u8 tph[0x1];
701 u8 rf[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]702 u8 dct[0x1];
703 u8 reserved_26[0x1];
704 u8 eth_net_offloads[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]705 u8 roce[0x1];
706 u8 atomic[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]707 u8 reserved_27[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]708
709 u8 cq_oi[0x1];
710 u8 cq_resize[0x1];
711 u8 cq_moderation[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]712 u8 reserved_28[0x3];
713 u8 cq_eq_remap[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]714 u8 pg[0x1];
715 u8 block_lb_mc[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]716 u8 reserved_29[0x1];
717 u8 scqe_break_moderation[0x1];
718 u8 reserved_30[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]719 u8 cd[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]720 u8 reserved_31[0x1];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]721 u8 apm[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]722 u8 reserved_32[0x7];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]723 u8 qkv[0x1];
724 u8 pkv[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]725 u8 reserved_33[0x4];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]726 u8 xrc[0x1];
727 u8 ud[0x1];
728 u8 uc[0x1];
729 u8 rc[0x1];
730
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]731 u8 reserved_34[0xa];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]732 u8 uar_sz[0x6];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]733 u8 reserved_35[0x8];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]734 u8 log_pg_sz[0x8];
735
736 u8 bf[0x1];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]737 u8 reserved_36[0x1];
738 u8 pad_tx_eth_packet[0x1];
739 u8 reserved_37[0x8];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]740 u8 log_bf_reg_size[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]741 u8 reserved_38[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]742
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]743 u8 reserved_39[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]744 u8 max_wqe_sz_sq[0x10];
745
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]746 u8 reserved_40[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]747 u8 max_wqe_sz_rq[0x10];
748
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]749 u8 reserved_41[0x10];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]750 u8 max_wqe_sz_sq_dc[0x10];
751
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]752 u8 reserved_42[0x7];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]753 u8 max_qp_mcg[0x19];
754
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]755 u8 reserved_43[0x18];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]756 u8 log_max_mcg[0x8];
757
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]758 u8 reserved_44[0x3];
759 u8 log_max_transport_domain[0x5];
760 u8 reserved_45[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]761 u8 log_max_pd[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]762 u8 reserved_46[0xb];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]763 u8 log_max_xrcd[0x5];
764
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]765 u8 reserved_47[0x20];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]766
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]767 u8 reserved_48[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]768 u8 log_max_rq[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]769 u8 reserved_49[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]770 u8 log_max_sq[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]771 u8 reserved_50[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]772 u8 log_max_tir[0x5];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]773 u8 reserved_51[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]774 u8 log_max_tis[0x5];
775
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]776 u8 basic_cyclic_rcv_wqe[0x1];
777 u8 reserved_52[0x2];
778 u8 log_max_rmp[0x5];
779 u8 reserved_53[0x3];
780 u8 log_max_rqt[0x5];
781 u8 reserved_54[0x3];
782 u8 log_max_rqt_size[0x5];
783 u8 reserved_55[0x3];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]784 u8 log_max_tis_per_sq[0x5];
785
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]786 u8 reserved_56[0x3];
787 u8 log_max_stride_sz_rq[0x5];
788 u8 reserved_57[0x3];
789 u8 log_min_stride_sz_rq[0x5];
790 u8 reserved_58[0x3];
791 u8 log_max_stride_sz_sq[0x5];
792 u8 reserved_59[0x3];
793 u8 log_min_stride_sz_sq[0x5];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]794
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]795 u8 reserved_60[0x1b];
796 u8 log_max_wq_sz[0x5];
797
798 u8 reserved_61[0xa0];
799
800 u8 reserved_62[0x3];
801 u8 log_max_l2_table[0x5];
802 u8 reserved_63[0x8];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]803 u8 log_uar_page_sz[0x10];
804
Matan Barak7c60bcb2015-12-15 20:30:11 +0200[diff] [blame]805 u8 reserved_64[0x20];
806 u8 device_frequency_mhz[0x20];
807 u8 device_frequency_khz[0x20];
808 u8 reserved_65[0xa0];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]809
Matan Barak7c60bcb2015-12-15 20:30:11 +0200[diff] [blame]810 u8 reserved_66[0x1f];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]811 u8 cqe_zip[0x1];
812
813 u8 cqe_zip_timeout[0x10];
814 u8 cqe_zip_max_num[0x10];
815
Matan Barak7c60bcb2015-12-15 20:30:11 +0200[diff] [blame]816 u8 reserved_67[0x220];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]817};
818
819enum {
820 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
821 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
822};
823
824struct mlx5_ifc_dest_format_struct_bits {
825 u8 destination_type[0x8];
826 u8 destination_id[0x18];
827
828 u8 reserved_0[0x20];
829};
830
831struct mlx5_ifc_fte_match_param_bits {
832 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
833
834 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
835
836 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
837
838 u8 reserved_0[0xa00];
839};
840
841enum {
842 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
843 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
844 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
845 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
846 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
847};
848
849struct mlx5_ifc_rx_hash_field_select_bits {
850 u8 l3_prot_type[0x1];
851 u8 l4_prot_type[0x1];
852 u8 selected_fields[0x1e];
853};
854
855enum {
856 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
857 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
858};
859
860enum {
861 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
862 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
863};
864
865struct mlx5_ifc_wq_bits {
866 u8 wq_type[0x4];
867 u8 wq_signature[0x1];
868 u8 end_padding_mode[0x2];
869 u8 cd_slave[0x1];
870 u8 reserved_0[0x18];
871
872 u8 hds_skip_first_sge[0x1];
873 u8 log2_hds_buf_size[0x3];
874 u8 reserved_1[0x7];
875 u8 page_offset[0x5];
876 u8 lwm[0x10];
877
878 u8 reserved_2[0x8];
879 u8 pd[0x18];
880
881 u8 reserved_3[0x8];
882 u8 uar_page[0x18];
883
884 u8 dbr_addr[0x40];
885
886 u8 hw_counter[0x20];
887
888 u8 sw_counter[0x20];
889
890 u8 reserved_4[0xc];
891 u8 log_wq_stride[0x4];
892 u8 reserved_5[0x3];
893 u8 log_wq_pg_sz[0x5];
894 u8 reserved_6[0x3];
895 u8 log_wq_sz[0x5];
896
897 u8 reserved_7[0x4e0];
898
899 struct mlx5_ifc_cmd_pas_bits pas[0];
900};
901
902struct mlx5_ifc_rq_num_bits {
903 u8 reserved_0[0x8];
904 u8 rq_num[0x18];
905};
906
907struct mlx5_ifc_mac_address_layout_bits {
908 u8 reserved_0[0x10];
909 u8 mac_addr_47_32[0x10];
910
911 u8 mac_addr_31_0[0x20];
912};
913
914struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
915 u8 reserved_0[0xa0];
916
917 u8 min_time_between_cnps[0x20];
918
919 u8 reserved_1[0x12];
920 u8 cnp_dscp[0x6];
921 u8 reserved_2[0x5];
922 u8 cnp_802p_prio[0x3];
923
924 u8 reserved_3[0x720];
925};
926
927struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
928 u8 reserved_0[0x60];
929
930 u8 reserved_1[0x4];
931 u8 clamp_tgt_rate[0x1];
932 u8 reserved_2[0x3];
933 u8 clamp_tgt_rate_after_time_inc[0x1];
934 u8 reserved_3[0x17];
935
936 u8 reserved_4[0x20];
937
938 u8 rpg_time_reset[0x20];
939
940 u8 rpg_byte_reset[0x20];
941
942 u8 rpg_threshold[0x20];
943
944 u8 rpg_max_rate[0x20];
945
946 u8 rpg_ai_rate[0x20];
947
948 u8 rpg_hai_rate[0x20];
949
950 u8 rpg_gd[0x20];
951
952 u8 rpg_min_dec_fac[0x20];
953
954 u8 rpg_min_rate[0x20];
955
956 u8 reserved_5[0xe0];
957
958 u8 rate_to_set_on_first_cnp[0x20];
959
960 u8 dce_tcp_g[0x20];
961
962 u8 dce_tcp_rtt[0x20];
963
964 u8 rate_reduce_monitor_period[0x20];
965
966 u8 reserved_6[0x20];
967
968 u8 initial_alpha_value[0x20];
969
970 u8 reserved_7[0x4a0];
971};
972
973struct mlx5_ifc_cong_control_802_1qau_rp_bits {
974 u8 reserved_0[0x80];
975
976 u8 rppp_max_rps[0x20];
977
978 u8 rpg_time_reset[0x20];
979
980 u8 rpg_byte_reset[0x20];
981
982 u8 rpg_threshold[0x20];
983
984 u8 rpg_max_rate[0x20];
985
986 u8 rpg_ai_rate[0x20];
987
988 u8 rpg_hai_rate[0x20];
989
990 u8 rpg_gd[0x20];
991
992 u8 rpg_min_dec_fac[0x20];
993
994 u8 rpg_min_rate[0x20];
995
996 u8 reserved_1[0x640];
997};
998
999enum {
1000 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1001 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1002 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1003};
1004
1005struct mlx5_ifc_resize_field_select_bits {
1006 u8 resize_field_select[0x20];
1007};
1008
1009enum {
1010 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1011 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1012 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1013 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1014};
1015
1016struct mlx5_ifc_modify_field_select_bits {
1017 u8 modify_field_select[0x20];
1018};
1019
1020struct mlx5_ifc_field_select_r_roce_np_bits {
1021 u8 field_select_r_roce_np[0x20];
1022};
1023
1024struct mlx5_ifc_field_select_r_roce_rp_bits {
1025 u8 field_select_r_roce_rp[0x20];
1026};
1027
1028enum {
1029 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1030 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1031 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1032 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1033 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1034 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1035 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1036 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1037 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1038 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1039};
1040
1041struct mlx5_ifc_field_select_802_1qau_rp_bits {
1042 u8 field_select_8021qaurp[0x20];
1043};
1044
1045struct mlx5_ifc_phys_layer_cntrs_bits {
1046 u8 time_since_last_clear_high[0x20];
1047
1048 u8 time_since_last_clear_low[0x20];
1049
1050 u8 symbol_errors_high[0x20];
1051
1052 u8 symbol_errors_low[0x20];
1053
1054 u8 sync_headers_errors_high[0x20];
1055
1056 u8 sync_headers_errors_low[0x20];
1057
1058 u8 edpl_bip_errors_lane0_high[0x20];
1059
1060 u8 edpl_bip_errors_lane0_low[0x20];
1061
1062 u8 edpl_bip_errors_lane1_high[0x20];
1063
1064 u8 edpl_bip_errors_lane1_low[0x20];
1065
1066 u8 edpl_bip_errors_lane2_high[0x20];
1067
1068 u8 edpl_bip_errors_lane2_low[0x20];
1069
1070 u8 edpl_bip_errors_lane3_high[0x20];
1071
1072 u8 edpl_bip_errors_lane3_low[0x20];
1073
1074 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1075
1076 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1077
1078 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1079
1080 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1081
1082 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1083
1084 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1085
1086 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1087
1088 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1089
1090 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1091
1092 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1093
1094 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1095
1096 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1097
1098 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1099
1100 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1101
1102 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1103
1104 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1105
1106 u8 rs_fec_corrected_blocks_high[0x20];
1107
1108 u8 rs_fec_corrected_blocks_low[0x20];
1109
1110 u8 rs_fec_uncorrectable_blocks_high[0x20];
1111
1112 u8 rs_fec_uncorrectable_blocks_low[0x20];
1113
1114 u8 rs_fec_no_errors_blocks_high[0x20];
1115
1116 u8 rs_fec_no_errors_blocks_low[0x20];
1117
1118 u8 rs_fec_single_error_blocks_high[0x20];
1119
1120 u8 rs_fec_single_error_blocks_low[0x20];
1121
1122 u8 rs_fec_corrected_symbols_total_high[0x20];
1123
1124 u8 rs_fec_corrected_symbols_total_low[0x20];
1125
1126 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1127
1128 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1129
1130 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1131
1132 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1133
1134 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1135
1136 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1137
1138 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1139
1140 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1141
1142 u8 link_down_events[0x20];
1143
1144 u8 successful_recovery_events[0x20];
1145
1146 u8 reserved_0[0x180];
1147};
1148
1149struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1150 u8 transmit_queue_high[0x20];
1151
1152 u8 transmit_queue_low[0x20];
1153
1154 u8 reserved_0[0x780];
1155};
1156
1157struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1158 u8 rx_octets_high[0x20];
1159
1160 u8 rx_octets_low[0x20];
1161
1162 u8 reserved_0[0xc0];
1163
1164 u8 rx_frames_high[0x20];
1165
1166 u8 rx_frames_low[0x20];
1167
1168 u8 tx_octets_high[0x20];
1169
1170 u8 tx_octets_low[0x20];
1171
1172 u8 reserved_1[0xc0];
1173
1174 u8 tx_frames_high[0x20];
1175
1176 u8 tx_frames_low[0x20];
1177
1178 u8 rx_pause_high[0x20];
1179
1180 u8 rx_pause_low[0x20];
1181
1182 u8 rx_pause_duration_high[0x20];
1183
1184 u8 rx_pause_duration_low[0x20];
1185
1186 u8 tx_pause_high[0x20];
1187
1188 u8 tx_pause_low[0x20];
1189
1190 u8 tx_pause_duration_high[0x20];
1191
1192 u8 tx_pause_duration_low[0x20];
1193
1194 u8 rx_pause_transition_high[0x20];
1195
1196 u8 rx_pause_transition_low[0x20];
1197
1198 u8 reserved_2[0x400];
1199};
1200
1201struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1202 u8 port_transmit_wait_high[0x20];
1203
1204 u8 port_transmit_wait_low[0x20];
1205
1206 u8 reserved_0[0x780];
1207};
1208
1209struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1210 u8 dot3stats_alignment_errors_high[0x20];
1211
1212 u8 dot3stats_alignment_errors_low[0x20];
1213
1214 u8 dot3stats_fcs_errors_high[0x20];
1215
1216 u8 dot3stats_fcs_errors_low[0x20];
1217
1218 u8 dot3stats_single_collision_frames_high[0x20];
1219
1220 u8 dot3stats_single_collision_frames_low[0x20];
1221
1222 u8 dot3stats_multiple_collision_frames_high[0x20];
1223
1224 u8 dot3stats_multiple_collision_frames_low[0x20];
1225
1226 u8 dot3stats_sqe_test_errors_high[0x20];
1227
1228 u8 dot3stats_sqe_test_errors_low[0x20];
1229
1230 u8 dot3stats_deferred_transmissions_high[0x20];
1231
1232 u8 dot3stats_deferred_transmissions_low[0x20];
1233
1234 u8 dot3stats_late_collisions_high[0x20];
1235
1236 u8 dot3stats_late_collisions_low[0x20];
1237
1238 u8 dot3stats_excessive_collisions_high[0x20];
1239
1240 u8 dot3stats_excessive_collisions_low[0x20];
1241
1242 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1243
1244 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1245
1246 u8 dot3stats_carrier_sense_errors_high[0x20];
1247
1248 u8 dot3stats_carrier_sense_errors_low[0x20];
1249
1250 u8 dot3stats_frame_too_longs_high[0x20];
1251
1252 u8 dot3stats_frame_too_longs_low[0x20];
1253
1254 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1255
1256 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1257
1258 u8 dot3stats_symbol_errors_high[0x20];
1259
1260 u8 dot3stats_symbol_errors_low[0x20];
1261
1262 u8 dot3control_in_unknown_opcodes_high[0x20];
1263
1264 u8 dot3control_in_unknown_opcodes_low[0x20];
1265
1266 u8 dot3in_pause_frames_high[0x20];
1267
1268 u8 dot3in_pause_frames_low[0x20];
1269
1270 u8 dot3out_pause_frames_high[0x20];
1271
1272 u8 dot3out_pause_frames_low[0x20];
1273
1274 u8 reserved_0[0x3c0];
1275};
1276
1277struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1278 u8 ether_stats_drop_events_high[0x20];
1279
1280 u8 ether_stats_drop_events_low[0x20];
1281
1282 u8 ether_stats_octets_high[0x20];
1283
1284 u8 ether_stats_octets_low[0x20];
1285
1286 u8 ether_stats_pkts_high[0x20];
1287
1288 u8 ether_stats_pkts_low[0x20];
1289
1290 u8 ether_stats_broadcast_pkts_high[0x20];
1291
1292 u8 ether_stats_broadcast_pkts_low[0x20];
1293
1294 u8 ether_stats_multicast_pkts_high[0x20];
1295
1296 u8 ether_stats_multicast_pkts_low[0x20];
1297
1298 u8 ether_stats_crc_align_errors_high[0x20];
1299
1300 u8 ether_stats_crc_align_errors_low[0x20];
1301
1302 u8 ether_stats_undersize_pkts_high[0x20];
1303
1304 u8 ether_stats_undersize_pkts_low[0x20];
1305
1306 u8 ether_stats_oversize_pkts_high[0x20];
1307
1308 u8 ether_stats_oversize_pkts_low[0x20];
1309
1310 u8 ether_stats_fragments_high[0x20];
1311
1312 u8 ether_stats_fragments_low[0x20];
1313
1314 u8 ether_stats_jabbers_high[0x20];
1315
1316 u8 ether_stats_jabbers_low[0x20];
1317
1318 u8 ether_stats_collisions_high[0x20];
1319
1320 u8 ether_stats_collisions_low[0x20];
1321
1322 u8 ether_stats_pkts64octets_high[0x20];
1323
1324 u8 ether_stats_pkts64octets_low[0x20];
1325
1326 u8 ether_stats_pkts65to127octets_high[0x20];
1327
1328 u8 ether_stats_pkts65to127octets_low[0x20];
1329
1330 u8 ether_stats_pkts128to255octets_high[0x20];
1331
1332 u8 ether_stats_pkts128to255octets_low[0x20];
1333
1334 u8 ether_stats_pkts256to511octets_high[0x20];
1335
1336 u8 ether_stats_pkts256to511octets_low[0x20];
1337
1338 u8 ether_stats_pkts512to1023octets_high[0x20];
1339
1340 u8 ether_stats_pkts512to1023octets_low[0x20];
1341
1342 u8 ether_stats_pkts1024to1518octets_high[0x20];
1343
1344 u8 ether_stats_pkts1024to1518octets_low[0x20];
1345
1346 u8 ether_stats_pkts1519to2047octets_high[0x20];
1347
1348 u8 ether_stats_pkts1519to2047octets_low[0x20];
1349
1350 u8 ether_stats_pkts2048to4095octets_high[0x20];
1351
1352 u8 ether_stats_pkts2048to4095octets_low[0x20];
1353
1354 u8 ether_stats_pkts4096to8191octets_high[0x20];
1355
1356 u8 ether_stats_pkts4096to8191octets_low[0x20];
1357
1358 u8 ether_stats_pkts8192to10239octets_high[0x20];
1359
1360 u8 ether_stats_pkts8192to10239octets_low[0x20];
1361
1362 u8 reserved_0[0x280];
1363};
1364
1365struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1366 u8 if_in_octets_high[0x20];
1367
1368 u8 if_in_octets_low[0x20];
1369
1370 u8 if_in_ucast_pkts_high[0x20];
1371
1372 u8 if_in_ucast_pkts_low[0x20];
1373
1374 u8 if_in_discards_high[0x20];
1375
1376 u8 if_in_discards_low[0x20];
1377
1378 u8 if_in_errors_high[0x20];
1379
1380 u8 if_in_errors_low[0x20];
1381
1382 u8 if_in_unknown_protos_high[0x20];
1383
1384 u8 if_in_unknown_protos_low[0x20];
1385
1386 u8 if_out_octets_high[0x20];
1387
1388 u8 if_out_octets_low[0x20];
1389
1390 u8 if_out_ucast_pkts_high[0x20];
1391
1392 u8 if_out_ucast_pkts_low[0x20];
1393
1394 u8 if_out_discards_high[0x20];
1395
1396 u8 if_out_discards_low[0x20];
1397
1398 u8 if_out_errors_high[0x20];
1399
1400 u8 if_out_errors_low[0x20];
1401
1402 u8 if_in_multicast_pkts_high[0x20];
1403
1404 u8 if_in_multicast_pkts_low[0x20];
1405
1406 u8 if_in_broadcast_pkts_high[0x20];
1407
1408 u8 if_in_broadcast_pkts_low[0x20];
1409
1410 u8 if_out_multicast_pkts_high[0x20];
1411
1412 u8 if_out_multicast_pkts_low[0x20];
1413
1414 u8 if_out_broadcast_pkts_high[0x20];
1415
1416 u8 if_out_broadcast_pkts_low[0x20];
1417
1418 u8 reserved_0[0x480];
1419};
1420
1421struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1422 u8 a_frames_transmitted_ok_high[0x20];
1423
1424 u8 a_frames_transmitted_ok_low[0x20];
1425
1426 u8 a_frames_received_ok_high[0x20];
1427
1428 u8 a_frames_received_ok_low[0x20];
1429
1430 u8 a_frame_check_sequence_errors_high[0x20];
1431
1432 u8 a_frame_check_sequence_errors_low[0x20];
1433
1434 u8 a_alignment_errors_high[0x20];
1435
1436 u8 a_alignment_errors_low[0x20];
1437
1438 u8 a_octets_transmitted_ok_high[0x20];
1439
1440 u8 a_octets_transmitted_ok_low[0x20];
1441
1442 u8 a_octets_received_ok_high[0x20];
1443
1444 u8 a_octets_received_ok_low[0x20];
1445
1446 u8 a_multicast_frames_xmitted_ok_high[0x20];
1447
1448 u8 a_multicast_frames_xmitted_ok_low[0x20];
1449
1450 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1451
1452 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1453
1454 u8 a_multicast_frames_received_ok_high[0x20];
1455
1456 u8 a_multicast_frames_received_ok_low[0x20];
1457
1458 u8 a_broadcast_frames_received_ok_high[0x20];
1459
1460 u8 a_broadcast_frames_received_ok_low[0x20];
1461
1462 u8 a_in_range_length_errors_high[0x20];
1463
1464 u8 a_in_range_length_errors_low[0x20];
1465
1466 u8 a_out_of_range_length_field_high[0x20];
1467
1468 u8 a_out_of_range_length_field_low[0x20];
1469
1470 u8 a_frame_too_long_errors_high[0x20];
1471
1472 u8 a_frame_too_long_errors_low[0x20];
1473
1474 u8 a_symbol_error_during_carrier_high[0x20];
1475
1476 u8 a_symbol_error_during_carrier_low[0x20];
1477
1478 u8 a_mac_control_frames_transmitted_high[0x20];
1479
1480 u8 a_mac_control_frames_transmitted_low[0x20];
1481
1482 u8 a_mac_control_frames_received_high[0x20];
1483
1484 u8 a_mac_control_frames_received_low[0x20];
1485
1486 u8 a_unsupported_opcodes_received_high[0x20];
1487
1488 u8 a_unsupported_opcodes_received_low[0x20];
1489
1490 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1491
1492 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1493
1494 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1495
1496 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1497
1498 u8 reserved_0[0x300];
1499};
1500
1501struct mlx5_ifc_cmd_inter_comp_event_bits {
1502 u8 command_completion_vector[0x20];
1503
1504 u8 reserved_0[0xc0];
1505};
1506
1507struct mlx5_ifc_stall_vl_event_bits {
1508 u8 reserved_0[0x18];
1509 u8 port_num[0x1];
1510 u8 reserved_1[0x3];
1511 u8 vl[0x4];
1512
1513 u8 reserved_2[0xa0];
1514};
1515
1516struct mlx5_ifc_db_bf_congestion_event_bits {
1517 u8 event_subtype[0x8];
1518 u8 reserved_0[0x8];
1519 u8 congestion_level[0x8];
1520 u8 reserved_1[0x8];
1521
1522 u8 reserved_2[0xa0];
1523};
1524
1525struct mlx5_ifc_gpio_event_bits {
1526 u8 reserved_0[0x60];
1527
1528 u8 gpio_event_hi[0x20];
1529
1530 u8 gpio_event_lo[0x20];
1531
1532 u8 reserved_1[0x40];
1533};
1534
1535struct mlx5_ifc_port_state_change_event_bits {
1536 u8 reserved_0[0x40];
1537
1538 u8 port_num[0x4];
1539 u8 reserved_1[0x1c];
1540
1541 u8 reserved_2[0x80];
1542};
1543
1544struct mlx5_ifc_dropped_packet_logged_bits {
1545 u8 reserved_0[0xe0];
1546};
1547
1548enum {
1549 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1550 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1551};
1552
1553struct mlx5_ifc_cq_error_bits {
1554 u8 reserved_0[0x8];
1555 u8 cqn[0x18];
1556
1557 u8 reserved_1[0x20];
1558
1559 u8 reserved_2[0x18];
1560 u8 syndrome[0x8];
1561
1562 u8 reserved_3[0x80];
1563};
1564
1565struct mlx5_ifc_rdma_page_fault_event_bits {
1566 u8 bytes_committed[0x20];
1567
1568 u8 r_key[0x20];
1569
1570 u8 reserved_0[0x10];
1571 u8 packet_len[0x10];
1572
1573 u8 rdma_op_len[0x20];
1574
1575 u8 rdma_va[0x40];
1576
1577 u8 reserved_1[0x5];
1578 u8 rdma[0x1];
1579 u8 write[0x1];
1580 u8 requestor[0x1];
1581 u8 qp_number[0x18];
1582};
1583
1584struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1585 u8 bytes_committed[0x20];
1586
1587 u8 reserved_0[0x10];
1588 u8 wqe_index[0x10];
1589
1590 u8 reserved_1[0x10];
1591 u8 len[0x10];
1592
1593 u8 reserved_2[0x60];
1594
1595 u8 reserved_3[0x5];
1596 u8 rdma[0x1];
1597 u8 write_read[0x1];
1598 u8 requestor[0x1];
1599 u8 qpn[0x18];
1600};
1601
1602struct mlx5_ifc_qp_events_bits {
1603 u8 reserved_0[0xa0];
1604
1605 u8 type[0x8];
1606 u8 reserved_1[0x18];
1607
1608 u8 reserved_2[0x8];
1609 u8 qpn_rqn_sqn[0x18];
1610};
1611
1612struct mlx5_ifc_dct_events_bits {
1613 u8 reserved_0[0xc0];
1614
1615 u8 reserved_1[0x8];
1616 u8 dct_number[0x18];
1617};
1618
1619struct mlx5_ifc_comp_event_bits {
1620 u8 reserved_0[0xc0];
1621
1622 u8 reserved_1[0x8];
1623 u8 cq_number[0x18];
1624};
1625
1626enum {
1627 MLX5_QPC_STATE_RST = 0x0,
1628 MLX5_QPC_STATE_INIT = 0x1,
1629 MLX5_QPC_STATE_RTR = 0x2,
1630 MLX5_QPC_STATE_RTS = 0x3,
1631 MLX5_QPC_STATE_SQER = 0x4,
1632 MLX5_QPC_STATE_ERR = 0x6,
1633 MLX5_QPC_STATE_SQD = 0x7,
1634 MLX5_QPC_STATE_SUSPENDED = 0x9,
1635};
1636
1637enum {
1638 MLX5_QPC_ST_RC = 0x0,
1639 MLX5_QPC_ST_UC = 0x1,
1640 MLX5_QPC_ST_UD = 0x2,
1641 MLX5_QPC_ST_XRC = 0x3,
1642 MLX5_QPC_ST_DCI = 0x5,
1643 MLX5_QPC_ST_QP0 = 0x7,
1644 MLX5_QPC_ST_QP1 = 0x8,
1645 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1646 MLX5_QPC_ST_REG_UMR = 0xc,
1647};
1648
1649enum {
1650 MLX5_QPC_PM_STATE_ARMED = 0x0,
1651 MLX5_QPC_PM_STATE_REARM = 0x1,
1652 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1653 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1654};
1655
1656enum {
1657 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1658 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1659};
1660
1661enum {
1662 MLX5_QPC_MTU_256_BYTES = 0x1,
1663 MLX5_QPC_MTU_512_BYTES = 0x2,
1664 MLX5_QPC_MTU_1K_BYTES = 0x3,
1665 MLX5_QPC_MTU_2K_BYTES = 0x4,
1666 MLX5_QPC_MTU_4K_BYTES = 0x5,
1667 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1668};
1669
1670enum {
1671 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1672 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1673 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1674 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1675 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1676 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1677 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1678 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1679};
1680
1681enum {
1682 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1683 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1684 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1685};
1686
1687enum {
1688 MLX5_QPC_CS_RES_DISABLE = 0x0,
1689 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1690 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1691};
1692
1693struct mlx5_ifc_qpc_bits {
1694 u8 state[0x4];
1695 u8 reserved_0[0x4];
1696 u8 st[0x8];
1697 u8 reserved_1[0x3];
1698 u8 pm_state[0x2];
1699 u8 reserved_2[0x7];
1700 u8 end_padding_mode[0x2];
1701 u8 reserved_3[0x2];
1702
1703 u8 wq_signature[0x1];
1704 u8 block_lb_mc[0x1];
1705 u8 atomic_like_write_en[0x1];
1706 u8 latency_sensitive[0x1];
1707 u8 reserved_4[0x1];
1708 u8 drain_sigerr[0x1];
1709 u8 reserved_5[0x2];
1710 u8 pd[0x18];
1711
1712 u8 mtu[0x3];
1713 u8 log_msg_max[0x5];
1714 u8 reserved_6[0x1];
1715 u8 log_rq_size[0x4];
1716 u8 log_rq_stride[0x3];
1717 u8 no_sq[0x1];
1718 u8 log_sq_size[0x4];
1719 u8 reserved_7[0x6];
1720 u8 rlky[0x1];
1721 u8 reserved_8[0x4];
1722
1723 u8 counter_set_id[0x8];
1724 u8 uar_page[0x18];
1725
1726 u8 reserved_9[0x8];
1727 u8 user_index[0x18];
1728
1729 u8 reserved_10[0x3];
1730 u8 log_page_size[0x5];
1731 u8 remote_qpn[0x18];
1732
1733 struct mlx5_ifc_ads_bits primary_address_path;
1734
1735 struct mlx5_ifc_ads_bits secondary_address_path;
1736
1737 u8 log_ack_req_freq[0x4];
1738 u8 reserved_11[0x4];
1739 u8 log_sra_max[0x3];
1740 u8 reserved_12[0x2];
1741 u8 retry_count[0x3];
1742 u8 rnr_retry[0x3];
1743 u8 reserved_13[0x1];
1744 u8 fre[0x1];
1745 u8 cur_rnr_retry[0x3];
1746 u8 cur_retry_count[0x3];
1747 u8 reserved_14[0x5];
1748
1749 u8 reserved_15[0x20];
1750
1751 u8 reserved_16[0x8];
1752 u8 next_send_psn[0x18];
1753
1754 u8 reserved_17[0x8];
1755 u8 cqn_snd[0x18];
1756
1757 u8 reserved_18[0x40];
1758
1759 u8 reserved_19[0x8];
1760 u8 last_acked_psn[0x18];
1761
1762 u8 reserved_20[0x8];
1763 u8 ssn[0x18];
1764
1765 u8 reserved_21[0x8];
1766 u8 log_rra_max[0x3];
1767 u8 reserved_22[0x1];
1768 u8 atomic_mode[0x4];
1769 u8 rre[0x1];
1770 u8 rwe[0x1];
1771 u8 rae[0x1];
1772 u8 reserved_23[0x1];
1773 u8 page_offset[0x6];
1774 u8 reserved_24[0x3];
1775 u8 cd_slave_receive[0x1];
1776 u8 cd_slave_send[0x1];
1777 u8 cd_master[0x1];
1778
1779 u8 reserved_25[0x3];
1780 u8 min_rnr_nak[0x5];
1781 u8 next_rcv_psn[0x18];
1782
1783 u8 reserved_26[0x8];
1784 u8 xrcd[0x18];
1785
1786 u8 reserved_27[0x8];
1787 u8 cqn_rcv[0x18];
1788
1789 u8 dbr_addr[0x40];
1790
1791 u8 q_key[0x20];
1792
1793 u8 reserved_28[0x5];
1794 u8 rq_type[0x3];
1795 u8 srqn_rmpn[0x18];
1796
1797 u8 reserved_29[0x8];
1798 u8 rmsn[0x18];
1799
1800 u8 hw_sq_wqebb_counter[0x10];
1801 u8 sw_sq_wqebb_counter[0x10];
1802
1803 u8 hw_rq_counter[0x20];
1804
1805 u8 sw_rq_counter[0x20];
1806
1807 u8 reserved_30[0x20];
1808
1809 u8 reserved_31[0xf];
1810 u8 cgs[0x1];
1811 u8 cs_req[0x8];
1812 u8 cs_res[0x8];
1813
1814 u8 dc_access_key[0x40];
1815
1816 u8 reserved_32[0xc0];
1817};
1818
1819struct mlx5_ifc_roce_addr_layout_bits {
1820 u8 source_l3_address[16][0x8];
1821
1822 u8 reserved_0[0x3];
1823 u8 vlan_valid[0x1];
1824 u8 vlan_id[0xc];
1825 u8 source_mac_47_32[0x10];
1826
1827 u8 source_mac_31_0[0x20];
1828
1829 u8 reserved_1[0x14];
1830 u8 roce_l3_type[0x4];
1831 u8 roce_version[0x8];
1832
1833 u8 reserved_2[0x20];
1834};
1835
1836union mlx5_ifc_hca_cap_union_bits {
1837 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1838 struct mlx5_ifc_odp_cap_bits odp_cap;
1839 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1840 struct mlx5_ifc_roce_cap_bits roce_cap;
1841 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1842 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1843 u8 reserved_0[0x8000];
1844};
1845
1846enum {
1847 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1848 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1849 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1850};
1851
1852struct mlx5_ifc_flow_context_bits {
1853 u8 reserved_0[0x20];
1854
1855 u8 group_id[0x20];
1856
1857 u8 reserved_1[0x8];
1858 u8 flow_tag[0x18];
1859
1860 u8 reserved_2[0x10];
1861 u8 action[0x10];
1862
1863 u8 reserved_3[0x8];
1864 u8 destination_list_size[0x18];
1865
1866 u8 reserved_4[0x160];
1867
1868 struct mlx5_ifc_fte_match_param_bits match_value;
1869
1870 u8 reserved_5[0x600];
1871
1872 struct mlx5_ifc_dest_format_struct_bits destination[0];
1873};
1874
1875enum {
1876 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1877 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1878};
1879
1880struct mlx5_ifc_xrc_srqc_bits {
1881 u8 state[0x4];
1882 u8 log_xrc_srq_size[0x4];
1883 u8 reserved_0[0x18];
1884
1885 u8 wq_signature[0x1];
1886 u8 cont_srq[0x1];
1887 u8 reserved_1[0x1];
1888 u8 rlky[0x1];
1889 u8 basic_cyclic_rcv_wqe[0x1];
1890 u8 log_rq_stride[0x3];
1891 u8 xrcd[0x18];
1892
1893 u8 page_offset[0x6];
1894 u8 reserved_2[0x2];
1895 u8 cqn[0x18];
1896
1897 u8 reserved_3[0x20];
1898
1899 u8 user_index_equal_xrc_srqn[0x1];
1900 u8 reserved_4[0x1];
1901 u8 log_page_size[0x6];
1902 u8 user_index[0x18];
1903
1904 u8 reserved_5[0x20];
1905
1906 u8 reserved_6[0x8];
1907 u8 pd[0x18];
1908
1909 u8 lwm[0x10];
1910 u8 wqe_cnt[0x10];
1911
1912 u8 reserved_7[0x40];
1913
1914 u8 db_record_addr_h[0x20];
1915
1916 u8 db_record_addr_l[0x1e];
1917 u8 reserved_8[0x2];
1918
1919 u8 reserved_9[0x80];
1920};
1921
1922struct mlx5_ifc_traffic_counter_bits {
1923 u8 packets[0x40];
1924
1925 u8 octets[0x40];
1926};
1927
1928struct mlx5_ifc_tisc_bits {
1929 u8 reserved_0[0xc];
1930 u8 prio[0x4];
1931 u8 reserved_1[0x10];
1932
1933 u8 reserved_2[0x100];
1934
1935 u8 reserved_3[0x8];
1936 u8 transport_domain[0x18];
1937
1938 u8 reserved_4[0x3c0];
1939};
1940
1941enum {
1942 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1943 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1944};
1945
1946enum {
1947 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1948 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1949};
1950
1951enum {
Saeed Mahameed2be69672015-07-23 23:35:56 +0300[diff] [blame]1952 MLX5_RX_HASH_FN_NONE = 0x0,
1953 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1954 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]1955};
1956
1957enum {
1958 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1959 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1960};
1961
1962struct mlx5_ifc_tirc_bits {
1963 u8 reserved_0[0x20];
1964
1965 u8 disp_type[0x4];
1966 u8 reserved_1[0x1c];
1967
1968 u8 reserved_2[0x40];
1969
1970 u8 reserved_3[0x4];
1971 u8 lro_timeout_period_usecs[0x10];
1972 u8 lro_enable_mask[0x4];
1973 u8 lro_max_ip_payload_size[0x8];
1974
1975 u8 reserved_4[0x40];
1976
1977 u8 reserved_5[0x8];
1978 u8 inline_rqn[0x18];
1979
1980 u8 rx_hash_symmetric[0x1];
1981 u8 reserved_6[0x1];
1982 u8 tunneled_offload_en[0x1];
1983 u8 reserved_7[0x5];
1984 u8 indirect_table[0x18];
1985
1986 u8 rx_hash_fn[0x4];
1987 u8 reserved_8[0x2];
1988 u8 self_lb_block[0x2];
1989 u8 transport_domain[0x18];
1990
1991 u8 rx_hash_toeplitz_key[10][0x20];
1992
1993 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1994
1995 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1996
1997 u8 reserved_9[0x4c0];
1998};
1999
2000enum {
2001 MLX5_SRQC_STATE_GOOD = 0x0,
2002 MLX5_SRQC_STATE_ERROR = 0x1,
2003};
2004
2005struct mlx5_ifc_srqc_bits {
2006 u8 state[0x4];
2007 u8 log_srq_size[0x4];
2008 u8 reserved_0[0x18];
2009
2010 u8 wq_signature[0x1];
2011 u8 cont_srq[0x1];
2012 u8 reserved_1[0x1];
2013 u8 rlky[0x1];
2014 u8 reserved_2[0x1];
2015 u8 log_rq_stride[0x3];
2016 u8 xrcd[0x18];
2017
2018 u8 page_offset[0x6];
2019 u8 reserved_3[0x2];
2020 u8 cqn[0x18];
2021
2022 u8 reserved_4[0x20];
2023
2024 u8 reserved_5[0x2];
2025 u8 log_page_size[0x6];
2026 u8 reserved_6[0x18];
2027
2028 u8 reserved_7[0x20];
2029
2030 u8 reserved_8[0x8];
2031 u8 pd[0x18];
2032
2033 u8 lwm[0x10];
2034 u8 wqe_cnt[0x10];
2035
2036 u8 reserved_9[0x40];
2037
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]2038 u8 dbr_addr[0x40];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2039
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]2040 u8 reserved_10[0x80];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2041};
2042
2043enum {
2044 MLX5_SQC_STATE_RST = 0x0,
2045 MLX5_SQC_STATE_RDY = 0x1,
2046 MLX5_SQC_STATE_ERR = 0x3,
2047};
2048
2049struct mlx5_ifc_sqc_bits {
2050 u8 rlky[0x1];
2051 u8 cd_master[0x1];
2052 u8 fre[0x1];
2053 u8 flush_in_error_en[0x1];
2054 u8 reserved_0[0x4];
2055 u8 state[0x4];
2056 u8 reserved_1[0x14];
2057
2058 u8 reserved_2[0x8];
2059 u8 user_index[0x18];
2060
2061 u8 reserved_3[0x8];
2062 u8 cqn[0x18];
2063
2064 u8 reserved_4[0xa0];
2065
2066 u8 tis_lst_sz[0x10];
2067 u8 reserved_5[0x10];
2068
2069 u8 reserved_6[0x40];
2070
2071 u8 reserved_7[0x8];
2072 u8 tis_num_0[0x18];
2073
2074 struct mlx5_ifc_wq_bits wq;
2075};
2076
2077struct mlx5_ifc_rqtc_bits {
2078 u8 reserved_0[0xa0];
2079
2080 u8 reserved_1[0x10];
2081 u8 rqt_max_size[0x10];
2082
2083 u8 reserved_2[0x10];
2084 u8 rqt_actual_size[0x10];
2085
2086 u8 reserved_3[0x6a0];
2087
2088 struct mlx5_ifc_rq_num_bits rq_num[0];
2089};
2090
2091enum {
2092 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2093 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2094};
2095
2096enum {
2097 MLX5_RQC_STATE_RST = 0x0,
2098 MLX5_RQC_STATE_RDY = 0x1,
2099 MLX5_RQC_STATE_ERR = 0x3,
2100};
2101
2102struct mlx5_ifc_rqc_bits {
2103 u8 rlky[0x1];
2104 u8 reserved_0[0x2];
2105 u8 vsd[0x1];
2106 u8 mem_rq_type[0x4];
2107 u8 state[0x4];
2108 u8 reserved_1[0x1];
2109 u8 flush_in_error_en[0x1];
2110 u8 reserved_2[0x12];
2111
2112 u8 reserved_3[0x8];
2113 u8 user_index[0x18];
2114
2115 u8 reserved_4[0x8];
2116 u8 cqn[0x18];
2117
2118 u8 counter_set_id[0x8];
2119 u8 reserved_5[0x18];
2120
2121 u8 reserved_6[0x8];
2122 u8 rmpn[0x18];
2123
2124 u8 reserved_7[0xe0];
2125
2126 struct mlx5_ifc_wq_bits wq;
2127};
2128
2129enum {
2130 MLX5_RMPC_STATE_RDY = 0x1,
2131 MLX5_RMPC_STATE_ERR = 0x3,
2132};
2133
2134struct mlx5_ifc_rmpc_bits {
2135 u8 reserved_0[0x8];
2136 u8 state[0x4];
2137 u8 reserved_1[0x14];
2138
2139 u8 basic_cyclic_rcv_wqe[0x1];
2140 u8 reserved_2[0x1f];
2141
2142 u8 reserved_3[0x140];
2143
2144 struct mlx5_ifc_wq_bits wq;
2145};
2146
2147enum {
2148 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2149};
2150
2151struct mlx5_ifc_nic_vport_context_bits {
2152 u8 reserved_0[0x1f];
2153 u8 roce_en[0x1];
2154
Achiad Shochat9efa7522015-12-23 18:47:20 +0200[diff] [blame]2155 u8 reserved_1[0x120];
2156
2157 u8 system_image_guid[0x40];
2158 u8 port_guid[0x40];
2159 u8 node_guid[0x40];
2160
2161 u8 reserved_5[0x140];
2162 u8 qkey_violation_counter[0x10];
2163 u8 reserved_6[0x430];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2164
2165 u8 reserved_2[0x5];
2166 u8 allowed_list_type[0x3];
2167 u8 reserved_3[0xc];
2168 u8 allowed_list_size[0xc];
2169
2170 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2171
2172 u8 reserved_4[0x20];
2173
2174 u8 current_uc_mac_address[0][0x40];
2175};
2176
2177enum {
2178 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2179 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2180 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2181};
2182
2183struct mlx5_ifc_mkc_bits {
2184 u8 reserved_0[0x1];
2185 u8 free[0x1];
2186 u8 reserved_1[0xd];
2187 u8 small_fence_on_rdma_read_response[0x1];
2188 u8 umr_en[0x1];
2189 u8 a[0x1];
2190 u8 rw[0x1];
2191 u8 rr[0x1];
2192 u8 lw[0x1];
2193 u8 lr[0x1];
2194 u8 access_mode[0x2];
2195 u8 reserved_2[0x8];
2196
2197 u8 qpn[0x18];
2198 u8 mkey_7_0[0x8];
2199
2200 u8 reserved_3[0x20];
2201
2202 u8 length64[0x1];
2203 u8 bsf_en[0x1];
2204 u8 sync_umr[0x1];
2205 u8 reserved_4[0x2];
2206 u8 expected_sigerr_count[0x1];
2207 u8 reserved_5[0x1];
2208 u8 en_rinval[0x1];
2209 u8 pd[0x18];
2210
2211 u8 start_addr[0x40];
2212
2213 u8 len[0x40];
2214
2215 u8 bsf_octword_size[0x20];
2216
2217 u8 reserved_6[0x80];
2218
2219 u8 translations_octword_size[0x20];
2220
2221 u8 reserved_7[0x1b];
2222 u8 log_page_size[0x5];
2223
2224 u8 reserved_8[0x20];
2225};
2226
2227struct mlx5_ifc_pkey_bits {
2228 u8 reserved_0[0x10];
2229 u8 pkey[0x10];
2230};
2231
2232struct mlx5_ifc_array128_auto_bits {
2233 u8 array128_auto[16][0x8];
2234};
2235
2236struct mlx5_ifc_hca_vport_context_bits {
2237 u8 field_select[0x20];
2238
2239 u8 reserved_0[0xe0];
2240
2241 u8 sm_virt_aware[0x1];
2242 u8 has_smi[0x1];
2243 u8 has_raw[0x1];
2244 u8 grh_required[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]2245 u8 reserved_1[0xc];
2246 u8 port_physical_state[0x4];
2247 u8 vport_state_policy[0x4];
2248 u8 port_state[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2249 u8 vport_state[0x4];
2250
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]2251 u8 reserved_2[0x20];
2252
2253 u8 system_image_guid[0x40];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2254
2255 u8 port_guid[0x40];
2256
2257 u8 node_guid[0x40];
2258
2259 u8 cap_mask1[0x20];
2260
2261 u8 cap_mask1_field_select[0x20];
2262
2263 u8 cap_mask2[0x20];
2264
2265 u8 cap_mask2_field_select[0x20];
2266
2267 u8 reserved_3[0x80];
2268
2269 u8 lid[0x10];
2270 u8 reserved_4[0x4];
2271 u8 init_type_reply[0x4];
2272 u8 lmc[0x3];
2273 u8 subnet_timeout[0x5];
2274
2275 u8 sm_lid[0x10];
2276 u8 sm_sl[0x4];
2277 u8 reserved_5[0xc];
2278
2279 u8 qkey_violation_counter[0x10];
2280 u8 pkey_violation_counter[0x10];
2281
2282 u8 reserved_6[0xca0];
2283};
2284
2285enum {
2286 MLX5_EQC_STATUS_OK = 0x0,
2287 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2288};
2289
2290enum {
2291 MLX5_EQC_ST_ARMED = 0x9,
2292 MLX5_EQC_ST_FIRED = 0xa,
2293};
2294
2295struct mlx5_ifc_eqc_bits {
2296 u8 status[0x4];
2297 u8 reserved_0[0x9];
2298 u8 ec[0x1];
2299 u8 oi[0x1];
2300 u8 reserved_1[0x5];
2301 u8 st[0x4];
2302 u8 reserved_2[0x8];
2303
2304 u8 reserved_3[0x20];
2305
2306 u8 reserved_4[0x14];
2307 u8 page_offset[0x6];
2308 u8 reserved_5[0x6];
2309
2310 u8 reserved_6[0x3];
2311 u8 log_eq_size[0x5];
2312 u8 uar_page[0x18];
2313
2314 u8 reserved_7[0x20];
2315
2316 u8 reserved_8[0x18];
2317 u8 intr[0x8];
2318
2319 u8 reserved_9[0x3];
2320 u8 log_page_size[0x5];
2321 u8 reserved_10[0x18];
2322
2323 u8 reserved_11[0x60];
2324
2325 u8 reserved_12[0x8];
2326 u8 consumer_counter[0x18];
2327
2328 u8 reserved_13[0x8];
2329 u8 producer_counter[0x18];
2330
2331 u8 reserved_14[0x80];
2332};
2333
2334enum {
2335 MLX5_DCTC_STATE_ACTIVE = 0x0,
2336 MLX5_DCTC_STATE_DRAINING = 0x1,
2337 MLX5_DCTC_STATE_DRAINED = 0x2,
2338};
2339
2340enum {
2341 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2342 MLX5_DCTC_CS_RES_NA = 0x1,
2343 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2344};
2345
2346enum {
2347 MLX5_DCTC_MTU_256_BYTES = 0x1,
2348 MLX5_DCTC_MTU_512_BYTES = 0x2,
2349 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2350 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2351 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2352};
2353
2354struct mlx5_ifc_dctc_bits {
2355 u8 reserved_0[0x4];
2356 u8 state[0x4];
2357 u8 reserved_1[0x18];
2358
2359 u8 reserved_2[0x8];
2360 u8 user_index[0x18];
2361
2362 u8 reserved_3[0x8];
2363 u8 cqn[0x18];
2364
2365 u8 counter_set_id[0x8];
2366 u8 atomic_mode[0x4];
2367 u8 rre[0x1];
2368 u8 rwe[0x1];
2369 u8 rae[0x1];
2370 u8 atomic_like_write_en[0x1];
2371 u8 latency_sensitive[0x1];
2372 u8 rlky[0x1];
2373 u8 free_ar[0x1];
2374 u8 reserved_4[0xd];
2375
2376 u8 reserved_5[0x8];
2377 u8 cs_res[0x8];
2378 u8 reserved_6[0x3];
2379 u8 min_rnr_nak[0x5];
2380 u8 reserved_7[0x8];
2381
2382 u8 reserved_8[0x8];
2383 u8 srqn[0x18];
2384
2385 u8 reserved_9[0x8];
2386 u8 pd[0x18];
2387
2388 u8 tclass[0x8];
2389 u8 reserved_10[0x4];
2390 u8 flow_label[0x14];
2391
2392 u8 dc_access_key[0x40];
2393
2394 u8 reserved_11[0x5];
2395 u8 mtu[0x3];
2396 u8 port[0x8];
2397 u8 pkey_index[0x10];
2398
2399 u8 reserved_12[0x8];
2400 u8 my_addr_index[0x8];
2401 u8 reserved_13[0x8];
2402 u8 hop_limit[0x8];
2403
2404 u8 dc_access_key_violation_count[0x20];
2405
2406 u8 reserved_14[0x14];
2407 u8 dei_cfi[0x1];
2408 u8 eth_prio[0x3];
2409 u8 ecn[0x2];
2410 u8 dscp[0x6];
2411
2412 u8 reserved_15[0x40];
2413};
2414
2415enum {
2416 MLX5_CQC_STATUS_OK = 0x0,
2417 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2418 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2419};
2420
2421enum {
2422 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2423 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2424};
2425
2426enum {
2427 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2428 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2429 MLX5_CQC_ST_FIRED = 0xa,
2430};
2431
2432struct mlx5_ifc_cqc_bits {
2433 u8 status[0x4];
2434 u8 reserved_0[0x4];
2435 u8 cqe_sz[0x3];
2436 u8 cc[0x1];
2437 u8 reserved_1[0x1];
2438 u8 scqe_break_moderation_en[0x1];
2439 u8 oi[0x1];
2440 u8 reserved_2[0x2];
2441 u8 cqe_zip_en[0x1];
2442 u8 mini_cqe_res_format[0x2];
2443 u8 st[0x4];
2444 u8 reserved_3[0x8];
2445
2446 u8 reserved_4[0x20];
2447
2448 u8 reserved_5[0x14];
2449 u8 page_offset[0x6];
2450 u8 reserved_6[0x6];
2451
2452 u8 reserved_7[0x3];
2453 u8 log_cq_size[0x5];
2454 u8 uar_page[0x18];
2455
2456 u8 reserved_8[0x4];
2457 u8 cq_period[0xc];
2458 u8 cq_max_count[0x10];
2459
2460 u8 reserved_9[0x18];
2461 u8 c_eqn[0x8];
2462
2463 u8 reserved_10[0x3];
2464 u8 log_page_size[0x5];
2465 u8 reserved_11[0x18];
2466
2467 u8 reserved_12[0x20];
2468
2469 u8 reserved_13[0x8];
2470 u8 last_notified_index[0x18];
2471
2472 u8 reserved_14[0x8];
2473 u8 last_solicit_index[0x18];
2474
2475 u8 reserved_15[0x8];
2476 u8 consumer_counter[0x18];
2477
2478 u8 reserved_16[0x8];
2479 u8 producer_counter[0x18];
2480
2481 u8 reserved_17[0x40];
2482
2483 u8 dbr_addr[0x40];
2484};
2485
2486union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2487 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2488 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2489 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2490 u8 reserved_0[0x800];
2491};
2492
2493struct mlx5_ifc_query_adapter_param_block_bits {
Majd Dibbiny211e6c82015-06-04 19:30:42 +0300[diff] [blame]2494 u8 reserved_0[0xc0];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2495
Majd Dibbiny211e6c82015-06-04 19:30:42 +0300[diff] [blame]2496 u8 reserved_1[0x8];
2497 u8 ieee_vendor_id[0x18];
2498
2499 u8 reserved_2[0x10];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2500 u8 vsd_vendor_id[0x10];
2501
2502 u8 vsd[208][0x8];
2503
2504 u8 vsd_contd_psid[16][0x8];
2505};
2506
2507union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2508 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2509 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2510 u8 reserved_0[0x20];
2511};
2512
2513union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2514 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2515 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2516 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2517 u8 reserved_0[0x20];
2518};
2519
2520union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2521 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2522 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2523 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2524 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2525 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2526 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2527 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2528 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2529 u8 reserved_0[0x7c0];
2530};
2531
2532union mlx5_ifc_event_auto_bits {
2533 struct mlx5_ifc_comp_event_bits comp_event;
2534 struct mlx5_ifc_dct_events_bits dct_events;
2535 struct mlx5_ifc_qp_events_bits qp_events;
2536 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2537 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2538 struct mlx5_ifc_cq_error_bits cq_error;
2539 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2540 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2541 struct mlx5_ifc_gpio_event_bits gpio_event;
2542 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2543 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2544 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2545 u8 reserved_0[0xe0];
2546};
2547
2548struct mlx5_ifc_health_buffer_bits {
2549 u8 reserved_0[0x100];
2550
2551 u8 assert_existptr[0x20];
2552
2553 u8 assert_callra[0x20];
2554
2555 u8 reserved_1[0x40];
2556
2557 u8 fw_version[0x20];
2558
2559 u8 hw_id[0x20];
2560
2561 u8 reserved_2[0x20];
2562
2563 u8 irisc_index[0x8];
2564 u8 synd[0x8];
2565 u8 ext_synd[0x10];
2566};
2567
2568struct mlx5_ifc_register_loopback_control_bits {
2569 u8 no_lb[0x1];
2570 u8 reserved_0[0x7];
2571 u8 port[0x8];
2572 u8 reserved_1[0x10];
2573
2574 u8 reserved_2[0x60];
2575};
2576
2577struct mlx5_ifc_teardown_hca_out_bits {
2578 u8 status[0x8];
2579 u8 reserved_0[0x18];
2580
2581 u8 syndrome[0x20];
2582
2583 u8 reserved_1[0x40];
2584};
2585
2586enum {
2587 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2588 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2589};
2590
2591struct mlx5_ifc_teardown_hca_in_bits {
2592 u8 opcode[0x10];
2593 u8 reserved_0[0x10];
2594
2595 u8 reserved_1[0x10];
2596 u8 op_mod[0x10];
2597
2598 u8 reserved_2[0x10];
2599 u8 profile[0x10];
2600
2601 u8 reserved_3[0x20];
2602};
2603
2604struct mlx5_ifc_sqerr2rts_qp_out_bits {
2605 u8 status[0x8];
2606 u8 reserved_0[0x18];
2607
2608 u8 syndrome[0x20];
2609
2610 u8 reserved_1[0x40];
2611};
2612
2613struct mlx5_ifc_sqerr2rts_qp_in_bits {
2614 u8 opcode[0x10];
2615 u8 reserved_0[0x10];
2616
2617 u8 reserved_1[0x10];
2618 u8 op_mod[0x10];
2619
2620 u8 reserved_2[0x8];
2621 u8 qpn[0x18];
2622
2623 u8 reserved_3[0x20];
2624
2625 u8 opt_param_mask[0x20];
2626
2627 u8 reserved_4[0x20];
2628
2629 struct mlx5_ifc_qpc_bits qpc;
2630
2631 u8 reserved_5[0x80];
2632};
2633
2634struct mlx5_ifc_sqd2rts_qp_out_bits {
2635 u8 status[0x8];
2636 u8 reserved_0[0x18];
2637
2638 u8 syndrome[0x20];
2639
2640 u8 reserved_1[0x40];
2641};
2642
2643struct mlx5_ifc_sqd2rts_qp_in_bits {
2644 u8 opcode[0x10];
2645 u8 reserved_0[0x10];
2646
2647 u8 reserved_1[0x10];
2648 u8 op_mod[0x10];
2649
2650 u8 reserved_2[0x8];
2651 u8 qpn[0x18];
2652
2653 u8 reserved_3[0x20];
2654
2655 u8 opt_param_mask[0x20];
2656
2657 u8 reserved_4[0x20];
2658
2659 struct mlx5_ifc_qpc_bits qpc;
2660
2661 u8 reserved_5[0x80];
2662};
2663
2664struct mlx5_ifc_set_roce_address_out_bits {
2665 u8 status[0x8];
2666 u8 reserved_0[0x18];
2667
2668 u8 syndrome[0x20];
2669
2670 u8 reserved_1[0x40];
2671};
2672
2673struct mlx5_ifc_set_roce_address_in_bits {
2674 u8 opcode[0x10];
2675 u8 reserved_0[0x10];
2676
2677 u8 reserved_1[0x10];
2678 u8 op_mod[0x10];
2679
2680 u8 roce_address_index[0x10];
2681 u8 reserved_2[0x10];
2682
2683 u8 reserved_3[0x20];
2684
2685 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2686};
2687
2688struct mlx5_ifc_set_mad_demux_out_bits {
2689 u8 status[0x8];
2690 u8 reserved_0[0x18];
2691
2692 u8 syndrome[0x20];
2693
2694 u8 reserved_1[0x40];
2695};
2696
2697enum {
2698 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2699 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2700};
2701
2702struct mlx5_ifc_set_mad_demux_in_bits {
2703 u8 opcode[0x10];
2704 u8 reserved_0[0x10];
2705
2706 u8 reserved_1[0x10];
2707 u8 op_mod[0x10];
2708
2709 u8 reserved_2[0x20];
2710
2711 u8 reserved_3[0x6];
2712 u8 demux_mode[0x2];
2713 u8 reserved_4[0x18];
2714};
2715
2716struct mlx5_ifc_set_l2_table_entry_out_bits {
2717 u8 status[0x8];
2718 u8 reserved_0[0x18];
2719
2720 u8 syndrome[0x20];
2721
2722 u8 reserved_1[0x40];
2723};
2724
2725struct mlx5_ifc_set_l2_table_entry_in_bits {
2726 u8 opcode[0x10];
2727 u8 reserved_0[0x10];
2728
2729 u8 reserved_1[0x10];
2730 u8 op_mod[0x10];
2731
2732 u8 reserved_2[0x60];
2733
2734 u8 reserved_3[0x8];
2735 u8 table_index[0x18];
2736
2737 u8 reserved_4[0x20];
2738
2739 u8 reserved_5[0x13];
2740 u8 vlan_valid[0x1];
2741 u8 vlan[0xc];
2742
2743 struct mlx5_ifc_mac_address_layout_bits mac_address;
2744
2745 u8 reserved_6[0xc0];
2746};
2747
2748struct mlx5_ifc_set_issi_out_bits {
2749 u8 status[0x8];
2750 u8 reserved_0[0x18];
2751
2752 u8 syndrome[0x20];
2753
2754 u8 reserved_1[0x40];
2755};
2756
2757struct mlx5_ifc_set_issi_in_bits {
2758 u8 opcode[0x10];
2759 u8 reserved_0[0x10];
2760
2761 u8 reserved_1[0x10];
2762 u8 op_mod[0x10];
2763
2764 u8 reserved_2[0x10];
2765 u8 current_issi[0x10];
2766
2767 u8 reserved_3[0x20];
2768};
2769
2770struct mlx5_ifc_set_hca_cap_out_bits {
2771 u8 status[0x8];
2772 u8 reserved_0[0x18];
2773
2774 u8 syndrome[0x20];
2775
2776 u8 reserved_1[0x40];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]2777};
2778
2779struct mlx5_ifc_set_hca_cap_in_bits {
2780 u8 opcode[0x10];
2781 u8 reserved_0[0x10];
2782
2783 u8 reserved_1[0x10];
2784 u8 op_mod[0x10];
2785
2786 u8 reserved_2[0x40];
2787
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]2788 union mlx5_ifc_hca_cap_union_bits capability;
2789};
2790
2791struct mlx5_ifc_set_fte_out_bits {
2792 u8 status[0x8];
2793 u8 reserved_0[0x18];
2794
2795 u8 syndrome[0x20];
2796
2797 u8 reserved_1[0x40];
2798};
2799
2800struct mlx5_ifc_set_fte_in_bits {
2801 u8 opcode[0x10];
2802 u8 reserved_0[0x10];
2803
2804 u8 reserved_1[0x10];
2805 u8 op_mod[0x10];
2806
2807 u8 reserved_2[0x40];
2808
2809 u8 table_type[0x8];
2810 u8 reserved_3[0x18];
2811
2812 u8 reserved_4[0x8];
2813 u8 table_id[0x18];
2814
2815 u8 reserved_5[0x40];
2816
2817 u8 flow_index[0x20];
2818
2819 u8 reserved_6[0xe0];
2820
2821 struct mlx5_ifc_flow_context_bits flow_context;
2822};
2823
2824struct mlx5_ifc_rts2rts_qp_out_bits {
2825 u8 status[0x8];
2826 u8 reserved_0[0x18];
2827
2828 u8 syndrome[0x20];
2829
2830 u8 reserved_1[0x40];
2831};
2832
2833struct mlx5_ifc_rts2rts_qp_in_bits {
2834 u8 opcode[0x10];
2835 u8 reserved_0[0x10];
2836
2837 u8 reserved_1[0x10];
2838 u8 op_mod[0x10];
2839
2840 u8 reserved_2[0x8];
2841 u8 qpn[0x18];
2842
2843 u8 reserved_3[0x20];
2844
2845 u8 opt_param_mask[0x20];
2846
2847 u8 reserved_4[0x20];
2848
2849 struct mlx5_ifc_qpc_bits qpc;
2850
2851 u8 reserved_5[0x80];
2852};
2853
2854struct mlx5_ifc_rtr2rts_qp_out_bits {
2855 u8 status[0x8];
2856 u8 reserved_0[0x18];
2857
2858 u8 syndrome[0x20];
2859
2860 u8 reserved_1[0x40];
2861};
2862
2863struct mlx5_ifc_rtr2rts_qp_in_bits {
2864 u8 opcode[0x10];
2865 u8 reserved_0[0x10];
2866
2867 u8 reserved_1[0x10];
2868 u8 op_mod[0x10];
2869
2870 u8 reserved_2[0x8];
2871 u8 qpn[0x18];
2872
2873 u8 reserved_3[0x20];
2874
2875 u8 opt_param_mask[0x20];
2876
2877 u8 reserved_4[0x20];
2878
2879 struct mlx5_ifc_qpc_bits qpc;
2880
2881 u8 reserved_5[0x80];
2882};
2883
2884struct mlx5_ifc_rst2init_qp_out_bits {
2885 u8 status[0x8];
2886 u8 reserved_0[0x18];
2887
2888 u8 syndrome[0x20];
2889
2890 u8 reserved_1[0x40];
2891};
2892
2893struct mlx5_ifc_rst2init_qp_in_bits {
2894 u8 opcode[0x10];
2895 u8 reserved_0[0x10];
2896
2897 u8 reserved_1[0x10];
2898 u8 op_mod[0x10];
2899
2900 u8 reserved_2[0x8];
2901 u8 qpn[0x18];
2902
2903 u8 reserved_3[0x20];
2904
2905 u8 opt_param_mask[0x20];
2906
2907 u8 reserved_4[0x20];
2908
2909 struct mlx5_ifc_qpc_bits qpc;
2910
2911 u8 reserved_5[0x80];
2912};
2913
2914struct mlx5_ifc_query_xrc_srq_out_bits {
2915 u8 status[0x8];
2916 u8 reserved_0[0x18];
2917
2918 u8 syndrome[0x20];
2919
2920 u8 reserved_1[0x40];
2921
2922 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2923
2924 u8 reserved_2[0x600];
2925
2926 u8 pas[0][0x40];
2927};
2928
2929struct mlx5_ifc_query_xrc_srq_in_bits {
2930 u8 opcode[0x10];
2931 u8 reserved_0[0x10];
2932
2933 u8 reserved_1[0x10];
2934 u8 op_mod[0x10];
2935
2936 u8 reserved_2[0x8];
2937 u8 xrc_srqn[0x18];
2938
2939 u8 reserved_3[0x20];
2940};
2941
2942enum {
2943 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2944 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2945};
2946
2947struct mlx5_ifc_query_vport_state_out_bits {
2948 u8 status[0x8];
2949 u8 reserved_0[0x18];
2950
2951 u8 syndrome[0x20];
2952
2953 u8 reserved_1[0x20];
2954
2955 u8 reserved_2[0x18];
2956 u8 admin_state[0x4];
2957 u8 state[0x4];
2958};
2959
2960enum {
2961 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
2962};
2963
2964struct mlx5_ifc_query_vport_state_in_bits {
2965 u8 opcode[0x10];
2966 u8 reserved_0[0x10];
2967
2968 u8 reserved_1[0x10];
2969 u8 op_mod[0x10];
2970
2971 u8 other_vport[0x1];
2972 u8 reserved_2[0xf];
2973 u8 vport_number[0x10];
2974
2975 u8 reserved_3[0x20];
2976};
2977
2978struct mlx5_ifc_query_vport_counter_out_bits {
2979 u8 status[0x8];
2980 u8 reserved_0[0x18];
2981
2982 u8 syndrome[0x20];
2983
2984 u8 reserved_1[0x40];
2985
2986 struct mlx5_ifc_traffic_counter_bits received_errors;
2987
2988 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2989
2990 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2991
2992 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2993
2994 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2995
2996 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2997
2998 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2999
3000 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3001
3002 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3003
3004 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3005
3006 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3007
3008 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3009
3010 u8 reserved_2[0xa00];
3011};
3012
3013enum {
3014 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3015};
3016
3017struct mlx5_ifc_query_vport_counter_in_bits {
3018 u8 opcode[0x10];
3019 u8 reserved_0[0x10];
3020
3021 u8 reserved_1[0x10];
3022 u8 op_mod[0x10];
3023
3024 u8 other_vport[0x1];
3025 u8 reserved_2[0xf];
3026 u8 vport_number[0x10];
3027
3028 u8 reserved_3[0x60];
3029
3030 u8 clear[0x1];
3031 u8 reserved_4[0x1f];
3032
3033 u8 reserved_5[0x20];
3034};
3035
3036struct mlx5_ifc_query_tis_out_bits {
3037 u8 status[0x8];
3038 u8 reserved_0[0x18];
3039
3040 u8 syndrome[0x20];
3041
3042 u8 reserved_1[0x40];
3043
3044 struct mlx5_ifc_tisc_bits tis_context;
3045};
3046
3047struct mlx5_ifc_query_tis_in_bits {
3048 u8 opcode[0x10];
3049 u8 reserved_0[0x10];
3050
3051 u8 reserved_1[0x10];
3052 u8 op_mod[0x10];
3053
3054 u8 reserved_2[0x8];
3055 u8 tisn[0x18];
3056
3057 u8 reserved_3[0x20];
3058};
3059
3060struct mlx5_ifc_query_tir_out_bits {
3061 u8 status[0x8];
3062 u8 reserved_0[0x18];
3063
3064 u8 syndrome[0x20];
3065
3066 u8 reserved_1[0xc0];
3067
3068 struct mlx5_ifc_tirc_bits tir_context;
3069};
3070
3071struct mlx5_ifc_query_tir_in_bits {
3072 u8 opcode[0x10];
3073 u8 reserved_0[0x10];
3074
3075 u8 reserved_1[0x10];
3076 u8 op_mod[0x10];
3077
3078 u8 reserved_2[0x8];
3079 u8 tirn[0x18];
3080
3081 u8 reserved_3[0x20];
3082};
3083
3084struct mlx5_ifc_query_srq_out_bits {
3085 u8 status[0x8];
3086 u8 reserved_0[0x18];
3087
3088 u8 syndrome[0x20];
3089
3090 u8 reserved_1[0x40];
3091
3092 struct mlx5_ifc_srqc_bits srq_context_entry;
3093
3094 u8 reserved_2[0x600];
3095
3096 u8 pas[0][0x40];
3097};
3098
3099struct mlx5_ifc_query_srq_in_bits {
3100 u8 opcode[0x10];
3101 u8 reserved_0[0x10];
3102
3103 u8 reserved_1[0x10];
3104 u8 op_mod[0x10];
3105
3106 u8 reserved_2[0x8];
3107 u8 srqn[0x18];
3108
3109 u8 reserved_3[0x20];
3110};
3111
3112struct mlx5_ifc_query_sq_out_bits {
3113 u8 status[0x8];
3114 u8 reserved_0[0x18];
3115
3116 u8 syndrome[0x20];
3117
3118 u8 reserved_1[0xc0];
3119
3120 struct mlx5_ifc_sqc_bits sq_context;
3121};
3122
3123struct mlx5_ifc_query_sq_in_bits {
3124 u8 opcode[0x10];
3125 u8 reserved_0[0x10];
3126
3127 u8 reserved_1[0x10];
3128 u8 op_mod[0x10];
3129
3130 u8 reserved_2[0x8];
3131 u8 sqn[0x18];
3132
3133 u8 reserved_3[0x20];
3134};
3135
3136struct mlx5_ifc_query_special_contexts_out_bits {
3137 u8 status[0x8];
3138 u8 reserved_0[0x18];
3139
3140 u8 syndrome[0x20];
3141
3142 u8 reserved_1[0x20];
3143
3144 u8 resd_lkey[0x20];
3145};
3146
3147struct mlx5_ifc_query_special_contexts_in_bits {
3148 u8 opcode[0x10];
3149 u8 reserved_0[0x10];
3150
3151 u8 reserved_1[0x10];
3152 u8 op_mod[0x10];
3153
3154 u8 reserved_2[0x40];
3155};
3156
3157struct mlx5_ifc_query_rqt_out_bits {
3158 u8 status[0x8];
3159 u8 reserved_0[0x18];
3160
3161 u8 syndrome[0x20];
3162
3163 u8 reserved_1[0xc0];
3164
3165 struct mlx5_ifc_rqtc_bits rqt_context;
3166};
3167
3168struct mlx5_ifc_query_rqt_in_bits {
3169 u8 opcode[0x10];
3170 u8 reserved_0[0x10];
3171
3172 u8 reserved_1[0x10];
3173 u8 op_mod[0x10];
3174
3175 u8 reserved_2[0x8];
3176 u8 rqtn[0x18];
3177
3178 u8 reserved_3[0x20];
3179};
3180
3181struct mlx5_ifc_query_rq_out_bits {
3182 u8 status[0x8];
3183 u8 reserved_0[0x18];
3184
3185 u8 syndrome[0x20];
3186
3187 u8 reserved_1[0xc0];
3188
3189 struct mlx5_ifc_rqc_bits rq_context;
3190};
3191
3192struct mlx5_ifc_query_rq_in_bits {
3193 u8 opcode[0x10];
3194 u8 reserved_0[0x10];
3195
3196 u8 reserved_1[0x10];
3197 u8 op_mod[0x10];
3198
3199 u8 reserved_2[0x8];
3200 u8 rqn[0x18];
3201
3202 u8 reserved_3[0x20];
3203};
3204
3205struct mlx5_ifc_query_roce_address_out_bits {
3206 u8 status[0x8];
3207 u8 reserved_0[0x18];
3208
3209 u8 syndrome[0x20];
3210
3211 u8 reserved_1[0x40];
3212
3213 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3214};
3215
3216struct mlx5_ifc_query_roce_address_in_bits {
3217 u8 opcode[0x10];
3218 u8 reserved_0[0x10];
3219
3220 u8 reserved_1[0x10];
3221 u8 op_mod[0x10];
3222
3223 u8 roce_address_index[0x10];
3224 u8 reserved_2[0x10];
3225
3226 u8 reserved_3[0x20];
3227};
3228
3229struct mlx5_ifc_query_rmp_out_bits {
3230 u8 status[0x8];
3231 u8 reserved_0[0x18];
3232
3233 u8 syndrome[0x20];
3234
3235 u8 reserved_1[0xc0];
3236
3237 struct mlx5_ifc_rmpc_bits rmp_context;
3238};
3239
3240struct mlx5_ifc_query_rmp_in_bits {
3241 u8 opcode[0x10];
3242 u8 reserved_0[0x10];
3243
3244 u8 reserved_1[0x10];
3245 u8 op_mod[0x10];
3246
3247 u8 reserved_2[0x8];
3248 u8 rmpn[0x18];
3249
3250 u8 reserved_3[0x20];
3251};
3252
3253struct mlx5_ifc_query_qp_out_bits {
3254 u8 status[0x8];
3255 u8 reserved_0[0x18];
3256
3257 u8 syndrome[0x20];
3258
3259 u8 reserved_1[0x40];
3260
3261 u8 opt_param_mask[0x20];
3262
3263 u8 reserved_2[0x20];
3264
3265 struct mlx5_ifc_qpc_bits qpc;
3266
3267 u8 reserved_3[0x80];
3268
3269 u8 pas[0][0x40];
3270};
3271
3272struct mlx5_ifc_query_qp_in_bits {
3273 u8 opcode[0x10];
3274 u8 reserved_0[0x10];
3275
3276 u8 reserved_1[0x10];
3277 u8 op_mod[0x10];
3278
3279 u8 reserved_2[0x8];
3280 u8 qpn[0x18];
3281
3282 u8 reserved_3[0x20];
3283};
3284
3285struct mlx5_ifc_query_q_counter_out_bits {
3286 u8 status[0x8];
3287 u8 reserved_0[0x18];
3288
3289 u8 syndrome[0x20];
3290
3291 u8 reserved_1[0x40];
3292
3293 u8 rx_write_requests[0x20];
3294
3295 u8 reserved_2[0x20];
3296
3297 u8 rx_read_requests[0x20];
3298
3299 u8 reserved_3[0x20];
3300
3301 u8 rx_atomic_requests[0x20];
3302
3303 u8 reserved_4[0x20];
3304
3305 u8 rx_dct_connect[0x20];
3306
3307 u8 reserved_5[0x20];
3308
3309 u8 out_of_buffer[0x20];
3310
3311 u8 reserved_6[0x20];
3312
3313 u8 out_of_sequence[0x20];
3314
3315 u8 reserved_7[0x620];
3316};
3317
3318struct mlx5_ifc_query_q_counter_in_bits {
3319 u8 opcode[0x10];
3320 u8 reserved_0[0x10];
3321
3322 u8 reserved_1[0x10];
3323 u8 op_mod[0x10];
3324
3325 u8 reserved_2[0x80];
3326
3327 u8 clear[0x1];
3328 u8 reserved_3[0x1f];
3329
3330 u8 reserved_4[0x18];
3331 u8 counter_set_id[0x8];
3332};
3333
3334struct mlx5_ifc_query_pages_out_bits {
3335 u8 status[0x8];
3336 u8 reserved_0[0x18];
3337
3338 u8 syndrome[0x20];
3339
3340 u8 reserved_1[0x10];
3341 u8 function_id[0x10];
3342
3343 u8 num_pages[0x20];
3344};
3345
3346enum {
3347 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3348 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3349 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3350};
3351
3352struct mlx5_ifc_query_pages_in_bits {
3353 u8 opcode[0x10];
3354 u8 reserved_0[0x10];
3355
3356 u8 reserved_1[0x10];
3357 u8 op_mod[0x10];
3358
3359 u8 reserved_2[0x10];
3360 u8 function_id[0x10];
3361
3362 u8 reserved_3[0x20];
3363};
3364
3365struct mlx5_ifc_query_nic_vport_context_out_bits {
3366 u8 status[0x8];
3367 u8 reserved_0[0x18];
3368
3369 u8 syndrome[0x20];
3370
3371 u8 reserved_1[0x40];
3372
3373 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3374};
3375
3376struct mlx5_ifc_query_nic_vport_context_in_bits {
3377 u8 opcode[0x10];
3378 u8 reserved_0[0x10];
3379
3380 u8 reserved_1[0x10];
3381 u8 op_mod[0x10];
3382
3383 u8 other_vport[0x1];
3384 u8 reserved_2[0xf];
3385 u8 vport_number[0x10];
3386
3387 u8 reserved_3[0x5];
3388 u8 allowed_list_type[0x3];
3389 u8 reserved_4[0x18];
3390};
3391
3392struct mlx5_ifc_query_mkey_out_bits {
3393 u8 status[0x8];
3394 u8 reserved_0[0x18];
3395
3396 u8 syndrome[0x20];
3397
3398 u8 reserved_1[0x40];
3399
3400 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3401
3402 u8 reserved_2[0x600];
3403
3404 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3405
3406 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3407};
3408
3409struct mlx5_ifc_query_mkey_in_bits {
3410 u8 opcode[0x10];
3411 u8 reserved_0[0x10];
3412
3413 u8 reserved_1[0x10];
3414 u8 op_mod[0x10];
3415
3416 u8 reserved_2[0x8];
3417 u8 mkey_index[0x18];
3418
3419 u8 pg_access[0x1];
3420 u8 reserved_3[0x1f];
3421};
3422
3423struct mlx5_ifc_query_mad_demux_out_bits {
3424 u8 status[0x8];
3425 u8 reserved_0[0x18];
3426
3427 u8 syndrome[0x20];
3428
3429 u8 reserved_1[0x40];
3430
3431 u8 mad_dumux_parameters_block[0x20];
3432};
3433
3434struct mlx5_ifc_query_mad_demux_in_bits {
3435 u8 opcode[0x10];
3436 u8 reserved_0[0x10];
3437
3438 u8 reserved_1[0x10];
3439 u8 op_mod[0x10];
3440
3441 u8 reserved_2[0x40];
3442};
3443
3444struct mlx5_ifc_query_l2_table_entry_out_bits {
3445 u8 status[0x8];
3446 u8 reserved_0[0x18];
3447
3448 u8 syndrome[0x20];
3449
3450 u8 reserved_1[0xa0];
3451
3452 u8 reserved_2[0x13];
3453 u8 vlan_valid[0x1];
3454 u8 vlan[0xc];
3455
3456 struct mlx5_ifc_mac_address_layout_bits mac_address;
3457
3458 u8 reserved_3[0xc0];
3459};
3460
3461struct mlx5_ifc_query_l2_table_entry_in_bits {
3462 u8 opcode[0x10];
3463 u8 reserved_0[0x10];
3464
3465 u8 reserved_1[0x10];
3466 u8 op_mod[0x10];
3467
3468 u8 reserved_2[0x60];
3469
3470 u8 reserved_3[0x8];
3471 u8 table_index[0x18];
3472
3473 u8 reserved_4[0x140];
3474};
3475
3476struct mlx5_ifc_query_issi_out_bits {
3477 u8 status[0x8];
3478 u8 reserved_0[0x18];
3479
3480 u8 syndrome[0x20];
3481
3482 u8 reserved_1[0x10];
3483 u8 current_issi[0x10];
3484
3485 u8 reserved_2[0xa0];
3486
3487 u8 supported_issi_reserved[76][0x8];
3488 u8 supported_issi_dw0[0x20];
3489};
3490
3491struct mlx5_ifc_query_issi_in_bits {
3492 u8 opcode[0x10];
3493 u8 reserved_0[0x10];
3494
3495 u8 reserved_1[0x10];
3496 u8 op_mod[0x10];
3497
3498 u8 reserved_2[0x40];
3499};
3500
3501struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3502 u8 status[0x8];
3503 u8 reserved_0[0x18];
3504
3505 u8 syndrome[0x20];
3506
3507 u8 reserved_1[0x40];
3508
3509 struct mlx5_ifc_pkey_bits pkey[0];
3510};
3511
3512struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3513 u8 opcode[0x10];
3514 u8 reserved_0[0x10];
3515
3516 u8 reserved_1[0x10];
3517 u8 op_mod[0x10];
3518
3519 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]3520 u8 reserved_2[0xb];
3521 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3522 u8 vport_number[0x10];
3523
3524 u8 reserved_3[0x10];
3525 u8 pkey_index[0x10];
3526};
3527
3528struct mlx5_ifc_query_hca_vport_gid_out_bits {
3529 u8 status[0x8];
3530 u8 reserved_0[0x18];
3531
3532 u8 syndrome[0x20];
3533
3534 u8 reserved_1[0x20];
3535
3536 u8 gids_num[0x10];
3537 u8 reserved_2[0x10];
3538
3539 struct mlx5_ifc_array128_auto_bits gid[0];
3540};
3541
3542struct mlx5_ifc_query_hca_vport_gid_in_bits {
3543 u8 opcode[0x10];
3544 u8 reserved_0[0x10];
3545
3546 u8 reserved_1[0x10];
3547 u8 op_mod[0x10];
3548
3549 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]3550 u8 reserved_2[0xb];
3551 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3552 u8 vport_number[0x10];
3553
3554 u8 reserved_3[0x10];
3555 u8 gid_index[0x10];
3556};
3557
3558struct mlx5_ifc_query_hca_vport_context_out_bits {
3559 u8 status[0x8];
3560 u8 reserved_0[0x18];
3561
3562 u8 syndrome[0x20];
3563
3564 u8 reserved_1[0x40];
3565
3566 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3567};
3568
3569struct mlx5_ifc_query_hca_vport_context_in_bits {
3570 u8 opcode[0x10];
3571 u8 reserved_0[0x10];
3572
3573 u8 reserved_1[0x10];
3574 u8 op_mod[0x10];
3575
3576 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]3577 u8 reserved_2[0xb];
3578 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3579 u8 vport_number[0x10];
3580
3581 u8 reserved_3[0x20];
3582};
3583
3584struct mlx5_ifc_query_hca_cap_out_bits {
3585 u8 status[0x8];
3586 u8 reserved_0[0x18];
3587
3588 u8 syndrome[0x20];
3589
3590 u8 reserved_1[0x40];
3591
3592 union mlx5_ifc_hca_cap_union_bits capability;
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3593};
3594
3595struct mlx5_ifc_query_hca_cap_in_bits {
3596 u8 opcode[0x10];
3597 u8 reserved_0[0x10];
3598
3599 u8 reserved_1[0x10];
3600 u8 op_mod[0x10];
3601
3602 u8 reserved_2[0x40];
3603};
3604
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3605struct mlx5_ifc_query_flow_table_out_bits {
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3606 u8 status[0x8];
3607 u8 reserved_0[0x18];
3608
3609 u8 syndrome[0x20];
3610
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3611 u8 reserved_1[0x80];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3612
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3613 u8 reserved_2[0x8];
3614 u8 level[0x8];
3615 u8 reserved_3[0x8];
3616 u8 log_size[0x8];
3617
3618 u8 reserved_4[0x120];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3619};
3620
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3621struct mlx5_ifc_query_flow_table_in_bits {
3622 u8 opcode[0x10];
3623 u8 reserved_0[0x10];
3624
3625 u8 reserved_1[0x10];
3626 u8 op_mod[0x10];
3627
3628 u8 reserved_2[0x40];
3629
3630 u8 table_type[0x8];
3631 u8 reserved_3[0x18];
3632
3633 u8 reserved_4[0x8];
3634 u8 table_id[0x18];
3635
3636 u8 reserved_5[0x140];
3637};
3638
3639struct mlx5_ifc_query_fte_out_bits {
3640 u8 status[0x8];
3641 u8 reserved_0[0x18];
3642
3643 u8 syndrome[0x20];
3644
3645 u8 reserved_1[0x1c0];
3646
3647 struct mlx5_ifc_flow_context_bits flow_context;
3648};
3649
3650struct mlx5_ifc_query_fte_in_bits {
3651 u8 opcode[0x10];
3652 u8 reserved_0[0x10];
3653
3654 u8 reserved_1[0x10];
3655 u8 op_mod[0x10];
3656
3657 u8 reserved_2[0x40];
3658
3659 u8 table_type[0x8];
3660 u8 reserved_3[0x18];
3661
3662 u8 reserved_4[0x8];
3663 u8 table_id[0x18];
3664
3665 u8 reserved_5[0x40];
3666
3667 u8 flow_index[0x20];
3668
3669 u8 reserved_6[0xe0];
3670};
3671
3672enum {
3673 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3674 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3675 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3676};
3677
3678struct mlx5_ifc_query_flow_group_out_bits {
3679 u8 status[0x8];
3680 u8 reserved_0[0x18];
3681
3682 u8 syndrome[0x20];
3683
3684 u8 reserved_1[0xa0];
3685
3686 u8 start_flow_index[0x20];
3687
3688 u8 reserved_2[0x20];
3689
3690 u8 end_flow_index[0x20];
3691
3692 u8 reserved_3[0xa0];
3693
3694 u8 reserved_4[0x18];
3695 u8 match_criteria_enable[0x8];
3696
3697 struct mlx5_ifc_fte_match_param_bits match_criteria;
3698
3699 u8 reserved_5[0xe00];
3700};
3701
3702struct mlx5_ifc_query_flow_group_in_bits {
3703 u8 opcode[0x10];
3704 u8 reserved_0[0x10];
3705
3706 u8 reserved_1[0x10];
3707 u8 op_mod[0x10];
3708
3709 u8 reserved_2[0x40];
3710
3711 u8 table_type[0x8];
3712 u8 reserved_3[0x18];
3713
3714 u8 reserved_4[0x8];
3715 u8 table_id[0x18];
3716
3717 u8 group_id[0x20];
3718
3719 u8 reserved_5[0x120];
3720};
3721
3722struct mlx5_ifc_query_eq_out_bits {
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]3723 u8 status[0x8];
3724 u8 reserved_0[0x18];
3725
3726 u8 syndrome[0x20];
3727
3728 u8 reserved_1[0x40];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]3729
3730 struct mlx5_ifc_eqc_bits eq_context_entry;
3731
3732 u8 reserved_2[0x40];
3733
3734 u8 event_bitmask[0x40];
3735
3736 u8 reserved_3[0x580];
3737
3738 u8 pas[0][0x40];
3739};
3740
3741struct mlx5_ifc_query_eq_in_bits {
3742 u8 opcode[0x10];
3743 u8 reserved_0[0x10];
3744
3745 u8 reserved_1[0x10];
3746 u8 op_mod[0x10];
3747
3748 u8 reserved_2[0x18];
3749 u8 eq_number[0x8];
3750
3751 u8 reserved_3[0x20];
3752};
3753
3754struct mlx5_ifc_query_dct_out_bits {
3755 u8 status[0x8];
3756 u8 reserved_0[0x18];
3757
3758 u8 syndrome[0x20];
3759
3760 u8 reserved_1[0x40];
3761
3762 struct mlx5_ifc_dctc_bits dct_context_entry;
3763
3764 u8 reserved_2[0x180];
3765};
3766
3767struct mlx5_ifc_query_dct_in_bits {
3768 u8 opcode[0x10];
3769 u8 reserved_0[0x10];
3770
3771 u8 reserved_1[0x10];
3772 u8 op_mod[0x10];
3773
3774 u8 reserved_2[0x8];
3775 u8 dctn[0x18];
3776
3777 u8 reserved_3[0x20];
3778};
3779
3780struct mlx5_ifc_query_cq_out_bits {
3781 u8 status[0x8];
3782 u8 reserved_0[0x18];
3783
3784 u8 syndrome[0x20];
3785
3786 u8 reserved_1[0x40];
3787
3788 struct mlx5_ifc_cqc_bits cq_context;
3789
3790 u8 reserved_2[0x600];
3791
3792 u8 pas[0][0x40];
3793};
3794
3795struct mlx5_ifc_query_cq_in_bits {
3796 u8 opcode[0x10];
3797 u8 reserved_0[0x10];
3798
3799 u8 reserved_1[0x10];
3800 u8 op_mod[0x10];
3801
3802 u8 reserved_2[0x8];
3803 u8 cqn[0x18];
3804
3805 u8 reserved_3[0x20];
3806};
3807
3808struct mlx5_ifc_query_cong_status_out_bits {
3809 u8 status[0x8];
3810 u8 reserved_0[0x18];
3811
3812 u8 syndrome[0x20];
3813
3814 u8 reserved_1[0x20];
3815
3816 u8 enable[0x1];
3817 u8 tag_enable[0x1];
3818 u8 reserved_2[0x1e];
3819};
3820
3821struct mlx5_ifc_query_cong_status_in_bits {
3822 u8 opcode[0x10];
3823 u8 reserved_0[0x10];
3824
3825 u8 reserved_1[0x10];
3826 u8 op_mod[0x10];
3827
3828 u8 reserved_2[0x18];
3829 u8 priority[0x4];
3830 u8 cong_protocol[0x4];
3831
3832 u8 reserved_3[0x20];
3833};
3834
3835struct mlx5_ifc_query_cong_statistics_out_bits {
3836 u8 status[0x8];
3837 u8 reserved_0[0x18];
3838
3839 u8 syndrome[0x20];
3840
3841 u8 reserved_1[0x40];
3842
3843 u8 cur_flows[0x20];
3844
3845 u8 sum_flows[0x20];
3846
3847 u8 cnp_ignored_high[0x20];
3848
3849 u8 cnp_ignored_low[0x20];
3850
3851 u8 cnp_handled_high[0x20];
3852
3853 u8 cnp_handled_low[0x20];
3854
3855 u8 reserved_2[0x100];
3856
3857 u8 time_stamp_high[0x20];
3858
3859 u8 time_stamp_low[0x20];
3860
3861 u8 accumulators_period[0x20];
3862
3863 u8 ecn_marked_roce_packets_high[0x20];
3864
3865 u8 ecn_marked_roce_packets_low[0x20];
3866
3867 u8 cnps_sent_high[0x20];
3868
3869 u8 cnps_sent_low[0x20];
3870
3871 u8 reserved_3[0x560];
3872};
3873
3874struct mlx5_ifc_query_cong_statistics_in_bits {
3875 u8 opcode[0x10];
3876 u8 reserved_0[0x10];
3877
3878 u8 reserved_1[0x10];
3879 u8 op_mod[0x10];
3880
3881 u8 clear[0x1];
3882 u8 reserved_2[0x1f];
3883
3884 u8 reserved_3[0x20];
3885};
3886
3887struct mlx5_ifc_query_cong_params_out_bits {
3888 u8 status[0x8];
3889 u8 reserved_0[0x18];
3890
3891 u8 syndrome[0x20];
3892
3893 u8 reserved_1[0x40];
3894
3895 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3896};
3897
3898struct mlx5_ifc_query_cong_params_in_bits {
3899 u8 opcode[0x10];
3900 u8 reserved_0[0x10];
3901
3902 u8 reserved_1[0x10];
3903 u8 op_mod[0x10];
3904
3905 u8 reserved_2[0x1c];
3906 u8 cong_protocol[0x4];
3907
3908 u8 reserved_3[0x20];
3909};
3910
3911struct mlx5_ifc_query_adapter_out_bits {
3912 u8 status[0x8];
3913 u8 reserved_0[0x18];
3914
3915 u8 syndrome[0x20];
3916
3917 u8 reserved_1[0x40];
3918
3919 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3920};
3921
3922struct mlx5_ifc_query_adapter_in_bits {
3923 u8 opcode[0x10];
3924 u8 reserved_0[0x10];
3925
3926 u8 reserved_1[0x10];
3927 u8 op_mod[0x10];
3928
3929 u8 reserved_2[0x40];
3930};
3931
3932struct mlx5_ifc_qp_2rst_out_bits {
3933 u8 status[0x8];
3934 u8 reserved_0[0x18];
3935
3936 u8 syndrome[0x20];
3937
3938 u8 reserved_1[0x40];
3939};
3940
3941struct mlx5_ifc_qp_2rst_in_bits {
3942 u8 opcode[0x10];
3943 u8 reserved_0[0x10];
3944
3945 u8 reserved_1[0x10];
3946 u8 op_mod[0x10];
3947
3948 u8 reserved_2[0x8];
3949 u8 qpn[0x18];
3950
3951 u8 reserved_3[0x20];
3952};
3953
3954struct mlx5_ifc_qp_2err_out_bits {
3955 u8 status[0x8];
3956 u8 reserved_0[0x18];
3957
3958 u8 syndrome[0x20];
3959
3960 u8 reserved_1[0x40];
3961};
3962
3963struct mlx5_ifc_qp_2err_in_bits {
3964 u8 opcode[0x10];
3965 u8 reserved_0[0x10];
3966
3967 u8 reserved_1[0x10];
3968 u8 op_mod[0x10];
3969
3970 u8 reserved_2[0x8];
3971 u8 qpn[0x18];
3972
3973 u8 reserved_3[0x20];
3974};
3975
3976struct mlx5_ifc_page_fault_resume_out_bits {
3977 u8 status[0x8];
3978 u8 reserved_0[0x18];
3979
3980 u8 syndrome[0x20];
3981
3982 u8 reserved_1[0x40];
3983};
3984
3985struct mlx5_ifc_page_fault_resume_in_bits {
3986 u8 opcode[0x10];
3987 u8 reserved_0[0x10];
3988
3989 u8 reserved_1[0x10];
3990 u8 op_mod[0x10];
3991
3992 u8 error[0x1];
3993 u8 reserved_2[0x4];
3994 u8 rdma[0x1];
3995 u8 read_write[0x1];
3996 u8 req_res[0x1];
3997 u8 qpn[0x18];
3998
3999 u8 reserved_3[0x20];
4000};
4001
4002struct mlx5_ifc_nop_out_bits {
4003 u8 status[0x8];
4004 u8 reserved_0[0x18];
4005
4006 u8 syndrome[0x20];
4007
4008 u8 reserved_1[0x40];
4009};
4010
4011struct mlx5_ifc_nop_in_bits {
4012 u8 opcode[0x10];
4013 u8 reserved_0[0x10];
4014
4015 u8 reserved_1[0x10];
4016 u8 op_mod[0x10];
4017
4018 u8 reserved_2[0x40];
4019};
4020
4021struct mlx5_ifc_modify_vport_state_out_bits {
4022 u8 status[0x8];
4023 u8 reserved_0[0x18];
4024
4025 u8 syndrome[0x20];
4026
4027 u8 reserved_1[0x40];
4028};
4029
4030struct mlx5_ifc_modify_vport_state_in_bits {
4031 u8 opcode[0x10];
4032 u8 reserved_0[0x10];
4033
4034 u8 reserved_1[0x10];
4035 u8 op_mod[0x10];
4036
4037 u8 other_vport[0x1];
4038 u8 reserved_2[0xf];
4039 u8 vport_number[0x10];
4040
4041 u8 reserved_3[0x18];
4042 u8 admin_state[0x4];
4043 u8 reserved_4[0x4];
4044};
4045
4046struct mlx5_ifc_modify_tis_out_bits {
4047 u8 status[0x8];
4048 u8 reserved_0[0x18];
4049
4050 u8 syndrome[0x20];
4051
4052 u8 reserved_1[0x40];
4053};
4054
majd@mellanox.com75850d02016-01-14 19:13:06 +0200[diff] [blame^]4055struct mlx5_ifc_modify_tis_bitmask_bits {
4056 u8 reserved_0[0x20];
4057
4058 u8 reserved_1[0x1f];
4059 u8 prio[0x1];
4060};
4061
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4062struct mlx5_ifc_modify_tis_in_bits {
4063 u8 opcode[0x10];
4064 u8 reserved_0[0x10];
4065
4066 u8 reserved_1[0x10];
4067 u8 op_mod[0x10];
4068
4069 u8 reserved_2[0x8];
4070 u8 tisn[0x18];
4071
4072 u8 reserved_3[0x20];
4073
majd@mellanox.com75850d02016-01-14 19:13:06 +0200[diff] [blame^]4074 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4075
4076 u8 reserved_4[0x40];
4077
4078 struct mlx5_ifc_tisc_bits ctx;
4079};
4080
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4081struct mlx5_ifc_modify_tir_bitmask_bits {
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]4082 u8 reserved_0[0x20];
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4083
Tariq Toukan66189962015-11-12 19:35:26 +0200[diff] [blame]4084 u8 reserved_1[0x1b];
4085 u8 self_lb_en[0x1];
4086 u8 reserved_2[0x3];
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4087 u8 lro[0x1];
4088};
4089
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4090struct mlx5_ifc_modify_tir_out_bits {
4091 u8 status[0x8];
4092 u8 reserved_0[0x18];
4093
4094 u8 syndrome[0x20];
4095
4096 u8 reserved_1[0x40];
4097};
4098
4099struct mlx5_ifc_modify_tir_in_bits {
4100 u8 opcode[0x10];
4101 u8 reserved_0[0x10];
4102
4103 u8 reserved_1[0x10];
4104 u8 op_mod[0x10];
4105
4106 u8 reserved_2[0x8];
4107 u8 tirn[0x18];
4108
4109 u8 reserved_3[0x20];
4110
Achiad Shochatd9eea402015-08-04 14:05:42 +0300[diff] [blame]4111 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4112
4113 u8 reserved_4[0x40];
4114
4115 struct mlx5_ifc_tirc_bits ctx;
4116};
4117
4118struct mlx5_ifc_modify_sq_out_bits {
4119 u8 status[0x8];
4120 u8 reserved_0[0x18];
4121
4122 u8 syndrome[0x20];
4123
4124 u8 reserved_1[0x40];
4125};
4126
4127struct mlx5_ifc_modify_sq_in_bits {
4128 u8 opcode[0x10];
4129 u8 reserved_0[0x10];
4130
4131 u8 reserved_1[0x10];
4132 u8 op_mod[0x10];
4133
4134 u8 sq_state[0x4];
4135 u8 reserved_2[0x4];
4136 u8 sqn[0x18];
4137
4138 u8 reserved_3[0x20];
4139
4140 u8 modify_bitmask[0x40];
4141
4142 u8 reserved_4[0x40];
4143
4144 struct mlx5_ifc_sqc_bits ctx;
4145};
4146
4147struct mlx5_ifc_modify_rqt_out_bits {
4148 u8 status[0x8];
4149 u8 reserved_0[0x18];
4150
4151 u8 syndrome[0x20];
4152
4153 u8 reserved_1[0x40];
4154};
4155
Achiad Shochat5c503682015-08-04 14:05:43 +0300[diff] [blame]4156struct mlx5_ifc_rqt_bitmask_bits {
4157 u8 reserved[0x20];
4158
4159 u8 reserved1[0x1f];
4160 u8 rqn_list[0x1];
4161};
4162
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4163struct mlx5_ifc_modify_rqt_in_bits {
4164 u8 opcode[0x10];
4165 u8 reserved_0[0x10];
4166
4167 u8 reserved_1[0x10];
4168 u8 op_mod[0x10];
4169
4170 u8 reserved_2[0x8];
4171 u8 rqtn[0x18];
4172
4173 u8 reserved_3[0x20];
4174
Achiad Shochat5c503682015-08-04 14:05:43 +0300[diff] [blame]4175 struct mlx5_ifc_rqt_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4176
4177 u8 reserved_4[0x40];
4178
4179 struct mlx5_ifc_rqtc_bits ctx;
4180};
4181
4182struct mlx5_ifc_modify_rq_out_bits {
4183 u8 status[0x8];
4184 u8 reserved_0[0x18];
4185
4186 u8 syndrome[0x20];
4187
4188 u8 reserved_1[0x40];
4189};
4190
4191struct mlx5_ifc_modify_rq_in_bits {
4192 u8 opcode[0x10];
4193 u8 reserved_0[0x10];
4194
4195 u8 reserved_1[0x10];
4196 u8 op_mod[0x10];
4197
4198 u8 rq_state[0x4];
4199 u8 reserved_2[0x4];
4200 u8 rqn[0x18];
4201
4202 u8 reserved_3[0x20];
4203
4204 u8 modify_bitmask[0x40];
4205
4206 u8 reserved_4[0x40];
4207
4208 struct mlx5_ifc_rqc_bits ctx;
4209};
4210
4211struct mlx5_ifc_modify_rmp_out_bits {
4212 u8 status[0x8];
4213 u8 reserved_0[0x18];
4214
4215 u8 syndrome[0x20];
4216
4217 u8 reserved_1[0x40];
4218};
4219
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]4220struct mlx5_ifc_rmp_bitmask_bits {
4221 u8 reserved[0x20];
4222
4223 u8 reserved1[0x1f];
4224 u8 lwm[0x1];
4225};
4226
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4227struct mlx5_ifc_modify_rmp_in_bits {
4228 u8 opcode[0x10];
4229 u8 reserved_0[0x10];
4230
4231 u8 reserved_1[0x10];
4232 u8 op_mod[0x10];
4233
4234 u8 rmp_state[0x4];
4235 u8 reserved_2[0x4];
4236 u8 rmpn[0x18];
4237
4238 u8 reserved_3[0x20];
4239
Haggai Abramonvsky01949d02015-06-04 19:30:38 +0300[diff] [blame]4240 struct mlx5_ifc_rmp_bitmask_bits bitmask;
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4241
4242 u8 reserved_4[0x40];
4243
4244 struct mlx5_ifc_rmpc_bits ctx;
4245};
4246
4247struct mlx5_ifc_modify_nic_vport_context_out_bits {
4248 u8 status[0x8];
4249 u8 reserved_0[0x18];
4250
4251 u8 syndrome[0x20];
4252
4253 u8 reserved_1[0x40];
4254};
4255
4256struct mlx5_ifc_modify_nic_vport_field_select_bits {
4257 u8 reserved_0[0x1c];
4258 u8 permanent_address[0x1];
4259 u8 addresses_list[0x1];
4260 u8 roce_en[0x1];
4261 u8 reserved_1[0x1];
4262};
4263
4264struct mlx5_ifc_modify_nic_vport_context_in_bits {
4265 u8 opcode[0x10];
4266 u8 reserved_0[0x10];
4267
4268 u8 reserved_1[0x10];
4269 u8 op_mod[0x10];
4270
4271 u8 other_vport[0x1];
4272 u8 reserved_2[0xf];
4273 u8 vport_number[0x10];
4274
4275 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4276
4277 u8 reserved_3[0x780];
4278
4279 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4280};
4281
4282struct mlx5_ifc_modify_hca_vport_context_out_bits {
4283 u8 status[0x8];
4284 u8 reserved_0[0x18];
4285
4286 u8 syndrome[0x20];
4287
4288 u8 reserved_1[0x40];
4289};
4290
4291struct mlx5_ifc_modify_hca_vport_context_in_bits {
4292 u8 opcode[0x10];
4293 u8 reserved_0[0x10];
4294
4295 u8 reserved_1[0x10];
4296 u8 op_mod[0x10];
4297
4298 u8 other_vport[0x1];
Majd Dibbiny707c4602015-06-04 19:30:41 +0300[diff] [blame]4299 u8 reserved_2[0xb];
4300 u8 port_num[0x4];
Saeed Mahameede2816822015-05-28 22:28:40 +0300[diff] [blame]4301 u8 vport_number[0x10];
4302
4303 u8 reserved_3[0x20];
4304
4305 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4306};
4307
4308struct mlx5_ifc_modify_cq_out_bits {
4309 u8 status[0x8];
4310 u8 reserved_0[0x18];
4311
4312 u8 syndrome[0x20];
4313
4314 u8 reserved_1[0x40];
4315};
4316
4317enum {
4318 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4319 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4320};
4321
4322struct mlx5_ifc_modify_cq_in_bits {
4323 u8 opcode[0x10];
4324 u8 reserved_0[0x10];
4325
4326 u8 reserved_1[0x10];
4327 u8 op_mod[0x10];
4328
4329 u8 reserved_2[0x8];
4330 u8 cqn[0x18];
4331
4332 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4333
4334 struct mlx5_ifc_cqc_bits cq_context;
4335
4336 u8 reserved_3[0x600];
4337
4338 u8 pas[0][0x40];
4339};
4340
4341struct mlx5_ifc_modify_cong_status_out_bits {
4342 u8 status[0x8];
4343 u8 reserved_0[0x18];
4344
4345 u8 syndrome[0x20];
4346
4347 u8 reserved_1[0x40];
4348};
4349
4350struct mlx5_ifc_modify_cong_status_in_bits {
4351 u8 opcode[0x10];
4352 u8 reserved_0[0x10];
4353
4354 u8 reserved_1[0x10];
4355 u8 op_mod[0x10];
4356
4357 u8 reserved_2[0x18];
4358 u8 priority[0x4];
4359 u8 cong_protocol[0x4];
4360
4361 u8 enable[0x1];
4362 u8 tag_enable[0x1];
4363 u8 reserved_3[0x1e];
4364};
4365
4366struct mlx5_ifc_modify_cong_params_out_bits {
4367 u8 status[0x8];
4368 u8 reserved_0[0x18];
4369
4370 u8 syndrome[0x20];
4371
4372 u8 reserved_1[0x40];
4373};
4374
4375struct mlx5_ifc_modify_cong_params_in_bits {
4376 u8 opcode[0x10];
4377 u8 reserved_0[0x10];
4378
4379 u8 reserved_1[0x10];
4380 u8 op_mod[0x10];
4381
4382 u8 reserved_2[0x1c];
4383 u8 cong_protocol[0x4];
4384
4385 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4386
4387 u8 reserved_3[0x80];
4388
4389 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4390};
4391
4392struct mlx5_ifc_manage_pages_out_bits {
4393 u8 status[0x8];
4394 u8 reserved_0[0x18];
4395
4396 u8 syndrome[0x20];
4397
4398 u8 output_num_entries[0x20];
4399
4400 u8 reserved_1[0x20];
4401
4402 u8 pas[0][0x40];
4403};
4404
4405enum {
4406 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4407 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4408 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4409};
4410
4411struct mlx5_ifc_manage_pages_in_bits {
4412 u8 opcode[0x10];
4413 u8 reserved_0[0x10];
4414
4415 u8 reserved_1[0x10];
4416 u8 op_mod[0x10];
4417
4418 u8 reserved_2[0x10];
4419 u8 function_id[0x10];
4420
4421 u8 input_num_entries[0x20];
4422
4423 u8 pas[0][0x40];
4424};
4425
4426struct mlx5_ifc_mad_ifc_out_bits {
4427 u8 status[0x8];
4428 u8 reserved_0[0x18];
4429
4430 u8 syndrome[0x20];
4431
4432 u8 reserved_1[0x40];
4433
4434 u8 response_mad_packet[256][0x8];
4435};
4436
4437struct mlx5_ifc_mad_ifc_in_bits {
4438 u8 opcode[0x10];
4439 u8 reserved_0[0x10];
4440
4441 u8 reserved_1[0x10];
4442 u8 op_mod[0x10];
4443
4444 u8 remote_lid[0x10];
4445 u8 reserved_2[0x8];
4446 u8 port[0x8];
4447
4448 u8 reserved_3[0x20];
4449
4450 u8 mad[256][0x8];
4451};
4452
4453struct mlx5_ifc_init_hca_out_bits {
4454 u8 status[0x8];
4455 u8 reserved_0[0x18];
4456
4457 u8 syndrome[0x20];
4458
4459 u8 reserved_1[0x40];
4460};
4461
4462struct mlx5_ifc_init_hca_in_bits {
4463 u8 opcode[0x10];
4464 u8 reserved_0[0x10];
4465
4466 u8 reserved_1[0x10];
4467 u8 op_mod[0x10];
4468
4469 u8 reserved_2[0x40];
4470};
4471
4472struct mlx5_ifc_init2rtr_qp_out_bits {
4473 u8 status[0x8];
4474 u8 reserved_0[0x18];
4475
4476 u8 syndrome[0x20];
4477
4478 u8 reserved_1[0x40];
4479};
4480
4481struct mlx5_ifc_init2rtr_qp_in_bits {
4482 u8 opcode[0x10];
4483 u8 reserved_0[0x10];
4484
4485 u8 reserved_1[0x10];
4486 u8 op_mod[0x10];
4487
4488 u8 reserved_2[0x8];
4489 u8 qpn[0x18];
4490
4491 u8 reserved_3[0x20];
4492
4493 u8 opt_param_mask[0x20];
4494
4495 u8 reserved_4[0x20];
4496
4497 struct mlx5_ifc_qpc_bits qpc;
4498
4499 u8 reserved_5[0x80];
4500};
4501
4502struct mlx5_ifc_init2init_qp_out_bits {
4503 u8 status[0x8];
4504 u8 reserved_0[0x18];
4505
4506 u8 syndrome[0x20];
4507
4508 u8 reserved_1[0x40];
4509};
4510
4511struct mlx5_ifc_init2init_qp_in_bits {
4512 u8 opcode[0x10];
4513 u8 reserved_0[0x10];
4514
4515 u8 reserved_1[0x10];
4516 u8 op_mod[0x10];
4517
4518 u8 reserved_2[0x8];
4519 u8 qpn[0x18];
4520
4521 u8 reserved_3[0x20];
4522
4523 u8 opt_param_mask[0x20];
4524
4525 u8 reserved_4[0x20];
4526
4527 struct mlx5_ifc_qpc_bits qpc;
4528
4529 u8 reserved_5[0x80];
4530};
4531
4532struct mlx5_ifc_get_dropped_packet_log_out_bits {
4533 u8 status[0x8];
4534 u8 reserved_0[0x18];
4535
4536 u8 syndrome[0x20];
4537
4538 u8 reserved_1[0x40];
4539
4540 u8 packet_headers_log[128][0x8];
4541
4542 u8 packet_syndrome[64][0x8];
4543};
4544
4545struct mlx5_ifc_get_dropped_packet_log_in_bits {
4546 u8 opcode[0x10];
4547 u8 reserved_0[0x10];
4548
4549 u8 reserved_1[0x10];
4550 u8 op_mod[0x10];
4551
4552 u8 reserved_2[0x40];
4553};
4554
4555struct mlx5_ifc_gen_eqe_in_bits {
4556 u8 opcode[0x10];
4557 u8 reserved_0[0x10];
4558
4559 u8 reserved_1[0x10];
4560 u8 op_mod[0x10];
4561
4562 u8 reserved_2[0x18];
4563 u8 eq_number[0x8];
4564
4565 u8 reserved_3[0x20];
4566
4567 u8 eqe[64][0x8];
4568};
4569
4570struct mlx5_ifc_gen_eq_out_bits {
4571 u8 status[0x8];
4572 u8 reserved_0[0x18];
4573
4574 u8 syndrome[0x20];
4575
4576 u8 reserved_1[0x40];
4577};
4578
4579struct mlx5_ifc_enable_hca_out_bits {
4580 u8 status[0x8];
4581 u8 reserved_0[0x18];
4582
4583 u8 syndrome[0x20];
4584
4585 u8 reserved_1[0x20];
4586};
4587
4588struct mlx5_ifc_enable_hca_in_bits {
4589 u8 opcode[0x10];
4590 u8 reserved_0[0x10];
4591
4592 u8 reserved_1[0x10];
4593 u8 op_mod[0x10];
4594
4595 u8 reserved_2[0x10];
4596 u8 function_id[0x10];
4597
4598 u8 reserved_3[0x20];
4599};
4600
4601struct mlx5_ifc_drain_dct_out_bits {
4602 u8 status[0x8];
4603 u8 reserved_0[0x18];
4604
4605 u8 syndrome[0x20];
4606
4607 u8 reserved_1[0x40];
4608};
4609
4610struct mlx5_ifc_drain_dct_in_bits {
4611 u8 opcode[0x10];
4612 u8 reserved_0[0x10];
4613
4614 u8 reserved_1[0x10];
4615 u8 op_mod[0x10];
4616
4617 u8 reserved_2[0x8];
4618 u8 dctn[0x18];
4619
4620 u8 reserved_3[0x20];
4621};
4622
4623struct mlx5_ifc_disable_hca_out_bits {
4624 u8 status[0x8];
4625 u8 reserved_0[0x18];
4626
4627 u8 syndrome[0x20];
4628
4629 u8 reserved_1[0x20];
4630};
4631
4632struct mlx5_ifc_disable_hca_in_bits {
4633 u8 opcode[0x10];
4634 u8 reserved_0[0x10];
4635
4636 u8 reserved_1[0x10];
4637 u8 op_mod[0x10];
4638
4639 u8 reserved_2[0x10];
4640 u8 function_id[0x10];
4641
4642 u8 reserved_3[0x20];
4643};
4644
4645struct mlx5_ifc_detach_from_mcg_out_bits {
4646 u8 status[0x8];
4647 u8 reserved_0[0x18];
4648
4649 u8 syndrome[0x20];
4650
4651 u8 reserved_1[0x40];
4652};
4653
4654struct mlx5_ifc_detach_from_mcg_in_bits {
4655 u8 opcode[0x10];
4656 u8 reserved_0[0x10];
4657
4658 u8 reserved_1[0x10];
4659 u8 op_mod[0x10];
4660
4661 u8 reserved_2[0x8];
4662 u8 qpn[0x18];
4663
4664 u8 reserved_3[0x20];
4665
4666 u8 multicast_gid[16][0x8];
4667};
4668
4669struct mlx5_ifc_destroy_xrc_srq_out_bits {
4670 u8 status[0x8];
4671 u8 reserved_0[0x18];
4672
4673 u8 syndrome[0x20];
4674
4675 u8 reserved_1[0x40];
4676};
4677
4678struct mlx5_ifc_destroy_xrc_srq_in_bits {
4679 u8 opcode[0x10];
4680 u8 reserved_0[0x10];
4681
4682 u8 reserved_1[0x10];
4683 u8 op_mod[0x10];
4684
4685 u8 reserved_2[0x8];
4686 u8 xrc_srqn[0x18];
4687
4688 u8 reserved_3[0x20];
4689};
4690
4691struct mlx5_ifc_destroy_tis_out_bits {
4692 u8 status[0x8];
4693 u8 reserved_0[0x18];
4694
4695 u8 syndrome[0x20];
4696
4697 u8 reserved_1[0x40];
4698};
4699
4700struct mlx5_ifc_destroy_tis_in_bits {
4701 u8 opcode[0x10];
4702 u8 reserved_0[0x10];
4703
4704 u8 reserved_1[0x10];
4705 u8 op_mod[0x10];
4706
4707 u8 reserved_2[0x8];
4708 u8 tisn[0x18];
4709
4710 u8 reserved_3[0x20];
4711};
4712
4713struct mlx5_ifc_destroy_tir_out_bits {
4714 u8 status[0x8];
4715 u8 reserved_0[0x18];
4716
4717 u8 syndrome[0x20];
4718
4719 u8 reserved_1[0x40];
4720};
4721
4722struct mlx5_ifc_destroy_tir_in_bits {
4723 u8 opcode[0x10];
4724 u8 reserved_0[0x10];
4725
4726 u8 reserved_1[0x10];
4727 u8 op_mod[0x10];
4728
4729 u8 reserved_2[0x8];
4730 u8 tirn[0x18];
4731
4732 u8 reserved_3[0x20];
4733};
4734
4735struct mlx5_ifc_destroy_srq_out_bits {
4736 u8 status[0x8];
4737 u8 reserved_0[0x18];
4738
4739 u8 syndrome[0x20];
4740
4741 u8 reserved_1[0x40];
4742};
4743
4744struct mlx5_ifc_destroy_srq_in_bits {
4745 u8 opcode[0x10];
4746 u8 reserved_0[0x10];
4747
4748 u8 reserved_1[0x10];
4749 u8 op_mod[0x10];
4750
4751 u8 reserved_2[0x8];
4752 u8 srqn[0x18];
4753
4754 u8 reserved_3[0x20];
4755};
4756
4757struct mlx5_ifc_destroy_sq_out_bits {
4758 u8 status[0x8];
4759 u8 reserved_0[0x18];
4760
4761 u8 syndrome[0x20];
4762
4763 u8 reserved_1[0x40];
4764};
4765
4766struct mlx5_ifc_destroy_sq_in_bits {
4767 u8 opcode[0x10];
4768 u8 reserved_0[0x10];
4769
4770 u8 reserved_1[0x10];
4771 u8 op_mod[0x10];
4772
4773 u8 reserved_2[0x8];
4774 u8 sqn[0x18];
4775
4776 u8 reserved_3[0x20];
4777};
4778
4779struct mlx5_ifc_destroy_rqt_out_bits {
4780 u8 status[0x8];
4781 u8 reserved_0[0x18];
4782
4783 u8 syndrome[0x20];
4784
4785 u8 reserved_1[0x40];
4786};
4787
4788struct mlx5_ifc_destroy_rqt_in_bits {
4789 u8 opcode[0x10];
4790 u8 reserved_0[0x10];
4791
4792 u8 reserved_1[0x10];
4793 u8 op_mod[0x10];
4794
4795 u8 reserved_2[0x8];
4796 u8 rqtn[0x18];
4797
4798 u8 reserved_3[0x20];
4799};
4800
4801struct mlx5_ifc_destroy_rq_out_bits {
4802 u8 status[0x8];
4803 u8 reserved_0[0x18];
4804
4805 u8 syndrome[0x20];
4806
4807 u8 reserved_1[0x40];
4808};
4809
4810struct mlx5_ifc_destroy_rq_in_bits {
4811 u8 opcode[0x10];
4812 u8 reserved_0[0x10];
4813
4814 u8 reserved_1[0x10];
4815 u8 op_mod[0x10];
4816
4817 u8 reserved_2[0x8];
4818 u8 rqn[0x18];
4819
4820 u8 reserved_3[0x20];
4821};
4822
4823struct mlx5_ifc_destroy_rmp_out_bits {
4824 u8 status[0x8];
4825 u8 reserved_0[0x18];
4826
4827 u8 syndrome[0x20];
4828
4829 u8 reserved_1[0x40];
4830};
4831
4832struct mlx5_ifc_destroy_rmp_in_bits {
4833 u8 opcode[0x10];
4834 u8 reserved_0[0x10];
4835
4836 u8 reserved_1[0x10];
4837 u8 op_mod[0x10];
4838
4839 u8 reserved_2[0x8];
4840 u8 rmpn[0x18];
4841
4842 u8 reserved_3[0x20];
4843};
4844
4845struct mlx5_ifc_destroy_qp_out_bits {
4846 u8 status[0x8];
4847 u8 reserved_0[0x18];
4848
4849 u8 syndrome[0x20];
4850
4851 u8 reserved_1[0x40];
4852};
4853
4854struct mlx5_ifc_destroy_qp_in_bits {
4855 u8 opcode[0x10];
4856 u8 reserved_0[0x10];
4857
4858 u8 reserved_1[0x10];
4859 u8 op_mod[0x10];
4860
4861 u8 reserved_2[0x8];
4862 u8 qpn[0x18];
4863
4864 u8 reserved_3[0x20];
4865};
4866
4867struct mlx5_ifc_destroy_psv_out_bits {
4868 u8 status[0x8];
4869 u8 reserved_0[0x18];
4870
4871 u8 syndrome[0x20];
4872
4873 u8 reserved_1[0x40];
4874};
4875
4876struct mlx5_ifc_destroy_psv_in_bits {
4877 u8 opcode[0x10];
4878 u8 reserved_0[0x10];
4879
4880 u8 reserved_1[0x10];
4881 u8 op_mod[0x10];
4882
4883 u8 reserved_2[0x8];
4884 u8 psvn[0x18];
4885
4886 u8 reserved_3[0x20];
4887};
4888
4889struct mlx5_ifc_destroy_mkey_out_bits {
4890 u8 status[0x8];
4891 u8 reserved_0[0x18];
4892
4893 u8 syndrome[0x20];
4894
4895 u8 reserved_1[0x40];
4896};
4897
4898struct mlx5_ifc_destroy_mkey_in_bits {
4899 u8 opcode[0x10];
4900 u8 reserved_0[0x10];
4901
4902 u8 reserved_1[0x10];
4903 u8 op_mod[0x10];
4904
4905 u8 reserved_2[0x8];
4906 u8 mkey_index[0x18];
4907
4908 u8 reserved_3[0x20];
4909};
4910
4911struct mlx5_ifc_destroy_flow_table_out_bits {
4912 u8 status[0x8];
4913 u8 reserved_0[0x18];
4914
4915 u8 syndrome[0x20];
4916
4917 u8 reserved_1[0x40];
4918};
4919
4920struct mlx5_ifc_destroy_flow_table_in_bits {
4921 u8 opcode[0x10];
4922 u8 reserved_0[0x10];
4923
4924 u8 reserved_1[0x10];
4925 u8 op_mod[0x10];
4926
4927 u8 reserved_2[0x40];
4928
4929 u8 table_type[0x8];
4930 u8 reserved_3[0x18];
4931
4932 u8 reserved_4[0x8];
4933 u8 table_id[0x18];
4934
4935 u8 reserved_5[0x140];
4936};
4937
4938struct mlx5_ifc_destroy_flow_group_out_bits {
4939 u8 status[0x8];
4940 u8 reserved_0[0x18];
4941
4942 u8 syndrome[0x20];
4943
4944 u8 reserved_1[0x40];
4945};
4946
4947struct mlx5_ifc_destroy_flow_group_in_bits {
4948 u8 opcode[0x10];
4949 u8 reserved_0[0x10];
4950
4951 u8 reserved_1[0x10];
4952 u8 op_mod[0x10];
4953
4954 u8 reserved_2[0x40];
4955
4956 u8 table_type[0x8];
4957 u8 reserved_3[0x18];
4958
4959 u8 reserved_4[0x8];
4960 u8 table_id[0x18];
4961
4962 u8 group_id[0x20];
4963
4964 u8 reserved_5[0x120];
4965};
4966
4967struct mlx5_ifc_destroy_eq_out_bits {
4968 u8 status[0x8];
4969 u8 reserved_0[0x18];
4970
4971 u8 syndrome[0x20];
4972
4973 u8 reserved_1[0x40];
4974};
4975
4976struct mlx5_ifc_destroy_eq_in_bits {
4977 u8 opcode[0x10];
4978 u8 reserved_0[0x10];
4979
4980 u8 reserved_1[0x10];
4981 u8 op_mod[0x10];
4982
4983 u8 reserved_2[0x18];
4984 u8 eq_number[0x8];
4985
4986 u8 reserved_3[0x20];
4987};
4988
4989struct mlx5_ifc_destroy_dct_out_bits {
4990 u8 status[0x8];
4991 u8 reserved_0[0x18];
4992
4993 u8 syndrome[0x20];
4994
4995 u8 reserved_1[0x40];
4996};
4997
4998struct mlx5_ifc_destroy_dct_in_bits {
4999 u8 opcode[0x10];
5000 u8 reserved_0[0x10];
5001
5002 u8 reserved_1[0x10];
5003 u8 op_mod[0x10];
5004
5005 u8 reserved_2[0x8];
5006 u8 dctn[0x18];
5007
5008 u8 reserved_3[0x20];
5009};
5010
5011struct mlx5_ifc_destroy_cq_out_bits {
5012 u8 status[0x8];
5013 u8 reserved_0[0x18];
5014
5015 u8 syndrome[0x20];
5016
5017 u8 reserved_1[0x40];
5018};
5019
5020struct mlx5_ifc_destroy_cq_in_bits {
5021 u8 opcode[0x10];
5022 u8 reserved_0[0x10];
5023
5024 u8 reserved_1[0x10];
5025 u8 op_mod[0x10];
5026
5027 u8 reserved_2[0x8];
5028 u8 cqn[0x18];
5029
5030 u8 reserved_3[0x20];
5031};
5032
5033struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5034 u8 status[0x8];
5035 u8 reserved_0[0x18];
5036
5037 u8 syndrome[0x20];
5038
5039 u8 reserved_1[0x40];
5040};
5041
5042struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5043 u8 opcode[0x10];
5044 u8 reserved_0[0x10];
5045
5046 u8 reserved_1[0x10];
5047 u8 op_mod[0x10];
5048
5049 u8 reserved_2[0x20];
5050
5051 u8 reserved_3[0x10];
5052 u8 vxlan_udp_port[0x10];
5053};
5054
5055struct mlx5_ifc_delete_l2_table_entry_out_bits {
5056 u8 status[0x8];
5057 u8 reserved_0[0x18];
5058
5059 u8 syndrome[0x20];
5060
5061 u8 reserved_1[0x40];
5062};
5063
5064struct mlx5_ifc_delete_l2_table_entry_in_bits {
5065 u8 opcode[0x10];
5066 u8 reserved_0[0x10];
5067
5068 u8 reserved_1[0x10];
5069 u8 op_mod[0x10];
5070
5071 u8 reserved_2[0x60];
5072
5073 u8 reserved_3[0x8];
5074 u8 table_index[0x18];
5075
5076 u8 reserved_4[0x140];
5077};
5078
5079struct mlx5_ifc_delete_fte_out_bits {
5080 u8 status[0x8];
5081 u8 reserved_0[0x18];
5082
5083 u8 syndrome[0x20];
5084
5085 u8 reserved_1[0x40];
5086};
5087
5088struct mlx5_ifc_delete_fte_in_bits {
5089 u8 opcode[0x10];
5090 u8 reserved_0[0x10];
5091
5092 u8 reserved_1[0x10];
5093 u8 op_mod[0x10];
5094
5095 u8 reserved_2[0x40];
5096
5097 u8 table_type[0x8];
5098 u8 reserved_3[0x18];
5099
5100 u8 reserved_4[0x8];
5101 u8 table_id[0x18];
5102
5103 u8 reserved_5[0x40];
5104
5105 u8 flow_index[0x20];
5106
5107 u8 reserved_6[0xe0];
5108};
5109
5110struct mlx5_ifc_dealloc_xrcd_out_bits {
5111 u8 status[0x8];
5112 u8 reserved_0[0x18];
5113
5114 u8 syndrome[0x20];
5115
5116 u8 reserved_1[0x40];
5117};
5118
5119struct mlx5_ifc_dealloc_xrcd_in_bits {
5120 u8 opcode[0x10];
5121 u8 reserved_0[0x10];
5122
5123 u8 reserved_1[0x10];
5124 u8 op_mod[0x10];
5125
5126 u8 reserved_2[0x8];
5127 u8 xrcd[0x18];
5128
5129 u8 reserved_3[0x20];
5130};
5131
5132struct mlx5_ifc_dealloc_uar_out_bits {
5133 u8 status[0x8];
5134 u8 reserved_0[0x18];
5135
5136 u8 syndrome[0x20];
5137
5138 u8 reserved_1[0x40];
5139};
5140
5141struct mlx5_ifc_dealloc_uar_in_bits {
5142 u8 opcode[0x10];
5143 u8 reserved_0[0x10];
5144
5145 u8 reserved_1[0x10];
5146 u8 op_mod[0x10];
5147
5148 u8 reserved_2[0x8];
5149 u8 uar[0x18];
5150
5151 u8 reserved_3[0x20];
5152};
5153
5154struct mlx5_ifc_dealloc_transport_domain_out_bits {
5155 u8 status[0x8];
5156 u8 reserved_0[0x18];
5157
5158 u8 syndrome[0x20];
5159
5160 u8 reserved_1[0x40];
5161};
5162
5163struct mlx5_ifc_dealloc_transport_domain_in_bits {
5164 u8 opcode[0x10];
5165 u8 reserved_0[0x10];
5166
5167 u8 reserved_1[0x10];
5168 u8 op_mod[0x10];
5169
5170 u8 reserved_2[0x8];
5171 u8 transport_domain[0x18];
5172
5173 u8 reserved_3[0x20];
5174};
5175
5176struct mlx5_ifc_dealloc_q_counter_out_bits {
5177 u8 status[0x8];
5178 u8 reserved_0[0x18];
5179
5180 u8 syndrome[0x20];
5181
5182 u8 reserved_1[0x40];
5183};
5184
5185struct mlx5_ifc_dealloc_q_counter_in_bits {
5186 u8 opcode[0x10];
5187 u8 reserved_0[0x10];
5188
5189 u8 reserved_1[0x10];
5190 u8 op_mod[0x10];
5191
5192 u8 reserved_2[0x18];
5193 u8 counter_set_id[0x8];
5194
5195 u8 reserved_3[0x20];
5196};
5197
5198struct mlx5_ifc_dealloc_pd_out_bits {
5199 u8 status[0x8];
5200 u8 reserved_0[0x18];
5201
5202 u8 syndrome[0x20];
5203
5204 u8 reserved_1[0x40];
5205};
5206
5207struct mlx5_ifc_dealloc_pd_in_bits {
5208 u8 opcode[0x10];
5209 u8 reserved_0[0x10];
5210
5211 u8 reserved_1[0x10];
5212 u8 op_mod[0x10];
5213
5214 u8 reserved_2[0x8];
5215 u8 pd[0x18];
5216
5217 u8 reserved_3[0x20];
5218};
5219
5220struct mlx5_ifc_create_xrc_srq_out_bits {
5221 u8 status[0x8];
5222 u8 reserved_0[0x18];
5223
5224 u8 syndrome[0x20];
5225
5226 u8 reserved_1[0x8];
5227 u8 xrc_srqn[0x18];
5228
5229 u8 reserved_2[0x20];
5230};
5231
5232struct mlx5_ifc_create_xrc_srq_in_bits {
5233 u8 opcode[0x10];
5234 u8 reserved_0[0x10];
5235
5236 u8 reserved_1[0x10];
5237 u8 op_mod[0x10];
5238
5239 u8 reserved_2[0x40];
5240
5241 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5242
5243 u8 reserved_3[0x600];
5244
5245 u8 pas[0][0x40];
5246};
5247
5248struct mlx5_ifc_create_tis_out_bits {
5249 u8 status[0x8];
5250 u8 reserved_0[0x18];
5251
5252 u8 syndrome[0x20];
5253
5254 u8 reserved_1[0x8];
5255 u8 tisn[0x18];
5256
5257 u8 reserved_2[0x20];
5258};
5259
5260struct mlx5_ifc_create_tis_in_bits {
5261 u8 opcode[0x10];
5262 u8 reserved_0[0x10];
5263
5264 u8 reserved_1[0x10];
5265 u8 op_mod[0x10];
5266
5267 u8 reserved_2[0xc0];
5268
5269 struct mlx5_ifc_tisc_bits ctx;
5270};
5271
5272struct mlx5_ifc_create_tir_out_bits {
5273 u8 status[0x8];
5274 u8 reserved_0[0x18];
5275
5276 u8 syndrome[0x20];
5277
5278 u8 reserved_1[0x8];
5279 u8 tirn[0x18];
5280
5281 u8 reserved_2[0x20];
5282};
5283
5284struct mlx5_ifc_create_tir_in_bits {
5285 u8 opcode[0x10];
5286 u8 reserved_0[0x10];
5287
5288 u8 reserved_1[0x10];
5289 u8 op_mod[0x10];
5290
5291 u8 reserved_2[0xc0];
5292
5293 struct mlx5_ifc_tirc_bits ctx;
5294};
5295
5296struct mlx5_ifc_create_srq_out_bits {
5297 u8 status[0x8];
5298 u8 reserved_0[0x18];
5299
5300 u8 syndrome[0x20];
5301
5302 u8 reserved_1[0x8];
5303 u8 srqn[0x18];
5304
5305 u8 reserved_2[0x20];
5306};
5307
5308struct mlx5_ifc_create_srq_in_bits {
5309 u8 opcode[0x10];
5310 u8 reserved_0[0x10];
5311
5312 u8 reserved_1[0x10];
5313 u8 op_mod[0x10];
5314
5315 u8 reserved_2[0x40];
5316
5317 struct mlx5_ifc_srqc_bits srq_context_entry;
5318
5319 u8 reserved_3[0x600];
5320
5321 u8 pas[0][0x40];
5322};
5323
5324struct mlx5_ifc_create_sq_out_bits {
5325 u8 status[0x8];
5326 u8 reserved_0[0x18];
5327
5328 u8 syndrome[0x20];
5329
5330 u8 reserved_1[0x8];
5331 u8 sqn[0x18];
5332
5333 u8 reserved_2[0x20];
5334};
5335
5336struct mlx5_ifc_create_sq_in_bits {
5337 u8 opcode[0x10];
5338 u8 reserved_0[0x10];
5339
5340 u8 reserved_1[0x10];
5341 u8 op_mod[0x10];
5342
5343 u8 reserved_2[0xc0];
5344
5345 struct mlx5_ifc_sqc_bits ctx;
5346};
5347
5348struct mlx5_ifc_create_rqt_out_bits {
5349 u8 status[0x8];
5350 u8 reserved_0[0x18];
5351
5352 u8 syndrome[0x20];
5353
5354 u8 reserved_1[0x8];
5355 u8 rqtn[0x18];
5356
5357 u8 reserved_2[0x20];
5358};
5359
5360struct mlx5_ifc_create_rqt_in_bits {
5361 u8 opcode[0x10];
5362 u8 reserved_0[0x10];
5363
5364 u8 reserved_1[0x10];
5365 u8 op_mod[0x10];
5366
5367 u8 reserved_2[0xc0];
5368
5369 struct mlx5_ifc_rqtc_bits rqt_context;
5370};
5371
5372struct mlx5_ifc_create_rq_out_bits {
5373 u8 status[0x8];
5374 u8 reserved_0[0x18];
5375
5376 u8 syndrome[0x20];
5377
5378 u8 reserved_1[0x8];
5379 u8 rqn[0x18];
5380
5381 u8 reserved_2[0x20];
5382};
5383
5384struct mlx5_ifc_create_rq_in_bits {
5385 u8 opcode[0x10];
5386 u8 reserved_0[0x10];
5387
5388 u8 reserved_1[0x10];
5389 u8 op_mod[0x10];
5390
5391 u8 reserved_2[0xc0];
5392
5393 struct mlx5_ifc_rqc_bits ctx;
5394};
5395
5396struct mlx5_ifc_create_rmp_out_bits {
5397 u8 status[0x8];
5398 u8 reserved_0[0x18];
5399
5400 u8 syndrome[0x20];
5401
5402 u8 reserved_1[0x8];
5403 u8 rmpn[0x18];
5404
5405 u8 reserved_2[0x20];
5406};
5407
5408struct mlx5_ifc_create_rmp_in_bits {
5409 u8 opcode[0x10];
5410 u8 reserved_0[0x10];
5411
5412 u8 reserved_1[0x10];
5413 u8 op_mod[0x10];
5414
5415 u8 reserved_2[0xc0];
5416
5417 struct mlx5_ifc_rmpc_bits ctx;
5418};
5419
5420struct mlx5_ifc_create_qp_out_bits {
5421 u8 status[0x8];
5422 u8 reserved_0[0x18];
5423
5424 u8 syndrome[0x20];
5425
5426 u8 reserved_1[0x8];
5427 u8 qpn[0x18];
5428
5429 u8 reserved_2[0x20];
5430};
5431
5432struct mlx5_ifc_create_qp_in_bits {
5433 u8 opcode[0x10];
5434 u8 reserved_0[0x10];
5435
5436 u8 reserved_1[0x10];
5437 u8 op_mod[0x10];
5438
5439 u8 reserved_2[0x40];
5440
5441 u8 opt_param_mask[0x20];
5442
5443 u8 reserved_3[0x20];
5444
5445 struct mlx5_ifc_qpc_bits qpc;
5446
5447 u8 reserved_4[0x80];
5448
5449 u8 pas[0][0x40];
5450};
5451
5452struct mlx5_ifc_create_psv_out_bits {
5453 u8 status[0x8];
5454 u8 reserved_0[0x18];
5455
5456 u8 syndrome[0x20];
5457
5458 u8 reserved_1[0x40];
5459
5460 u8 reserved_2[0x8];
5461 u8 psv0_index[0x18];
5462
5463 u8 reserved_3[0x8];
5464 u8 psv1_index[0x18];
5465
5466 u8 reserved_4[0x8];
5467 u8 psv2_index[0x18];
5468
5469 u8 reserved_5[0x8];
5470 u8 psv3_index[0x18];
5471};
5472
5473struct mlx5_ifc_create_psv_in_bits {
5474 u8 opcode[0x10];
5475 u8 reserved_0[0x10];
5476
5477 u8 reserved_1[0x10];
5478 u8 op_mod[0x10];
5479
5480 u8 num_psv[0x4];
5481 u8 reserved_2[0x4];
5482 u8 pd[0x18];
5483
5484 u8 reserved_3[0x20];
5485};
5486
5487struct mlx5_ifc_create_mkey_out_bits {
5488 u8 status[0x8];
5489 u8 reserved_0[0x18];
5490
5491 u8 syndrome[0x20];
5492
5493 u8 reserved_1[0x8];
5494 u8 mkey_index[0x18];
5495
5496 u8 reserved_2[0x20];
5497};
5498
5499struct mlx5_ifc_create_mkey_in_bits {
5500 u8 opcode[0x10];
5501 u8 reserved_0[0x10];
5502
5503 u8 reserved_1[0x10];
5504 u8 op_mod[0x10];
5505
5506 u8 reserved_2[0x20];
5507
5508 u8 pg_access[0x1];
5509 u8 reserved_3[0x1f];
5510
5511 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5512
5513 u8 reserved_4[0x80];
5514
5515 u8 translations_octword_actual_size[0x20];
5516
5517 u8 reserved_5[0x560];
5518
5519 u8 klm_pas_mtt[0][0x20];
5520};
5521
5522struct mlx5_ifc_create_flow_table_out_bits {
5523 u8 status[0x8];
5524 u8 reserved_0[0x18];
5525
5526 u8 syndrome[0x20];
5527
5528 u8 reserved_1[0x8];
5529 u8 table_id[0x18];
5530
5531 u8 reserved_2[0x20];
5532};
5533
5534struct mlx5_ifc_create_flow_table_in_bits {
5535 u8 opcode[0x10];
5536 u8 reserved_0[0x10];
5537
5538 u8 reserved_1[0x10];
5539 u8 op_mod[0x10];
5540
5541 u8 reserved_2[0x40];
5542
5543 u8 table_type[0x8];
5544 u8 reserved_3[0x18];
5545
5546 u8 reserved_4[0x20];
5547
5548 u8 reserved_5[0x8];
5549 u8 level[0x8];
5550 u8 reserved_6[0x8];
5551 u8 log_size[0x8];
5552
5553 u8 reserved_7[0x120];
5554};
5555
5556struct mlx5_ifc_create_flow_group_out_bits {
5557 u8 status[0x8];
5558 u8 reserved_0[0x18];
5559
5560 u8 syndrome[0x20];
5561
5562 u8 reserved_1[0x8];
5563 u8 group_id[0x18];
5564
5565 u8 reserved_2[0x20];
5566};
5567
5568enum {
5569 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5570 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5571 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5572};
5573
5574struct mlx5_ifc_create_flow_group_in_bits {
5575 u8 opcode[0x10];
5576 u8 reserved_0[0x10];
5577
5578 u8 reserved_1[0x10];
5579 u8 op_mod[0x10];
5580
5581 u8 reserved_2[0x40];
5582
5583 u8 table_type[0x8];
5584 u8 reserved_3[0x18];
5585
5586 u8 reserved_4[0x8];
5587 u8 table_id[0x18];
5588
5589 u8 reserved_5[0x20];
5590
5591 u8 start_flow_index[0x20];
5592
5593 u8 reserved_6[0x20];
5594
5595 u8 end_flow_index[0x20];
5596
5597 u8 reserved_7[0xa0];
5598
5599 u8 reserved_8[0x18];
5600 u8 match_criteria_enable[0x8];
5601
5602 struct mlx5_ifc_fte_match_param_bits match_criteria;
5603
5604 u8 reserved_9[0xe00];
5605};
5606
5607struct mlx5_ifc_create_eq_out_bits {
5608 u8 status[0x8];
5609 u8 reserved_0[0x18];
5610
5611 u8 syndrome[0x20];
5612
5613 u8 reserved_1[0x18];
5614 u8 eq_number[0x8];
5615
5616 u8 reserved_2[0x20];
5617};
5618
5619struct mlx5_ifc_create_eq_in_bits {
5620 u8 opcode[0x10];
5621 u8 reserved_0[0x10];
5622
5623 u8 reserved_1[0x10];
5624 u8 op_mod[0x10];
5625
5626 u8 reserved_2[0x40];
5627
5628 struct mlx5_ifc_eqc_bits eq_context_entry;
5629
5630 u8 reserved_3[0x40];
5631
5632 u8 event_bitmask[0x40];
5633
5634 u8 reserved_4[0x580];
5635
5636 u8 pas[0][0x40];
5637};
5638
5639struct mlx5_ifc_create_dct_out_bits {
5640 u8 status[0x8];
5641 u8 reserved_0[0x18];
5642
5643 u8 syndrome[0x20];
5644
5645 u8 reserved_1[0x8];
5646 u8 dctn[0x18];
5647
5648 u8 reserved_2[0x20];
5649};
5650
5651struct mlx5_ifc_create_dct_in_bits {
5652 u8 opcode[0x10];
5653 u8 reserved_0[0x10];
5654
5655 u8 reserved_1[0x10];
5656 u8 op_mod[0x10];
5657
5658 u8 reserved_2[0x40];
5659
5660 struct mlx5_ifc_dctc_bits dct_context_entry;
5661
5662 u8 reserved_3[0x180];
5663};
5664
5665struct mlx5_ifc_create_cq_out_bits {
5666 u8 status[0x8];
5667 u8 reserved_0[0x18];
5668
5669 u8 syndrome[0x20];
5670
5671 u8 reserved_1[0x8];
5672 u8 cqn[0x18];
5673
5674 u8 reserved_2[0x20];
5675};
5676
5677struct mlx5_ifc_create_cq_in_bits {
5678 u8 opcode[0x10];
5679 u8 reserved_0[0x10];
5680
5681 u8 reserved_1[0x10];
5682 u8 op_mod[0x10];
5683
5684 u8 reserved_2[0x40];
5685
5686 struct mlx5_ifc_cqc_bits cq_context;
5687
5688 u8 reserved_3[0x600];
5689
5690 u8 pas[0][0x40];
5691};
5692
5693struct mlx5_ifc_config_int_moderation_out_bits {
5694 u8 status[0x8];
5695 u8 reserved_0[0x18];
5696
5697 u8 syndrome[0x20];
5698
5699 u8 reserved_1[0x4];
5700 u8 min_delay[0xc];
5701 u8 int_vector[0x10];
5702
5703 u8 reserved_2[0x20];
5704};
5705
5706enum {
5707 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5708 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5709};
5710
5711struct mlx5_ifc_config_int_moderation_in_bits {
5712 u8 opcode[0x10];
5713 u8 reserved_0[0x10];
5714
5715 u8 reserved_1[0x10];
5716 u8 op_mod[0x10];
5717
5718 u8 reserved_2[0x4];
5719 u8 min_delay[0xc];
5720 u8 int_vector[0x10];
5721
5722 u8 reserved_3[0x20];
5723};
5724
5725struct mlx5_ifc_attach_to_mcg_out_bits {
5726 u8 status[0x8];
5727 u8 reserved_0[0x18];
5728
5729 u8 syndrome[0x20];
5730
5731 u8 reserved_1[0x40];
5732};
5733
5734struct mlx5_ifc_attach_to_mcg_in_bits {
5735 u8 opcode[0x10];
5736 u8 reserved_0[0x10];
5737
5738 u8 reserved_1[0x10];
5739 u8 op_mod[0x10];
5740
5741 u8 reserved_2[0x8];
5742 u8 qpn[0x18];
5743
5744 u8 reserved_3[0x20];
5745
5746 u8 multicast_gid[16][0x8];
5747};
5748
5749struct mlx5_ifc_arm_xrc_srq_out_bits {
5750 u8 status[0x8];
5751 u8 reserved_0[0x18];
5752
5753 u8 syndrome[0x20];
5754
5755 u8 reserved_1[0x40];
5756};
5757
5758enum {
5759 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5760};
5761
5762struct mlx5_ifc_arm_xrc_srq_in_bits {
5763 u8 opcode[0x10];
5764 u8 reserved_0[0x10];
5765
5766 u8 reserved_1[0x10];
5767 u8 op_mod[0x10];
5768
5769 u8 reserved_2[0x8];
5770 u8 xrc_srqn[0x18];
5771
5772 u8 reserved_3[0x10];
5773 u8 lwm[0x10];
5774};
5775
5776struct mlx5_ifc_arm_rq_out_bits {
5777 u8 status[0x8];
5778 u8 reserved_0[0x18];
5779
5780 u8 syndrome[0x20];
5781
5782 u8 reserved_1[0x40];
5783};
5784
5785enum {
5786 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5787};
5788
5789struct mlx5_ifc_arm_rq_in_bits {
5790 u8 opcode[0x10];
5791 u8 reserved_0[0x10];
5792
5793 u8 reserved_1[0x10];
5794 u8 op_mod[0x10];
5795
5796 u8 reserved_2[0x8];
5797 u8 srq_number[0x18];
5798
5799 u8 reserved_3[0x10];
5800 u8 lwm[0x10];
5801};
5802
5803struct mlx5_ifc_arm_dct_out_bits {
5804 u8 status[0x8];
5805 u8 reserved_0[0x18];
5806
5807 u8 syndrome[0x20];
5808
5809 u8 reserved_1[0x40];
5810};
5811
5812struct mlx5_ifc_arm_dct_in_bits {
5813 u8 opcode[0x10];
5814 u8 reserved_0[0x10];
5815
5816 u8 reserved_1[0x10];
5817 u8 op_mod[0x10];
5818
5819 u8 reserved_2[0x8];
5820 u8 dct_number[0x18];
5821
5822 u8 reserved_3[0x20];
5823};
5824
5825struct mlx5_ifc_alloc_xrcd_out_bits {
5826 u8 status[0x8];
5827 u8 reserved_0[0x18];
5828
5829 u8 syndrome[0x20];
5830
5831 u8 reserved_1[0x8];
5832 u8 xrcd[0x18];
5833
5834 u8 reserved_2[0x20];
5835};
5836
5837struct mlx5_ifc_alloc_xrcd_in_bits {
5838 u8 opcode[0x10];
5839 u8 reserved_0[0x10];
5840
5841 u8 reserved_1[0x10];
5842 u8 op_mod[0x10];
5843
5844 u8 reserved_2[0x40];
5845};
5846
5847struct mlx5_ifc_alloc_uar_out_bits {
5848 u8 status[0x8];
5849 u8 reserved_0[0x18];
5850
5851 u8 syndrome[0x20];
5852
5853 u8 reserved_1[0x8];
5854 u8 uar[0x18];
5855
5856 u8 reserved_2[0x20];
5857};
5858
5859struct mlx5_ifc_alloc_uar_in_bits {
5860 u8 opcode[0x10];
5861 u8 reserved_0[0x10];
5862
5863 u8 reserved_1[0x10];
5864 u8 op_mod[0x10];
5865
5866 u8 reserved_2[0x40];
5867};
5868
5869struct mlx5_ifc_alloc_transport_domain_out_bits {
5870 u8 status[0x8];
5871 u8 reserved_0[0x18];
5872
5873 u8 syndrome[0x20];
5874
5875 u8 reserved_1[0x8];
5876 u8 transport_domain[0x18];
5877
5878 u8 reserved_2[0x20];
5879};
5880
5881struct mlx5_ifc_alloc_transport_domain_in_bits {
5882 u8 opcode[0x10];
5883 u8 reserved_0[0x10];
5884
5885 u8 reserved_1[0x10];
5886 u8 op_mod[0x10];
5887
5888 u8 reserved_2[0x40];
5889};
5890
5891struct mlx5_ifc_alloc_q_counter_out_bits {
5892 u8 status[0x8];
5893 u8 reserved_0[0x18];
5894
5895 u8 syndrome[0x20];
5896
5897 u8 reserved_1[0x18];
5898 u8 counter_set_id[0x8];
5899
5900 u8 reserved_2[0x20];
5901};
5902
5903struct mlx5_ifc_alloc_q_counter_in_bits {
5904 u8 opcode[0x10];
5905 u8 reserved_0[0x10];
5906
5907 u8 reserved_1[0x10];
5908 u8 op_mod[0x10];
5909
5910 u8 reserved_2[0x40];
5911};
5912
5913struct mlx5_ifc_alloc_pd_out_bits {
5914 u8 status[0x8];
5915 u8 reserved_0[0x18];
5916
5917 u8 syndrome[0x20];
5918
5919 u8 reserved_1[0x8];
5920 u8 pd[0x18];
5921
5922 u8 reserved_2[0x20];
5923};
5924
5925struct mlx5_ifc_alloc_pd_in_bits {
5926 u8 opcode[0x10];
5927 u8 reserved_0[0x10];
5928
5929 u8 reserved_1[0x10];
5930 u8 op_mod[0x10];
5931
5932 u8 reserved_2[0x40];
5933};
5934
5935struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5936 u8 status[0x8];
5937 u8 reserved_0[0x18];
5938
5939 u8 syndrome[0x20];
5940
5941 u8 reserved_1[0x40];
5942};
5943
5944struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5945 u8 opcode[0x10];
5946 u8 reserved_0[0x10];
5947
5948 u8 reserved_1[0x10];
5949 u8 op_mod[0x10];
5950
5951 u8 reserved_2[0x20];
5952
5953 u8 reserved_3[0x10];
5954 u8 vxlan_udp_port[0x10];
5955};
5956
5957struct mlx5_ifc_access_register_out_bits {
5958 u8 status[0x8];
5959 u8 reserved_0[0x18];
5960
5961 u8 syndrome[0x20];
5962
5963 u8 reserved_1[0x40];
5964
5965 u8 register_data[0][0x20];
5966};
5967
5968enum {
5969 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5970 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5971};
5972
5973struct mlx5_ifc_access_register_in_bits {
5974 u8 opcode[0x10];
5975 u8 reserved_0[0x10];
5976
5977 u8 reserved_1[0x10];
5978 u8 op_mod[0x10];
5979
5980 u8 reserved_2[0x10];
5981 u8 register_id[0x10];
5982
5983 u8 argument[0x20];
5984
5985 u8 register_data[0][0x20];
5986};
5987
5988struct mlx5_ifc_sltp_reg_bits {
5989 u8 status[0x4];
5990 u8 version[0x4];
5991 u8 local_port[0x8];
5992 u8 pnat[0x2];
5993 u8 reserved_0[0x2];
5994 u8 lane[0x4];
5995 u8 reserved_1[0x8];
5996
5997 u8 reserved_2[0x20];
5998
5999 u8 reserved_3[0x7];
6000 u8 polarity[0x1];
6001 u8 ob_tap0[0x8];
6002 u8 ob_tap1[0x8];
6003 u8 ob_tap2[0x8];
6004
6005 u8 reserved_4[0xc];
6006 u8 ob_preemp_mode[0x4];
6007 u8 ob_reg[0x8];
6008 u8 ob_bias[0x8];
6009
6010 u8 reserved_5[0x20];
6011};
6012
6013struct mlx5_ifc_slrg_reg_bits {
6014 u8 status[0x4];
6015 u8 version[0x4];
6016 u8 local_port[0x8];
6017 u8 pnat[0x2];
6018 u8 reserved_0[0x2];
6019 u8 lane[0x4];
6020 u8 reserved_1[0x8];
6021
6022 u8 time_to_link_up[0x10];
6023 u8 reserved_2[0xc];
6024 u8 grade_lane_speed[0x4];
6025
6026 u8 grade_version[0x8];
6027 u8 grade[0x18];
6028
6029 u8 reserved_3[0x4];
6030 u8 height_grade_type[0x4];
6031 u8 height_grade[0x18];
6032
6033 u8 height_dz[0x10];
6034 u8 height_dv[0x10];
6035
6036 u8 reserved_4[0x10];
6037 u8 height_sigma[0x10];
6038
6039 u8 reserved_5[0x20];
6040
6041 u8 reserved_6[0x4];
6042 u8 phase_grade_type[0x4];
6043 u8 phase_grade[0x18];
6044
6045 u8 reserved_7[0x8];
6046 u8 phase_eo_pos[0x8];
6047 u8 reserved_8[0x8];
6048 u8 phase_eo_neg[0x8];
6049
6050 u8 ffe_set_tested[0x10];
6051 u8 test_errors_per_lane[0x10];
6052};
6053
6054struct mlx5_ifc_pvlc_reg_bits {
6055 u8 reserved_0[0x8];
6056 u8 local_port[0x8];
6057 u8 reserved_1[0x10];
6058
6059 u8 reserved_2[0x1c];
6060 u8 vl_hw_cap[0x4];
6061
6062 u8 reserved_3[0x1c];
6063 u8 vl_admin[0x4];
6064
6065 u8 reserved_4[0x1c];
6066 u8 vl_operational[0x4];
6067};
6068
6069struct mlx5_ifc_pude_reg_bits {
6070 u8 swid[0x8];
6071 u8 local_port[0x8];
6072 u8 reserved_0[0x4];
6073 u8 admin_status[0x4];
6074 u8 reserved_1[0x4];
6075 u8 oper_status[0x4];
6076
6077 u8 reserved_2[0x60];
6078};
6079
6080struct mlx5_ifc_ptys_reg_bits {
6081 u8 reserved_0[0x8];
6082 u8 local_port[0x8];
6083 u8 reserved_1[0xd];
6084 u8 proto_mask[0x3];
6085
6086 u8 reserved_2[0x40];
6087
6088 u8 eth_proto_capability[0x20];
6089
6090 u8 ib_link_width_capability[0x10];
6091 u8 ib_proto_capability[0x10];
6092
6093 u8 reserved_3[0x20];
6094
6095 u8 eth_proto_admin[0x20];
6096
6097 u8 ib_link_width_admin[0x10];
6098 u8 ib_proto_admin[0x10];
6099
6100 u8 reserved_4[0x20];
6101
6102 u8 eth_proto_oper[0x20];
6103
6104 u8 ib_link_width_oper[0x10];
6105 u8 ib_proto_oper[0x10];
6106
6107 u8 reserved_5[0x20];
6108
6109 u8 eth_proto_lp_advertise[0x20];
6110
6111 u8 reserved_6[0x60];
6112};
6113
6114struct mlx5_ifc_ptas_reg_bits {
6115 u8 reserved_0[0x20];
6116
6117 u8 algorithm_options[0x10];
6118 u8 reserved_1[0x4];
6119 u8 repetitions_mode[0x4];
6120 u8 num_of_repetitions[0x8];
6121
6122 u8 grade_version[0x8];
6123 u8 height_grade_type[0x4];
6124 u8 phase_grade_type[0x4];
6125 u8 height_grade_weight[0x8];
6126 u8 phase_grade_weight[0x8];
6127
6128 u8 gisim_measure_bits[0x10];
6129 u8 adaptive_tap_measure_bits[0x10];
6130
6131 u8 ber_bath_high_error_threshold[0x10];
6132 u8 ber_bath_mid_error_threshold[0x10];
6133
6134 u8 ber_bath_low_error_threshold[0x10];
6135 u8 one_ratio_high_threshold[0x10];
6136
6137 u8 one_ratio_high_mid_threshold[0x10];
6138 u8 one_ratio_low_mid_threshold[0x10];
6139
6140 u8 one_ratio_low_threshold[0x10];
6141 u8 ndeo_error_threshold[0x10];
6142
6143 u8 mixer_offset_step_size[0x10];
6144 u8 reserved_2[0x8];
6145 u8 mix90_phase_for_voltage_bath[0x8];
6146
6147 u8 mixer_offset_start[0x10];
6148 u8 mixer_offset_end[0x10];
6149
6150 u8 reserved_3[0x15];
6151 u8 ber_test_time[0xb];
6152};
6153
6154struct mlx5_ifc_pspa_reg_bits {
6155 u8 swid[0x8];
6156 u8 local_port[0x8];
6157 u8 sub_port[0x8];
6158 u8 reserved_0[0x8];
6159
6160 u8 reserved_1[0x20];
6161};
6162
6163struct mlx5_ifc_pqdr_reg_bits {
6164 u8 reserved_0[0x8];
6165 u8 local_port[0x8];
6166 u8 reserved_1[0x5];
6167 u8 prio[0x3];
6168 u8 reserved_2[0x6];
6169 u8 mode[0x2];
6170
6171 u8 reserved_3[0x20];
6172
6173 u8 reserved_4[0x10];
6174 u8 min_threshold[0x10];
6175
6176 u8 reserved_5[0x10];
6177 u8 max_threshold[0x10];
6178
6179 u8 reserved_6[0x10];
6180 u8 mark_probability_denominator[0x10];
6181
6182 u8 reserved_7[0x60];
6183};
6184
6185struct mlx5_ifc_ppsc_reg_bits {
6186 u8 reserved_0[0x8];
6187 u8 local_port[0x8];
6188 u8 reserved_1[0x10];
6189
6190 u8 reserved_2[0x60];
6191
6192 u8 reserved_3[0x1c];
6193 u8 wrps_admin[0x4];
6194
6195 u8 reserved_4[0x1c];
6196 u8 wrps_status[0x4];
6197
6198 u8 reserved_5[0x8];
6199 u8 up_threshold[0x8];
6200 u8 reserved_6[0x8];
6201 u8 down_threshold[0x8];
6202
6203 u8 reserved_7[0x20];
6204
6205 u8 reserved_8[0x1c];
6206 u8 srps_admin[0x4];
6207
6208 u8 reserved_9[0x1c];
6209 u8 srps_status[0x4];
6210
6211 u8 reserved_10[0x40];
6212};
6213
6214struct mlx5_ifc_pplr_reg_bits {
6215 u8 reserved_0[0x8];
6216 u8 local_port[0x8];
6217 u8 reserved_1[0x10];
6218
6219 u8 reserved_2[0x8];
6220 u8 lb_cap[0x8];
6221 u8 reserved_3[0x8];
6222 u8 lb_en[0x8];
6223};
6224
6225struct mlx5_ifc_pplm_reg_bits {
6226 u8 reserved_0[0x8];
6227 u8 local_port[0x8];
6228 u8 reserved_1[0x10];
6229
6230 u8 reserved_2[0x20];
6231
6232 u8 port_profile_mode[0x8];
6233 u8 static_port_profile[0x8];
6234 u8 active_port_profile[0x8];
6235 u8 reserved_3[0x8];
6236
6237 u8 retransmission_active[0x8];
6238 u8 fec_mode_active[0x18];
6239
6240 u8 reserved_4[0x20];
6241};
6242
6243struct mlx5_ifc_ppcnt_reg_bits {
6244 u8 swid[0x8];
6245 u8 local_port[0x8];
6246 u8 pnat[0x2];
6247 u8 reserved_0[0x8];
6248 u8 grp[0x6];
6249
6250 u8 clr[0x1];
6251 u8 reserved_1[0x1c];
6252 u8 prio_tc[0x3];
6253
6254 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6255};
6256
6257struct mlx5_ifc_ppad_reg_bits {
6258 u8 reserved_0[0x3];
6259 u8 single_mac[0x1];
6260 u8 reserved_1[0x4];
6261 u8 local_port[0x8];
6262 u8 mac_47_32[0x10];
6263
6264 u8 mac_31_0[0x20];
6265
6266 u8 reserved_2[0x40];
6267};
6268
6269struct mlx5_ifc_pmtu_reg_bits {
6270 u8 reserved_0[0x8];
6271 u8 local_port[0x8];
6272 u8 reserved_1[0x10];
6273
6274 u8 max_mtu[0x10];
6275 u8 reserved_2[0x10];
6276
6277 u8 admin_mtu[0x10];
6278 u8 reserved_3[0x10];
6279
6280 u8 oper_mtu[0x10];
6281 u8 reserved_4[0x10];
6282};
6283
6284struct mlx5_ifc_pmpr_reg_bits {
6285 u8 reserved_0[0x8];
6286 u8 module[0x8];
6287 u8 reserved_1[0x10];
6288
6289 u8 reserved_2[0x18];
6290 u8 attenuation_5g[0x8];
6291
6292 u8 reserved_3[0x18];
6293 u8 attenuation_7g[0x8];
6294
6295 u8 reserved_4[0x18];
6296 u8 attenuation_12g[0x8];
6297};
6298
6299struct mlx5_ifc_pmpe_reg_bits {
6300 u8 reserved_0[0x8];
6301 u8 module[0x8];
6302 u8 reserved_1[0xc];
6303 u8 module_status[0x4];
6304
6305 u8 reserved_2[0x60];
6306};
6307
6308struct mlx5_ifc_pmpc_reg_bits {
6309 u8 module_state_updated[32][0x8];
6310};
6311
6312struct mlx5_ifc_pmlpn_reg_bits {
6313 u8 reserved_0[0x4];
6314 u8 mlpn_status[0x4];
6315 u8 local_port[0x8];
6316 u8 reserved_1[0x10];
6317
6318 u8 e[0x1];
6319 u8 reserved_2[0x1f];
6320};
6321
6322struct mlx5_ifc_pmlp_reg_bits {
6323 u8 rxtx[0x1];
6324 u8 reserved_0[0x7];
6325 u8 local_port[0x8];
6326 u8 reserved_1[0x8];
6327 u8 width[0x8];
6328
6329 u8 lane0_module_mapping[0x20];
6330
6331 u8 lane1_module_mapping[0x20];
6332
6333 u8 lane2_module_mapping[0x20];
6334
6335 u8 lane3_module_mapping[0x20];
6336
6337 u8 reserved_2[0x160];
6338};
6339
6340struct mlx5_ifc_pmaos_reg_bits {
6341 u8 reserved_0[0x8];
6342 u8 module[0x8];
6343 u8 reserved_1[0x4];
6344 u8 admin_status[0x4];
6345 u8 reserved_2[0x4];
6346 u8 oper_status[0x4];
6347
6348 u8 ase[0x1];
6349 u8 ee[0x1];
6350 u8 reserved_3[0x1c];
6351 u8 e[0x2];
6352
6353 u8 reserved_4[0x40];
6354};
6355
6356struct mlx5_ifc_plpc_reg_bits {
6357 u8 reserved_0[0x4];
6358 u8 profile_id[0xc];
6359 u8 reserved_1[0x4];
6360 u8 proto_mask[0x4];
6361 u8 reserved_2[0x8];
6362
6363 u8 reserved_3[0x10];
6364 u8 lane_speed[0x10];
6365
6366 u8 reserved_4[0x17];
6367 u8 lpbf[0x1];
6368 u8 fec_mode_policy[0x8];
6369
6370 u8 retransmission_capability[0x8];
6371 u8 fec_mode_capability[0x18];
6372
6373 u8 retransmission_support_admin[0x8];
6374 u8 fec_mode_support_admin[0x18];
6375
6376 u8 retransmission_request_admin[0x8];
6377 u8 fec_mode_request_admin[0x18];
6378
6379 u8 reserved_5[0x80];
6380};
6381
6382struct mlx5_ifc_plib_reg_bits {
6383 u8 reserved_0[0x8];
6384 u8 local_port[0x8];
6385 u8 reserved_1[0x8];
6386 u8 ib_port[0x8];
6387
6388 u8 reserved_2[0x60];
6389};
6390
6391struct mlx5_ifc_plbf_reg_bits {
6392 u8 reserved_0[0x8];
6393 u8 local_port[0x8];
6394 u8 reserved_1[0xd];
6395 u8 lbf_mode[0x3];
6396
6397 u8 reserved_2[0x20];
6398};
6399
6400struct mlx5_ifc_pipg_reg_bits {
6401 u8 reserved_0[0x8];
6402 u8 local_port[0x8];
6403 u8 reserved_1[0x10];
6404
6405 u8 dic[0x1];
6406 u8 reserved_2[0x19];
6407 u8 ipg[0x4];
6408 u8 reserved_3[0x2];
6409};
6410
6411struct mlx5_ifc_pifr_reg_bits {
6412 u8 reserved_0[0x8];
6413 u8 local_port[0x8];
6414 u8 reserved_1[0x10];
6415
6416 u8 reserved_2[0xe0];
6417
6418 u8 port_filter[8][0x20];
6419
6420 u8 port_filter_update_en[8][0x20];
6421};
6422
6423struct mlx5_ifc_pfcc_reg_bits {
6424 u8 reserved_0[0x8];
6425 u8 local_port[0x8];
6426 u8 reserved_1[0x10];
6427
6428 u8 ppan[0x4];
6429 u8 reserved_2[0x4];
6430 u8 prio_mask_tx[0x8];
6431 u8 reserved_3[0x8];
6432 u8 prio_mask_rx[0x8];
6433
6434 u8 pptx[0x1];
6435 u8 aptx[0x1];
6436 u8 reserved_4[0x6];
6437 u8 pfctx[0x8];
6438 u8 reserved_5[0x10];
6439
6440 u8 pprx[0x1];
6441 u8 aprx[0x1];
6442 u8 reserved_6[0x6];
6443 u8 pfcrx[0x8];
6444 u8 reserved_7[0x10];
6445
6446 u8 reserved_8[0x80];
6447};
6448
6449struct mlx5_ifc_pelc_reg_bits {
6450 u8 op[0x4];
6451 u8 reserved_0[0x4];
6452 u8 local_port[0x8];
6453 u8 reserved_1[0x10];
6454
6455 u8 op_admin[0x8];
6456 u8 op_capability[0x8];
6457 u8 op_request[0x8];
6458 u8 op_active[0x8];
6459
6460 u8 admin[0x40];
6461
6462 u8 capability[0x40];
6463
6464 u8 request[0x40];
6465
6466 u8 active[0x40];
6467
6468 u8 reserved_2[0x80];
6469};
6470
6471struct mlx5_ifc_peir_reg_bits {
6472 u8 reserved_0[0x8];
6473 u8 local_port[0x8];
6474 u8 reserved_1[0x10];
6475
6476 u8 reserved_2[0xc];
6477 u8 error_count[0x4];
6478 u8 reserved_3[0x10];
6479
6480 u8 reserved_4[0xc];
6481 u8 lane[0x4];
6482 u8 reserved_5[0x8];
6483 u8 error_type[0x8];
6484};
6485
6486struct mlx5_ifc_pcap_reg_bits {
6487 u8 reserved_0[0x8];
6488 u8 local_port[0x8];
6489 u8 reserved_1[0x10];
6490
6491 u8 port_capability_mask[4][0x20];
6492};
6493
6494struct mlx5_ifc_paos_reg_bits {
6495 u8 swid[0x8];
6496 u8 local_port[0x8];
6497 u8 reserved_0[0x4];
6498 u8 admin_status[0x4];
6499 u8 reserved_1[0x4];
6500 u8 oper_status[0x4];
6501
6502 u8 ase[0x1];
6503 u8 ee[0x1];
6504 u8 reserved_2[0x1c];
6505 u8 e[0x2];
6506
6507 u8 reserved_3[0x40];
6508};
6509
6510struct mlx5_ifc_pamp_reg_bits {
6511 u8 reserved_0[0x8];
6512 u8 opamp_group[0x8];
6513 u8 reserved_1[0xc];
6514 u8 opamp_group_type[0x4];
6515
6516 u8 start_index[0x10];
6517 u8 reserved_2[0x4];
6518 u8 num_of_indices[0xc];
6519
6520 u8 index_data[18][0x10];
6521};
6522
6523struct mlx5_ifc_lane_2_module_mapping_bits {
6524 u8 reserved_0[0x6];
6525 u8 rx_lane[0x2];
6526 u8 reserved_1[0x6];
6527 u8 tx_lane[0x2];
6528 u8 reserved_2[0x8];
6529 u8 module[0x8];
6530};
6531
6532struct mlx5_ifc_bufferx_reg_bits {
6533 u8 reserved_0[0x6];
6534 u8 lossy[0x1];
6535 u8 epsb[0x1];
6536 u8 reserved_1[0xc];
6537 u8 size[0xc];
6538
6539 u8 xoff_threshold[0x10];
6540 u8 xon_threshold[0x10];
6541};
6542
6543struct mlx5_ifc_set_node_in_bits {
6544 u8 node_description[64][0x8];
6545};
6546
6547struct mlx5_ifc_register_power_settings_bits {
6548 u8 reserved_0[0x18];
6549 u8 power_settings_level[0x8];
6550
6551 u8 reserved_1[0x60];
6552};
6553
6554struct mlx5_ifc_register_host_endianness_bits {
6555 u8 he[0x1];
6556 u8 reserved_0[0x1f];
6557
6558 u8 reserved_1[0x60];
6559};
6560
6561struct mlx5_ifc_umr_pointer_desc_argument_bits {
6562 u8 reserved_0[0x20];
6563
6564 u8 mkey[0x20];
6565
6566 u8 addressh_63_32[0x20];
6567
6568 u8 addressl_31_0[0x20];
6569};
6570
6571struct mlx5_ifc_ud_adrs_vector_bits {
6572 u8 dc_key[0x40];
6573
6574 u8 ext[0x1];
6575 u8 reserved_0[0x7];
6576 u8 destination_qp_dct[0x18];
6577
6578 u8 static_rate[0x4];
6579 u8 sl_eth_prio[0x4];
6580 u8 fl[0x1];
6581 u8 mlid[0x7];
6582 u8 rlid_udp_sport[0x10];
6583
6584 u8 reserved_1[0x20];
6585
6586 u8 rmac_47_16[0x20];
6587
6588 u8 rmac_15_0[0x10];
6589 u8 tclass[0x8];
6590 u8 hop_limit[0x8];
6591
6592 u8 reserved_2[0x1];
6593 u8 grh[0x1];
6594 u8 reserved_3[0x2];
6595 u8 src_addr_index[0x8];
6596 u8 flow_label[0x14];
6597
6598 u8 rgid_rip[16][0x8];
6599};
6600
6601struct mlx5_ifc_pages_req_event_bits {
6602 u8 reserved_0[0x10];
6603 u8 function_id[0x10];
6604
6605 u8 num_pages[0x20];
6606
6607 u8 reserved_1[0xa0];
6608};
6609
6610struct mlx5_ifc_eqe_bits {
6611 u8 reserved_0[0x8];
6612 u8 event_type[0x8];
6613 u8 reserved_1[0x8];
6614 u8 event_sub_type[0x8];
6615
6616 u8 reserved_2[0xe0];
6617
6618 union mlx5_ifc_event_auto_bits event_data;
6619
6620 u8 reserved_3[0x10];
6621 u8 signature[0x8];
6622 u8 reserved_4[0x7];
6623 u8 owner[0x1];
6624};
6625
6626enum {
6627 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6628};
6629
6630struct mlx5_ifc_cmd_queue_entry_bits {
6631 u8 type[0x8];
6632 u8 reserved_0[0x18];
6633
6634 u8 input_length[0x20];
6635
6636 u8 input_mailbox_pointer_63_32[0x20];
6637
6638 u8 input_mailbox_pointer_31_9[0x17];
6639 u8 reserved_1[0x9];
6640
6641 u8 command_input_inline_data[16][0x8];
6642
6643 u8 command_output_inline_data[16][0x8];
6644
6645 u8 output_mailbox_pointer_63_32[0x20];
6646
6647 u8 output_mailbox_pointer_31_9[0x17];
6648 u8 reserved_2[0x9];
6649
6650 u8 output_length[0x20];
6651
6652 u8 token[0x8];
6653 u8 signature[0x8];
6654 u8 reserved_3[0x8];
6655 u8 status[0x7];
6656 u8 ownership[0x1];
6657};
6658
6659struct mlx5_ifc_cmd_out_bits {
6660 u8 status[0x8];
6661 u8 reserved_0[0x18];
6662
6663 u8 syndrome[0x20];
6664
6665 u8 command_output[0x20];
6666};
6667
6668struct mlx5_ifc_cmd_in_bits {
6669 u8 opcode[0x10];
6670 u8 reserved_0[0x10];
6671
6672 u8 reserved_1[0x10];
6673 u8 op_mod[0x10];
6674
6675 u8 command[0][0x20];
6676};
6677
6678struct mlx5_ifc_cmd_if_box_bits {
6679 u8 mailbox_data[512][0x8];
6680
6681 u8 reserved_0[0x180];
6682
6683 u8 next_pointer_63_32[0x20];
6684
6685 u8 next_pointer_31_10[0x16];
6686 u8 reserved_1[0xa];
6687
6688 u8 block_number[0x20];
6689
6690 u8 reserved_2[0x8];
6691 u8 token[0x8];
6692 u8 ctrl_signature[0x8];
6693 u8 signature[0x8];
6694};
6695
6696struct mlx5_ifc_mtt_bits {
6697 u8 ptag_63_32[0x20];
6698
6699 u8 ptag_31_8[0x18];
6700 u8 reserved_0[0x6];
6701 u8 wr_en[0x1];
6702 u8 rd_en[0x1];
6703};
6704
6705enum {
6706 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6707 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6708 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6709};
6710
6711enum {
6712 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6713 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6714 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6715};
6716
6717enum {
6718 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6719 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6720 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6721 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6722 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6723 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6729};
6730
6731struct mlx5_ifc_initial_seg_bits {
6732 u8 fw_rev_minor[0x10];
6733 u8 fw_rev_major[0x10];
6734
6735 u8 cmd_interface_rev[0x10];
6736 u8 fw_rev_subminor[0x10];
6737
6738 u8 reserved_0[0x40];
6739
6740 u8 cmdq_phy_addr_63_32[0x20];
6741
6742 u8 cmdq_phy_addr_31_12[0x14];
6743 u8 reserved_1[0x2];
6744 u8 nic_interface[0x2];
6745 u8 log_cmdq_size[0x4];
6746 u8 log_cmdq_stride[0x4];
6747
6748 u8 command_doorbell_vector[0x20];
6749
6750 u8 reserved_2[0xf00];
6751
6752 u8 initializing[0x1];
6753 u8 reserved_3[0x4];
6754 u8 nic_interface_supported[0x3];
6755 u8 reserved_4[0x18];
6756
6757 struct mlx5_ifc_health_buffer_bits health_buffer;
6758
6759 u8 no_dram_nic_offset[0x20];
6760
6761 u8 reserved_5[0x6e40];
6762
6763 u8 reserved_6[0x1f];
6764 u8 clear_int[0x1];
6765
6766 u8 health_syndrome[0x8];
6767 u8 health_counter[0x18];
6768
6769 u8 reserved_7[0x17fc0];
6770};
6771
6772union mlx5_ifc_ports_control_registers_document_bits {
6773 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6774 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6775 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6776 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6777 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6778 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6779 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6780 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6781 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6782 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6783 struct mlx5_ifc_paos_reg_bits paos_reg;
6784 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6785 struct mlx5_ifc_peir_reg_bits peir_reg;
6786 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6787 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6788 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6789 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6790 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6791 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6792 struct mlx5_ifc_plib_reg_bits plib_reg;
6793 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6794 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6795 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6796 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6797 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6798 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6799 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6800 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6801 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6802 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6803 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6804 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6805 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6806 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6807 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6808 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6809 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6810 struct mlx5_ifc_pude_reg_bits pude_reg;
6811 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6812 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6813 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6814 u8 reserved_0[0x60e0];
6815};
6816
6817union mlx5_ifc_debug_enhancements_document_bits {
6818 struct mlx5_ifc_health_buffer_bits health_buffer;
6819 u8 reserved_0[0x200];
6820};
6821
6822union mlx5_ifc_uplink_pci_interface_document_bits {
6823 struct mlx5_ifc_initial_seg_bits initial_seg;
6824 u8 reserved_0[0x20060];
Eli Cohenb7755162014-10-02 12:19:44 +0300[diff] [blame]6825};
6826
Eli Cohend29b7962014-10-02 12:19:43 +0300[diff] [blame]6827#endif /* MLX5_IFC_H */