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Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02001/*
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +02002 * GPIOs on MPC512x/8349/8572/8610 and compatible
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +02003 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
Rob Herring5af50732013-09-17 14:28:33 -050017#include <linux/of_irq.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020018#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090019#include <linux/slab.h>
Peter Korsgaard345e5c82010-01-07 17:57:46 +010020#include <linux/irq.h>
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020021
22#define MPC8XXX_GPIO_PINS 32
23
24#define GPIO_DIR 0x00
25#define GPIO_ODR 0x04
26#define GPIO_DAT 0x08
27#define GPIO_IER 0x0c
28#define GPIO_IMR 0x10
29#define GPIO_ICR 0x14
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +020030#define GPIO_ICR2 0x18
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020031
32struct mpc8xxx_gpio_chip {
33 struct of_mm_gpio_chip mm_gc;
34 spinlock_t lock;
35
36 /*
37 * shadowed data register to be able to clear/set output pins in
38 * open drain mode safely
39 */
40 u32 data;
Grant Likelybae1d8f2012-02-14 14:06:50 -070041 struct irq_domain *irq;
Uwe Kleine-König01a04dd2012-05-21 21:57:39 +020042 const void *of_dev_id_data;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020043};
44
45static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
46{
47 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
48}
49
50static inline struct mpc8xxx_gpio_chip *
51to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
52{
53 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
54}
55
56static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
57{
58 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
59
60 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
61}
62
Felix Radenskyc1a676d2009-08-12 08:57:39 +030063/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
64 * defined as output cannot be determined by reading GPDAT register,
65 * so we use shadow data register instead. The status of input pins
66 * is determined by reading GPDAT register.
67 */
68static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
69{
70 u32 val;
71 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
72 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
Liu Gang1aeef302013-11-22 16:12:40 +080073 u32 out_mask, out_shadow;
Felix Radenskyc1a676d2009-08-12 08:57:39 +030074
Liu Gang1aeef302013-11-22 16:12:40 +080075 out_mask = in_be32(mm->regs + GPIO_DIR);
Felix Radenskyc1a676d2009-08-12 08:57:39 +030076
Liu Gang1aeef302013-11-22 16:12:40 +080077 val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
78 out_shadow = mpc8xxx_gc->data & out_mask;
79
80 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
Felix Radenskyc1a676d2009-08-12 08:57:39 +030081}
82
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +020083static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
84{
85 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
86
87 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
88}
89
90static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
91{
92 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
93 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
94 unsigned long flags;
95
96 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
97
98 if (val)
99 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
100 else
101 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
102
103 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
104
105 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
106}
107
Rojhalat Ibrahime5db3b32014-11-04 17:12:09 +0100108static void mpc8xxx_gpio_set_multiple(struct gpio_chip *gc,
109 unsigned long *mask, unsigned long *bits)
110{
111 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
113 unsigned long flags;
114 int i;
115
116 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
117
118 for (i = 0; i < gc->ngpio; i++) {
119 if (*mask == 0)
120 break;
121 if (__test_and_clear_bit(i, mask)) {
122 if (test_bit(i, bits))
123 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(i);
124 else
125 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(i);
126 }
127 }
128
129 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
130
131 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
132}
133
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200134static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
135{
136 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
137 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
138 unsigned long flags;
139
140 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
141
142 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
143
144 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
145
146 return 0;
147}
148
149static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
150{
151 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
152 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
153 unsigned long flags;
154
155 mpc8xxx_gpio_set(gc, gpio, val);
156
157 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
158
159 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
160
161 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
162
163 return 0;
164}
165
Wolfram Sang28538df2011-12-13 10:12:48 +0100166static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
167{
168 /* GPIO 28..31 are input only on MPC5121 */
169 if (gpio >= 28)
170 return -EINVAL;
171
172 return mpc8xxx_gpio_dir_out(gc, gpio, val);
173}
174
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100175static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
176{
177 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
178 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
179
180 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
181 return irq_create_mapping(mpc8xxx_gc->irq, offset);
182 else
183 return -ENXIO;
184}
185
186static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
187{
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100188 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
Felix Radenskycfadd832011-10-11 10:24:21 +0200189 struct irq_chip *chip = irq_desc_get_chip(desc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100190 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
191 unsigned int mask;
192
193 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
194 if (mask)
195 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
196 32 - ffs(mask)));
Thomas Gleixnerd6de85e2012-05-03 12:22:06 +0200197 if (chip->irq_eoi)
198 chip->irq_eoi(&desc->irq_data);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100199}
200
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000201static void mpc8xxx_irq_unmask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100202{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000203 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100204 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
205 unsigned long flags;
206
207 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
208
Grant Likely476eb492011-05-04 15:02:15 +1000209 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100210
211 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
212}
213
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000214static void mpc8xxx_irq_mask(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100215{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000216 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100217 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
218 unsigned long flags;
219
220 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
221
Grant Likely476eb492011-05-04 15:02:15 +1000222 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100223
224 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
225}
226
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000227static void mpc8xxx_irq_ack(struct irq_data *d)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100228{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000229 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100230 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
231
Grant Likely476eb492011-05-04 15:02:15 +1000232 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100233}
234
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000235static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100236{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000237 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100238 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
239 unsigned long flags;
240
241 switch (flow_type) {
242 case IRQ_TYPE_EDGE_FALLING:
243 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
244 setbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000245 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100246 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
247 break;
248
249 case IRQ_TYPE_EDGE_BOTH:
250 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
251 clrbits32(mm->regs + GPIO_ICR,
Grant Likely476eb492011-05-04 15:02:15 +1000252 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100253 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 break;
255
256 default:
257 return -EINVAL;
258 }
259
260 return 0;
261}
262
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000263static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200264{
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000265 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200266 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
Grant Likely476eb492011-05-04 15:02:15 +1000267 unsigned long gpio = irqd_to_hwirq(d);
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200268 void __iomem *reg;
269 unsigned int shift;
270 unsigned long flags;
271
272 if (gpio < 16) {
273 reg = mm->regs + GPIO_ICR;
274 shift = (15 - gpio) * 2;
275 } else {
276 reg = mm->regs + GPIO_ICR2;
277 shift = (15 - (gpio % 16)) * 2;
278 }
279
280 switch (flow_type) {
281 case IRQ_TYPE_EDGE_FALLING:
282 case IRQ_TYPE_LEVEL_LOW:
283 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
284 clrsetbits_be32(reg, 3 << shift, 2 << shift);
285 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
286 break;
287
288 case IRQ_TYPE_EDGE_RISING:
289 case IRQ_TYPE_LEVEL_HIGH:
290 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
291 clrsetbits_be32(reg, 3 << shift, 1 << shift);
292 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
293 break;
294
295 case IRQ_TYPE_EDGE_BOTH:
296 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
297 clrbits32(reg, 3 << shift);
298 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
299 break;
300
301 default:
302 return -EINVAL;
303 }
304
305 return 0;
306}
307
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100308static struct irq_chip mpc8xxx_irq_chip = {
309 .name = "mpc8xxx-gpio",
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000310 .irq_unmask = mpc8xxx_irq_unmask,
311 .irq_mask = mpc8xxx_irq_mask,
312 .irq_ack = mpc8xxx_irq_ack,
313 .irq_set_type = mpc8xxx_irq_set_type,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100314};
315
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200316static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
317 irq_hw_number_t hwirq)
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100318{
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200319 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
320
321 if (mpc8xxx_gc->of_dev_id_data)
Lennert Buytenhek94347cb2011-03-08 22:26:58 +0000322 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200323
Linus Walleij5ba17ae2013-10-11 19:37:30 +0200324 irq_set_chip_data(irq, h->host_data);
325 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100326
327 return 0;
328}
329
Grant Likelybae1d8f2012-02-14 14:06:50 -0700330static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100331 .map = mpc8xxx_gpio_irq_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700332 .xlate = irq_domain_xlate_twocell,
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100333};
334
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200335static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
336 { .compatible = "fsl,mpc8349-gpio", },
337 { .compatible = "fsl,mpc8572-gpio", },
338 { .compatible = "fsl,mpc8610-gpio", },
339 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
Kumar Gala15a51482011-10-22 16:20:42 -0500340 { .compatible = "fsl,pq3-gpio", },
Anatolij Gustschind1dcfbb2011-01-08 16:51:16 +0100341 { .compatible = "fsl,qoriq-gpio", },
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200342 {}
343};
344
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200345static void __init mpc8xxx_add_controller(struct device_node *np)
346{
347 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
348 struct of_mm_gpio_chip *mm_gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200349 struct gpio_chip *gc;
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200350 const struct of_device_id *id;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100351 unsigned hwirq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200352 int ret;
353
354 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
355 if (!mpc8xxx_gc) {
356 ret = -ENOMEM;
357 goto err;
358 }
359
360 spin_lock_init(&mpc8xxx_gc->lock);
361
362 mm_gc = &mpc8xxx_gc->mm_gc;
Anton Vorontsova19e3da2010-06-08 07:48:16 -0600363 gc = &mm_gc->gc;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200364
365 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200366 gc->ngpio = MPC8XXX_GPIO_PINS;
367 gc->direction_input = mpc8xxx_gpio_dir_in;
Wolfram Sang28538df2011-12-13 10:12:48 +0100368 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
369 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
370 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
371 mpc8572_gpio_get : mpc8xxx_gpio_get;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200372 gc->set = mpc8xxx_gpio_set;
Rojhalat Ibrahime5db3b32014-11-04 17:12:09 +0100373 gc->set_multiple = mpc8xxx_gpio_set_multiple;
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100374 gc->to_irq = mpc8xxx_gpio_to_irq;
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200375
376 ret = of_mm_gpiochip_add(np, mm_gc);
377 if (ret)
378 goto err;
379
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100380 hwirq = irq_of_parse_and_map(np, 0);
381 if (hwirq == NO_IRQ)
382 goto skip_irq;
383
Grant Likelya8db8cf2012-02-14 14:06:54 -0700384 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
385 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100386 if (!mpc8xxx_gc->irq)
387 goto skip_irq;
388
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200389 id = of_match_node(mpc8xxx_gpio_ids, np);
390 if (id)
391 mpc8xxx_gc->of_dev_id_data = id->data;
392
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100393 /* ack and mask all irqs */
394 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
395 out_be32(mm_gc->regs + GPIO_IMR, 0);
396
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100397 irq_set_handler_data(hwirq, mpc8xxx_gc);
398 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
Peter Korsgaard345e5c82010-01-07 17:57:46 +0100399
400skip_irq:
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200401 return;
402
403err:
404 pr_err("%s: registration failed with status %d\n",
405 np->full_name, ret);
406 kfree(mpc8xxx_gc);
407
408 return;
409}
410
411static int __init mpc8xxx_add_gpiochips(void)
412{
413 struct device_node *np;
414
Anatolij Gustschine39d5ef2010-08-09 07:58:48 +0200415 for_each_matching_node(np, mpc8xxx_gpio_ids)
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200416 mpc8xxx_add_controller(np);
417
Peter Korsgaard1e16dfc2008-09-23 17:35:38 +0200418 return 0;
419}
420arch_initcall(mpc8xxx_add_gpiochips);