Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 1 | /* |
| 2 | * DMM IOMMU driver support functions for TI OMAP processors. |
| 3 | * |
| 4 | * Author: Rob Clark <rob@ti.com> |
| 5 | * Andy Gross <andy.gross@ti.com> |
| 6 | * |
| 7 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation version 2. |
| 12 | * |
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 14 | * kind, whether express or implied; without even the implied warranty |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
Laurent Pinchart | 2d278f5 | 2015-03-05 21:31:37 +0200 | [diff] [blame] | 18 | |
| 19 | #include <linux/completion.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/errno.h> |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 23 | #include <linux/init.h> |
Laurent Pinchart | 2d278f5 | 2015-03-05 21:31:37 +0200 | [diff] [blame] | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/list.h> |
| 26 | #include <linux/mm.h> |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 27 | #include <linux/module.h> |
| 28 | #include <linux/platform_device.h> /* platform_device() */ |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 29 | #include <linux/sched.h> |
Arnd Bergmann | 2d80245 | 2016-05-11 18:01:45 +0200 | [diff] [blame] | 30 | #include <linux/seq_file.h> |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 31 | #include <linux/slab.h> |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 32 | #include <linux/time.h> |
Laurent Pinchart | 2d278f5 | 2015-03-05 21:31:37 +0200 | [diff] [blame] | 33 | #include <linux/vmalloc.h> |
| 34 | #include <linux/wait.h> |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 35 | |
| 36 | #include "omap_dmm_tiler.h" |
| 37 | #include "omap_dmm_priv.h" |
| 38 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 39 | #define DMM_DRIVER_NAME "dmm" |
| 40 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 41 | /* mappings for associating views to luts */ |
| 42 | static struct tcm *containers[TILFMT_NFORMATS]; |
| 43 | static struct dmm *omap_dmm; |
| 44 | |
Tomi Valkeinen | 7cb0d6c | 2014-09-25 19:24:29 +0000 | [diff] [blame] | 45 | #if defined(CONFIG_OF) |
| 46 | static const struct of_device_id dmm_of_match[]; |
| 47 | #endif |
| 48 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 49 | /* global spinlock for protecting lists */ |
| 50 | static DEFINE_SPINLOCK(list_lock); |
| 51 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 52 | /* Geometry table */ |
| 53 | #define GEOM(xshift, yshift, bytes_per_pixel) { \ |
| 54 | .x_shft = (xshift), \ |
| 55 | .y_shft = (yshift), \ |
| 56 | .cpp = (bytes_per_pixel), \ |
| 57 | .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \ |
| 58 | .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \ |
| 59 | } |
| 60 | |
| 61 | static const struct { |
| 62 | uint32_t x_shft; /* unused X-bits (as part of bpp) */ |
| 63 | uint32_t y_shft; /* unused Y-bits (as part of bpp) */ |
| 64 | uint32_t cpp; /* bytes/chars per pixel */ |
| 65 | uint32_t slot_w; /* width of each slot (in pixels) */ |
| 66 | uint32_t slot_h; /* height of each slot (in pixels) */ |
| 67 | } geom[TILFMT_NFORMATS] = { |
Laurent Pinchart | 222025e | 2015-01-11 00:02:07 +0200 | [diff] [blame] | 68 | [TILFMT_8BIT] = GEOM(0, 0, 1), |
| 69 | [TILFMT_16BIT] = GEOM(0, 1, 2), |
| 70 | [TILFMT_32BIT] = GEOM(1, 1, 4), |
| 71 | [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1), |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | |
| 75 | /* lookup table for registers w/ per-engine instances */ |
| 76 | static const uint32_t reg[][4] = { |
Laurent Pinchart | 222025e | 2015-01-11 00:02:07 +0200 | [diff] [blame] | 77 | [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1, |
| 78 | DMM_PAT_STATUS__2, DMM_PAT_STATUS__3}, |
| 79 | [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1, |
| 80 | DMM_PAT_DESCR__2, DMM_PAT_DESCR__3}, |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 81 | }; |
| 82 | |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 83 | static u32 dmm_read(struct dmm *dmm, u32 reg) |
| 84 | { |
| 85 | return readl(dmm->base + reg); |
| 86 | } |
| 87 | |
| 88 | static void dmm_write(struct dmm *dmm, u32 val, u32 reg) |
| 89 | { |
| 90 | writel(val, dmm->base + reg); |
| 91 | } |
| 92 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 93 | /* simple allocator to grab next 16 byte aligned memory from txn */ |
| 94 | static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa) |
| 95 | { |
| 96 | void *ptr; |
| 97 | struct refill_engine *engine = txn->engine_handle; |
| 98 | |
| 99 | /* dmm programming requires 16 byte aligned addresses */ |
| 100 | txn->current_pa = round_up(txn->current_pa, 16); |
| 101 | txn->current_va = (void *)round_up((long)txn->current_va, 16); |
| 102 | |
| 103 | ptr = txn->current_va; |
| 104 | *pa = txn->current_pa; |
| 105 | |
| 106 | txn->current_pa += sz; |
| 107 | txn->current_va += sz; |
| 108 | |
| 109 | BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); |
| 110 | |
| 111 | return ptr; |
| 112 | } |
| 113 | |
| 114 | /* check status and spin until wait_mask comes true */ |
| 115 | static int wait_status(struct refill_engine *engine, uint32_t wait_mask) |
| 116 | { |
| 117 | struct dmm *dmm = engine->dmm; |
| 118 | uint32_t r = 0, err, i; |
| 119 | |
| 120 | i = DMM_FIXED_RETRY_COUNT; |
| 121 | while (true) { |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 122 | r = dmm_read(dmm, reg[PAT_STATUS][engine->id]); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 123 | err = r & DMM_PATSTATUS_ERR; |
| 124 | if (err) |
| 125 | return -EFAULT; |
| 126 | |
| 127 | if ((r & wait_mask) == wait_mask) |
| 128 | break; |
| 129 | |
| 130 | if (--i == 0) |
| 131 | return -ETIMEDOUT; |
| 132 | |
| 133 | udelay(1); |
| 134 | } |
| 135 | |
| 136 | return 0; |
| 137 | } |
| 138 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 139 | static void release_engine(struct refill_engine *engine) |
| 140 | { |
| 141 | unsigned long flags; |
| 142 | |
| 143 | spin_lock_irqsave(&list_lock, flags); |
| 144 | list_add(&engine->idle_node, &omap_dmm->idle_head); |
| 145 | spin_unlock_irqrestore(&list_lock, flags); |
| 146 | |
| 147 | atomic_inc(&omap_dmm->engine_counter); |
| 148 | wake_up_interruptible(&omap_dmm->engine_queue); |
| 149 | } |
| 150 | |
Andy Gross | d7de993 | 2012-08-09 00:14:56 -0500 | [diff] [blame] | 151 | static irqreturn_t omap_dmm_irq_handler(int irq, void *arg) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 152 | { |
| 153 | struct dmm *dmm = arg; |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 154 | uint32_t status = dmm_read(dmm, DMM_PAT_IRQSTATUS); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 155 | int i; |
| 156 | |
| 157 | /* ack IRQ */ |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 158 | dmm_write(dmm, status, DMM_PAT_IRQSTATUS); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 159 | |
| 160 | for (i = 0; i < dmm->num_engines; i++) { |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 161 | if (status & DMM_IRQSTAT_LST) { |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 162 | if (dmm->engines[i].async) |
| 163 | release_engine(&dmm->engines[i]); |
Tomi Valkeinen | 7439507 | 2014-12-17 14:34:23 +0200 | [diff] [blame] | 164 | |
| 165 | complete(&dmm->engines[i].compl); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 166 | } |
| 167 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 168 | status >>= 8; |
| 169 | } |
| 170 | |
| 171 | return IRQ_HANDLED; |
| 172 | } |
| 173 | |
| 174 | /** |
| 175 | * Get a handle for a DMM transaction |
| 176 | */ |
| 177 | static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm) |
| 178 | { |
| 179 | struct dmm_txn *txn = NULL; |
| 180 | struct refill_engine *engine = NULL; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 181 | int ret; |
| 182 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 183 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 184 | |
| 185 | /* wait until an engine is available */ |
| 186 | ret = wait_event_interruptible(omap_dmm->engine_queue, |
| 187 | atomic_add_unless(&omap_dmm->engine_counter, -1, 0)); |
| 188 | if (ret) |
| 189 | return ERR_PTR(ret); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 190 | |
| 191 | /* grab an idle engine */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 192 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 193 | if (!list_empty(&dmm->idle_head)) { |
| 194 | engine = list_entry(dmm->idle_head.next, struct refill_engine, |
| 195 | idle_node); |
| 196 | list_del(&engine->idle_node); |
| 197 | } |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 198 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 199 | |
| 200 | BUG_ON(!engine); |
| 201 | |
| 202 | txn = &engine->txn; |
| 203 | engine->tcm = tcm; |
| 204 | txn->engine_handle = engine; |
| 205 | txn->last_pat = NULL; |
| 206 | txn->current_va = engine->refill_va; |
| 207 | txn->current_pa = engine->refill_pa; |
| 208 | |
| 209 | return txn; |
| 210 | } |
| 211 | |
| 212 | /** |
| 213 | * Add region to DMM transaction. If pages or pages[i] is NULL, then the |
| 214 | * corresponding slot is cleared (ie. dummy_pa is programmed) |
| 215 | */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 216 | static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 217 | struct page **pages, uint32_t npages, uint32_t roll) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 218 | { |
Russell King | 2d31ca3 | 2014-07-12 10:53:41 +0100 | [diff] [blame] | 219 | dma_addr_t pat_pa = 0, data_pa = 0; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 220 | uint32_t *data; |
| 221 | struct pat *pat; |
| 222 | struct refill_engine *engine = txn->engine_handle; |
| 223 | int columns = (1 + area->x1 - area->x0); |
| 224 | int rows = (1 + area->y1 - area->y0); |
| 225 | int i = columns*rows; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 226 | |
| 227 | pat = alloc_dma(txn, sizeof(struct pat), &pat_pa); |
| 228 | |
| 229 | if (txn->last_pat) |
| 230 | txn->last_pat->next_pa = (uint32_t)pat_pa; |
| 231 | |
| 232 | pat->area = *area; |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 233 | |
| 234 | /* adjust Y coordinates based off of container parameters */ |
| 235 | pat->area.y0 += engine->tcm->y_offset; |
| 236 | pat->area.y1 += engine->tcm->y_offset; |
| 237 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 238 | pat->ctrl = (struct pat_ctrl){ |
| 239 | .start = 1, |
| 240 | .lut_id = engine->tcm->lut_id, |
| 241 | }; |
| 242 | |
Russell King | 2d31ca3 | 2014-07-12 10:53:41 +0100 | [diff] [blame] | 243 | data = alloc_dma(txn, 4*i, &data_pa); |
| 244 | /* FIXME: what if data_pa is more than 32-bit ? */ |
| 245 | pat->data_pa = data_pa; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 246 | |
| 247 | while (i--) { |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 248 | int n = i + roll; |
| 249 | if (n >= npages) |
| 250 | n -= npages; |
| 251 | data[i] = (pages && pages[n]) ? |
| 252 | page_to_phys(pages[n]) : engine->dmm->dummy_pa; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 253 | } |
| 254 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 255 | txn->last_pat = pat; |
| 256 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 257 | return; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | /** |
| 261 | * Commit the DMM transaction. |
| 262 | */ |
| 263 | static int dmm_txn_commit(struct dmm_txn *txn, bool wait) |
| 264 | { |
| 265 | int ret = 0; |
| 266 | struct refill_engine *engine = txn->engine_handle; |
| 267 | struct dmm *dmm = engine->dmm; |
| 268 | |
| 269 | if (!txn->last_pat) { |
| 270 | dev_err(engine->dmm->dev, "need at least one txn\n"); |
| 271 | ret = -EINVAL; |
| 272 | goto cleanup; |
| 273 | } |
| 274 | |
| 275 | txn->last_pat->next_pa = 0; |
Tomi Valkeinen | 4bdf5ec | 2018-09-26 12:11:27 +0300 | [diff] [blame] | 276 | /* ensure that the written descriptors are visible to DMM */ |
| 277 | wmb(); |
| 278 | |
| 279 | /* |
| 280 | * NOTE: the wmb() above should be enough, but there seems to be a bug |
| 281 | * in OMAP's memory barrier implementation, which in some rare cases may |
| 282 | * cause the writes not to be observable after wmb(). |
| 283 | */ |
| 284 | |
| 285 | /* read back to ensure the data is in RAM */ |
| 286 | readl(&txn->last_pat->next_pa); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 287 | |
| 288 | /* write to PAT_DESCR to clear out any pending transaction */ |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 289 | dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 290 | |
| 291 | /* wait for engine ready: */ |
| 292 | ret = wait_status(engine, DMM_PATSTATUS_READY); |
| 293 | if (ret) { |
| 294 | ret = -EFAULT; |
| 295 | goto cleanup; |
| 296 | } |
| 297 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 298 | /* mark whether it is async to denote list management in IRQ handler */ |
| 299 | engine->async = wait ? false : true; |
Tomi Valkeinen | 7439507 | 2014-12-17 14:34:23 +0200 | [diff] [blame] | 300 | reinit_completion(&engine->compl); |
| 301 | /* verify that the irq handler sees the 'async' and completion value */ |
Tomi Valkeinen | e7e24df | 2014-11-10 12:23:01 +0200 | [diff] [blame] | 302 | smp_mb(); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 303 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 304 | /* kick reload */ |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 305 | dmm_write(dmm, engine->refill_pa, reg[PAT_DESCR][engine->id]); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 306 | |
| 307 | if (wait) { |
Tomi Valkeinen | 7439507 | 2014-12-17 14:34:23 +0200 | [diff] [blame] | 308 | if (!wait_for_completion_timeout(&engine->compl, |
Tomi Valkeinen | 96cbd14 | 2015-04-28 14:01:32 +0300 | [diff] [blame] | 309 | msecs_to_jiffies(100))) { |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 310 | dev_err(dmm->dev, "timed out waiting for done\n"); |
| 311 | ret = -ETIMEDOUT; |
Peter Ujfalusi | abb3ee3 | 2017-09-29 14:49:49 +0300 | [diff] [blame] | 312 | goto cleanup; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 313 | } |
Peter Ujfalusi | abb3ee3 | 2017-09-29 14:49:49 +0300 | [diff] [blame] | 314 | |
| 315 | /* Check the engine status before continue */ |
| 316 | ret = wait_status(engine, DMM_PATSTATUS_READY | |
| 317 | DMM_PATSTATUS_VALID | DMM_PATSTATUS_DONE); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | cleanup: |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 321 | /* only place engine back on list if we are done with it */ |
| 322 | if (ret || wait) |
| 323 | release_engine(engine); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 324 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 325 | return ret; |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * DMM programming |
| 330 | */ |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 331 | static int fill(struct tcm_area *area, struct page **pages, |
| 332 | uint32_t npages, uint32_t roll, bool wait) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 333 | { |
| 334 | int ret = 0; |
| 335 | struct tcm_area slice, area_s; |
| 336 | struct dmm_txn *txn; |
| 337 | |
Tomi Valkeinen | 2bb2daf | 2015-04-28 14:01:34 +0300 | [diff] [blame] | 338 | /* |
| 339 | * FIXME |
| 340 | * |
| 341 | * Asynchronous fill does not work reliably, as the driver does not |
| 342 | * handle errors in the async code paths. The fill operation may |
| 343 | * silently fail, leading to leaking DMM engines, which may eventually |
| 344 | * lead to deadlock if we run out of DMM engines. |
| 345 | * |
| 346 | * For now, always set 'wait' so that we only use sync fills. Async |
| 347 | * fills should be fixed, or alternatively we could decide to only |
| 348 | * support sync fills and so the whole async code path could be removed. |
| 349 | */ |
| 350 | |
| 351 | wait = true; |
| 352 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 353 | txn = dmm_txn_init(omap_dmm, area->tcm); |
| 354 | if (IS_ERR_OR_NULL(txn)) |
Andy Gross | 295c799 | 2012-11-16 13:10:57 -0600 | [diff] [blame] | 355 | return -ENOMEM; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 356 | |
| 357 | tcm_for_each_slice(slice, *area, area_s) { |
| 358 | struct pat_area p_area = { |
| 359 | .x0 = slice.p0.x, .y0 = slice.p0.y, |
| 360 | .x1 = slice.p1.x, .y1 = slice.p1.y, |
| 361 | }; |
| 362 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 363 | dmm_txn_append(txn, &p_area, pages, npages, roll); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 364 | |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 365 | roll += tcm_sizeof(slice); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | ret = dmm_txn_commit(txn, wait); |
| 369 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 370 | return ret; |
| 371 | } |
| 372 | |
| 373 | /* |
| 374 | * Pin/unpin |
| 375 | */ |
| 376 | |
| 377 | /* note: slots for which pages[i] == NULL are filled w/ dummy page |
| 378 | */ |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 379 | int tiler_pin(struct tiler_block *block, struct page **pages, |
| 380 | uint32_t npages, uint32_t roll, bool wait) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 381 | { |
| 382 | int ret; |
| 383 | |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 384 | ret = fill(&block->area, pages, npages, roll, wait); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 385 | |
| 386 | if (ret) |
| 387 | tiler_unpin(block); |
| 388 | |
| 389 | return ret; |
| 390 | } |
| 391 | |
| 392 | int tiler_unpin(struct tiler_block *block) |
| 393 | { |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 394 | return fill(&block->area, NULL, 0, 0, false); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | /* |
| 398 | * Reserve/release |
| 399 | */ |
| 400 | struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, |
| 401 | uint16_t h, uint16_t align) |
| 402 | { |
| 403 | struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); |
| 404 | u32 min_align = 128; |
| 405 | int ret; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 406 | unsigned long flags; |
Andy Gross | 0d6fa53 | 2015-08-12 11:24:38 +0300 | [diff] [blame] | 407 | size_t slot_bytes; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 408 | |
| 409 | BUG_ON(!validfmt(fmt)); |
| 410 | |
| 411 | /* convert width/height to slots */ |
| 412 | w = DIV_ROUND_UP(w, geom[fmt].slot_w); |
| 413 | h = DIV_ROUND_UP(h, geom[fmt].slot_h); |
| 414 | |
| 415 | /* convert alignment to slots */ |
Andy Gross | 0d6fa53 | 2015-08-12 11:24:38 +0300 | [diff] [blame] | 416 | slot_bytes = geom[fmt].slot_w * geom[fmt].cpp; |
| 417 | min_align = max(min_align, slot_bytes); |
| 418 | align = (align > min_align) ? ALIGN(align, min_align) : min_align; |
| 419 | align /= slot_bytes; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 420 | |
| 421 | block->fmt = fmt; |
| 422 | |
Andy Gross | 0d6fa53 | 2015-08-12 11:24:38 +0300 | [diff] [blame] | 423 | ret = tcm_reserve_2d(containers[fmt], w, h, align, -1, slot_bytes, |
| 424 | &block->area); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 425 | if (ret) { |
| 426 | kfree(block); |
Rob Clark | 1c3a4dc | 2012-03-21 16:40:23 -0500 | [diff] [blame] | 427 | return ERR_PTR(-ENOMEM); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | /* add to allocation list */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 431 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 432 | list_add(&block->alloc_node, &omap_dmm->alloc_head); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 433 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 434 | |
| 435 | return block; |
| 436 | } |
| 437 | |
| 438 | struct tiler_block *tiler_reserve_1d(size_t size) |
| 439 | { |
| 440 | struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); |
| 441 | int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 442 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 443 | |
| 444 | if (!block) |
Andy Gross | d7de993 | 2012-08-09 00:14:56 -0500 | [diff] [blame] | 445 | return ERR_PTR(-ENOMEM); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 446 | |
| 447 | block->fmt = TILFMT_PAGE; |
| 448 | |
| 449 | if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages, |
| 450 | &block->area)) { |
| 451 | kfree(block); |
Rob Clark | 1c3a4dc | 2012-03-21 16:40:23 -0500 | [diff] [blame] | 452 | return ERR_PTR(-ENOMEM); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 453 | } |
| 454 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 455 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 456 | list_add(&block->alloc_node, &omap_dmm->alloc_head); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 457 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 458 | |
| 459 | return block; |
| 460 | } |
| 461 | |
| 462 | /* note: if you have pin'd pages, you should have already unpin'd first! */ |
| 463 | int tiler_release(struct tiler_block *block) |
| 464 | { |
| 465 | int ret = tcm_free(&block->area); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 466 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 467 | |
| 468 | if (block->area.tcm) |
| 469 | dev_err(omap_dmm->dev, "failed to release block\n"); |
| 470 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 471 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 472 | list_del(&block->alloc_node); |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 473 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 474 | |
| 475 | kfree(block); |
| 476 | return ret; |
| 477 | } |
| 478 | |
| 479 | /* |
| 480 | * Utils |
| 481 | */ |
| 482 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 483 | /* calculate the tiler space address of a pixel in a view orientation... |
| 484 | * below description copied from the display subsystem section of TRM: |
| 485 | * |
| 486 | * When the TILER is addressed, the bits: |
| 487 | * [28:27] = 0x0 for 8-bit tiled |
| 488 | * 0x1 for 16-bit tiled |
| 489 | * 0x2 for 32-bit tiled |
| 490 | * 0x3 for page mode |
| 491 | * [31:29] = 0x0 for 0-degree view |
| 492 | * 0x1 for 180-degree view + mirroring |
| 493 | * 0x2 for 0-degree view + mirroring |
| 494 | * 0x3 for 180-degree view |
| 495 | * 0x4 for 270-degree view + mirroring |
| 496 | * 0x5 for 270-degree view |
| 497 | * 0x6 for 90-degree view |
| 498 | * 0x7 for 90-degree view + mirroring |
| 499 | * Otherwise the bits indicated the corresponding bit address to access |
| 500 | * the SDRAM. |
| 501 | */ |
| 502 | static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 503 | { |
| 504 | u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment; |
| 505 | |
| 506 | x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft; |
| 507 | y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft; |
| 508 | alignment = geom[fmt].x_shft + geom[fmt].y_shft; |
| 509 | |
| 510 | /* validate coordinate */ |
| 511 | x_mask = MASK(x_bits); |
| 512 | y_mask = MASK(y_bits); |
| 513 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 514 | if (x < 0 || x > x_mask || y < 0 || y > y_mask) { |
| 515 | DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u", |
| 516 | x, x, x_mask, y, y, y_mask); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 517 | return 0; |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 518 | } |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 519 | |
| 520 | /* account for mirroring */ |
| 521 | if (orient & MASK_X_INVERT) |
| 522 | x ^= x_mask; |
| 523 | if (orient & MASK_Y_INVERT) |
| 524 | y ^= y_mask; |
| 525 | |
| 526 | /* get coordinate address */ |
| 527 | if (orient & MASK_XY_FLIP) |
| 528 | tmp = ((x << y_bits) + y); |
| 529 | else |
| 530 | tmp = ((y << x_bits) + x); |
| 531 | |
| 532 | return TIL_ADDR((tmp << alignment), orient, fmt); |
| 533 | } |
| 534 | |
| 535 | dma_addr_t tiler_ssptr(struct tiler_block *block) |
| 536 | { |
| 537 | BUG_ON(!validfmt(block->fmt)); |
| 538 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 539 | return TILVIEW_8BIT + tiler_get_address(block->fmt, 0, |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 540 | block->area.p0.x * geom[block->fmt].slot_w, |
| 541 | block->area.p0.y * geom[block->fmt].slot_h); |
| 542 | } |
| 543 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 544 | dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, |
| 545 | uint32_t x, uint32_t y) |
| 546 | { |
| 547 | struct tcm_pt *p = &block->area.p0; |
| 548 | BUG_ON(!validfmt(block->fmt)); |
| 549 | |
| 550 | return tiler_get_address(block->fmt, orient, |
| 551 | (p->x * geom[block->fmt].slot_w) + x, |
| 552 | (p->y * geom[block->fmt].slot_h) + y); |
| 553 | } |
| 554 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 555 | void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h) |
| 556 | { |
| 557 | BUG_ON(!validfmt(fmt)); |
| 558 | *w = round_up(*w, geom[fmt].slot_w); |
| 559 | *h = round_up(*h, geom[fmt].slot_h); |
| 560 | } |
| 561 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 562 | uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 563 | { |
| 564 | BUG_ON(!validfmt(fmt)); |
| 565 | |
Rob Clark | 3c810c6 | 2012-08-15 15:18:01 -0500 | [diff] [blame] | 566 | if (orient & MASK_XY_FLIP) |
| 567 | return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft); |
| 568 | else |
| 569 | return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 570 | } |
| 571 | |
| 572 | size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h) |
| 573 | { |
| 574 | tiler_align(fmt, &w, &h); |
| 575 | return geom[fmt].cpp * w * h; |
| 576 | } |
| 577 | |
| 578 | size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h) |
| 579 | { |
| 580 | BUG_ON(!validfmt(fmt)); |
| 581 | return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h; |
| 582 | } |
| 583 | |
Tomi Valkeinen | 7cb0d6c | 2014-09-25 19:24:29 +0000 | [diff] [blame] | 584 | uint32_t tiler_get_cpu_cache_flags(void) |
| 585 | { |
| 586 | return omap_dmm->plat_data->cpu_cache_flags; |
| 587 | } |
| 588 | |
Andy Gross | e5e4e9b | 2012-10-17 00:30:03 -0500 | [diff] [blame] | 589 | bool dmm_is_available(void) |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 590 | { |
| 591 | return omap_dmm ? true : false; |
| 592 | } |
| 593 | |
| 594 | static int omap_dmm_remove(struct platform_device *dev) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 595 | { |
| 596 | struct tiler_block *block, *_block; |
| 597 | int i; |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 598 | unsigned long flags; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 599 | |
| 600 | if (omap_dmm) { |
| 601 | /* free all area regions */ |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 602 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 603 | list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head, |
| 604 | alloc_node) { |
| 605 | list_del(&block->alloc_node); |
| 606 | kfree(block); |
| 607 | } |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 608 | spin_unlock_irqrestore(&list_lock, flags); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 609 | |
| 610 | for (i = 0; i < omap_dmm->num_lut; i++) |
| 611 | if (omap_dmm->tcm && omap_dmm->tcm[i]) |
| 612 | omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]); |
| 613 | kfree(omap_dmm->tcm); |
| 614 | |
| 615 | kfree(omap_dmm->engines); |
| 616 | if (omap_dmm->refill_va) |
Luis R. Rodriguez | f6e4566 | 2016-01-22 18:34:22 -0800 | [diff] [blame] | 617 | dma_free_wc(omap_dmm->dev, |
| 618 | REFILL_BUFFER_SIZE * omap_dmm->num_engines, |
| 619 | omap_dmm->refill_va, omap_dmm->refill_pa); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 620 | if (omap_dmm->dummy_page) |
| 621 | __free_page(omap_dmm->dummy_page); |
| 622 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 623 | if (omap_dmm->irq > 0) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 624 | free_irq(omap_dmm->irq, omap_dmm); |
| 625 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 626 | iounmap(omap_dmm->base); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 627 | kfree(omap_dmm); |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 628 | omap_dmm = NULL; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | return 0; |
| 632 | } |
| 633 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 634 | static int omap_dmm_probe(struct platform_device *dev) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 635 | { |
| 636 | int ret = -EFAULT, i; |
| 637 | struct tcm_area area = {0}; |
Andy Gross | 0f562d1 | 2012-10-11 23:06:43 -0500 | [diff] [blame] | 638 | u32 hwinfo, pat_geom; |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 639 | struct resource *mem; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 640 | |
| 641 | omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL); |
Joe Perches | 78110bb | 2013-02-11 09:41:29 -0800 | [diff] [blame] | 642 | if (!omap_dmm) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 643 | goto fail; |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 644 | |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 645 | /* initialize lists */ |
| 646 | INIT_LIST_HEAD(&omap_dmm->alloc_head); |
| 647 | INIT_LIST_HEAD(&omap_dmm->idle_head); |
| 648 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 649 | init_waitqueue_head(&omap_dmm->engine_queue); |
| 650 | |
Tomi Valkeinen | 7cb0d6c | 2014-09-25 19:24:29 +0000 | [diff] [blame] | 651 | if (dev->dev.of_node) { |
| 652 | const struct of_device_id *match; |
| 653 | |
| 654 | match = of_match_node(dmm_of_match, dev->dev.of_node); |
| 655 | if (!match) { |
| 656 | dev_err(&dev->dev, "failed to find matching device node\n"); |
Christophe JAILLET | 9301165 | 2017-09-24 08:01:03 +0200 | [diff] [blame] | 657 | ret = -ENODEV; |
| 658 | goto fail; |
Tomi Valkeinen | 7cb0d6c | 2014-09-25 19:24:29 +0000 | [diff] [blame] | 659 | } |
| 660 | |
| 661 | omap_dmm->plat_data = match->data; |
| 662 | } |
| 663 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 664 | /* lookup hwmod data - base address and irq */ |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 665 | mem = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 666 | if (!mem) { |
| 667 | dev_err(&dev->dev, "failed to get base address resource\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 668 | goto fail; |
| 669 | } |
| 670 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 671 | omap_dmm->base = ioremap(mem->start, SZ_2K); |
| 672 | |
| 673 | if (!omap_dmm->base) { |
| 674 | dev_err(&dev->dev, "failed to get dmm base address\n"); |
| 675 | goto fail; |
| 676 | } |
| 677 | |
| 678 | omap_dmm->irq = platform_get_irq(dev, 0); |
| 679 | if (omap_dmm->irq < 0) { |
| 680 | dev_err(&dev->dev, "failed to get IRQ resource\n"); |
| 681 | goto fail; |
| 682 | } |
| 683 | |
| 684 | omap_dmm->dev = &dev->dev; |
| 685 | |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 686 | hwinfo = dmm_read(omap_dmm, DMM_PAT_HWINFO); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 687 | omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; |
| 688 | omap_dmm->num_lut = (hwinfo >> 16) & 0x1F; |
| 689 | omap_dmm->container_width = 256; |
| 690 | omap_dmm->container_height = 128; |
| 691 | |
Andy Gross | faaa054 | 2012-10-12 11:18:11 -0500 | [diff] [blame] | 692 | atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); |
| 693 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 694 | /* read out actual LUT width and height */ |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 695 | pat_geom = dmm_read(omap_dmm, DMM_PAT_GEOMETRY); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 696 | omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5; |
| 697 | omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5; |
| 698 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 699 | /* increment LUT by one if on OMAP5 */ |
| 700 | /* LUT has twice the height, and is split into a separate container */ |
| 701 | if (omap_dmm->lut_height != omap_dmm->container_height) |
| 702 | omap_dmm->num_lut++; |
| 703 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 704 | /* initialize DMM registers */ |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 705 | dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__0); |
| 706 | dmm_write(omap_dmm, 0x88888888, DMM_PAT_VIEW__1); |
| 707 | dmm_write(omap_dmm, 0x80808080, DMM_PAT_VIEW_MAP__0); |
| 708 | dmm_write(omap_dmm, 0x80000000, DMM_PAT_VIEW_MAP_BASE); |
| 709 | dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__0); |
| 710 | dmm_write(omap_dmm, 0x88888888, DMM_TILER_OR__1); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 711 | |
| 712 | ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED, |
| 713 | "omap_dmm_irq_handler", omap_dmm); |
| 714 | |
| 715 | if (ret) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 716 | dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n", |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 717 | omap_dmm->irq, ret); |
| 718 | omap_dmm->irq = -1; |
| 719 | goto fail; |
| 720 | } |
| 721 | |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 722 | /* Enable all interrupts for each refill engine except |
| 723 | * ERR_LUT_MISS<n> (which is just advisory, and we don't care |
| 724 | * about because we want to be able to refill live scanout |
| 725 | * buffers for accelerated pan/scroll) and FILL_DSC<n> which |
| 726 | * we just generally don't care about. |
| 727 | */ |
Tomi Valkeinen | 8e54adf | 2015-08-07 14:31:28 +0300 | [diff] [blame] | 728 | dmm_write(omap_dmm, 0x7e7e7e7e, DMM_PAT_IRQENABLE_SET); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 729 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 730 | omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32); |
| 731 | if (!omap_dmm->dummy_page) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 732 | dev_err(&dev->dev, "could not allocate dummy page\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 733 | ret = -ENOMEM; |
| 734 | goto fail; |
| 735 | } |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 736 | |
| 737 | /* set dma mask for device */ |
Russell King | d6cfaab | 2013-06-10 18:41:59 +0100 | [diff] [blame] | 738 | ret = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); |
| 739 | if (ret) |
| 740 | goto fail; |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 741 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 742 | omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page); |
| 743 | |
| 744 | /* alloc refill memory */ |
Luis R. Rodriguez | f6e4566 | 2016-01-22 18:34:22 -0800 | [diff] [blame] | 745 | omap_dmm->refill_va = dma_alloc_wc(&dev->dev, |
| 746 | REFILL_BUFFER_SIZE * omap_dmm->num_engines, |
| 747 | &omap_dmm->refill_pa, GFP_KERNEL); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 748 | if (!omap_dmm->refill_va) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 749 | dev_err(&dev->dev, "could not allocate refill memory\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 750 | goto fail; |
| 751 | } |
| 752 | |
| 753 | /* alloc engines */ |
Joe Perches | 78110bb | 2013-02-11 09:41:29 -0800 | [diff] [blame] | 754 | omap_dmm->engines = kcalloc(omap_dmm->num_engines, |
| 755 | sizeof(struct refill_engine), GFP_KERNEL); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 756 | if (!omap_dmm->engines) { |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 757 | ret = -ENOMEM; |
| 758 | goto fail; |
| 759 | } |
| 760 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 761 | for (i = 0; i < omap_dmm->num_engines; i++) { |
| 762 | omap_dmm->engines[i].id = i; |
| 763 | omap_dmm->engines[i].dmm = omap_dmm; |
| 764 | omap_dmm->engines[i].refill_va = omap_dmm->refill_va + |
| 765 | (REFILL_BUFFER_SIZE * i); |
| 766 | omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + |
| 767 | (REFILL_BUFFER_SIZE * i); |
Tomi Valkeinen | 7439507 | 2014-12-17 14:34:23 +0200 | [diff] [blame] | 768 | init_completion(&omap_dmm->engines[i].compl); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 769 | |
| 770 | list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head); |
| 771 | } |
| 772 | |
Joe Perches | 78110bb | 2013-02-11 09:41:29 -0800 | [diff] [blame] | 773 | omap_dmm->tcm = kcalloc(omap_dmm->num_lut, sizeof(*omap_dmm->tcm), |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 774 | GFP_KERNEL); |
| 775 | if (!omap_dmm->tcm) { |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 776 | ret = -ENOMEM; |
| 777 | goto fail; |
| 778 | } |
| 779 | |
| 780 | /* init containers */ |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 781 | /* Each LUT is associated with a TCM (container manager). We use the |
| 782 | lut_id to denote the lut_id used to identify the correct LUT for |
| 783 | programming during reill operations */ |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 784 | for (i = 0; i < omap_dmm->num_lut; i++) { |
| 785 | omap_dmm->tcm[i] = sita_init(omap_dmm->container_width, |
Andy Gross | 0d6fa53 | 2015-08-12 11:24:38 +0300 | [diff] [blame] | 786 | omap_dmm->container_height); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 787 | |
| 788 | if (!omap_dmm->tcm[i]) { |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 789 | dev_err(&dev->dev, "failed to allocate container\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 790 | ret = -ENOMEM; |
| 791 | goto fail; |
| 792 | } |
| 793 | |
| 794 | omap_dmm->tcm[i]->lut_id = i; |
| 795 | } |
| 796 | |
| 797 | /* assign access mode containers to applicable tcm container */ |
| 798 | /* OMAP 4 has 1 container for all 4 views */ |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 799 | /* OMAP 5 has 2 containers, 1 for 2D and 1 for 1D */ |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 800 | containers[TILFMT_8BIT] = omap_dmm->tcm[0]; |
| 801 | containers[TILFMT_16BIT] = omap_dmm->tcm[0]; |
| 802 | containers[TILFMT_32BIT] = omap_dmm->tcm[0]; |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 803 | |
| 804 | if (omap_dmm->container_height != omap_dmm->lut_height) { |
| 805 | /* second LUT is used for PAGE mode. Programming must use |
| 806 | y offset that is added to all y coordinates. LUT id is still |
| 807 | 0, because it is the same LUT, just the upper 128 lines */ |
| 808 | containers[TILFMT_PAGE] = omap_dmm->tcm[1]; |
| 809 | omap_dmm->tcm[1]->y_offset = OMAP5_LUT_OFFSET; |
| 810 | omap_dmm->tcm[1]->lut_id = 0; |
| 811 | } else { |
| 812 | containers[TILFMT_PAGE] = omap_dmm->tcm[0]; |
| 813 | } |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 814 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 815 | area = (struct tcm_area) { |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 816 | .tcm = NULL, |
| 817 | .p1.x = omap_dmm->container_width - 1, |
| 818 | .p1.y = omap_dmm->container_height - 1, |
| 819 | }; |
| 820 | |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 821 | /* initialize all LUTs to dummy page entries */ |
| 822 | for (i = 0; i < omap_dmm->num_lut; i++) { |
| 823 | area.tcm = omap_dmm->tcm[i]; |
Rob Clark | a6a9182 | 2011-12-09 23:26:08 -0600 | [diff] [blame] | 824 | if (fill(&area, NULL, 0, 0, true)) |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 825 | dev_err(omap_dmm->dev, "refill failed"); |
| 826 | } |
| 827 | |
| 828 | dev_info(omap_dmm->dev, "initialized all PAT entries\n"); |
| 829 | |
| 830 | return 0; |
| 831 | |
| 832 | fail: |
Andy Gross | ef44593 | 2012-05-24 11:43:32 -0500 | [diff] [blame] | 833 | if (omap_dmm_remove(dev)) |
| 834 | dev_err(&dev->dev, "cleanup failed\n"); |
Andy Gross | 71e8831 | 2011-12-05 19:19:21 -0600 | [diff] [blame] | 835 | return ret; |
| 836 | } |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 837 | |
| 838 | /* |
| 839 | * debugfs support |
| 840 | */ |
| 841 | |
| 842 | #ifdef CONFIG_DEBUG_FS |
| 843 | |
| 844 | static const char *alphabet = "abcdefghijklmnopqrstuvwxyz" |
| 845 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789"; |
| 846 | static const char *special = ".,:;'\"`~!^-+"; |
| 847 | |
| 848 | static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a, |
| 849 | char c, bool ovw) |
| 850 | { |
| 851 | int x, y; |
| 852 | for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++) |
| 853 | for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++) |
| 854 | if (map[y][x] == ' ' || ovw) |
| 855 | map[y][x] = c; |
| 856 | } |
| 857 | |
| 858 | static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p, |
| 859 | char c) |
| 860 | { |
| 861 | map[p->y / ydiv][p->x / xdiv] = c; |
| 862 | } |
| 863 | |
| 864 | static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p) |
| 865 | { |
| 866 | return map[p->y / ydiv][p->x / xdiv]; |
| 867 | } |
| 868 | |
| 869 | static int map_width(int xdiv, int x0, int x1) |
| 870 | { |
| 871 | return (x1 / xdiv) - (x0 / xdiv) + 1; |
| 872 | } |
| 873 | |
| 874 | static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1) |
| 875 | { |
| 876 | char *p = map[yd] + (x0 / xdiv); |
| 877 | int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2; |
| 878 | if (w >= 0) { |
| 879 | p += w; |
| 880 | while (*nice) |
| 881 | *p++ = *nice++; |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | static void map_1d_info(char **map, int xdiv, int ydiv, char *nice, |
| 886 | struct tcm_area *a) |
| 887 | { |
| 888 | sprintf(nice, "%dK", tcm_sizeof(*a) * 4); |
| 889 | if (a->p0.y + 1 < a->p1.y) { |
| 890 | text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0, |
| 891 | 256 - 1); |
| 892 | } else if (a->p0.y < a->p1.y) { |
| 893 | if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1)) |
| 894 | text_map(map, xdiv, nice, a->p0.y / ydiv, |
| 895 | a->p0.x + xdiv, 256 - 1); |
| 896 | else if (strlen(nice) < map_width(xdiv, 0, a->p1.x)) |
| 897 | text_map(map, xdiv, nice, a->p1.y / ydiv, |
| 898 | 0, a->p1.y - xdiv); |
| 899 | } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) { |
| 900 | text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x); |
| 901 | } |
| 902 | } |
| 903 | |
| 904 | static void map_2d_info(char **map, int xdiv, int ydiv, char *nice, |
| 905 | struct tcm_area *a) |
| 906 | { |
| 907 | sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a)); |
| 908 | if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) |
| 909 | text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, |
| 910 | a->p0.x, a->p1.x); |
| 911 | } |
| 912 | |
| 913 | int tiler_map_show(struct seq_file *s, void *arg) |
| 914 | { |
| 915 | int xdiv = 2, ydiv = 1; |
| 916 | char **map = NULL, *global_map; |
| 917 | struct tiler_block *block; |
| 918 | struct tcm_area a, p; |
| 919 | int i; |
| 920 | const char *m2d = alphabet; |
| 921 | const char *a2d = special; |
| 922 | const char *m2dp = m2d, *a2dp = a2d; |
| 923 | char nice[128]; |
Andy Gross | 02646fb | 2012-03-05 10:48:38 -0600 | [diff] [blame] | 924 | int h_adj; |
| 925 | int w_adj; |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 926 | unsigned long flags; |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 927 | int lut_idx; |
| 928 | |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 929 | |
Andy Gross | 02646fb | 2012-03-05 10:48:38 -0600 | [diff] [blame] | 930 | if (!omap_dmm) { |
| 931 | /* early return if dmm/tiler device is not initialized */ |
| 932 | return 0; |
| 933 | } |
| 934 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 935 | h_adj = omap_dmm->container_height / ydiv; |
| 936 | w_adj = omap_dmm->container_width / xdiv; |
Andy Gross | 02646fb | 2012-03-05 10:48:38 -0600 | [diff] [blame] | 937 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 938 | map = kmalloc(h_adj * sizeof(*map), GFP_KERNEL); |
| 939 | global_map = kmalloc((w_adj + 1) * h_adj, GFP_KERNEL); |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 940 | |
| 941 | if (!map || !global_map) |
| 942 | goto error; |
| 943 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 944 | for (lut_idx = 0; lut_idx < omap_dmm->num_lut; lut_idx++) { |
Dan Carpenter | e1e9c90 | 2013-08-22 15:42:50 +0300 | [diff] [blame] | 945 | memset(map, 0, h_adj * sizeof(*map)); |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 946 | memset(global_map, ' ', (w_adj + 1) * h_adj); |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 947 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 948 | for (i = 0; i < omap_dmm->container_height; i++) { |
| 949 | map[i] = global_map + i * (w_adj + 1); |
| 950 | map[i][w_adj] = 0; |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 951 | } |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 952 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 953 | spin_lock_irqsave(&list_lock, flags); |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 954 | |
Andy Gross | c6b7ae55 | 2012-12-19 14:53:38 -0600 | [diff] [blame] | 955 | list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) { |
| 956 | if (block->area.tcm == omap_dmm->tcm[lut_idx]) { |
| 957 | if (block->fmt != TILFMT_PAGE) { |
| 958 | fill_map(map, xdiv, ydiv, &block->area, |
| 959 | *m2dp, true); |
| 960 | if (!*++a2dp) |
| 961 | a2dp = a2d; |
| 962 | if (!*++m2dp) |
| 963 | m2dp = m2d; |
| 964 | map_2d_info(map, xdiv, ydiv, nice, |
| 965 | &block->area); |
| 966 | } else { |
| 967 | bool start = read_map_pt(map, xdiv, |
| 968 | ydiv, &block->area.p0) == ' '; |
| 969 | bool end = read_map_pt(map, xdiv, ydiv, |
| 970 | &block->area.p1) == ' '; |
| 971 | |
| 972 | tcm_for_each_slice(a, block->area, p) |
| 973 | fill_map(map, xdiv, ydiv, &a, |
| 974 | '=', true); |
| 975 | fill_map_pt(map, xdiv, ydiv, |
| 976 | &block->area.p0, |
| 977 | start ? '<' : 'X'); |
| 978 | fill_map_pt(map, xdiv, ydiv, |
| 979 | &block->area.p1, |
| 980 | end ? '>' : 'X'); |
| 981 | map_1d_info(map, xdiv, ydiv, nice, |
| 982 | &block->area); |
| 983 | } |
| 984 | } |
| 985 | } |
| 986 | |
| 987 | spin_unlock_irqrestore(&list_lock, flags); |
| 988 | |
| 989 | if (s) { |
| 990 | seq_printf(s, "CONTAINER %d DUMP BEGIN\n", lut_idx); |
| 991 | for (i = 0; i < 128; i++) |
| 992 | seq_printf(s, "%03d:%s\n", i, map[i]); |
| 993 | seq_printf(s, "CONTAINER %d DUMP END\n", lut_idx); |
| 994 | } else { |
| 995 | dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP BEGIN\n", |
| 996 | lut_idx); |
| 997 | for (i = 0; i < 128; i++) |
| 998 | dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]); |
| 999 | dev_dbg(omap_dmm->dev, "CONTAINER %d DUMP END\n", |
| 1000 | lut_idx); |
| 1001 | } |
Andy Gross | 6169a148 | 2011-12-15 21:05:17 -0600 | [diff] [blame] | 1002 | } |
| 1003 | |
| 1004 | error: |
| 1005 | kfree(map); |
| 1006 | kfree(global_map); |
| 1007 | |
| 1008 | return 0; |
| 1009 | } |
| 1010 | #endif |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 1011 | |
Grygorii Strashko | 1d601da | 2015-02-25 20:08:20 +0200 | [diff] [blame] | 1012 | #ifdef CONFIG_PM_SLEEP |
Andy Gross | e78edba | 2012-12-19 14:53:37 -0600 | [diff] [blame] | 1013 | static int omap_dmm_resume(struct device *dev) |
| 1014 | { |
| 1015 | struct tcm_area area; |
| 1016 | int i; |
| 1017 | |
| 1018 | if (!omap_dmm) |
| 1019 | return -ENODEV; |
| 1020 | |
| 1021 | area = (struct tcm_area) { |
Andy Gross | e78edba | 2012-12-19 14:53:37 -0600 | [diff] [blame] | 1022 | .tcm = NULL, |
| 1023 | .p1.x = omap_dmm->container_width - 1, |
| 1024 | .p1.y = omap_dmm->container_height - 1, |
| 1025 | }; |
| 1026 | |
| 1027 | /* initialize all LUTs to dummy page entries */ |
| 1028 | for (i = 0; i < omap_dmm->num_lut; i++) { |
| 1029 | area.tcm = omap_dmm->tcm[i]; |
| 1030 | if (fill(&area, NULL, 0, 0, true)) |
| 1031 | dev_err(dev, "refill failed"); |
| 1032 | } |
| 1033 | |
| 1034 | return 0; |
| 1035 | } |
Andy Gross | e78edba | 2012-12-19 14:53:37 -0600 | [diff] [blame] | 1036 | #endif |
| 1037 | |
Grygorii Strashko | 1d601da | 2015-02-25 20:08:20 +0200 | [diff] [blame] | 1038 | static SIMPLE_DEV_PM_OPS(omap_dmm_pm_ops, NULL, omap_dmm_resume); |
| 1039 | |
Archit Taneja | 3d23234 | 2013-10-15 12:34:20 +0530 | [diff] [blame] | 1040 | #if defined(CONFIG_OF) |
Tomi Valkeinen | 7cb0d6c | 2014-09-25 19:24:29 +0000 | [diff] [blame] | 1041 | static const struct dmm_platform_data dmm_omap4_platform_data = { |
| 1042 | .cpu_cache_flags = OMAP_BO_WC, |
| 1043 | }; |
| 1044 | |
| 1045 | static const struct dmm_platform_data dmm_omap5_platform_data = { |
| 1046 | .cpu_cache_flags = OMAP_BO_UNCACHED, |
| 1047 | }; |
| 1048 | |
Archit Taneja | 3d23234 | 2013-10-15 12:34:20 +0530 | [diff] [blame] | 1049 | static const struct of_device_id dmm_of_match[] = { |
Tomi Valkeinen | 7cb0d6c | 2014-09-25 19:24:29 +0000 | [diff] [blame] | 1050 | { |
| 1051 | .compatible = "ti,omap4-dmm", |
| 1052 | .data = &dmm_omap4_platform_data, |
| 1053 | }, |
| 1054 | { |
| 1055 | .compatible = "ti,omap5-dmm", |
| 1056 | .data = &dmm_omap5_platform_data, |
| 1057 | }, |
Archit Taneja | 3d23234 | 2013-10-15 12:34:20 +0530 | [diff] [blame] | 1058 | {}, |
| 1059 | }; |
| 1060 | #endif |
| 1061 | |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 1062 | struct platform_driver omap_dmm_driver = { |
| 1063 | .probe = omap_dmm_probe, |
| 1064 | .remove = omap_dmm_remove, |
| 1065 | .driver = { |
| 1066 | .owner = THIS_MODULE, |
| 1067 | .name = DMM_DRIVER_NAME, |
Archit Taneja | 3d23234 | 2013-10-15 12:34:20 +0530 | [diff] [blame] | 1068 | .of_match_table = of_match_ptr(dmm_of_match), |
Andy Gross | e78edba | 2012-12-19 14:53:37 -0600 | [diff] [blame] | 1069 | .pm = &omap_dmm_pm_ops, |
Andy Gross | 5c13779 | 2012-03-05 10:48:39 -0600 | [diff] [blame] | 1070 | }, |
| 1071 | }; |
| 1072 | |
| 1073 | MODULE_LICENSE("GPL v2"); |
| 1074 | MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>"); |
| 1075 | MODULE_DESCRIPTION("OMAP DMM/Tiler Driver"); |