blob: a2432c6960db8f62fe7ab5a72ce89af6cbce4839 [file] [log] [blame]
Sascha Hauer6c7b068502012-03-07 21:01:28 +01001#ifndef __MACH_IMX_CLK_H
2#define __MACH_IMX_CLK_H
3
4#include <linux/spinlock.h>
5#include <linux/clk-provider.h>
Sascha Hauer3a84d172012-09-11 08:50:00 +02006
7extern spinlock_t imx_ccm_lock;
Sascha Hauer6c7b068502012-03-07 21:01:28 +01008
Sascha Hauer2af9e6d2012-03-09 09:11:55 +01009struct clk *imx_clk_pllv1(const char *name, const char *parent,
Sascha Hauer6c7b068502012-03-07 21:01:28 +010010 void __iomem *base);
11
Sascha Hauera547b812012-03-19 12:36:10 +010012struct clk *imx_clk_pllv2(const char *name, const char *parent,
13 void __iomem *base);
14
Shawn Guoa3f6b9d2012-04-04 16:02:28 +080015enum imx_pllv3_type {
16 IMX_PLLV3_GENERIC,
17 IMX_PLLV3_SYS,
18 IMX_PLLV3_USB,
19 IMX_PLLV3_AV,
20 IMX_PLLV3_ENET,
21 IMX_PLLV3_MLB,
22};
23
24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
Sascha Hauer2b254692012-11-22 10:18:41 +010025 const char *parent_name, void __iomem *base, u32 div_mask);
Shawn Guoa3f6b9d2012-04-04 16:02:28 +080026
Sascha Hauerb75c0152011-04-19 08:33:45 +020027struct clk *clk_register_gate2(struct device *dev, const char *name,
28 const char *parent_name, unsigned long flags,
29 void __iomem *reg, u8 bit_idx,
30 u8 clk_gate_flags, spinlock_t *lock);
31
Martin Fuzzey75f83d02013-04-23 20:16:59 +080032struct clk * imx_obtain_fixed_clock(
33 const char *name, unsigned long rate);
34
Sascha Hauerb75c0152011-04-19 08:33:45 +020035static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
36 void __iomem *reg, u8 shift)
37{
38 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
39 shift, 0, &imx_ccm_lock);
40}
41
Shawn Guoa10bd672012-04-04 16:07:53 +080042struct clk *imx_clk_pfd(const char *name, const char *parent_name,
43 void __iomem *reg, u8 idx);
44
Shawn Guo32af7a82012-04-04 16:20:56 +080045struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
46 void __iomem *reg, u8 shift, u8 width,
47 void __iomem *busy_reg, u8 busy_shift);
48
49struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
50 u8 width, void __iomem *busy_reg, u8 busy_shift,
51 const char **parent_names, int num_parents);
52
Sascha Hauer6c7b068502012-03-07 21:01:28 +010053static inline struct clk *imx_clk_fixed(const char *name, int rate)
54{
55 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
56}
57
58static inline struct clk *imx_clk_divider(const char *name, const char *parent,
59 void __iomem *reg, u8 shift, u8 width)
60{
61 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
62 reg, shift, width, 0, &imx_ccm_lock);
63}
64
Philipp Zabel3ce92172013-03-27 18:30:40 +010065static inline struct clk *imx_clk_divider_flags(const char *name,
66 const char *parent, void __iomem *reg, u8 shift, u8 width,
67 unsigned long flags)
68{
69 return clk_register_divider(NULL, name, parent, flags,
70 reg, shift, width, 0, &imx_ccm_lock);
71}
72
Sascha Hauer6c7b068502012-03-07 21:01:28 +010073static inline struct clk *imx_clk_gate(const char *name, const char *parent,
74 void __iomem *reg, u8 shift)
75{
76 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
77 shift, 0, &imx_ccm_lock);
78}
79
80static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
81 u8 shift, u8 width, const char **parents, int num_parents)
82{
83 return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift,
84 width, 0, &imx_ccm_lock);
85}
86
Philipp Zabel3ce92172013-03-27 18:30:40 +010087static inline struct clk *imx_clk_mux_flags(const char *name,
88 void __iomem *reg, u8 shift, u8 width, const char **parents,
89 int num_parents, unsigned long flags)
90{
91 return clk_register_mux(NULL, name, parents, num_parents,
92 flags, reg, shift, width, 0,
93 &imx_ccm_lock);
94}
95
Sascha Hauer6c7b068502012-03-07 21:01:28 +010096static inline struct clk *imx_clk_fixed_factor(const char *name,
97 const char *parent, unsigned int mult, unsigned int div)
98{
99 return clk_register_fixed_factor(NULL, name, parent,
100 CLK_SET_RATE_PARENT, mult, div);
101}
102
103#endif