Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. |
| 4 | * |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any |
| 6 | * purpose with or without fee is hereby granted, provided that the above |
| 7 | * copyright notice and this permission notice appear in all copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 16 | */ |
| 17 | |
| 18 | #ifndef _PCI_H_ |
| 19 | #define _PCI_H_ |
| 20 | |
| 21 | #include <linux/interrupt.h> |
| 22 | |
| 23 | #include "hw.h" |
| 24 | #include "ce.h" |
| 25 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 26 | /* |
| 27 | * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite |
| 28 | */ |
| 29 | #define DIAG_TRANSFER_LIMIT 2048 |
| 30 | |
| 31 | /* |
| 32 | * maximum number of bytes that can be |
| 33 | * handled atomically by DiagRead/DiagWrite |
| 34 | */ |
| 35 | #define DIAG_TRANSFER_LIMIT 2048 |
| 36 | |
| 37 | struct bmi_xfer { |
Michal Kazior | 2374b18 | 2014-07-14 16:25:25 +0300 | [diff] [blame] | 38 | bool tx_done; |
| 39 | bool rx_done; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 40 | bool wait_for_resp; |
| 41 | u32 resp_len; |
| 42 | }; |
| 43 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 44 | /* |
| 45 | * PCI-specific Target state |
| 46 | * |
| 47 | * NOTE: Structure is shared between Host software and Target firmware! |
| 48 | * |
| 49 | * Much of this may be of interest to the Host so |
| 50 | * HOST_INTEREST->hi_interconnect_state points here |
| 51 | * (and all members are 32-bit quantities in order to |
| 52 | * facilitate Host access). In particular, Host software is |
| 53 | * required to initialize pipe_cfg_addr and svc_to_pipe_map. |
| 54 | */ |
| 55 | struct pcie_state { |
| 56 | /* Pipe configuration Target address */ |
| 57 | /* NB: ce_pipe_config[CE_COUNT] */ |
| 58 | u32 pipe_cfg_addr; |
| 59 | |
| 60 | /* Service to pipe map Target address */ |
| 61 | /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */ |
| 62 | u32 svc_to_pipe_map; |
| 63 | |
| 64 | /* number of MSI interrupts requested */ |
| 65 | u32 msi_requested; |
| 66 | |
| 67 | /* number of MSI interrupts granted */ |
| 68 | u32 msi_granted; |
| 69 | |
| 70 | /* Message Signalled Interrupt address */ |
| 71 | u32 msi_addr; |
| 72 | |
| 73 | /* Base data */ |
| 74 | u32 msi_data; |
| 75 | |
| 76 | /* |
| 77 | * Data for firmware interrupt; |
| 78 | * MSI data for other interrupts are |
| 79 | * in various SoC registers |
| 80 | */ |
| 81 | u32 msi_fw_intr_data; |
| 82 | |
| 83 | /* PCIE_PWR_METHOD_* */ |
| 84 | u32 power_mgmt_method; |
| 85 | |
| 86 | /* PCIE_CONFIG_FLAG_* */ |
| 87 | u32 config_flags; |
| 88 | }; |
| 89 | |
| 90 | /* PCIE_CONFIG_FLAG definitions */ |
| 91 | #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 |
| 92 | |
| 93 | /* Host software's Copy Engine configuration. */ |
| 94 | #define CE_ATTR_FLAGS 0 |
| 95 | |
| 96 | /* |
| 97 | * Configuration information for a Copy Engine pipe. |
| 98 | * Passed from Host to Target during startup (one per CE). |
| 99 | * |
| 100 | * NOTE: Structure is shared between Host software and Target firmware! |
| 101 | */ |
| 102 | struct ce_pipe_config { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 103 | __le32 pipenum; |
| 104 | __le32 pipedir; |
| 105 | __le32 nentries; |
| 106 | __le32 nbytes_max; |
| 107 | __le32 flags; |
| 108 | __le32 reserved; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | /* |
| 112 | * Directions for interconnect pipe configuration. |
| 113 | * These definitions may be used during configuration and are shared |
| 114 | * between Host and Target. |
| 115 | * |
| 116 | * Pipe Directions are relative to the Host, so PIPEDIR_IN means |
| 117 | * "coming IN over air through Target to Host" as with a WiFi Rx operation. |
| 118 | * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" |
| 119 | * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" |
| 120 | * Target since things that are "PIPEDIR_OUT" are coming IN to the Target |
| 121 | * over the interconnect. |
| 122 | */ |
| 123 | #define PIPEDIR_NONE 0 |
| 124 | #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ |
| 125 | #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ |
| 126 | #define PIPEDIR_INOUT 3 /* bidirectional */ |
| 127 | |
| 128 | /* Establish a mapping between a service/direction and a pipe. */ |
| 129 | struct service_to_pipe { |
Michal Kazior | 0fdc14e4 | 2014-08-26 19:14:03 +0300 | [diff] [blame] | 130 | __le32 service_id; |
| 131 | __le32 pipedir; |
| 132 | __le32 pipenum; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 133 | }; |
| 134 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 135 | /* Per-pipe state. */ |
Michal Kazior | 87263e5 | 2013-08-27 13:08:01 +0200 | [diff] [blame] | 136 | struct ath10k_pci_pipe { |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 137 | /* Handle of underlying Copy Engine */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 138 | struct ath10k_ce_pipe *ce_hdl; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 139 | |
| 140 | /* Our pipe number; facilitiates use of pipe_info ptrs. */ |
| 141 | u8 pipe_num; |
| 142 | |
| 143 | /* Convenience back pointer to hif_ce_state. */ |
| 144 | struct ath10k *hif_ce_state; |
| 145 | |
| 146 | size_t buf_sz; |
| 147 | |
| 148 | /* protects compl_free and num_send_allowed */ |
| 149 | spinlock_t pipe_lock; |
| 150 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 151 | struct ath10k_pci *ar_pci; |
| 152 | struct tasklet_struct intr; |
| 153 | }; |
| 154 | |
Michal Kazior | 7505f7c | 2014-12-02 10:55:54 +0200 | [diff] [blame] | 155 | struct ath10k_pci_supp_chip { |
| 156 | u32 dev_id; |
| 157 | u32 rev_id; |
| 158 | }; |
| 159 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 160 | struct ath10k_pci { |
| 161 | struct pci_dev *pdev; |
| 162 | struct device *dev; |
| 163 | struct ath10k *ar; |
| 164 | void __iomem *mem; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 165 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 166 | /* |
| 167 | * Number of MSI interrupts granted, 0 --> using legacy PCI line |
| 168 | * interrupts. |
| 169 | */ |
| 170 | int num_msi_intrs; |
| 171 | |
| 172 | struct tasklet_struct intr_tq; |
| 173 | struct tasklet_struct msi_fw_err; |
| 174 | |
Michal Kazior | 87263e5 | 2013-08-27 13:08:01 +0200 | [diff] [blame] | 175 | struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX]; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 176 | |
| 177 | struct ath10k_hif_cb msg_callbacks_current; |
| 178 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 179 | /* Copy Engine used for Diagnostic Accesses */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 180 | struct ath10k_ce_pipe *ce_diag; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 181 | |
| 182 | /* FIXME: document what this really protects */ |
| 183 | spinlock_t ce_lock; |
| 184 | |
| 185 | /* Map CE id to ce_state */ |
Michal Kazior | 2aa3911 | 2013-08-27 13:08:02 +0200 | [diff] [blame] | 186 | struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 187 | struct timer_list rx_post_retry; |
Janusz Dziedzic | 76d870e | 2015-05-18 09:38:16 +0000 | [diff] [blame^] | 188 | |
| 189 | /* Due to HW quirks it is recommended to disable ASPM during device |
| 190 | * bootup. To do that the original PCI-E Link Control is stored before |
| 191 | * device bootup is executed and re-programmed later. |
| 192 | */ |
| 193 | u16 link_ctl; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 194 | }; |
| 195 | |
| 196 | static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) |
| 197 | { |
Michal Kazior | e7b5419 | 2014-08-07 11:03:27 +0200 | [diff] [blame] | 198 | return (struct ath10k_pci *)ar->drv_priv; |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 199 | } |
| 200 | |
Michal Kazior | 728f95e | 2014-08-22 14:33:14 +0200 | [diff] [blame] | 201 | #define ATH10K_PCI_RX_POST_RETRY_MS 50 |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 202 | #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */ |
Rajkumar Manoharan | 6c3d7d7 | 2015-01-26 22:13:06 +0530 | [diff] [blame] | 203 | #define PCIE_WAKE_TIMEOUT 10000 /* 10ms */ |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 204 | |
| 205 | #define BAR_NUM 0 |
| 206 | |
| 207 | #define CDC_WAR_MAGIC_STR 0xceef0000 |
| 208 | #define CDC_WAR_DATA_CE 4 |
| 209 | |
| 210 | /* |
| 211 | * TODO: Should be a function call specific to each Target-type. |
| 212 | * This convoluted macro converts from Target CPU Virtual Address Space to CE |
| 213 | * Address Space. As part of this process, we conservatively fetch the current |
| 214 | * PCIE_BAR. MOST of the time, this should match the upper bits of PCI space |
| 215 | * for this device; but that's not guaranteed. |
| 216 | */ |
| 217 | #define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \ |
| 218 | (((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \ |
| 219 | CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \ |
| 220 | 0x100000 | ((addr) & 0xfffff)) |
| 221 | |
| 222 | /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */ |
| 223 | #define DIAG_ACCESS_CE_TIMEOUT_MS 10 |
| 224 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 225 | /* Target exposes its registers for direct access. However before host can |
| 226 | * access them it needs to make sure the target is awake (ath10k_pci_wake, |
| 227 | * ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go |
| 228 | * to sleep unless host tells it to (ath10k_pci_sleep). |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 229 | * |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 230 | * If host tries to access target registers without waking it up it can |
| 231 | * scribble over host memory. |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 232 | * |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 233 | * If target is asleep waking it up may take up to even 2ms. |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 234 | */ |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 235 | |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 236 | static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, |
| 237 | u32 value) |
| 238 | { |
| 239 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 240 | |
Bartosz Markowski | 57a8930 | 2013-08-07 15:17:45 +0200 | [diff] [blame] | 241 | iowrite32(value, ar_pci->mem + offset); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) |
| 245 | { |
| 246 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 247 | |
| 248 | return ioread32(ar_pci->mem + offset); |
| 249 | } |
| 250 | |
Kalle Valo | 233eb97 | 2013-10-16 16:46:11 +0300 | [diff] [blame] | 251 | static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) |
| 252 | { |
| 253 | return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr); |
| 254 | } |
| 255 | |
| 256 | static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val) |
| 257 | { |
| 258 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val); |
| 259 | } |
| 260 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 261 | static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 262 | { |
Bartosz Markowski | 8cc8df9 | 2013-08-02 09:58:49 +0200 | [diff] [blame] | 263 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 264 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 265 | return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 266 | } |
| 267 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 268 | static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val) |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 269 | { |
Bartosz Markowski | 8cc8df9 | 2013-08-02 09:58:49 +0200 | [diff] [blame] | 270 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
| 271 | |
Michal Kazior | c0c378f | 2014-08-07 11:03:28 +0200 | [diff] [blame] | 272 | iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr); |
Kalle Valo | 5e3dd15 | 2013-06-12 20:52:10 +0300 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | #endif /* _PCI_H_ */ |