blob: 1e1531334c251579cac44d980973942f1df9391b [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000
3 *
4 * Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 */
7
8/*
9 * Special Thanks to Mark for his Six years of work.
10 *
11 * Copyright (c) 1995-1998 Mark Lord
12 * May be copied or modified under the terms of the GNU General Public License
13 */
14
15/*
16 * This module provides support for the bus-master IDE DMA functions
17 * of various PCI chipsets, including the Intel PIIX (i82371FB for
18 * the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and
19 * 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset)
20 * ("PIIX" stands for "PCI ISA IDE Xcellerator").
21 *
22 * Pretty much the same code works for other IDE PCI bus-mastering chipsets.
23 *
24 * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
25 *
26 * By default, DMA support is prepared for use, but is currently enabled only
27 * for drives which already have DMA enabled (UltraDMA or mode 2 multi/single),
28 * or which are recognized as "good" (see table below). Drives with only mode0
29 * or mode1 (multi/single) DMA should also work with this chipset/driver
30 * (eg. MC2112A) but are not enabled by default.
31 *
32 * Use "hdparm -i" to view modes supported by a given drive.
33 *
34 * The hdparm-3.5 (or later) utility can be used for manually enabling/disabling
35 * DMA support, but must be (re-)compiled against this kernel version or later.
36 *
37 * To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
38 * If problems arise, ide.c will disable DMA operation after a few retries.
39 * This error recovery mechanism works and has been extremely well exercised.
40 *
41 * IDE drives, depending on their vintage, may support several different modes
42 * of DMA operation. The boot-time modes are indicated with a "*" in
43 * the "hdparm -i" listing, and can be changed with *knowledgeable* use of
44 * the "hdparm -X" feature. There is seldom a need to do this, as drives
45 * normally power-up with their "best" PIO/DMA modes enabled.
46 *
47 * Testing has been done with a rather extensive number of drives,
48 * with Quantum & Western Digital models generally outperforming the pack,
49 * and Fujitsu & Conner (and some Seagate which are really Conner) drives
50 * showing more lackluster throughput.
51 *
52 * Keep an eye on /var/adm/messages for "DMA disabled" messages.
53 *
54 * Some people have reported trouble with Intel Zappa motherboards.
55 * This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
56 * available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
57 * (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
58 *
59 * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
60 * fixing the problem with the BIOS on some Acer motherboards.
61 *
62 * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
63 * "TX" chipset compatibility and for providing patches for the "TX" chipset.
64 *
65 * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
66 * at generic DMA -- his patches were referred to when preparing this code.
67 *
68 * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
69 * for supplying a Promise UDMA board & WD UDMA drive for this work!
70 *
71 * And, yes, Intel Zappa boards really *do* use both PIIX IDE ports.
72 *
73 * ATA-66/100 and recovery functions, I forgot the rest......
74 *
75 */
76
77#include <linux/config.h>
78#include <linux/module.h>
79#include <linux/types.h>
80#include <linux/kernel.h>
81#include <linux/timer.h>
82#include <linux/mm.h>
83#include <linux/interrupt.h>
84#include <linux/pci.h>
85#include <linux/init.h>
86#include <linux/ide.h>
87#include <linux/delay.h>
88#include <linux/scatterlist.h>
89
90#include <asm/io.h>
91#include <asm/irq.h>
92
93struct drive_list_entry {
94 const char *id_model;
95 const char *id_firmware;
96};
97
98static const struct drive_list_entry drive_whitelist [] = {
99
100 { "Micropolis 2112A" , "ALL" },
101 { "CONNER CTMA 4000" , "ALL" },
102 { "CONNER CTT8000-A" , "ALL" },
103 { "ST34342A" , "ALL" },
104 { NULL , NULL }
105};
106
107static const struct drive_list_entry drive_blacklist [] = {
108
109 { "WDC AC11000H" , "ALL" },
110 { "WDC AC22100H" , "ALL" },
111 { "WDC AC32500H" , "ALL" },
112 { "WDC AC33100H" , "ALL" },
113 { "WDC AC31600H" , "ALL" },
114 { "WDC AC32100H" , "24.09P07" },
115 { "WDC AC23200L" , "21.10N21" },
116 { "Compaq CRD-8241B" , "ALL" },
117 { "CRD-8400B" , "ALL" },
118 { "CRD-8480B", "ALL" },
119 { "CRD-8482B", "ALL" },
120 { "CRD-84" , "ALL" },
121 { "SanDisk SDP3B" , "ALL" },
122 { "SanDisk SDP3B-64" , "ALL" },
123 { "SANYO CD-ROM CRD" , "ALL" },
124 { "HITACHI CDR-8" , "ALL" },
125 { "HITACHI CDR-8335" , "ALL" },
126 { "HITACHI CDR-8435" , "ALL" },
127 { "Toshiba CD-ROM XM-6202B" , "ALL" },
128 { "CD-532E-A" , "ALL" },
129 { "E-IDE CD-ROM CR-840", "ALL" },
130 { "CD-ROM Drive/F5A", "ALL" },
131 { "WPI CDD-820", "ALL" },
132 { "SAMSUNG CD-ROM SC-148C", "ALL" },
133 { "SAMSUNG CD-ROM SC", "ALL" },
134 { "SanDisk SDP3B-64" , "ALL" },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 { "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" },
136 { "_NEC DV5800A", "ALL" },
137 { NULL , NULL }
138
139};
140
141/**
142 * in_drive_list - look for drive in black/white list
143 * @id: drive identifier
144 * @drive_table: list to inspect
145 *
146 * Look for a drive in the blacklist and the whitelist tables
147 * Returns 1 if the drive is found in the table.
148 */
149
150static int in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
151{
152 for ( ; drive_table->id_model ; drive_table++)
153 if ((!strcmp(drive_table->id_model, id->model)) &&
154 ((strstr(drive_table->id_firmware, id->fw_rev)) ||
155 (!strcmp(drive_table->id_firmware, "ALL"))))
156 return 1;
157 return 0;
158}
159
160/**
161 * ide_dma_intr - IDE DMA interrupt handler
162 * @drive: the drive the interrupt is for
163 *
164 * Handle an interrupt completing a read/write DMA transfer on an
165 * IDE device
166 */
167
168ide_startstop_t ide_dma_intr (ide_drive_t *drive)
169{
170 u8 stat = 0, dma_stat = 0;
171
172 dma_stat = HWIF(drive)->ide_dma_end(drive);
173 stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
174 if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
175 if (!dma_stat) {
176 struct request *rq = HWGROUP(drive)->rq;
177
178 if (rq->rq_disk) {
179 ide_driver_t *drv;
180
181 drv = *(ide_driver_t **)rq->rq_disk->private_data;;
182 drv->end_request(drive, 1, rq->nr_sectors);
183 } else
184 ide_end_request(drive, 1, rq->nr_sectors);
185 return ide_stopped;
186 }
187 printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
188 drive->name, dma_stat);
189 }
190 return ide_error(drive, "dma_intr", stat);
191}
192
193EXPORT_SYMBOL_GPL(ide_dma_intr);
194
195#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
196/**
197 * ide_build_sglist - map IDE scatter gather for DMA I/O
198 * @drive: the drive to build the DMA table for
199 * @rq: the request holding the sg list
200 *
201 * Perform the PCI mapping magic necessary to access the source or
202 * target buffers of a request via PCI DMA. The lower layers of the
203 * kernel provide the necessary cache management so that we can
204 * operate in a portable fashion
205 */
206
207int ide_build_sglist(ide_drive_t *drive, struct request *rq)
208{
209 ide_hwif_t *hwif = HWIF(drive);
210 struct scatterlist *sg = hwif->sg_table;
211
212 if ((rq->flags & REQ_DRIVE_TASKFILE) && rq->nr_sectors > 256)
213 BUG();
214
215 ide_map_sg(drive, rq);
216
217 if (rq_data_dir(rq) == READ)
218 hwif->sg_dma_direction = PCI_DMA_FROMDEVICE;
219 else
220 hwif->sg_dma_direction = PCI_DMA_TODEVICE;
221
222 return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
223}
224
225EXPORT_SYMBOL_GPL(ide_build_sglist);
226
227/**
228 * ide_build_dmatable - build IDE DMA table
229 *
230 * ide_build_dmatable() prepares a dma request. We map the command
231 * to get the pci bus addresses of the buffers and then build up
232 * the PRD table that the IDE layer wants to be fed. The code
233 * knows about the 64K wrap bug in the CS5530.
234 *
235 * Returns the number of built PRD entries if all went okay,
236 * returns 0 otherwise.
237 *
238 * May also be invoked from trm290.c
239 */
240
241int ide_build_dmatable (ide_drive_t *drive, struct request *rq)
242{
243 ide_hwif_t *hwif = HWIF(drive);
244 unsigned int *table = hwif->dmatable_cpu;
245 unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
246 unsigned int count = 0;
247 int i;
248 struct scatterlist *sg;
249
250 hwif->sg_nents = i = ide_build_sglist(drive, rq);
251
252 if (!i)
253 return 0;
254
255 sg = hwif->sg_table;
256 while (i) {
257 u32 cur_addr;
258 u32 cur_len;
259
260 cur_addr = sg_dma_address(sg);
261 cur_len = sg_dma_len(sg);
262
263 /*
264 * Fill in the dma table, without crossing any 64kB boundaries.
265 * Most hardware requires 16-bit alignment of all blocks,
266 * but the trm290 requires 32-bit alignment.
267 */
268
269 while (cur_len) {
270 if (count++ >= PRD_ENTRIES) {
271 printk(KERN_ERR "%s: DMA table too small\n", drive->name);
272 goto use_pio_instead;
273 } else {
274 u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff);
275
276 if (bcount > cur_len)
277 bcount = cur_len;
278 *table++ = cpu_to_le32(cur_addr);
279 xcount = bcount & 0xffff;
280 if (is_trm290)
281 xcount = ((xcount >> 2) - 1) << 16;
282 if (xcount == 0x0000) {
283 /*
284 * Most chipsets correctly interpret a length of 0x0000 as 64KB,
285 * but at least one (e.g. CS5530) misinterprets it as zero (!).
286 * So here we break the 64KB entry into two 32KB entries instead.
287 */
288 if (count++ >= PRD_ENTRIES) {
289 printk(KERN_ERR "%s: DMA table too small\n", drive->name);
290 goto use_pio_instead;
291 }
292 *table++ = cpu_to_le32(0x8000);
293 *table++ = cpu_to_le32(cur_addr + 0x8000);
294 xcount = 0x8000;
295 }
296 *table++ = cpu_to_le32(xcount);
297 cur_addr += bcount;
298 cur_len -= bcount;
299 }
300 }
301
302 sg++;
303 i--;
304 }
305
306 if (count) {
307 if (!is_trm290)
308 *--table |= cpu_to_le32(0x80000000);
309 return count;
310 }
311 printk(KERN_ERR "%s: empty DMA table?\n", drive->name);
312use_pio_instead:
313 pci_unmap_sg(hwif->pci_dev,
314 hwif->sg_table,
315 hwif->sg_nents,
316 hwif->sg_dma_direction);
317 return 0; /* revert to PIO for this request */
318}
319
320EXPORT_SYMBOL_GPL(ide_build_dmatable);
321
322/**
323 * ide_destroy_dmatable - clean up DMA mapping
324 * @drive: The drive to unmap
325 *
326 * Teardown mappings after DMA has completed. This must be called
327 * after the completion of each use of ide_build_dmatable and before
328 * the next use of ide_build_dmatable. Failure to do so will cause
329 * an oops as only one mapping can be live for each target at a given
330 * time.
331 */
332
333void ide_destroy_dmatable (ide_drive_t *drive)
334{
335 struct pci_dev *dev = HWIF(drive)->pci_dev;
336 struct scatterlist *sg = HWIF(drive)->sg_table;
337 int nents = HWIF(drive)->sg_nents;
338
339 pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction);
340}
341
342EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
343
344/**
345 * config_drive_for_dma - attempt to activate IDE DMA
346 * @drive: the drive to place in DMA mode
347 *
348 * If the drive supports at least mode 2 DMA or UDMA of any kind
349 * then attempt to place it into DMA mode. Drives that are known to
350 * support DMA but predate the DMA properties or that are known
351 * to have DMA handling bugs are also set up appropriately based
352 * on the good/bad drive lists.
353 */
354
355static int config_drive_for_dma (ide_drive_t *drive)
356{
357 struct hd_driveid *id = drive->id;
358 ide_hwif_t *hwif = HWIF(drive);
359
360 if ((id->capability & 1) && hwif->autodma) {
361 /*
362 * Enable DMA on any drive that has
363 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
364 */
365 if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f))
366 return hwif->ide_dma_on(drive);
367 /*
368 * Enable DMA on any drive that has mode2 DMA
369 * (multi or single) enabled
370 */
371 if (id->field_valid & 2) /* regular DMA */
372 if ((id->dma_mword & 0x404) == 0x404 ||
373 (id->dma_1word & 0x404) == 0x404)
374 return hwif->ide_dma_on(drive);
375
376 /* Consult the list of known "good" drives */
377 if (__ide_dma_good_drive(drive))
378 return hwif->ide_dma_on(drive);
379 }
380// if (hwif->tuneproc != NULL) hwif->tuneproc(drive, 255);
381 return hwif->ide_dma_off_quietly(drive);
382}
383
384/**
385 * dma_timer_expiry - handle a DMA timeout
386 * @drive: Drive that timed out
387 *
388 * An IDE DMA transfer timed out. In the event of an error we ask
389 * the driver to resolve the problem, if a DMA transfer is still
390 * in progress we continue to wait (arguably we need to add a
391 * secondary 'I don't care what the drive thinks' timeout here)
392 * Finally if we have an interrupt we let it complete the I/O.
393 * But only one time - we clear expiry and if it's still not
394 * completed after WAIT_CMD, we error and retry in PIO.
395 * This can occur if an interrupt is lost or due to hang or bugs.
396 */
397
398static int dma_timer_expiry (ide_drive_t *drive)
399{
400 ide_hwif_t *hwif = HWIF(drive);
401 u8 dma_stat = hwif->INB(hwif->dma_status);
402
403 printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n",
404 drive->name, dma_stat);
405
406 if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
407 return WAIT_CMD;
408
409 HWGROUP(drive)->expiry = NULL; /* one free ride for now */
410
411 /* 1 dmaing, 2 error, 4 intr */
412 if (dma_stat & 2) /* ERROR */
413 return -1;
414
415 if (dma_stat & 1) /* DMAing */
416 return WAIT_CMD;
417
418 if (dma_stat & 4) /* Got an Interrupt */
419 return WAIT_CMD;
420
421 return 0; /* Status is unknown -- reset the bus */
422}
423
424/**
425 * __ide_dma_host_off - Generic DMA kill
426 * @drive: drive to control
427 *
428 * Perform the generic IDE controller DMA off operation. This
429 * works for most IDE bus mastering controllers
430 */
431
432int __ide_dma_host_off (ide_drive_t *drive)
433{
434 ide_hwif_t *hwif = HWIF(drive);
435 u8 unit = (drive->select.b.unit & 0x01);
436 u8 dma_stat = hwif->INB(hwif->dma_status);
437
438 hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status);
439 return 0;
440}
441
442EXPORT_SYMBOL(__ide_dma_host_off);
443
444/**
445 * __ide_dma_host_off_quietly - Generic DMA kill
446 * @drive: drive to control
447 *
448 * Turn off the current DMA on this IDE controller.
449 */
450
451int __ide_dma_off_quietly (ide_drive_t *drive)
452{
453 drive->using_dma = 0;
454 ide_toggle_bounce(drive, 0);
455
456 if (HWIF(drive)->ide_dma_host_off(drive))
457 return 1;
458
459 return 0;
460}
461
462EXPORT_SYMBOL(__ide_dma_off_quietly);
463#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
464
465/**
466 * __ide_dma_off - disable DMA on a device
467 * @drive: drive to disable DMA on
468 *
469 * Disable IDE DMA for a device on this IDE controller.
470 * Inform the user that DMA has been disabled.
471 */
472
473int __ide_dma_off (ide_drive_t *drive)
474{
475 printk(KERN_INFO "%s: DMA disabled\n", drive->name);
476 return HWIF(drive)->ide_dma_off_quietly(drive);
477}
478
479EXPORT_SYMBOL(__ide_dma_off);
480
481#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
482/**
483 * __ide_dma_host_on - Enable DMA on a host
484 * @drive: drive to enable for DMA
485 *
486 * Enable DMA on an IDE controller following generic bus mastering
487 * IDE controller behaviour
488 */
489
490int __ide_dma_host_on (ide_drive_t *drive)
491{
492 if (drive->using_dma) {
493 ide_hwif_t *hwif = HWIF(drive);
494 u8 unit = (drive->select.b.unit & 0x01);
495 u8 dma_stat = hwif->INB(hwif->dma_status);
496
497 hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status);
498 return 0;
499 }
500 return 1;
501}
502
503EXPORT_SYMBOL(__ide_dma_host_on);
504
505/**
506 * __ide_dma_on - Enable DMA on a device
507 * @drive: drive to enable DMA on
508 *
509 * Enable IDE DMA for a device on this IDE controller.
510 */
511
512int __ide_dma_on (ide_drive_t *drive)
513{
514 /* consult the list of known "bad" drives */
515 if (__ide_dma_bad_drive(drive))
516 return 1;
517
518 drive->using_dma = 1;
519 ide_toggle_bounce(drive, 1);
520
521 if (HWIF(drive)->ide_dma_host_on(drive))
522 return 1;
523
524 return 0;
525}
526
527EXPORT_SYMBOL(__ide_dma_on);
528
529/**
530 * __ide_dma_check - check DMA setup
531 * @drive: drive to check
532 *
533 * Don't use - due for extermination
534 */
535
536int __ide_dma_check (ide_drive_t *drive)
537{
538 return config_drive_for_dma(drive);
539}
540
541EXPORT_SYMBOL(__ide_dma_check);
542
543/**
544 * ide_dma_setup - begin a DMA phase
545 * @drive: target device
546 *
547 * Build an IDE DMA PRD (IDE speak for scatter gather table)
548 * and then set up the DMA transfer registers for a device
549 * that follows generic IDE PCI DMA behaviour. Controllers can
550 * override this function if they need to
551 *
552 * Returns 0 on success. If a PIO fallback is required then 1
553 * is returned.
554 */
555
556int ide_dma_setup(ide_drive_t *drive)
557{
558 ide_hwif_t *hwif = drive->hwif;
559 struct request *rq = HWGROUP(drive)->rq;
560 unsigned int reading;
561 u8 dma_stat;
562
563 if (rq_data_dir(rq))
564 reading = 0;
565 else
566 reading = 1 << 3;
567
568 /* fall back to pio! */
569 if (!ide_build_dmatable(drive, rq)) {
570 ide_map_sg(drive, rq);
571 return 1;
572 }
573
574 /* PRD table */
575 hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable);
576
577 /* specify r/w */
578 hwif->OUTB(reading, hwif->dma_command);
579
580 /* read dma_status for INTR & ERROR flags */
581 dma_stat = hwif->INB(hwif->dma_status);
582
583 /* clear INTR & ERROR flags */
584 hwif->OUTB(dma_stat|6, hwif->dma_status);
585 drive->waiting_for_dma = 1;
586 return 0;
587}
588
589EXPORT_SYMBOL_GPL(ide_dma_setup);
590
591static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
592{
593 /* issue cmd to drive */
594 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry);
595}
596
597void ide_dma_start(ide_drive_t *drive)
598{
599 ide_hwif_t *hwif = HWIF(drive);
600 u8 dma_cmd = hwif->INB(hwif->dma_command);
601
602 /* Note that this is done *after* the cmd has
603 * been issued to the drive, as per the BM-IDE spec.
604 * The Promise Ultra33 doesn't work correctly when
605 * we do this part before issuing the drive cmd.
606 */
607 /* start DMA */
608 hwif->OUTB(dma_cmd|1, hwif->dma_command);
609 hwif->dma = 1;
610 wmb();
611}
612
613EXPORT_SYMBOL_GPL(ide_dma_start);
614
615/* returns 1 on error, 0 otherwise */
616int __ide_dma_end (ide_drive_t *drive)
617{
618 ide_hwif_t *hwif = HWIF(drive);
619 u8 dma_stat = 0, dma_cmd = 0;
620
621 drive->waiting_for_dma = 0;
622 /* get dma_command mode */
623 dma_cmd = hwif->INB(hwif->dma_command);
624 /* stop DMA */
625 hwif->OUTB(dma_cmd&~1, hwif->dma_command);
626 /* get DMA status */
627 dma_stat = hwif->INB(hwif->dma_status);
628 /* clear the INTR & ERROR bits */
629 hwif->OUTB(dma_stat|6, hwif->dma_status);
630 /* purge DMA mappings */
631 ide_destroy_dmatable(drive);
632 /* verify good DMA status */
633 hwif->dma = 0;
634 wmb();
635 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
636}
637
638EXPORT_SYMBOL(__ide_dma_end);
639
640/* returns 1 if dma irq issued, 0 otherwise */
641static int __ide_dma_test_irq(ide_drive_t *drive)
642{
643 ide_hwif_t *hwif = HWIF(drive);
644 u8 dma_stat = hwif->INB(hwif->dma_status);
645
646#if 0 /* do not set unless you know what you are doing */
647 if (dma_stat & 4) {
648 u8 stat = hwif->INB(IDE_STATUS_REG);
649 hwif->OUTB(hwif->dma_status, dma_stat & 0xE4);
650 }
651#endif
652 /* return 1 if INTR asserted */
653 if ((dma_stat & 4) == 4)
654 return 1;
655 if (!drive->waiting_for_dma)
656 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
657 drive->name, __FUNCTION__);
658 return 0;
659}
660#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
661
662int __ide_dma_bad_drive (ide_drive_t *drive)
663{
664 struct hd_driveid *id = drive->id;
665
666 int blacklist = in_drive_list(id, drive_blacklist);
667 if (blacklist) {
668 printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
669 drive->name, id->model);
670 return blacklist;
671 }
672 return 0;
673}
674
675EXPORT_SYMBOL(__ide_dma_bad_drive);
676
677int __ide_dma_good_drive (ide_drive_t *drive)
678{
679 struct hd_driveid *id = drive->id;
680 return in_drive_list(id, drive_whitelist);
681}
682
683EXPORT_SYMBOL(__ide_dma_good_drive);
684
685int ide_use_dma(ide_drive_t *drive)
686{
687 struct hd_driveid *id = drive->id;
688 ide_hwif_t *hwif = drive->hwif;
689
690 /* consult the list of known "bad" drives */
691 if (__ide_dma_bad_drive(drive))
692 return 0;
693
694 /* capable of UltraDMA modes */
695 if (id->field_valid & 4) {
696 if (hwif->ultra_mask & id->dma_ultra)
697 return 1;
698 }
699
700 /* capable of regular DMA modes */
701 if (id->field_valid & 2) {
702 if (hwif->mwdma_mask & id->dma_mword)
703 return 1;
704 if (hwif->swdma_mask & id->dma_1word)
705 return 1;
706 }
707
708 /* consult the list of known "good" drives */
709 if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
710 return 1;
711
712 return 0;
713}
714
715EXPORT_SYMBOL_GPL(ide_use_dma);
716
717void ide_dma_verbose(ide_drive_t *drive)
718{
719 struct hd_driveid *id = drive->id;
720 ide_hwif_t *hwif = HWIF(drive);
721
722 if (id->field_valid & 4) {
723 if ((id->dma_ultra >> 8) && (id->dma_mword >> 8))
724 goto bug_dma_off;
725 if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) {
726 if (((id->dma_ultra >> 11) & 0x1F) &&
727 eighty_ninty_three(drive)) {
728 if ((id->dma_ultra >> 15) & 1) {
729 printk(", UDMA(mode 7)");
730 } else if ((id->dma_ultra >> 14) & 1) {
731 printk(", UDMA(133)");
732 } else if ((id->dma_ultra >> 13) & 1) {
733 printk(", UDMA(100)");
734 } else if ((id->dma_ultra >> 12) & 1) {
735 printk(", UDMA(66)");
736 } else if ((id->dma_ultra >> 11) & 1) {
737 printk(", UDMA(44)");
738 } else
739 goto mode_two;
740 } else {
741 mode_two:
742 if ((id->dma_ultra >> 10) & 1) {
743 printk(", UDMA(33)");
744 } else if ((id->dma_ultra >> 9) & 1) {
745 printk(", UDMA(25)");
746 } else if ((id->dma_ultra >> 8) & 1) {
747 printk(", UDMA(16)");
748 }
749 }
750 } else {
751 printk(", (U)DMA"); /* Can be BIOS-enabled! */
752 }
753 } else if (id->field_valid & 2) {
754 if ((id->dma_mword >> 8) && (id->dma_1word >> 8))
755 goto bug_dma_off;
756 printk(", DMA");
757 } else if (id->field_valid & 1) {
758 printk(", BUG");
759 }
760 return;
761bug_dma_off:
762 printk(", BUG DMA OFF");
763 hwif->ide_dma_off_quietly(drive);
764 return;
765}
766
767EXPORT_SYMBOL(ide_dma_verbose);
768
769#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
770int __ide_dma_lostirq (ide_drive_t *drive)
771{
772 printk("%s: DMA interrupt recovery\n", drive->name);
773 return 1;
774}
775
776EXPORT_SYMBOL(__ide_dma_lostirq);
777
778int __ide_dma_timeout (ide_drive_t *drive)
779{
780 printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
781 if (HWIF(drive)->ide_dma_test_irq(drive))
782 return 0;
783
784 return HWIF(drive)->ide_dma_end(drive);
785}
786
787EXPORT_SYMBOL(__ide_dma_timeout);
788
789/*
790 * Needed for allowing full modular support of ide-driver
791 */
792static int ide_release_dma_engine(ide_hwif_t *hwif)
793{
794 if (hwif->dmatable_cpu) {
795 pci_free_consistent(hwif->pci_dev,
796 PRD_ENTRIES * PRD_BYTES,
797 hwif->dmatable_cpu,
798 hwif->dmatable_dma);
799 hwif->dmatable_cpu = NULL;
800 }
801 return 1;
802}
803
804static int ide_release_iomio_dma(ide_hwif_t *hwif)
805{
806 if ((hwif->dma_extra) && (hwif->channel == 0))
807 release_region((hwif->dma_base + 16), hwif->dma_extra);
808 release_region(hwif->dma_base, 8);
809 if (hwif->dma_base2)
810 release_region(hwif->dma_base, 8);
811 return 1;
812}
813
814/*
815 * Needed for allowing full modular support of ide-driver
816 */
817int ide_release_dma (ide_hwif_t *hwif)
818{
819 if (hwif->mmio == 2)
820 return 1;
821 if (hwif->chipset == ide_etrax100)
822 return 1;
823
824 ide_release_dma_engine(hwif);
825 return ide_release_iomio_dma(hwif);
826}
827
828static int ide_allocate_dma_engine(ide_hwif_t *hwif)
829{
830 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
831 PRD_ENTRIES * PRD_BYTES,
832 &hwif->dmatable_dma);
833
834 if (hwif->dmatable_cpu)
835 return 0;
836
837 printk(KERN_ERR "%s: -- Error, unable to allocate%s DMA table(s).\n",
838 hwif->cds->name, !hwif->dmatable_cpu ? " CPU" : "");
839
840 ide_release_dma_engine(hwif);
841 return 1;
842}
843
844static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
845{
846 printk(KERN_INFO " %s: MMIO-DMA ", hwif->name);
847
848 hwif->dma_base = base;
849 if (hwif->cds->extra && hwif->channel == 0)
850 hwif->dma_extra = hwif->cds->extra;
851
852 if(hwif->mate)
853 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
854 else
855 hwif->dma_master = base;
856 return 0;
857}
858
859static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
860{
861 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx",
862 hwif->name, base, base + ports - 1);
863 if (!request_region(base, ports, hwif->name)) {
864 printk(" -- Error, ports in use.\n");
865 return 1;
866 }
867 hwif->dma_base = base;
868 if ((hwif->cds->extra) && (hwif->channel == 0)) {
869 request_region(base+16, hwif->cds->extra, hwif->cds->name);
870 hwif->dma_extra = hwif->cds->extra;
871 }
872
873 if(hwif->mate)
874 hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
875 else
876 hwif->dma_master = base;
877 if (hwif->dma_base2) {
878 if (!request_region(hwif->dma_base2, ports, hwif->name))
879 {
880 printk(" -- Error, secondary ports in use.\n");
881 release_region(base, ports);
882 return 1;
883 }
884 }
885 return 0;
886}
887
888static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
889{
890 if (hwif->mmio == 2)
891 return ide_mapped_mmio_dma(hwif, base,ports);
892 BUG_ON(hwif->mmio == 1);
893 return ide_iomio_dma(hwif, base, ports);
894}
895
896/*
897 * This can be called for a dynamically installed interface. Don't __init it
898 */
899void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports)
900{
901 if (ide_dma_iobase(hwif, dma_base, num_ports))
902 return;
903
904 if (ide_allocate_dma_engine(hwif)) {
905 ide_release_dma(hwif);
906 return;
907 }
908
909 if (!(hwif->dma_command))
910 hwif->dma_command = hwif->dma_base;
911 if (!(hwif->dma_vendor1))
912 hwif->dma_vendor1 = (hwif->dma_base + 1);
913 if (!(hwif->dma_status))
914 hwif->dma_status = (hwif->dma_base + 2);
915 if (!(hwif->dma_vendor3))
916 hwif->dma_vendor3 = (hwif->dma_base + 3);
917 if (!(hwif->dma_prdtable))
918 hwif->dma_prdtable = (hwif->dma_base + 4);
919
920 if (!hwif->ide_dma_off_quietly)
921 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
922 if (!hwif->ide_dma_host_off)
923 hwif->ide_dma_host_off = &__ide_dma_host_off;
924 if (!hwif->ide_dma_on)
925 hwif->ide_dma_on = &__ide_dma_on;
926 if (!hwif->ide_dma_host_on)
927 hwif->ide_dma_host_on = &__ide_dma_host_on;
928 if (!hwif->ide_dma_check)
929 hwif->ide_dma_check = &__ide_dma_check;
930 if (!hwif->dma_setup)
931 hwif->dma_setup = &ide_dma_setup;
932 if (!hwif->dma_exec_cmd)
933 hwif->dma_exec_cmd = &ide_dma_exec_cmd;
934 if (!hwif->dma_start)
935 hwif->dma_start = &ide_dma_start;
936 if (!hwif->ide_dma_end)
937 hwif->ide_dma_end = &__ide_dma_end;
938 if (!hwif->ide_dma_test_irq)
939 hwif->ide_dma_test_irq = &__ide_dma_test_irq;
940 if (!hwif->ide_dma_timeout)
941 hwif->ide_dma_timeout = &__ide_dma_timeout;
942 if (!hwif->ide_dma_lostirq)
943 hwif->ide_dma_lostirq = &__ide_dma_lostirq;
944
945 if (hwif->chipset != ide_trm290) {
946 u8 dma_stat = hwif->INB(hwif->dma_status);
947 printk(", BIOS settings: %s:%s, %s:%s",
948 hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio",
949 hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio");
950 }
951 printk("\n");
952
953 if (!(hwif->dma_master))
954 BUG();
955}
956
957EXPORT_SYMBOL_GPL(ide_setup_dma);
958#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */