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Komal Shah7768a132006-09-29 01:59:18 -07001/*
2 * linux/drivers/char/watchdog/omap_wdt.c
3 *
4 * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
19 * Based on SoftDog driver by Alan Cox <alan@redhat.com>
20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
29#include <linux/module.h>
30#include <linux/config.h>
31#include <linux/types.h>
32#include <linux/kernel.h>
33#include <linux/fs.h>
34#include <linux/mm.h>
35#include <linux/miscdevice.h>
36#include <linux/watchdog.h>
37#include <linux/reboot.h>
38#include <linux/smp_lock.h>
39#include <linux/init.h>
40#include <linux/err.h>
41#include <linux/platform_device.h>
42#include <linux/moduleparam.h>
43#include <linux/clk.h>
44
45#include <asm/io.h>
46#include <asm/uaccess.h>
47#include <asm/hardware.h>
48#include <asm/bitops.h>
49
50#include <asm/arch/prcm.h>
51
52#include "omap_wdt.h"
53
54static unsigned timer_margin;
55module_param(timer_margin, uint, 0);
56MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
57
58static int omap_wdt_users;
59static struct clk *armwdt_ck = NULL;
60static struct clk *mpu_wdt_ick = NULL;
61static struct clk *mpu_wdt_fck = NULL;
62
63static unsigned int wdt_trgr_pattern = 0x1234;
64
65static void omap_wdt_ping(void)
66{
67 /* wait for posted write to complete */
68 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
69 cpu_relax();
70 wdt_trgr_pattern = ~wdt_trgr_pattern;
71 omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
72 /* wait for posted write to complete */
73 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
74 cpu_relax();
75 /* reloaded WCRR from WLDR */
76}
77
78static void omap_wdt_enable(void)
79{
80 /* Sequence to enable the watchdog */
81 omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
82 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
83 cpu_relax();
84 omap_writel(0x4444, OMAP_WATCHDOG_SPR);
85 while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
86 cpu_relax();
87}
88
89static void omap_wdt_disable(void)
90{
91 /* sequence required to disable watchdog */
92 omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
93 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
94 cpu_relax();
95 omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
96 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
97 cpu_relax();
98}
99
100static void omap_wdt_adjust_timeout(unsigned new_timeout)
101{
102 if (new_timeout < TIMER_MARGIN_MIN)
103 new_timeout = TIMER_MARGIN_DEFAULT;
104 if (new_timeout > TIMER_MARGIN_MAX)
105 new_timeout = TIMER_MARGIN_MAX;
106 timer_margin = new_timeout;
107}
108
109static void omap_wdt_set_timeout(void)
110{
111 u32 pre_margin = GET_WLDR_VAL(timer_margin);
112
113 /* just count up at 32 KHz */
114 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
115 cpu_relax();
116 omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
117 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
118 cpu_relax();
119}
120
121/*
122 * Allow only one task to hold it open
123 */
124
125static int omap_wdt_open(struct inode *inode, struct file *file)
126{
127 if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
128 return -EBUSY;
129
130 if (cpu_is_omap16xx())
131 clk_enable(armwdt_ck); /* Enable the clock */
132
133 if (cpu_is_omap24xx()) {
134 clk_enable(mpu_wdt_ick); /* Enable the interface clock */
135 clk_enable(mpu_wdt_fck); /* Enable the functional clock */
136 }
137
138 /* initialize prescaler */
139 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
140 cpu_relax();
141 omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
142 while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
143 cpu_relax();
144
145 omap_wdt_set_timeout();
146 omap_wdt_enable();
147 return 0;
148}
149
150static int omap_wdt_release(struct inode *inode, struct file *file)
151{
152 /*
153 * Shut off the timer unless NOWAYOUT is defined.
154 */
155#ifndef CONFIG_WATCHDOG_NOWAYOUT
156 omap_wdt_disable();
157
158 if (cpu_is_omap16xx()) {
159 clk_disable(armwdt_ck); /* Disable the clock */
160 clk_put(armwdt_ck);
161 armwdt_ck = NULL;
162 }
163
164 if (cpu_is_omap24xx()) {
165 clk_disable(mpu_wdt_ick); /* Disable the clock */
166 clk_disable(mpu_wdt_fck); /* Disable the clock */
167 clk_put(mpu_wdt_ick);
168 clk_put(mpu_wdt_fck);
169 mpu_wdt_ick = NULL;
170 mpu_wdt_fck = NULL;
171 }
172#else
173 printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
174#endif
175 omap_wdt_users = 0;
176 return 0;
177}
178
179static ssize_t
180omap_wdt_write(struct file *file, const char __user *data,
181 size_t len, loff_t *ppos)
182{
183 /* Refresh LOAD_TIME. */
184 if (len)
185 omap_wdt_ping();
186 return len;
187}
188
189static int
190omap_wdt_ioctl(struct inode *inode, struct file *file,
191 unsigned int cmd, unsigned long arg)
192{
193 int new_margin;
194 static struct watchdog_info ident = {
195 .identity = "OMAP Watchdog",
196 .options = WDIOF_SETTIMEOUT,
197 .firmware_version = 0,
198 };
199
200 switch (cmd) {
201 default:
202 return -ENOIOCTLCMD;
203 case WDIOC_GETSUPPORT:
204 return copy_to_user((struct watchdog_info __user *)arg, &ident,
205 sizeof(ident));
206 case WDIOC_GETSTATUS:
207 return put_user(0, (int __user *)arg);
208 case WDIOC_GETBOOTSTATUS:
209 if (cpu_is_omap16xx())
210 return put_user(omap_readw(ARM_SYSST),
211 (int __user *)arg);
212 if (cpu_is_omap24xx())
213 return put_user(omap_prcm_get_reset_sources(),
214 (int __user *)arg);
215 case WDIOC_KEEPALIVE:
216 omap_wdt_ping();
217 return 0;
218 case WDIOC_SETTIMEOUT:
219 if (get_user(new_margin, (int __user *)arg))
220 return -EFAULT;
221 omap_wdt_adjust_timeout(new_margin);
222
223 omap_wdt_disable();
224 omap_wdt_set_timeout();
225 omap_wdt_enable();
226
227 omap_wdt_ping();
228 /* Fall */
229 case WDIOC_GETTIMEOUT:
230 return put_user(timer_margin, (int __user *)arg);
231 }
232}
233
234static struct file_operations omap_wdt_fops = {
235 .owner = THIS_MODULE,
236 .write = omap_wdt_write,
237 .ioctl = omap_wdt_ioctl,
238 .open = omap_wdt_open,
239 .release = omap_wdt_release,
240};
241
242static struct miscdevice omap_wdt_miscdev = {
243 .minor = WATCHDOG_MINOR,
244 .name = "watchdog",
245 .fops = &omap_wdt_fops
246};
247
248static int __init omap_wdt_probe(struct platform_device *pdev)
249{
250 struct resource *res, *mem;
251 int ret;
252
253 /* reserve static register mappings */
254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
255 if (!res)
256 return -ENOENT;
257
258 mem = request_mem_region(res->start, res->end - res->start + 1,
259 pdev->name);
260 if (mem == NULL)
261 return -EBUSY;
262
263 platform_set_drvdata(pdev, mem);
264
265 omap_wdt_users = 0;
266
267 if (cpu_is_omap16xx()) {
268 armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
269 if (IS_ERR(armwdt_ck)) {
270 ret = PTR_ERR(armwdt_ck);
271 armwdt_ck = NULL;
272 goto fail;
273 }
274 }
275
276 if (cpu_is_omap24xx()) {
277 mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
278 if (IS_ERR(mpu_wdt_ick)) {
279 ret = PTR_ERR(mpu_wdt_ick);
280 mpu_wdt_ick = NULL;
281 goto fail;
282 }
283 mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
284 if (IS_ERR(mpu_wdt_fck)) {
285 ret = PTR_ERR(mpu_wdt_fck);
286 mpu_wdt_fck = NULL;
287 goto fail;
288 }
289 }
290
291 omap_wdt_disable();
292 omap_wdt_adjust_timeout(timer_margin);
293
294 omap_wdt_miscdev.dev = &pdev->dev;
295 ret = misc_register(&omap_wdt_miscdev);
296 if (ret)
297 goto fail;
298
299 pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
300
301 /* autogate OCP interface clock */
302 omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
303 return 0;
304
305fail:
306 if (armwdt_ck)
307 clk_put(armwdt_ck);
308 if (mpu_wdt_ick)
309 clk_put(mpu_wdt_ick);
310 if (mpu_wdt_fck)
311 clk_put(mpu_wdt_fck);
312 release_resource(mem);
313 return ret;
314}
315
316static void omap_wdt_shutdown(struct platform_device *pdev)
317{
318 omap_wdt_disable();
319}
320
321static int omap_wdt_remove(struct platform_device *pdev)
322{
323 struct resource *mem = platform_get_drvdata(pdev);
324 misc_deregister(&omap_wdt_miscdev);
325 release_resource(mem);
326 if (armwdt_ck)
327 clk_put(armwdt_ck);
328 if (mpu_wdt_ick)
329 clk_put(mpu_wdt_ick);
330 if (mpu_wdt_fck)
331 clk_put(mpu_wdt_fck);
332 return 0;
333}
334
335#ifdef CONFIG_PM
336
337/* REVISIT ... not clear this is the best way to handle system suspend; and
338 * it's very inappropriate for selective device suspend (e.g. suspending this
339 * through sysfs rather than by stopping the watchdog daemon). Also, this
340 * may not play well enough with NOWAYOUT...
341 */
342
343static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
344{
345 if (omap_wdt_users)
346 omap_wdt_disable();
347 return 0;
348}
349
350static int omap_wdt_resume(struct platform_device *pdev)
351{
352 if (omap_wdt_users) {
353 omap_wdt_enable();
354 omap_wdt_ping();
355 }
356 return 0;
357}
358
359#else
360#define omap_wdt_suspend NULL
361#define omap_wdt_resume NULL
362#endif
363
364static struct platform_driver omap_wdt_driver = {
365 .probe = omap_wdt_probe,
366 .remove = omap_wdt_remove,
367 .shutdown = omap_wdt_shutdown,
368 .suspend = omap_wdt_suspend,
369 .resume = omap_wdt_resume,
370 .driver = {
371 .owner = THIS_MODULE,
372 .name = "omap_wdt",
373 },
374};
375
376static int __init omap_wdt_init(void)
377{
378 return platform_driver_register(&omap_wdt_driver);
379}
380
381static void __exit omap_wdt_exit(void)
382{
383 platform_driver_unregister(&omap_wdt_driver);
384}
385
386module_init(omap_wdt_init);
387module_exit(omap_wdt_exit);
388
389MODULE_AUTHOR("George G. Davis");
390MODULE_LICENSE("GPL");
391MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);