| Raghu Vatsavayi | f21fb3e | 2015-06-09 18:15:23 -0700 | [diff] [blame] | 1 | /********************************************************************** |
| 2 | * Author: Cavium, Inc. |
| 3 | * |
| 4 | * Contact: support@cavium.com |
| 5 | * Please include "LiquidIO" in the subject. |
| 6 | * |
| 7 | * Copyright (c) 2003-2015 Cavium, Inc. |
| 8 | * |
| 9 | * This file is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License, Version 2, as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This file is distributed in the hope that it will be useful, but |
| 14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
| 16 | * NONINFRINGEMENT. See the GNU General Public License for more |
| 17 | * details. |
| 18 | * |
| 19 | * This file may also be available under a different license from Cavium. |
| 20 | * Contact Cavium, Inc. for more information |
| 21 | **********************************************************************/ |
| 22 | |
| 23 | /*! \file cn66xx_regs.h |
| 24 | * \brief Host Driver: Register Address and Register Mask values for |
| 25 | * Octeon CN66XX devices. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CN66XX_REGS_H__ |
| 29 | #define __CN66XX_REGS_H__ |
| 30 | |
| 31 | #define CN6XXX_XPANSION_BAR 0x30 |
| 32 | |
| 33 | #define CN6XXX_MSI_CAP 0x50 |
| 34 | #define CN6XXX_MSI_ADDR_LO 0x54 |
| 35 | #define CN6XXX_MSI_ADDR_HI 0x58 |
| 36 | #define CN6XXX_MSI_DATA 0x5C |
| 37 | |
| 38 | #define CN6XXX_PCIE_CAP 0x70 |
| 39 | #define CN6XXX_PCIE_DEVCAP 0x74 |
| 40 | #define CN6XXX_PCIE_DEVCTL 0x78 |
| 41 | #define CN6XXX_PCIE_LINKCAP 0x7C |
| 42 | #define CN6XXX_PCIE_LINKCTL 0x80 |
| 43 | #define CN6XXX_PCIE_SLOTCAP 0x84 |
| 44 | #define CN6XXX_PCIE_SLOTCTL 0x88 |
| 45 | |
| 46 | #define CN6XXX_PCIE_ENH_CAP 0x100 |
| 47 | #define CN6XXX_PCIE_UNCORR_ERR_STATUS 0x104 |
| 48 | #define CN6XXX_PCIE_UNCORR_ERR_MASK 0x108 |
| 49 | #define CN6XXX_PCIE_UNCORR_ERR 0x10C |
| 50 | #define CN6XXX_PCIE_CORR_ERR_STATUS 0x110 |
| 51 | #define CN6XXX_PCIE_CORR_ERR_MASK 0x114 |
| 52 | #define CN6XXX_PCIE_ADV_ERR_CAP 0x118 |
| 53 | |
| 54 | #define CN6XXX_PCIE_ACK_REPLAY_TIMER 0x700 |
| 55 | #define CN6XXX_PCIE_OTHER_MSG 0x704 |
| 56 | #define CN6XXX_PCIE_PORT_FORCE_LINK 0x708 |
| 57 | #define CN6XXX_PCIE_ACK_FREQ 0x70C |
| 58 | #define CN6XXX_PCIE_PORT_LINK_CTL 0x710 |
| 59 | #define CN6XXX_PCIE_LANE_SKEW 0x714 |
| 60 | #define CN6XXX_PCIE_SYM_NUM 0x718 |
| 61 | #define CN6XXX_PCIE_FLTMSK 0x720 |
| 62 | |
| 63 | /* ############## BAR0 Registers ################ */ |
| 64 | |
| 65 | #define CN6XXX_SLI_CTL_PORT0 0x0050 |
| 66 | #define CN6XXX_SLI_CTL_PORT1 0x0060 |
| 67 | |
| 68 | #define CN6XXX_SLI_WINDOW_CTL 0x02E0 |
| 69 | #define CN6XXX_SLI_DBG_DATA 0x0310 |
| 70 | #define CN6XXX_SLI_SCRATCH1 0x03C0 |
| 71 | #define CN6XXX_SLI_SCRATCH2 0x03D0 |
| 72 | #define CN6XXX_SLI_CTL_STATUS 0x0570 |
| 73 | |
| 74 | #define CN6XXX_WIN_WR_ADDR_LO 0x0000 |
| 75 | #define CN6XXX_WIN_WR_ADDR_HI 0x0004 |
| 76 | #define CN6XXX_WIN_WR_ADDR64 CN6XXX_WIN_WR_ADDR_LO |
| 77 | |
| 78 | #define CN6XXX_WIN_RD_ADDR_LO 0x0010 |
| 79 | #define CN6XXX_WIN_RD_ADDR_HI 0x0014 |
| 80 | #define CN6XXX_WIN_RD_ADDR64 CN6XXX_WIN_RD_ADDR_LO |
| 81 | |
| 82 | #define CN6XXX_WIN_WR_DATA_LO 0x0020 |
| 83 | #define CN6XXX_WIN_WR_DATA_HI 0x0024 |
| 84 | #define CN6XXX_WIN_WR_DATA64 CN6XXX_WIN_WR_DATA_LO |
| 85 | |
| 86 | #define CN6XXX_WIN_RD_DATA_LO 0x0040 |
| 87 | #define CN6XXX_WIN_RD_DATA_HI 0x0044 |
| 88 | #define CN6XXX_WIN_RD_DATA64 CN6XXX_WIN_RD_DATA_LO |
| 89 | |
| 90 | #define CN6XXX_WIN_WR_MASK_LO 0x0030 |
| 91 | #define CN6XXX_WIN_WR_MASK_HI 0x0034 |
| 92 | #define CN6XXX_WIN_WR_MASK_REG CN6XXX_WIN_WR_MASK_LO |
| 93 | |
| 94 | /* 1 register (32-bit) to enable Input queues */ |
| 95 | #define CN6XXX_SLI_PKT_INSTR_ENB 0x1000 |
| 96 | |
| 97 | /* 1 register (32-bit) to enable Output queues */ |
| 98 | #define CN6XXX_SLI_PKT_OUT_ENB 0x1010 |
| 99 | |
| 100 | /* 1 register (32-bit) to determine whether Output queues are in reset. */ |
| 101 | #define CN6XXX_SLI_PORT_IN_RST_OQ 0x11F0 |
| 102 | |
| 103 | /* 1 register (32-bit) to determine whether Input queues are in reset. */ |
| 104 | #define CN6XXX_SLI_PORT_IN_RST_IQ 0x11F4 |
| 105 | |
| 106 | /*###################### REQUEST QUEUE #########################*/ |
| 107 | |
| 108 | /* 1 register (32-bit) - instr. size of each input queue. */ |
| 109 | #define CN6XXX_SLI_PKT_INSTR_SIZE 0x1020 |
| 110 | |
| 111 | /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ |
| 112 | #define CN6XXX_SLI_IQ_INSTR_COUNT_START 0x2000 |
| 113 | |
| 114 | /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */ |
| 115 | #define CN6XXX_SLI_IQ_BASE_ADDR_START64 0x2800 |
| 116 | |
| 117 | /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ |
| 118 | #define CN6XXX_SLI_IQ_DOORBELL_START 0x2C00 |
| 119 | |
| 120 | /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ |
| 121 | #define CN6XXX_SLI_IQ_SIZE_START 0x3000 |
| 122 | |
| 123 | /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */ |
| 124 | #define CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 0x3400 |
| 125 | |
| 126 | /* 1 register (64-bit) - Back Pressure for each input queue - SLI_PKT0_IN_BP */ |
| 127 | #define CN66XX_SLI_INPUT_BP_START64 0x3800 |
| 128 | |
| 129 | /* Each Input Queue register is at a 16-byte Offset in BAR0 */ |
| 130 | #define CN6XXX_IQ_OFFSET 0x10 |
| 131 | |
| 132 | /* 1 register (32-bit) - ES, RO, NS, Arbitration for Input Queue Data & |
| 133 | * gather list fetches. SLI_PKT_INPUT_CONTROL. |
| 134 | */ |
| 135 | #define CN6XXX_SLI_PKT_INPUT_CONTROL 0x1170 |
| 136 | |
| 137 | /* 1 register (64-bit) - Number of instructions to read at one time |
| 138 | * - 2 bits for each input ring. SLI_PKT_INSTR_RD_SIZE. |
| 139 | */ |
| 140 | #define CN6XXX_SLI_PKT_INSTR_RD_SIZE 0x11A0 |
| 141 | |
| 142 | /* 1 register (64-bit) - Assign Input ring to MAC port |
| 143 | * - 2 bits for each input ring. SLI_PKT_IN_PCIE_PORT. |
| 144 | */ |
| 145 | #define CN6XXX_SLI_IN_PCIE_PORT 0x11B0 |
| 146 | |
| 147 | /*------- Request Queue Macros ---------*/ |
| 148 | #define CN6XXX_SLI_IQ_BASE_ADDR64(iq) \ |
| 149 | (CN6XXX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN6XXX_IQ_OFFSET)) |
| 150 | |
| 151 | #define CN6XXX_SLI_IQ_SIZE(iq) \ |
| 152 | (CN6XXX_SLI_IQ_SIZE_START + ((iq) * CN6XXX_IQ_OFFSET)) |
| 153 | |
| 154 | #define CN6XXX_SLI_IQ_PKT_INSTR_HDR64(iq) \ |
| 155 | (CN6XXX_SLI_IQ_PKT_INSTR_HDR_START64 + ((iq) * CN6XXX_IQ_OFFSET)) |
| 156 | |
| 157 | #define CN6XXX_SLI_IQ_DOORBELL(iq) \ |
| 158 | (CN6XXX_SLI_IQ_DOORBELL_START + ((iq) * CN6XXX_IQ_OFFSET)) |
| 159 | |
| 160 | #define CN6XXX_SLI_IQ_INSTR_COUNT(iq) \ |
| 161 | (CN6XXX_SLI_IQ_INSTR_COUNT_START + ((iq) * CN6XXX_IQ_OFFSET)) |
| 162 | |
| 163 | #define CN66XX_SLI_IQ_BP64(iq) \ |
| 164 | (CN66XX_SLI_INPUT_BP_START64 + ((iq) * CN6XXX_IQ_OFFSET)) |
| 165 | |
| 166 | /*------------------ Masks ----------------*/ |
| 167 | #define CN6XXX_INPUT_CTL_ROUND_ROBIN_ARB BIT(22) |
| 168 | #define CN6XXX_INPUT_CTL_DATA_NS BIT(8) |
| 169 | #define CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) |
| 170 | #define CN6XXX_INPUT_CTL_DATA_RO BIT(5) |
| 171 | #define CN6XXX_INPUT_CTL_USE_CSR BIT(4) |
| 172 | #define CN6XXX_INPUT_CTL_GATHER_NS BIT(3) |
| 173 | #define CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP BIT(2) |
| 174 | #define CN6XXX_INPUT_CTL_GATHER_RO BIT(1) |
| 175 | |
| 176 | #ifdef __BIG_ENDIAN_BITFIELD |
| 177 | #define CN6XXX_INPUT_CTL_MASK \ |
| 178 | (CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP \ |
| 179 | | CN6XXX_INPUT_CTL_USE_CSR \ |
| 180 | | CN6XXX_INPUT_CTL_GATHER_ES_64B_SWAP) |
| 181 | #else |
| 182 | #define CN6XXX_INPUT_CTL_MASK \ |
| 183 | (CN6XXX_INPUT_CTL_DATA_ES_64B_SWAP \ |
| 184 | | CN6XXX_INPUT_CTL_USE_CSR) |
| 185 | #endif |
| 186 | |
| 187 | /*############################ OUTPUT QUEUE #########################*/ |
| 188 | |
| 189 | /* 32 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ |
| 190 | #define CN6XXX_SLI_OQ0_BUFF_INFO_SIZE 0x0C00 |
| 191 | |
| 192 | /* 32 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ |
| 193 | #define CN6XXX_SLI_OQ_BASE_ADDR_START64 0x1400 |
| 194 | |
| 195 | /* 32 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ |
| 196 | #define CN6XXX_SLI_OQ_PKT_CREDITS_START 0x1800 |
| 197 | |
| 198 | /* 32 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ |
| 199 | #define CN6XXX_SLI_OQ_SIZE_START 0x1C00 |
| 200 | |
| 201 | /* 32 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ |
| 202 | #define CN6XXX_SLI_OQ_PKT_SENT_START 0x2400 |
| 203 | |
| 204 | /* Each Output Queue register is at a 16-byte Offset in BAR0 */ |
| 205 | #define CN6XXX_OQ_OFFSET 0x10 |
| 206 | |
| 207 | /* 1 register (32-bit) - 1 bit for each output queue |
| 208 | * - Relaxed Ordering setting for reading Output Queues descriptors |
| 209 | * - SLI_PKT_SLIST_ROR |
| 210 | */ |
| 211 | #define CN6XXX_SLI_PKT_SLIST_ROR 0x1030 |
| 212 | |
| 213 | /* 1 register (32-bit) - 1 bit for each output queue |
| 214 | * - No Snoop mode for reading Output Queues descriptors |
| 215 | * - SLI_PKT_SLIST_NS |
| 216 | */ |
| 217 | #define CN6XXX_SLI_PKT_SLIST_NS 0x1040 |
| 218 | |
| 219 | /* 1 register (64-bit) - 2 bits for each output queue |
| 220 | * - Endian-Swap mode for reading Output Queue descriptors |
| 221 | * - SLI_PKT_SLIST_ES |
| 222 | */ |
| 223 | #define CN6XXX_SLI_PKT_SLIST_ES64 0x1050 |
| 224 | |
| 225 | /* 1 register (32-bit) - 1 bit for each output queue |
| 226 | * - InfoPtr mode for Output Queues. |
| 227 | * - SLI_PKT_IPTR |
| 228 | */ |
| 229 | #define CN6XXX_SLI_PKT_IPTR 0x1070 |
| 230 | |
| 231 | /* 1 register (32-bit) - 1 bit for each output queue |
| 232 | * - DPTR format selector for Output queues. |
| 233 | * - SLI_PKT_DPADDR |
| 234 | */ |
| 235 | #define CN6XXX_SLI_PKT_DPADDR 0x1080 |
| 236 | |
| 237 | /* 1 register (32-bit) - 1 bit for each output queue |
| 238 | * - Relaxed Ordering setting for reading Output Queues data |
| 239 | * - SLI_PKT_DATA_OUT_ROR |
| 240 | */ |
| 241 | #define CN6XXX_SLI_PKT_DATA_OUT_ROR 0x1090 |
| 242 | |
| 243 | /* 1 register (32-bit) - 1 bit for each output queue |
| 244 | * - No Snoop mode for reading Output Queues data |
| 245 | * - SLI_PKT_DATA_OUT_NS |
| 246 | */ |
| 247 | #define CN6XXX_SLI_PKT_DATA_OUT_NS 0x10A0 |
| 248 | |
| 249 | /* 1 register (64-bit) - 2 bits for each output queue |
| 250 | * - Endian-Swap mode for reading Output Queue data |
| 251 | * - SLI_PKT_DATA_OUT_ES |
| 252 | */ |
| 253 | #define CN6XXX_SLI_PKT_DATA_OUT_ES64 0x10B0 |
| 254 | |
| 255 | /* 1 register (32-bit) - 1 bit for each output queue |
| 256 | * - Controls whether SLI_PKTn_CNTS is incremented for bytes or for packets. |
| 257 | * - SLI_PKT_OUT_BMODE |
| 258 | */ |
| 259 | #define CN6XXX_SLI_PKT_OUT_BMODE 0x10D0 |
| 260 | |
| 261 | /* 1 register (64-bit) - 2 bits for each output queue |
| 262 | * - Assign PCIE port for Output queues |
| 263 | * - SLI_PKT_PCIE_PORT. |
| 264 | */ |
| 265 | #define CN6XXX_SLI_PKT_PCIE_PORT64 0x10E0 |
| 266 | |
| 267 | /* 1 (64-bit) register for Output Queue Packet Count Interrupt Threshold |
| 268 | * & Time Threshold. The same setting applies to all 32 queues. |
| 269 | * The register is defined as a 64-bit registers, but we use the |
| 270 | * 32-bit offsets to define distinct addresses. |
| 271 | */ |
| 272 | #define CN6XXX_SLI_OQ_INT_LEVEL_PKTS 0x1120 |
| 273 | #define CN6XXX_SLI_OQ_INT_LEVEL_TIME 0x1124 |
| 274 | |
| 275 | /* 1 (64-bit register) for Output Queue backpressure across all rings. */ |
| 276 | #define CN6XXX_SLI_OQ_WMARK 0x1180 |
| 277 | |
| 278 | /* 1 register to control output queue global backpressure & ring enable. */ |
| 279 | #define CN6XXX_SLI_PKT_CTL 0x1220 |
| 280 | |
| 281 | /*------- Output Queue Macros ---------*/ |
| 282 | #define CN6XXX_SLI_OQ_BASE_ADDR64(oq) \ |
| 283 | (CN6XXX_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN6XXX_OQ_OFFSET)) |
| 284 | |
| 285 | #define CN6XXX_SLI_OQ_SIZE(oq) \ |
| 286 | (CN6XXX_SLI_OQ_SIZE_START + ((oq) * CN6XXX_OQ_OFFSET)) |
| 287 | |
| 288 | #define CN6XXX_SLI_OQ_BUFF_INFO_SIZE(oq) \ |
| 289 | (CN6XXX_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN6XXX_OQ_OFFSET)) |
| 290 | |
| 291 | #define CN6XXX_SLI_OQ_PKTS_SENT(oq) \ |
| 292 | (CN6XXX_SLI_OQ_PKT_SENT_START + ((oq) * CN6XXX_OQ_OFFSET)) |
| 293 | |
| 294 | #define CN6XXX_SLI_OQ_PKTS_CREDIT(oq) \ |
| 295 | (CN6XXX_SLI_OQ_PKT_CREDITS_START + ((oq) * CN6XXX_OQ_OFFSET)) |
| 296 | |
| 297 | /*######################### DMA Counters #########################*/ |
| 298 | |
| 299 | /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */ |
| 300 | #define CN6XXX_DMA_CNT_START 0x0400 |
| 301 | |
| 302 | /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values |
| 303 | * SLI_DMA_0_TIM |
| 304 | */ |
| 305 | #define CN6XXX_DMA_TIM_START 0x0420 |
| 306 | |
| 307 | /* 2 registers (64-bit) - DMA count & Time Interrupt threshold - |
| 308 | * SLI_DMA_0_INT_LEVEL |
| 309 | */ |
| 310 | #define CN6XXX_DMA_INT_LEVEL_START 0x03E0 |
| 311 | |
| 312 | /* Each DMA register is at a 16-byte Offset in BAR0 */ |
| 313 | #define CN6XXX_DMA_OFFSET 0x10 |
| 314 | |
| 315 | /*---------- DMA Counter Macros ---------*/ |
| 316 | #define CN6XXX_DMA_CNT(dq) \ |
| 317 | (CN6XXX_DMA_CNT_START + ((dq) * CN6XXX_DMA_OFFSET)) |
| 318 | |
| 319 | #define CN6XXX_DMA_INT_LEVEL(dq) \ |
| 320 | (CN6XXX_DMA_INT_LEVEL_START + ((dq) * CN6XXX_DMA_OFFSET)) |
| 321 | |
| 322 | #define CN6XXX_DMA_PKT_INT_LEVEL(dq) \ |
| 323 | (CN6XXX_DMA_INT_LEVEL_START + ((dq) * CN6XXX_DMA_OFFSET)) |
| 324 | |
| 325 | #define CN6XXX_DMA_TIME_INT_LEVEL(dq) \ |
| 326 | (CN6XXX_DMA_INT_LEVEL_START + 4 + ((dq) * CN6XXX_DMA_OFFSET)) |
| 327 | |
| 328 | #define CN6XXX_DMA_TIM(dq) \ |
| 329 | (CN6XXX_DMA_TIM_START + ((dq) * CN6XXX_DMA_OFFSET)) |
| 330 | |
| 331 | /*######################## INTERRUPTS #########################*/ |
| 332 | |
| 333 | /* 1 register (64-bit) for Interrupt Summary */ |
| 334 | #define CN6XXX_SLI_INT_SUM64 0x0330 |
| 335 | |
| 336 | /* 1 register (64-bit) for Interrupt Enable */ |
| 337 | #define CN6XXX_SLI_INT_ENB64_PORT0 0x0340 |
| 338 | #define CN6XXX_SLI_INT_ENB64_PORT1 0x0350 |
| 339 | |
| 340 | /* 1 register (32-bit) to enable Output Queue Packet/Byte Count Interrupt */ |
| 341 | #define CN6XXX_SLI_PKT_CNT_INT_ENB 0x1150 |
| 342 | |
| 343 | /* 1 register (32-bit) to enable Output Queue Packet Timer Interrupt */ |
| 344 | #define CN6XXX_SLI_PKT_TIME_INT_ENB 0x1160 |
| 345 | |
| 346 | /* 1 register (32-bit) to indicate which Output Queue reached pkt threshold */ |
| 347 | #define CN6XXX_SLI_PKT_CNT_INT 0x1130 |
| 348 | |
| 349 | /* 1 register (32-bit) to indicate which Output Queue reached time threshold */ |
| 350 | #define CN6XXX_SLI_PKT_TIME_INT 0x1140 |
| 351 | |
| 352 | /*------------------ Interrupt Masks ----------------*/ |
| 353 | |
| 354 | #define CN6XXX_INTR_RML_TIMEOUT_ERR BIT(1) |
| 355 | #define CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR BIT(2) |
| 356 | #define CN6XXX_INTR_IO2BIG_ERR BIT(3) |
| 357 | #define CN6XXX_INTR_PKT_COUNT BIT(4) |
| 358 | #define CN6XXX_INTR_PKT_TIME BIT(5) |
| 359 | #define CN6XXX_INTR_M0UPB0_ERR BIT(8) |
| 360 | #define CN6XXX_INTR_M0UPWI_ERR BIT(9) |
| 361 | #define CN6XXX_INTR_M0UNB0_ERR BIT(10) |
| 362 | #define CN6XXX_INTR_M0UNWI_ERR BIT(11) |
| 363 | #define CN6XXX_INTR_M1UPB0_ERR BIT(12) |
| 364 | #define CN6XXX_INTR_M1UPWI_ERR BIT(13) |
| 365 | #define CN6XXX_INTR_M1UNB0_ERR BIT(14) |
| 366 | #define CN6XXX_INTR_M1UNWI_ERR BIT(15) |
| 367 | #define CN6XXX_INTR_MIO_INT0 BIT(16) |
| 368 | #define CN6XXX_INTR_MIO_INT1 BIT(17) |
| 369 | #define CN6XXX_INTR_MAC_INT0 BIT(18) |
| 370 | #define CN6XXX_INTR_MAC_INT1 BIT(19) |
| 371 | |
| 372 | #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32) |
| 373 | #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33) |
| 374 | #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34) |
| 375 | #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35) |
| 376 | #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36) |
| 377 | #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37) |
| 378 | #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48) |
| 379 | #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49) |
| 380 | #define CN6XXX_INTR_POUT_ERR BIT_ULL(50) |
| 381 | #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51) |
| 382 | #define CN6XXX_INTR_PGL_ERR BIT_ULL(52) |
| 383 | #define CN6XXX_INTR_PDI_ERR BIT_ULL(53) |
| 384 | #define CN6XXX_INTR_POP_ERR BIT_ULL(54) |
| 385 | #define CN6XXX_INTR_PINS_ERR BIT_ULL(55) |
| 386 | #define CN6XXX_INTR_SPRT0_ERR BIT_ULL(56) |
| 387 | #define CN6XXX_INTR_SPRT1_ERR BIT_ULL(57) |
| 388 | #define CN6XXX_INTR_ILL_PAD_ERR BIT_ULL(60) |
| 389 | |
| 390 | #define CN6XXX_INTR_DMA0_DATA (CN6XXX_INTR_DMA0_TIME) |
| 391 | |
| 392 | #define CN6XXX_INTR_DMA1_DATA (CN6XXX_INTR_DMA1_TIME) |
| 393 | |
| 394 | #define CN6XXX_INTR_DMA_DATA \ |
| 395 | (CN6XXX_INTR_DMA0_DATA | CN6XXX_INTR_DMA1_DATA) |
| 396 | |
| 397 | #define CN6XXX_INTR_PKT_DATA (CN6XXX_INTR_PKT_TIME | \ |
| 398 | CN6XXX_INTR_PKT_COUNT) |
| 399 | |
| 400 | /* Sum of interrupts for all PCI-Express Data Interrupts */ |
| 401 | #define CN6XXX_INTR_PCIE_DATA \ |
| 402 | (CN6XXX_INTR_DMA_DATA | CN6XXX_INTR_PKT_DATA) |
| 403 | |
| 404 | #define CN6XXX_INTR_MIO \ |
| 405 | (CN6XXX_INTR_MIO_INT0 | CN6XXX_INTR_MIO_INT1) |
| 406 | |
| 407 | #define CN6XXX_INTR_MAC \ |
| 408 | (CN6XXX_INTR_MAC_INT0 | CN6XXX_INTR_MAC_INT1) |
| 409 | |
| 410 | /* Sum of interrupts for error events */ |
| 411 | #define CN6XXX_INTR_ERR \ |
| 412 | (CN6XXX_INTR_BAR0_RW_TIMEOUT_ERR \ |
| 413 | | CN6XXX_INTR_IO2BIG_ERR \ |
| 414 | | CN6XXX_INTR_M0UPB0_ERR \ |
| 415 | | CN6XXX_INTR_M0UPWI_ERR \ |
| 416 | | CN6XXX_INTR_M0UNB0_ERR \ |
| 417 | | CN6XXX_INTR_M0UNWI_ERR \ |
| 418 | | CN6XXX_INTR_M1UPB0_ERR \ |
| 419 | | CN6XXX_INTR_M1UPWI_ERR \ |
| 420 | | CN6XXX_INTR_M1UPB0_ERR \ |
| 421 | | CN6XXX_INTR_M1UNWI_ERR \ |
| 422 | | CN6XXX_INTR_INSTR_DB_OF_ERR \ |
| 423 | | CN6XXX_INTR_SLIST_DB_OF_ERR \ |
| 424 | | CN6XXX_INTR_POUT_ERR \ |
| 425 | | CN6XXX_INTR_PIN_BP_ERR \ |
| 426 | | CN6XXX_INTR_PGL_ERR \ |
| 427 | | CN6XXX_INTR_PDI_ERR \ |
| 428 | | CN6XXX_INTR_POP_ERR \ |
| 429 | | CN6XXX_INTR_PINS_ERR \ |
| 430 | | CN6XXX_INTR_SPRT0_ERR \ |
| 431 | | CN6XXX_INTR_SPRT1_ERR \ |
| 432 | | CN6XXX_INTR_ILL_PAD_ERR) |
| 433 | |
| 434 | /* Programmed Mask for Interrupt Sum */ |
| 435 | #define CN6XXX_INTR_MASK \ |
| 436 | (CN6XXX_INTR_PCIE_DATA \ |
| 437 | | CN6XXX_INTR_DMA0_FORCE \ |
| 438 | | CN6XXX_INTR_DMA1_FORCE \ |
| 439 | | CN6XXX_INTR_MIO \ |
| 440 | | CN6XXX_INTR_MAC \ |
| 441 | | CN6XXX_INTR_ERR) |
| 442 | |
| 443 | #define CN6XXX_SLI_S2M_PORT0_CTL 0x3D80 |
| 444 | #define CN6XXX_SLI_S2M_PORT1_CTL 0x3D90 |
| 445 | #define CN6XXX_SLI_S2M_PORTX_CTL(port) \ |
| 446 | (CN6XXX_SLI_S2M_PORT0_CTL + (port * 0x10)) |
| 447 | |
| 448 | #define CN6XXX_SLI_INT_ENB64(port) \ |
| 449 | (CN6XXX_SLI_INT_ENB64_PORT0 + (port * 0x10)) |
| 450 | |
| 451 | #define CN6XXX_SLI_MAC_NUMBER 0x3E00 |
| 452 | |
| 453 | /* CN6XXX BAR1 Index registers. */ |
| 454 | #define CN6XXX_PEM_BAR1_INDEX000 0x00011800C00000A8ULL |
| 455 | #define CN6XXX_PEM_OFFSET 0x0000000001000000ULL |
| 456 | |
| 457 | #define CN6XXX_BAR1_INDEX_START CN6XXX_PEM_BAR1_INDEX000 |
| 458 | #define CN6XXX_PCI_BAR1_OFFSET 0x8 |
| 459 | |
| 460 | #define CN6XXX_BAR1_REG(idx, port) \ |
| 461 | (CN6XXX_BAR1_INDEX_START + (port * CN6XXX_PEM_OFFSET) + \ |
| 462 | (CN6XXX_PCI_BAR1_OFFSET * (idx))) |
| 463 | |
| 464 | /*############################ DPI #########################*/ |
| 465 | |
| 466 | #define CN6XXX_DPI_CTL 0x0001df0000000040ULL |
| 467 | |
| 468 | #define CN6XXX_DPI_DMA_CONTROL 0x0001df0000000048ULL |
| 469 | |
| 470 | #define CN6XXX_DPI_REQ_GBL_ENB 0x0001df0000000050ULL |
| 471 | |
| 472 | #define CN6XXX_DPI_REQ_ERR_RSP 0x0001df0000000058ULL |
| 473 | |
| 474 | #define CN6XXX_DPI_REQ_ERR_RST 0x0001df0000000060ULL |
| 475 | |
| 476 | #define CN6XXX_DPI_DMA_ENG0_ENB 0x0001df0000000080ULL |
| 477 | |
| 478 | #define CN6XXX_DPI_DMA_ENG_ENB(q_no) \ |
| 479 | (CN6XXX_DPI_DMA_ENG0_ENB + (q_no * 8)) |
| 480 | |
| 481 | #define CN6XXX_DPI_DMA_ENG0_BUF 0x0001df0000000880ULL |
| 482 | |
| 483 | #define CN6XXX_DPI_DMA_ENG_BUF(q_no) \ |
| 484 | (CN6XXX_DPI_DMA_ENG0_BUF + (q_no * 8)) |
| 485 | |
| 486 | #define CN6XXX_DPI_SLI_PRT0_CFG 0x0001df0000000900ULL |
| 487 | #define CN6XXX_DPI_SLI_PRT1_CFG 0x0001df0000000908ULL |
| 488 | #define CN6XXX_DPI_SLI_PRTX_CFG(port) \ |
| 489 | (CN6XXX_DPI_SLI_PRT0_CFG + (port * 0x10)) |
| 490 | |
| 491 | #define CN6XXX_DPI_DMA_COMMIT_MODE BIT_ULL(58) |
| 492 | #define CN6XXX_DPI_DMA_PKT_HP BIT_ULL(57) |
| 493 | #define CN6XXX_DPI_DMA_PKT_EN BIT_ULL(56) |
| 494 | #define CN6XXX_DPI_DMA_O_ES BIT_ULL(15) |
| 495 | #define CN6XXX_DPI_DMA_O_MODE BIT_ULL(14) |
| 496 | |
| 497 | #define CN6XXX_DPI_DMA_CTL_MASK \ |
| 498 | (CN6XXX_DPI_DMA_COMMIT_MODE | \ |
| 499 | CN6XXX_DPI_DMA_PKT_HP | \ |
| 500 | CN6XXX_DPI_DMA_PKT_EN | \ |
| 501 | CN6XXX_DPI_DMA_O_ES | \ |
| 502 | CN6XXX_DPI_DMA_O_MODE) |
| 503 | |
| 504 | /*############################ CIU #########################*/ |
| 505 | |
| 506 | #define CN6XXX_CIU_SOFT_BIST 0x0001070000000738ULL |
| 507 | #define CN6XXX_CIU_SOFT_RST 0x0001070000000740ULL |
| 508 | |
| 509 | /*############################ MIO #########################*/ |
| 510 | #define CN6XXX_MIO_PTP_CLOCK_CFG 0x0001070000000f00ULL |
| 511 | #define CN6XXX_MIO_PTP_CLOCK_LO 0x0001070000000f08ULL |
| 512 | #define CN6XXX_MIO_PTP_CLOCK_HI 0x0001070000000f10ULL |
| 513 | #define CN6XXX_MIO_PTP_CLOCK_COMP 0x0001070000000f18ULL |
| 514 | #define CN6XXX_MIO_PTP_TIMESTAMP 0x0001070000000f20ULL |
| 515 | #define CN6XXX_MIO_PTP_EVT_CNT 0x0001070000000f28ULL |
| 516 | #define CN6XXX_MIO_PTP_CKOUT_THRESH_LO 0x0001070000000f30ULL |
| 517 | #define CN6XXX_MIO_PTP_CKOUT_THRESH_HI 0x0001070000000f38ULL |
| 518 | #define CN6XXX_MIO_PTP_CKOUT_HI_INCR 0x0001070000000f40ULL |
| 519 | #define CN6XXX_MIO_PTP_CKOUT_LO_INCR 0x0001070000000f48ULL |
| 520 | #define CN6XXX_MIO_PTP_PPS_THRESH_LO 0x0001070000000f50ULL |
| 521 | #define CN6XXX_MIO_PTP_PPS_THRESH_HI 0x0001070000000f58ULL |
| 522 | #define CN6XXX_MIO_PTP_PPS_HI_INCR 0x0001070000000f60ULL |
| 523 | #define CN6XXX_MIO_PTP_PPS_LO_INCR 0x0001070000000f68ULL |
| 524 | |
| 525 | #define CN6XXX_MIO_QLM4_CFG 0x00011800000015B0ULL |
| 526 | #define CN6XXX_MIO_RST_BOOT 0x0001180000001600ULL |
| 527 | |
| 528 | #define CN6XXX_MIO_QLM_CFG_MASK 0x7 |
| 529 | |
| 530 | /*############################ LMC #########################*/ |
| 531 | |
| 532 | #define CN6XXX_LMC0_RESET_CTL 0x0001180088000180ULL |
| 533 | #define CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL |
| 534 | |
| 535 | #endif |