Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/irqdomain.h> |
| 14 | #include <linux/irq.h> |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 15 | #include <linux/kthread.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 16 | |
| 17 | #include "msm_drv.h" |
| 18 | #include "sde_kms.h" |
| 19 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 20 | static void sde_irq_callback_handler(void *arg, int irq_idx) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 21 | { |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 22 | struct sde_kms *sde_kms = arg; |
| 23 | struct sde_irq *irq_obj = &sde_kms->irq_obj; |
| 24 | |
| 25 | /* |
| 26 | * Perform registered function callback |
| 27 | */ |
| 28 | if (irq_obj->irq_cb_tbl && irq_obj->irq_cb_tbl[irq_idx].func) |
| 29 | irq_obj->irq_cb_tbl[irq_idx].func( |
| 30 | irq_obj->irq_cb_tbl[irq_idx].arg, |
| 31 | irq_idx); |
| 32 | |
| 33 | /* |
| 34 | * Clear pending interrupt status in HW. |
| 35 | * NOTE: sde_irq_callback_handler is protected by top-level |
| 36 | * spinlock, so it is safe to clear any interrupt status here. |
| 37 | */ |
| 38 | sde_kms->hw_intr->ops.clear_interrupt_status( |
| 39 | sde_kms->hw_intr, |
| 40 | irq_idx); |
| 41 | } |
| 42 | |
| 43 | static void sde_irq_intf_error_handler(void *arg, int irq_idx) |
| 44 | { |
| 45 | DRM_ERROR("INTF underrun detected, irq_idx=%d\n", irq_idx); |
| 46 | } |
| 47 | |
| 48 | void sde_set_irqmask(struct sde_kms *sde_kms, uint32_t reg, uint32_t irqmask) |
| 49 | { |
| 50 | if (!sde_kms || !sde_kms->hw_intr || |
| 51 | !sde_kms->hw_intr->ops.set_mask) |
| 52 | return; |
| 53 | |
| 54 | sde_kms->hw_intr->ops.set_mask(sde_kms->hw_intr, reg, irqmask); |
| 55 | } |
| 56 | |
| 57 | int sde_irq_idx_lookup(struct sde_kms *sde_kms, enum sde_intr_type intr_type, |
| 58 | u32 instance_idx) |
| 59 | { |
| 60 | if (!sde_kms || !sde_kms->hw_intr || |
| 61 | !sde_kms->hw_intr->ops.irq_idx_lookup) |
| 62 | return -EINVAL; |
| 63 | |
| 64 | return sde_kms->hw_intr->ops.irq_idx_lookup(intr_type, |
| 65 | instance_idx); |
| 66 | } |
| 67 | |
| 68 | int sde_enable_irq(struct sde_kms *sde_kms, int *irq_idxs, u32 irq_count) |
| 69 | { |
| 70 | int i; |
| 71 | int ret = 0; |
| 72 | |
| 73 | if (!sde_kms || !irq_idxs || !sde_kms->hw_intr || |
| 74 | !sde_kms->hw_intr->ops.enable_irq) |
| 75 | return -EINVAL; |
| 76 | |
| 77 | for (i = 0; i < irq_count; i++) { |
| 78 | ret = sde_kms->hw_intr->ops.enable_irq( |
| 79 | sde_kms->hw_intr, |
| 80 | irq_idxs[i]); |
| 81 | if (ret) { |
| 82 | DRM_ERROR("Fail to enable IRQ for irq_idx:%d\n", |
| 83 | irq_idxs[i]); |
| 84 | return ret; |
| 85 | } |
| 86 | } |
| 87 | |
| 88 | return ret; |
| 89 | } |
| 90 | |
| 91 | int sde_disable_irq(struct sde_kms *sde_kms, int *irq_idxs, u32 irq_count) |
| 92 | { |
| 93 | int i; |
| 94 | int ret = 0; |
| 95 | |
| 96 | if (!sde_kms || !irq_idxs || !sde_kms->hw_intr || |
| 97 | !sde_kms->hw_intr->ops.disable_irq) |
| 98 | return -EINVAL; |
| 99 | |
| 100 | for (i = 0; i < irq_count; i++) { |
| 101 | ret = sde_kms->hw_intr->ops.disable_irq( |
| 102 | sde_kms->hw_intr, |
| 103 | irq_idxs[i]); |
| 104 | if (ret) { |
| 105 | DRM_ERROR("Fail to disable IRQ for irq_idx:%d\n", |
| 106 | irq_idxs[i]); |
| 107 | return ret; |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | return ret; |
| 112 | } |
| 113 | |
| 114 | int sde_register_irq_callback(struct sde_kms *sde_kms, int irq_idx, |
| 115 | struct sde_irq_callback *register_irq_cb) |
| 116 | { |
| 117 | struct sde_irq_callback *irq_cb_tbl; |
| 118 | unsigned long irq_flags; |
| 119 | |
| 120 | /* |
| 121 | * We allow NULL register_irq_cb as input for callback registration |
| 122 | */ |
| 123 | if (!sde_kms || !sde_kms->irq_obj.irq_cb_tbl) |
| 124 | return -EINVAL; |
| 125 | |
| 126 | if (irq_idx < 0 || irq_idx >= sde_kms->hw_intr->irq_idx_tbl_size) { |
| 127 | DRM_ERROR("invalid IRQ index: [%d]\n", irq_idx); |
| 128 | return -EINVAL; |
| 129 | } |
| 130 | |
| 131 | irq_cb_tbl = sde_kms->irq_obj.irq_cb_tbl; |
| 132 | spin_lock_irqsave(&sde_kms->irq_obj.cb_lock, irq_flags); |
| 133 | irq_cb_tbl[irq_idx].func = register_irq_cb ? |
| 134 | register_irq_cb->func : NULL; |
| 135 | irq_cb_tbl[irq_idx].arg = register_irq_cb ? |
| 136 | register_irq_cb->arg : NULL; |
| 137 | spin_unlock_irqrestore(&sde_kms->irq_obj.cb_lock, irq_flags); |
| 138 | |
| 139 | return 0; |
| 140 | } |
| 141 | |
| 142 | void sde_clear_all_irqs(struct sde_kms *sde_kms) |
| 143 | { |
| 144 | if (!sde_kms || !sde_kms->hw_intr || |
| 145 | !sde_kms->hw_intr->ops.clear_all_irqs) |
| 146 | return; |
| 147 | |
| 148 | sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr); |
| 149 | } |
| 150 | |
| 151 | void sde_disable_all_irqs(struct sde_kms *sde_kms) |
| 152 | { |
| 153 | if (!sde_kms || !sde_kms->hw_intr || |
| 154 | !sde_kms->hw_intr->ops.disable_all_irqs) |
| 155 | return; |
| 156 | |
| 157 | sde_kms->hw_intr->ops.disable_all_irqs(sde_kms->hw_intr); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | void sde_irq_preinstall(struct msm_kms *kms) |
| 161 | { |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 162 | struct sde_kms *sde_kms = to_sde_kms(kms); |
| 163 | |
| 164 | sde_enable(sde_kms); |
| 165 | sde_clear_all_irqs(sde_kms); |
| 166 | sde_disable_all_irqs(sde_kms); |
| 167 | sde_disable(sde_kms); |
| 168 | |
| 169 | spin_lock_init(&sde_kms->irq_obj.cb_lock); |
| 170 | |
| 171 | /* Create irq callbacks for all possible irq_idx */ |
| 172 | sde_kms->irq_obj.total_irqs = sde_kms->hw_intr->irq_idx_tbl_size; |
| 173 | sde_kms->irq_obj.irq_cb_tbl = kcalloc(sde_kms->irq_obj.total_irqs, |
| 174 | sizeof(struct sde_irq_callback), GFP_KERNEL); |
| 175 | if (!sde_kms->irq_obj.irq_cb_tbl) |
| 176 | DRM_ERROR("Fail to allocate memory of IRQ callback list\n"); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | int sde_irq_postinstall(struct msm_kms *kms) |
| 180 | { |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 181 | struct sde_kms *sde_kms = to_sde_kms(kms); |
| 182 | struct sde_irq_callback irq_cb; |
| 183 | int irq_idx; |
| 184 | int i; |
| 185 | |
| 186 | irq_cb.func = sde_irq_intf_error_handler; |
| 187 | irq_cb.arg = sde_kms; |
| 188 | |
| 189 | /* Register interface underrun callback */ |
| 190 | sde_enable(sde_kms); |
| 191 | for (i = 0; i < sde_kms->catalog->intf_count; i++) { |
| 192 | irq_idx = sde_irq_idx_lookup(sde_kms, |
| 193 | SDE_IRQ_TYPE_INTF_UNDER_RUN, i+INTF_0); |
| 194 | sde_register_irq_callback(sde_kms, irq_idx, &irq_cb); |
| 195 | sde_enable_irq(sde_kms, &irq_idx, 1); |
| 196 | } |
| 197 | sde_disable(sde_kms); |
| 198 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | void sde_irq_uninstall(struct msm_kms *kms) |
| 203 | { |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 204 | struct sde_kms *sde_kms = to_sde_kms(kms); |
| 205 | |
| 206 | sde_enable(sde_kms); |
| 207 | sde_clear_all_irqs(sde_kms); |
| 208 | sde_disable_all_irqs(sde_kms); |
| 209 | sde_disable(sde_kms); |
| 210 | |
| 211 | kfree(sde_kms->irq_obj.irq_cb_tbl); |
| 212 | } |
| 213 | |
| 214 | static void _sde_irq_mdp_done(struct sde_kms *sde_kms) |
| 215 | { |
| 216 | /* |
| 217 | * Read interrupt status from all sources. Interrupt status are |
| 218 | * stored within hw_intr. |
| 219 | * Function will also clear the interrupt status after reading. |
| 220 | * Individual interrupt status bit will only get stored if it |
| 221 | * is enabled. |
| 222 | */ |
| 223 | sde_kms->hw_intr->ops.get_interrupt_statuses(sde_kms->hw_intr); |
| 224 | |
| 225 | /* |
| 226 | * Dispatch to HW driver to handle interrupt lookup that is being |
| 227 | * fired. When matching interrupt is located, HW driver will call to |
| 228 | * sde_irq_callback_handler with the irq_idx from the lookup table. |
| 229 | * sde_irq_callback_handler will perform the registered function |
| 230 | * callback, and do the interrupt status clearing once the registered |
| 231 | * callback is finished. |
| 232 | */ |
| 233 | sde_kms->hw_intr->ops.dispatch_irqs( |
| 234 | sde_kms->hw_intr, |
| 235 | sde_irq_callback_handler, |
| 236 | sde_kms); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | irqreturn_t sde_irq(struct msm_kms *kms) |
| 240 | { |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 241 | struct sde_kms *sde_kms = to_sde_kms(kms); |
| 242 | u32 interrupts; |
| 243 | |
| 244 | sde_kms->hw_intr->ops.get_interrupt_sources(sde_kms->hw_intr, |
| 245 | &interrupts); |
| 246 | |
| 247 | /* |
| 248 | * Taking care of MDP interrupt |
| 249 | */ |
| 250 | if (interrupts & IRQ_SOURCE_MDP) { |
| 251 | interrupts &= ~IRQ_SOURCE_MDP; |
| 252 | _sde_irq_mdp_done(sde_kms); |
| 253 | } |
| 254 | |
| 255 | /* |
| 256 | * Routing all other interrupts to external drivers |
| 257 | */ |
| 258 | while (interrupts) { |
| 259 | irq_hw_number_t hwirq = fls(interrupts) - 1; |
| 260 | |
| 261 | generic_handle_irq(irq_find_mapping( |
| 262 | sde_kms->irqcontroller.domain, hwirq)); |
| 263 | interrupts &= ~(1 << hwirq); |
| 264 | } |
| 265 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 266 | return IRQ_HANDLED; |
| 267 | } |
| 268 | |
| 269 | int sde_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) |
| 270 | { |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 271 | return sde_crtc_vblank(crtc); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | void sde_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc) |
| 275 | { |
| 276 | } |
| 277 | |
| 278 | static void sde_hw_irq_mask(struct irq_data *irqd) |
| 279 | { |
| 280 | struct sde_kms *sde_kms = irq_data_get_irq_chip_data(irqd); |
| 281 | |
| 282 | /* memory barrier */ |
| 283 | smp_mb__before_atomic(); |
| 284 | clear_bit(irqd->hwirq, &sde_kms->irqcontroller.enabled_mask); |
| 285 | /* memory barrier */ |
| 286 | smp_mb__after_atomic(); |
| 287 | } |
| 288 | |
| 289 | static void sde_hw_irq_unmask(struct irq_data *irqd) |
| 290 | { |
| 291 | struct sde_kms *sde_kms = irq_data_get_irq_chip_data(irqd); |
| 292 | |
| 293 | /* memory barrier */ |
| 294 | smp_mb__before_atomic(); |
| 295 | set_bit(irqd->hwirq, &sde_kms->irqcontroller.enabled_mask); |
| 296 | /* memory barrier */ |
| 297 | smp_mb__after_atomic(); |
| 298 | } |
| 299 | |
| 300 | static struct irq_chip sde_hw_irq_chip = { |
| 301 | .name = "sde", |
| 302 | .irq_mask = sde_hw_irq_mask, |
| 303 | .irq_unmask = sde_hw_irq_unmask, |
| 304 | }; |
| 305 | |
| 306 | static int sde_hw_irqdomain_map(struct irq_domain *d, |
| 307 | unsigned int irq, irq_hw_number_t hwirq) |
| 308 | { |
| 309 | struct sde_kms *sde_kms = d->host_data; |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame^] | 310 | uint32_t valid_irqs; |
| 311 | |
| 312 | sde_kms->hw_intr->ops.get_valid_interrupts(sde_kms->hw_intr, |
| 313 | &valid_irqs); |
| 314 | |
| 315 | if (!(valid_irqs & (1 << hwirq))) |
| 316 | return -EPERM; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 317 | |
| 318 | irq_set_chip_and_handler(irq, &sde_hw_irq_chip, handle_level_irq); |
| 319 | irq_set_chip_data(irq, sde_kms); |
| 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static const struct irq_domain_ops sde_hw_irqdomain_ops = { |
| 325 | .map = sde_hw_irqdomain_map, |
| 326 | .xlate = irq_domain_xlate_onecell, |
| 327 | }; |
| 328 | |
| 329 | int sde_irq_domain_init(struct sde_kms *sde_kms) |
| 330 | { |
| 331 | struct device *dev = sde_kms->dev->dev; |
| 332 | struct irq_domain *d; |
| 333 | |
| 334 | d = irq_domain_add_linear(dev->of_node, 32, |
| 335 | &sde_hw_irqdomain_ops, sde_kms); |
| 336 | |
| 337 | if (!d) |
| 338 | return -ENXIO; |
| 339 | |
| 340 | sde_kms->irqcontroller.enabled_mask = 0; |
| 341 | sde_kms->irqcontroller.domain = d; |
| 342 | |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | int sde_irq_domain_fini(struct sde_kms *sde_kms) |
| 347 | { |
| 348 | if (sde_kms->irqcontroller.domain) { |
| 349 | irq_domain_remove(sde_kms->irqcontroller.domain); |
| 350 | sde_kms->irqcontroller.domain = NULL; |
| 351 | } |
| 352 | return 0; |
| 353 | } |
| 354 | |