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Shawn Guo082d33d2013-04-02 13:15:16 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Anson Huang22724cf12014-01-20 20:02:38 +080013#include <dt-bindings/gpio/gpio.h>
Anson Huang8e4422a2013-12-19 16:07:24 -050014#include <dt-bindings/input/input.h>
15
Shawn Guo082d33d2013-04-02 13:15:16 +080016/ {
Sascha Hauer48f51962014-05-07 15:19:00 +020017 chosen {
18 stdout-path = &uart1;
19 };
20
Shawn Guo082d33d2013-04-02 13:15:16 +080021 memory {
22 reg = <0x10000000 0x40000000>;
23 };
24
25 regulators {
26 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080027 #address-cells = <1>;
28 #size-cells = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080029
Shawn Guo56160e32014-02-07 23:22:50 +080030 reg_usb_otg_vbus: regulator@0 {
Shawn Guo082d33d2013-04-02 13:15:16 +080031 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080032 reg = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080033 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 22 0>;
37 enable-active-high;
38 };
Nicolin Chenfdbfb432013-06-13 19:51:00 +080039
Shawn Guo56160e32014-02-07 23:22:50 +080040 reg_usb_h1_vbus: regulator@1 {
Peter Chen015fa462013-08-12 16:46:24 +080041 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080042 reg = <1>;
Peter Chen015fa462013-08-12 16:46:24 +080043 regulator-name = "usb_h1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&gpio1 29 0>;
47 enable-active-high;
48 };
49
Shawn Guo56160e32014-02-07 23:22:50 +080050 reg_audio: regulator@2 {
Nicolin Chenfdbfb432013-06-13 19:51:00 +080051 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080052 reg = <2>;
Nicolin Chenfdbfb432013-06-13 19:51:00 +080053 regulator-name = "wm8962-supply";
54 gpio = <&gpio4 10 0>;
55 enable-active-high;
56 };
Lucas Stach78827ec2014-07-23 19:29:11 +020057
58 reg_pcie: regulator@3 {
59 compatible = "regulator-fixed";
60 reg = <3>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_pcie_reg>;
63 regulator-name = "MPCIE_3V3";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 gpio = <&gpio3 19 0>;
67 regulator-always-on;
68 enable-active-high;
69 };
Shawn Guo082d33d2013-04-02 13:15:16 +080070 };
71
72 gpio-keys {
73 compatible = "gpio-keys";
Anson Huang8e4422a2013-12-19 16:07:24 -050074 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_gpio_keys>;
76
77 power {
78 label = "Power Button";
Anson Huang22724cf12014-01-20 20:02:38 +080079 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
Anson Huang8e4422a2013-12-19 16:07:24 -050080 gpio-key,wakeup;
81 linux,code = <KEY_POWER>;
82 };
Shawn Guo082d33d2013-04-02 13:15:16 +080083
84 volume-up {
85 label = "Volume Up";
Anson Huang22724cf12014-01-20 20:02:38 +080086 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
Fabio Estevam6c306402013-07-19 10:40:23 -030087 gpio-key,wakeup;
Anson Huang8e4422a2013-12-19 16:07:24 -050088 linux,code = <KEY_VOLUMEUP>;
Shawn Guo082d33d2013-04-02 13:15:16 +080089 };
90
91 volume-down {
92 label = "Volume Down";
Anson Huang22724cf12014-01-20 20:02:38 +080093 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
Fabio Estevam6c306402013-07-19 10:40:23 -030094 gpio-key,wakeup;
Anson Huang8e4422a2013-12-19 16:07:24 -050095 linux,code = <KEY_VOLUMEDOWN>;
Shawn Guo082d33d2013-04-02 13:15:16 +080096 };
97 };
Nicolin Chen77b38fc2013-06-14 13:22:46 +080098
99 sound {
100 compatible = "fsl,imx6q-sabresd-wm8962",
101 "fsl,imx-audio-wm8962";
102 model = "wm8962-audio";
103 ssi-controller = <&ssi2>;
104 audio-codec = <&codec>;
105 audio-routing =
106 "Headphone Jack", "HPOUTL",
107 "Headphone Jack", "HPOUTR",
108 "Ext Spk", "SPKOUTL",
109 "Ext Spk", "SPKOUTR",
110 "MICBIAS", "AMIC",
111 "IN3R", "MICBIAS",
112 "DMIC", "MICBIAS",
113 "DMICDAT", "DMIC";
114 mux-int-port = <2>;
115 mux-ext-port = <3>;
116 };
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300117
118 backlight {
119 compatible = "pwm-backlight";
120 pwms = <&pwm1 0 5000000>;
121 brightness-levels = <0 4 8 16 32 64 128 255>;
122 default-brightness-level = <7>;
123 status = "okay";
124 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100125
126 leds {
127 compatible = "gpio-leds";
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_gpio_leds>;
130
131 red {
132 gpios = <&gpio1 2 0>;
133 default-state = "on";
134 };
135 };
Shawn Guo082d33d2013-04-02 13:15:16 +0800136};
137
Nicolin Chen48828702013-06-14 13:19:57 +0800138&audmux {
139 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800140 pinctrl-0 = <&pinctrl_audmux>;
Nicolin Chen48828702013-06-14 13:19:57 +0800141 status = "okay";
142};
143
Huang Shijie9110ede2013-06-21 10:19:11 +0800144&ecspi1 {
145 fsl,spi-num-chipselects = <1>;
146 cs-gpios = <&gpio4 9 0>;
147 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800148 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijie9110ede2013-06-21 10:19:11 +0800149 status = "okay";
150
151 flash: m25p80@0 {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "st,m25p32";
155 spi-max-frequency = <20000000>;
156 reg = <0>;
157 };
158};
159
Shawn Guo082d33d2013-04-02 13:15:16 +0800160&fec {
161 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800162 pinctrl-0 = <&pinctrl_enet>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800163 phy-mode = "rgmii";
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300164 phy-reset-gpios = <&gpio1 25 0>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800165 status = "okay";
166};
167
Fabio Estevamad704562014-04-22 10:04:59 -0300168&hdmi {
169 ddc-i2c-bus = <&i2c2>;
170 status = "okay";
171};
172
Nicolin Chen20426fe2013-06-13 19:51:01 +0800173&i2c1 {
174 clock-frequency = <100000>;
175 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800176 pinctrl-0 = <&pinctrl_i2c1>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800177 status = "okay";
178
179 codec: wm8962@1a {
180 compatible = "wlf,wm8962";
181 reg = <0x1a>;
Shawn Guoa94f8ec2013-07-18 14:42:28 +0800182 clocks = <&clks 201>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800183 DCVDD-supply = <&reg_audio>;
184 DBVDD-supply = <&reg_audio>;
185 AVDD-supply = <&reg_audio>;
186 CPVDD-supply = <&reg_audio>;
187 MICVDD-supply = <&reg_audio>;
188 PLLVDD-supply = <&reg_audio>;
189 SPKVDD1-supply = <&reg_audio>;
190 SPKVDD2-supply = <&reg_audio>;
191 gpio-cfg = <
192 0x0000 /* 0:Default */
193 0x0000 /* 1:Default */
194 0x0013 /* 2:FN_DMICCLK */
195 0x0000 /* 3:Default */
196 0x8014 /* 4:FN_DMICCDAT */
197 0x0000 /* 5:Default */
198 >;
199 };
200};
201
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200202&i2c2 {
203 clock-frequency = <100000>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c2>;
206 status = "okay";
207
208 pmic: pfuze100@08 {
209 compatible = "fsl,pfuze100";
210 reg = <0x08>;
211
212 regulators {
213 sw1a_reg: sw1ab {
214 regulator-min-microvolt = <300000>;
215 regulator-max-microvolt = <1875000>;
216 regulator-boot-on;
217 regulator-always-on;
218 regulator-ramp-delay = <6250>;
219 };
220
221 sw1c_reg: sw1c {
222 regulator-min-microvolt = <300000>;
223 regulator-max-microvolt = <1875000>;
224 regulator-boot-on;
225 regulator-always-on;
226 regulator-ramp-delay = <6250>;
227 };
228
229 sw2_reg: sw2 {
230 regulator-min-microvolt = <800000>;
231 regulator-max-microvolt = <3300000>;
232 regulator-boot-on;
233 regulator-always-on;
234 };
235
236 sw3a_reg: sw3a {
237 regulator-min-microvolt = <400000>;
238 regulator-max-microvolt = <1975000>;
239 regulator-boot-on;
240 regulator-always-on;
241 };
242
243 sw3b_reg: sw3b {
244 regulator-min-microvolt = <400000>;
245 regulator-max-microvolt = <1975000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
249
250 sw4_reg: sw4 {
251 regulator-min-microvolt = <800000>;
252 regulator-max-microvolt = <3300000>;
253 };
254
255 swbst_reg: swbst {
256 regulator-min-microvolt = <5000000>;
257 regulator-max-microvolt = <5150000>;
258 };
259
260 snvs_reg: vsnvs {
261 regulator-min-microvolt = <1000000>;
262 regulator-max-microvolt = <3000000>;
263 regulator-boot-on;
264 regulator-always-on;
265 };
266
267 vref_reg: vrefddr {
268 regulator-boot-on;
269 regulator-always-on;
270 };
271
272 vgen1_reg: vgen1 {
273 regulator-min-microvolt = <800000>;
274 regulator-max-microvolt = <1550000>;
275 };
276
277 vgen2_reg: vgen2 {
278 regulator-min-microvolt = <800000>;
279 regulator-max-microvolt = <1550000>;
280 };
281
282 vgen3_reg: vgen3 {
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <3300000>;
285 };
286
287 vgen4_reg: vgen4 {
288 regulator-min-microvolt = <1800000>;
289 regulator-max-microvolt = <3300000>;
290 regulator-always-on;
291 };
292
293 vgen5_reg: vgen5 {
294 regulator-min-microvolt = <1800000>;
295 regulator-max-microvolt = <3300000>;
296 regulator-always-on;
297 };
298
299 vgen6_reg: vgen6 {
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <3300000>;
302 regulator-always-on;
303 };
304 };
305 };
306};
307
Fabio Estevam38501172013-07-24 17:20:03 -0300308&i2c3 {
309 clock-frequency = <100000>;
310 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800311 pinctrl-0 = <&pinctrl_i2c3>;
Fabio Estevam38501172013-07-24 17:20:03 -0300312 status = "okay";
313
314 egalax_ts@04 {
315 compatible = "eeti,egalax_ts";
316 reg = <0x04>;
317 interrupt-parent = <&gpio6>;
318 interrupts = <7 2>;
319 wakeup-gpios = <&gpio6 7 0>;
320 };
321};
322
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800323&iomuxc {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_hog>;
326
Shawn Guo817c27a2013-10-23 15:36:09 +0800327 imx6qdl-sabresd {
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800328 pinctrl_hog: hoggrp {
329 fsl,pins = <
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800330 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
331 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
332 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
333 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
334 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
Fabio Estevam38501172013-07-24 17:20:03 -0300335 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
Peter Chen015fa462013-08-12 16:46:24 +0800336 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
Peter Chene3c68c82013-08-12 16:51:39 +0800337 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300338 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800339 >;
340 };
Shawn Guo817c27a2013-10-23 15:36:09 +0800341
342 pinctrl_audmux: audmuxgrp {
343 fsl,pins = <
Nicolin Chen77112dd2014-02-08 10:14:28 +0800344 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
345 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
346 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
347 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800348 >;
349 };
350
351 pinctrl_ecspi1: ecspi1grp {
352 fsl,pins = <
353 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
354 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
355 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
Fabio Estevamf3c72382014-05-14 16:53:55 -0300356 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800357 >;
358 };
359
360 pinctrl_enet: enetgrp {
361 fsl,pins = <
362 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
363 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
364 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
365 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
366 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
367 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
368 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
369 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
370 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
371 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
372 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
373 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
374 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
375 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
376 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
377 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
378 >;
379 };
380
Anson Huang8e4422a2013-12-19 16:07:24 -0500381 pinctrl_gpio_keys: gpio_keysgrp {
382 fsl,pins = <
383 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
384 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
385 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
386 >;
387 };
388
Shawn Guo817c27a2013-10-23 15:36:09 +0800389 pinctrl_i2c1: i2c1grp {
390 fsl,pins = <
391 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
392 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
393 >;
394 };
395
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200396 pinctrl_i2c2: i2c2grp {
397 fsl,pins = <
398 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
399 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
400 >;
401 };
402
Shawn Guo817c27a2013-10-23 15:36:09 +0800403 pinctrl_i2c3: i2c3grp {
404 fsl,pins = <
405 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
406 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
407 >;
408 };
409
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200410 pinctrl_pcie: pciegrp {
411 fsl,pins = <
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200412 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
413 >;
414 };
415
Lucas Stach78827ec2014-07-23 19:29:11 +0200416 pinctrl_pcie_reg: pciereggrp {
417 fsl,pins = <
418 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
419 >;
420 };
421
Shawn Guo817c27a2013-10-23 15:36:09 +0800422 pinctrl_pwm1: pwm1grp {
423 fsl,pins = <
424 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
425 >;
426 };
427
428 pinctrl_uart1: uart1grp {
429 fsl,pins = <
430 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
431 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
432 >;
433 };
434
435 pinctrl_usbotg: usbotggrp {
436 fsl,pins = <
437 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
438 >;
439 };
440
441 pinctrl_usdhc2: usdhc2grp {
442 fsl,pins = <
443 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
444 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
445 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
446 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
447 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
448 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
449 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
450 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
451 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
452 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
453 >;
454 };
455
456 pinctrl_usdhc3: usdhc3grp {
457 fsl,pins = <
458 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
459 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
460 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
461 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
462 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
463 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
464 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
465 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
466 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
467 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
468 >;
469 };
Fabio Estevame02ab39a2014-05-08 11:10:56 -0300470
471 pinctrl_usdhc4: usdhc4grp {
472 fsl,pins = <
473 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
474 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
475 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
476 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
477 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
478 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
479 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
480 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
481 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
482 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
483 >;
484 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800485 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100486
487 gpio_leds {
488 pinctrl_gpio_leds: gpioledsgrp {
489 fsl,pins = <
490 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
491 >;
492 };
493 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800494};
495
Shawn Guob7fb7102013-07-16 22:15:18 +0800496&ldb {
497 status = "okay";
498
499 lvds-channel@1 {
500 fsl,data-mapping = "spwg";
501 fsl,data-width = <18>;
502 status = "okay";
503
504 display-timings {
505 native-mode = <&timing0>;
506 timing0: hsd100pxn1 {
507 clock-frequency = <65000000>;
508 hactive = <1024>;
509 vactive = <768>;
510 hback-porch = <220>;
511 hfront-porch = <40>;
512 vback-porch = <21>;
513 vfront-porch = <7>;
514 hsync-len = <60>;
515 vsync-len = <10>;
516 };
517 };
518 };
519};
520
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200521&pcie {
522 pinctrl-names = "default";
523 pinctrl-0 = <&pinctrl_pcie>;
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200524 reset-gpio = <&gpio7 12 0>;
525 status = "okay";
526};
527
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300528&pwm1 {
529 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800530 pinctrl-0 = <&pinctrl_pwm1>;
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300531 status = "okay";
532};
533
Nicolin Chen48828702013-06-14 13:19:57 +0800534&ssi2 {
Nicolin Chen48828702013-06-14 13:19:57 +0800535 status = "okay";
536};
537
Shawn Guo082d33d2013-04-02 13:15:16 +0800538&uart1 {
539 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800540 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800541 status = "okay";
542};
543
544&usbh1 {
Peter Chen015fa462013-08-12 16:46:24 +0800545 vbus-supply = <&reg_usb_h1_vbus>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800546 status = "okay";
547};
548
549&usbotg {
550 vbus-supply = <&reg_usb_otg_vbus>;
551 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800552 pinctrl-0 = <&pinctrl_usbotg>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800553 disable-over-current;
554 status = "okay";
555};
556
557&usdhc2 {
558 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800559 pinctrl-0 = <&pinctrl_usdhc2>;
Fabio Estevame3678172013-09-17 13:46:23 -0300560 bus-width = <8>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800561 cd-gpios = <&gpio2 2 0>;
562 wp-gpios = <&gpio2 3 0>;
563 status = "okay";
564};
565
566&usdhc3 {
567 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800568 pinctrl-0 = <&pinctrl_usdhc3>;
Fabio Estevame3678172013-09-17 13:46:23 -0300569 bus-width = <8>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800570 cd-gpios = <&gpio2 0 0>;
571 wp-gpios = <&gpio2 1 0>;
572 status = "okay";
573};
Fabio Estevame02ab39a2014-05-08 11:10:56 -0300574
575&usdhc4 {
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_usdhc4>;
578 bus-width = <8>;
579 non-removable;
580 no-1-8-v;
581 status = "okay";
582};