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Magnus Dammb2623a62010-03-19 04:47:10 +00001/*
2 * Header for the new SH dmaengine driver
3 *
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef SH_DMA_H
11#define SH_DMA_H
12
Magnus Dammb2623a62010-03-19 04:47:10 +000013#include <linux/dmaengine.h>
Guennadi Liakhovetski5902c9a2012-05-09 17:09:14 +020014#include <linux/list.h>
15#include <linux/shdma-base.h>
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020016#include <linux/types.h>
17
18struct device;
Magnus Dammb2623a62010-03-19 04:47:10 +000019
20/* Used by slave DMA clients to request DMA to/from a specific peripheral */
21struct sh_dmae_slave {
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020022 struct shdma_slave shdma_slave; /* Set by the platform */
Magnus Dammb2623a62010-03-19 04:47:10 +000023};
24
Guennadi Liakhovetskice3a1ab2012-05-09 17:09:21 +020025/*
26 * Supplied by platforms to specify, how a DMA channel has to be configured for
27 * a certain peripheral
28 */
Magnus Dammb2623a62010-03-19 04:47:10 +000029struct sh_dmae_slave_config {
Guennadi Liakhovetskic2cdb7e2012-07-05 12:29:41 +020030 int slave_id;
31 dma_addr_t addr;
32 u32 chcr;
33 char mid_rid;
Magnus Dammb2623a62010-03-19 04:47:10 +000034};
35
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020036/**
37 * struct sh_dmae_channel - DMAC channel platform data
38 * @offset: register offset within the main IOMEM resource
39 * @dmars: channel DMARS register offset
40 * @chclr_offset: channel CHCLR register offset
41 * @dmars_bit: channel DMARS field offset within the register
42 * @chclr_bit: bit position, to be set to reset the channel
43 */
Magnus Dammb2623a62010-03-19 04:47:10 +000044struct sh_dmae_channel {
45 unsigned int offset;
46 unsigned int dmars;
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010047 unsigned int chclr_offset;
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020048 unsigned char dmars_bit;
49 unsigned char chclr_bit;
Magnus Dammb2623a62010-03-19 04:47:10 +000050};
51
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020052/**
53 * struct sh_dmae_pdata - DMAC platform data
54 * @slave: array of slaves
55 * @slave_num: number of slaves in the above array
56 * @channel: array of DMA channels
57 * @channel_num: number of channels in the above array
58 * @ts_low_shift: shift of the low part of the TS field
59 * @ts_low_mask: low TS field mask
60 * @ts_high_shift: additional shift of the high part of the TS field
61 * @ts_high_mask: high TS field mask
62 * @ts_shift: array of Transfer Size shifts, indexed by TS value
63 * @ts_shift_num: number of shifts in the above array
64 * @dmaor_init: DMAOR initialisation value
65 * @chcr_offset: CHCR address offset
66 * @chcr_ie_bit: CHCR Interrupt Enable bit
67 * @dmaor_is_32bit: DMAOR is a 32-bit register
68 * @needs_tend_set: the TEND register has to be set
69 * @no_dmars: DMAC has no DMARS registers
70 * @chclr_present: DMAC has one or several CHCLR registers
71 * @chclr_bitwise: channel CHCLR registers are bitwise
72 * @slave_only: DMAC cannot be used for MEMCPY
73 */
Magnus Dammb2623a62010-03-19 04:47:10 +000074struct sh_dmae_pdata {
Guennadi Liakhovetski5bac9422010-04-21 15:36:49 +000075 const struct sh_dmae_slave_config *slave;
Magnus Dammb2623a62010-03-19 04:47:10 +000076 int slave_num;
Guennadi Liakhovetski5bac9422010-04-21 15:36:49 +000077 const struct sh_dmae_channel *channel;
Magnus Dammb2623a62010-03-19 04:47:10 +000078 int channel_num;
79 unsigned int ts_low_shift;
80 unsigned int ts_low_mask;
81 unsigned int ts_high_shift;
82 unsigned int ts_high_mask;
Guennadi Liakhovetski5bac9422010-04-21 15:36:49 +000083 const unsigned int *ts_shift;
Magnus Dammb2623a62010-03-19 04:47:10 +000084 int ts_shift_num;
85 u16 dmaor_init;
Kuninori Morimoto5899a722011-06-17 08:20:40 +000086 unsigned int chcr_offset;
Kuninori Morimoto67c62692011-06-17 08:20:51 +000087 u32 chcr_ie_bit;
Kuninori Morimotoe76c3af2011-06-17 08:20:56 +000088
89 unsigned int dmaor_is_32bit:1;
Kuninori Morimoto260bf2c2011-06-17 08:21:05 +000090 unsigned int needs_tend_set:1;
91 unsigned int no_dmars:1;
Guennadi Liakhovetskic11b46c322012-01-04 15:34:17 +010092 unsigned int chclr_present:1;
Guennadi Liakhovetskica8b3872013-07-10 12:09:47 +020093 unsigned int chclr_bitwise:1;
Guennadi Liakhovetskie9c8d7a02012-01-18 10:14:25 +010094 unsigned int slave_only:1;
Magnus Dammb2623a62010-03-19 04:47:10 +000095};
96
Magnus Dammb2623a62010-03-19 04:47:10 +000097/* DMAOR definitions */
Geert Uytterhoeven6b32faf2014-06-20 14:37:38 +020098#define DMAOR_AE 0x00000004 /* Address Error Flag */
Magnus Dammb2623a62010-03-19 04:47:10 +000099#define DMAOR_NMIF 0x00000002
Geert Uytterhoeven6b32faf2014-06-20 14:37:38 +0200100#define DMAOR_DME 0x00000001 /* DMA Master Enable */
Magnus Dammb2623a62010-03-19 04:47:10 +0000101
102/* Definitions for the SuperH DMAC */
Geert Uytterhoeven6b32faf2014-06-20 14:37:38 +0200103#define DM_INC 0x00004000 /* Destination addresses are incremented */
104#define DM_DEC 0x00008000 /* Destination addresses are decremented */
105#define DM_FIX 0x0000c000 /* Destination address is fixed */
106#define SM_INC 0x00001000 /* Source addresses are incremented */
107#define SM_DEC 0x00002000 /* Source addresses are decremented */
108#define SM_FIX 0x00003000 /* Source address is fixed */
109#define RS_AUTO 0x00000400 /* Auto Request */
110#define RS_ERS 0x00000800 /* DMA extended resource selector */
111#define CHCR_DE 0x00000001 /* DMA Enable */
112#define CHCR_TE 0x00000002 /* Transfer End Flag */
113#define CHCR_IE 0x00000004 /* Interrupt Enable */
Magnus Dammb2623a62010-03-19 04:47:10 +0000114
Magnus Dammb2623a62010-03-19 04:47:10 +0000115#endif