blob: 4bb91a970f1f48eee6919e5104c8075f0481f71e [file] [log] [blame]
Johannes Weinere5083a62009-03-04 16:21:31 +01001/*
2 * xtensa mmu stuff
3 *
4 * Extracted from init.c
5 */
6#include <linux/percpu.h>
7#include <linux/init.h>
8#include <linux/string.h>
9#include <linux/slab.h>
10#include <linux/cache.h>
11
12#include <asm/tlb.h>
13#include <asm/tlbflush.h>
14#include <asm/mmu_context.h>
15#include <asm/page.h>
16
17DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
18
19void __init paging_init(void)
20{
21 memset(swapper_pg_dir, 0, PAGE_SIZE);
22}
23
24/*
25 * Flush the mmu and reset associated register to default values.
26 */
27void __init init_mmu(void)
28{
29 /* Writing zeros to the <t>TLBCFG special registers ensure
30 * that valid values exist in the register. For existing
31 * PGSZID<w> fields, zero selects the first element of the
32 * page-size array. For nonexistent PGSZID<w> fields, zero is
33 * the best value to write. Also, when changing PGSZID<w>
34 * fields, the corresponding TLB must be flushed.
35 */
36 set_itlbcfg_register(0);
37 set_dtlbcfg_register(0);
38 flush_tlb_all();
39
40 /* Set rasid register to a known value. */
41
42 set_rasid_register(ASID_USER_FIRST);
43
44 /* Set PTEVADDR special register to the start of the page
45 * table, which is in kernel mappable space (ie. not
46 * statically mapped). This register's value is undefined on
47 * reset.
48 */
49 set_ptevaddr_register(PGTABLE_START);
50}
51
52struct kmem_cache *pgtable_cache __read_mostly;
53
54static void pgd_ctor(void *addr)
55{
56 pte_t *ptep = (pte_t *)addr;
57 int i;
58
59 for (i = 0; i < 1024; i++, ptep++)
60 pte_clear(NULL, 0, ptep);
61
62}
63
64void __init pgtable_cache_init(void)
65{
66 pgtable_cache = kmem_cache_create("pgd",
67 PAGE_SIZE, PAGE_SIZE,
68 SLAB_HWCACHE_ALIGN,
69 pgd_ctor);
70}