Jarod Wilson | 7963eb4 | 2010-01-04 18:02:27 -0500 | [diff] [blame^] | 1 | /*************************************************************************** |
| 2 | * Copyright (c) 1999-2009, Broadcom Corporation. |
| 3 | * |
| 4 | * Name: bcm_70012_regs.h |
| 5 | * |
| 6 | * Description: BCM70012 registers |
| 7 | * |
| 8 | ******************************************************************** |
| 9 | * This header is free software: you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU Lesser General Public License as published |
| 11 | * by the Free Software Foundation, either version 2.1 of the License. |
| 12 | * |
| 13 | * This header is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU Lesser General Public License for more details. |
| 17 | * You should have received a copy of the GNU Lesser General Public License |
| 18 | * along with this header. If not, see <http://www.gnu.org/licenses/>. |
| 19 | ***************************************************************************/ |
| 20 | |
| 21 | #ifndef MACFILE_H__ |
| 22 | #define MACFILE_H__ |
| 23 | |
| 24 | /** |
| 25 | * m = memory, c = core, r = register, f = field, d = data. |
| 26 | */ |
| 27 | #if !defined(GET_FIELD) && !defined(SET_FIELD) |
| 28 | #define BRCM_ALIGN(c,r,f) c##_##r##_##f##_ALIGN |
| 29 | #define BRCM_BITS(c,r,f) c##_##r##_##f##_BITS |
| 30 | #define BRCM_MASK(c,r,f) c##_##r##_##f##_MASK |
| 31 | #define BRCM_SHIFT(c,r,f) c##_##r##_##f##_SHIFT |
| 32 | |
| 33 | #define GET_FIELD(m,c,r,f) \ |
| 34 | ((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f)) |
| 35 | |
| 36 | #define SET_FIELD(m,c,r,f,d) \ |
| 37 | ((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \ |
| 38 | BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \ |
| 39 | ) |
| 40 | |
| 41 | #define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d) |
| 42 | #define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d) |
| 43 | #define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d) |
| 44 | |
| 45 | #endif /* GET & SET */ |
| 46 | |
| 47 | /**************************************************************************** |
| 48 | * Core Enums. |
| 49 | ***************************************************************************/ |
| 50 | /**************************************************************************** |
| 51 | * Enums: AES_RGR_BRIDGE_RESET_CTRL |
| 52 | ***************************************************************************/ |
| 53 | #define AES_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 54 | #define AES_RGR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 55 | |
| 56 | /**************************************************************************** |
| 57 | * Enums: CCE_RGR_BRIDGE_RESET_CTRL |
| 58 | ***************************************************************************/ |
| 59 | #define CCE_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 60 | #define CCE_RGR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 61 | |
| 62 | /**************************************************************************** |
| 63 | * Enums: DBU_RGR_BRIDGE_RESET_CTRL |
| 64 | ***************************************************************************/ |
| 65 | #define DBU_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 66 | #define DBU_RGR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 67 | |
| 68 | /**************************************************************************** |
| 69 | * Enums: DCI_RGR_BRIDGE_RESET_CTRL |
| 70 | ***************************************************************************/ |
| 71 | #define DCI_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 72 | #define DCI_RGR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 73 | |
| 74 | /**************************************************************************** |
| 75 | * Enums: GISB_ARBITER_DEASSERT_ASSERT |
| 76 | ***************************************************************************/ |
| 77 | #define GISB_ARBITER_DEASSERT_ASSERT_DEASSERT 0 |
| 78 | #define GISB_ARBITER_DEASSERT_ASSERT_ASSERT 1 |
| 79 | |
| 80 | /**************************************************************************** |
| 81 | * Enums: GISB_ARBITER_UNMASK_MASK |
| 82 | ***************************************************************************/ |
| 83 | #define GISB_ARBITER_UNMASK_MASK_UNMASK 0 |
| 84 | #define GISB_ARBITER_UNMASK_MASK_MASK 1 |
| 85 | |
| 86 | /**************************************************************************** |
| 87 | * Enums: GISB_ARBITER_DISABLE_ENABLE |
| 88 | ***************************************************************************/ |
| 89 | #define GISB_ARBITER_DISABLE_ENABLE_DISABLE 0 |
| 90 | #define GISB_ARBITER_DISABLE_ENABLE_ENABLE 1 |
| 91 | |
| 92 | /**************************************************************************** |
| 93 | * Enums: I2C_GR_BRIDGE_RESET_CTRL |
| 94 | ***************************************************************************/ |
| 95 | #define I2C_GR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 96 | #define I2C_GR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 97 | |
| 98 | /**************************************************************************** |
| 99 | * Enums: MISC_GR_BRIDGE_RESET_CTRL |
| 100 | ***************************************************************************/ |
| 101 | #define MISC_GR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 102 | #define MISC_GR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 103 | |
| 104 | /**************************************************************************** |
| 105 | * Enums: OTP_GR_BRIDGE_RESET_CTRL |
| 106 | ***************************************************************************/ |
| 107 | #define OTP_GR_BRIDGE_RESET_CTRL_DEASSERT 0 |
| 108 | #define OTP_GR_BRIDGE_RESET_CTRL_ASSERT 1 |
| 109 | |
| 110 | /**************************************************************************** |
| 111 | * BCM70012_TGT_TOP_PCIE_CFG |
| 112 | ***************************************************************************/ |
| 113 | #define PCIE_CFG_DEVICE_VENDOR_ID 0x00000000 /* DEVICE_VENDOR_ID Register */ |
| 114 | #define PCIE_CFG_STATUS_COMMAND 0x00000004 /* STATUS_COMMAND Register */ |
| 115 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID 0x00000008 /* PCI_CLASSCODE_AND_REVISION_ID Register */ |
| 116 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE 0x0000000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */ |
| 117 | #define PCIE_CFG_BASE_ADDRESS_1 0x00000010 /* BASE_ADDRESS_1 Register */ |
| 118 | #define PCIE_CFG_BASE_ADDRESS_2 0x00000014 /* BASE_ADDRESS_2 Register */ |
| 119 | #define PCIE_CFG_BASE_ADDRESS_3 0x00000018 /* BASE_ADDRESS_3 Register */ |
| 120 | #define PCIE_CFG_BASE_ADDRESS_4 0x0000001c /* BASE_ADDRESS_4 Register */ |
| 121 | #define PCIE_CFG_CARDBUS_CIS_POINTER 0x00000028 /* CARDBUS_CIS_POINTER Register */ |
| 122 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID 0x0000002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */ |
| 123 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS 0x00000030 /* EXPANSION_ROM_BASE_ADDRESS Register */ |
| 124 | #define PCIE_CFG_CAPABILITIES_POINTER 0x00000034 /* CAPABILITIES_POINTER Register */ |
| 125 | #define PCIE_CFG_INTERRUPT 0x0000003c /* INTERRUPT Register */ |
| 126 | #define PCIE_CFG_VPD_CAPABILITIES 0x00000040 /* VPD_CAPABILITIES Register */ |
| 127 | #define PCIE_CFG_VPD_DATA 0x00000044 /* VPD_DATA Register */ |
| 128 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY 0x00000048 /* POWER_MANAGEMENT_CAPABILITY Register */ |
| 129 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS 0x0000004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */ |
| 130 | #define PCIE_CFG_MSI_CAPABILITY_HEADER 0x00000050 /* MSI_CAPABILITY_HEADER Register */ |
| 131 | #define PCIE_CFG_MSI_LOWER_ADDRESS 0x00000054 /* MSI_LOWER_ADDRESS Register */ |
| 132 | #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER 0x00000058 /* MSI_UPPER_ADDRESS_REGISTER Register */ |
| 133 | #define PCIE_CFG_MSI_DATA 0x0000005c /* MSI_DATA Register */ |
| 134 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER 0x00000060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */ |
| 135 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES 0x00000064 /* RESET_COUNTERS_INITIAL_VALUES Register */ |
| 136 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL 0x00000068 /* MISCELLANEOUS_HOST_CONTROL Register */ |
| 137 | #define PCIE_CFG_SPARE 0x0000006c /* SPARE Register */ |
| 138 | #define PCIE_CFG_PCI_STATE 0x00000070 /* PCI_STATE Register */ |
| 139 | #define PCIE_CFG_CLOCK_CONTROL 0x00000074 /* CLOCK_CONTROL Register */ |
| 140 | #define PCIE_CFG_REGISTER_BASE 0x00000078 /* REGISTER_BASE Register */ |
| 141 | #define PCIE_CFG_MEMORY_BASE 0x0000007c /* MEMORY_BASE Register */ |
| 142 | #define PCIE_CFG_REGISTER_DATA 0x00000080 /* REGISTER_DATA Register */ |
| 143 | #define PCIE_CFG_MEMORY_DATA 0x00000084 /* MEMORY_DATA Register */ |
| 144 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE 0x00000088 /* EXPANSION_ROM_BAR_SIZE Register */ |
| 145 | #define PCIE_CFG_EXPANSION_ROM_ADDRESS 0x0000008c /* EXPANSION_ROM_ADDRESS Register */ |
| 146 | #define PCIE_CFG_EXPANSION_ROM_DATA 0x00000090 /* EXPANSION_ROM_DATA Register */ |
| 147 | #define PCIE_CFG_VPD_INTERFACE 0x00000094 /* VPD_INTERFACE Register */ |
| 148 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER 0x00000098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */ |
| 149 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER 0x0000009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */ |
| 150 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER 0x000000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */ |
| 151 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER 0x000000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */ |
| 152 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER 0x000000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */ |
| 153 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER 0x000000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */ |
| 154 | #define PCIE_CFG_INT_MAILBOX_UPPER 0x000000b0 /* INT_MAILBOX_UPPER Register */ |
| 155 | #define PCIE_CFG_INT_MAILBOX_LOWER 0x000000b4 /* INT_MAILBOX_LOWER Register */ |
| 156 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION 0x000000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */ |
| 157 | #define PCIE_CFG_FUNCTION_EVENT 0x000000c0 /* FUNCTION_EVENT Register */ |
| 158 | #define PCIE_CFG_FUNCTION_EVENT_MASK 0x000000c4 /* FUNCTION_EVENT_MASK Register */ |
| 159 | #define PCIE_CFG_FUNCTION_PRESENT 0x000000c8 /* FUNCTION_PRESENT Register */ |
| 160 | #define PCIE_CFG_PCIE_CAPABILITIES 0x000000cc /* PCIE_CAPABILITIES Register */ |
| 161 | #define PCIE_CFG_DEVICE_CAPABILITIES 0x000000d0 /* DEVICE_CAPABILITIES Register */ |
| 162 | #define PCIE_CFG_DEVICE_STATUS_CONTROL 0x000000d4 /* DEVICE_STATUS_CONTROL Register */ |
| 163 | #define PCIE_CFG_LINK_CAPABILITY 0x000000d8 /* LINK_CAPABILITY Register */ |
| 164 | #define PCIE_CFG_LINK_STATUS_CONTROL 0x000000dc /* LINK_STATUS_CONTROL Register */ |
| 165 | #define PCIE_CFG_DEVICE_CAPABILITIES_2 0x000000f0 /* DEVICE_CAPABILITIES_2 Register */ |
| 166 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2 0x000000f4 /* DEVICE_STATUS_CONTROL_2 Register */ |
| 167 | #define PCIE_CFG_LINK_CAPABILITIES_2 0x000000f8 /* LINK_CAPABILITIES_2 Register */ |
| 168 | #define PCIE_CFG_LINK_STATUS_CONTROL_2 0x000000fc /* LINK_STATUS_CONTROL_2 Register */ |
| 169 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER 0x00000100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */ |
| 170 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS 0x00000104 /* UNCORRECTABLE_ERROR_STATUS Register */ |
| 171 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK 0x00000108 /* UNCORRECTABLE_ERROR_MASK Register */ |
| 172 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY 0x0000010c /* UNCORRECTABLE_ERROR_SEVERITY Register */ |
| 173 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS 0x00000110 /* CORRECTABLE_ERROR_STATUS Register */ |
| 174 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK 0x00000114 /* CORRECTABLE_ERROR_MASK Register */ |
| 175 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL 0x00000118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */ |
| 176 | #define PCIE_CFG_HEADER_LOG_1 0x0000011c /* HEADER_LOG_1 Register */ |
| 177 | #define PCIE_CFG_HEADER_LOG_2 0x00000120 /* HEADER_LOG_2 Register */ |
| 178 | #define PCIE_CFG_HEADER_LOG_3 0x00000124 /* HEADER_LOG_3 Register */ |
| 179 | #define PCIE_CFG_HEADER_LOG_4 0x00000128 /* HEADER_LOG_4 Register */ |
| 180 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER 0x0000013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */ |
| 181 | #define PCIE_CFG_PORT_VC_CAPABILITY 0x00000140 /* PORT_VC_CAPABILITY Register */ |
| 182 | #define PCIE_CFG_PORT_VC_CAPABILITY_2 0x00000144 /* PORT_VC_CAPABILITY_2 Register */ |
| 183 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL 0x00000148 /* PORT_VC_STATUS_CONTROL Register */ |
| 184 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY 0x0000014c /* VC_RESOURCE_CAPABILITY Register */ |
| 185 | #define PCIE_CFG_VC_RESOURCE_CONTROL 0x00000150 /* VC_RESOURCE_CONTROL Register */ |
| 186 | #define PCIE_CFG_VC_RESOURCE_STATUS 0x00000154 /* VC_RESOURCE_STATUS Register */ |
| 187 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER 0x00000160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */ |
| 188 | #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW 0x00000164 /* DEVICE_SERIAL_NO_LOWER_DW Register */ |
| 189 | #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW 0x00000168 /* DEVICE_SERIAL_NO_UPPER_DW Register */ |
| 190 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER 0x0000016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */ |
| 191 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT 0x00000170 /* POWER_BUDGETING_DATA_SELECT Register */ |
| 192 | #define PCIE_CFG_POWER_BUDGETING_DATA 0x00000174 /* POWER_BUDGETING_DATA Register */ |
| 193 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY 0x00000178 /* POWER_BUDGETING_CAPABILITY Register */ |
| 194 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1 0x0000017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */ |
| 195 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3 0x00000180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */ |
| 196 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5 0x00000184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */ |
| 197 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7 0x00000188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */ |
| 198 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING 0x0000018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */ |
| 199 | |
| 200 | |
| 201 | /**************************************************************************** |
| 202 | * BCM70012_TGT_TOP_PCIE_TL |
| 203 | ***************************************************************************/ |
| 204 | #define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ |
| 205 | #define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ |
| 206 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ |
| 207 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0000040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ |
| 208 | #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ |
| 209 | #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00000414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ |
| 210 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00000418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ |
| 211 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0000041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ |
| 212 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00000420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ |
| 213 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00000424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ |
| 214 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0000043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ |
| 215 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00000458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ |
| 216 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0000045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ |
| 217 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00000460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ |
| 218 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00000464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ |
| 219 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00000468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ |
| 220 | #define PCIE_TL_TL_DEBUG 0x0000046c /* TL_DEBUG Register */ |
| 221 | |
| 222 | |
| 223 | /**************************************************************************** |
| 224 | * BCM70012_TGT_TOP_PCIE_DLL |
| 225 | ***************************************************************************/ |
| 226 | #define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ |
| 227 | #define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ |
| 228 | #define PCIE_DLL_DATA_LINK_ATTENTION 0x00000508 /* DATA_LINK_ATTENTION Register */ |
| 229 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0000050c /* DATA_LINK_ATTENTION_MASK Register */ |
| 230 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ |
| 231 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ |
| 232 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ |
| 233 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0000051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ |
| 234 | #define PCIE_DLL_DATA_LINK_REPLAY 0x00000520 /* DATA_LINK_REPLAY Register */ |
| 235 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00000524 /* DATA_LINK_ACK_TIMEOUT Register */ |
| 236 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00000528 /* POWER_MANAGEMENT_THRESHOLD Register */ |
| 237 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0000052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ |
| 238 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00000530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ |
| 239 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00000534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ |
| 240 | #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00000538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ |
| 241 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0000053c /* ERROR_COUNT_THRESHOLD Register */ |
| 242 | #define PCIE_DLL_TL_ERROR_COUNTER 0x00000540 /* TL_ERROR_COUNTER Register */ |
| 243 | #define PCIE_DLL_DLLP_ERROR_COUNTER 0x00000544 /* DLLP_ERROR_COUNTER Register */ |
| 244 | #define PCIE_DLL_NAK_RECEIVED_COUNTER 0x00000548 /* NAK_RECEIVED_COUNTER Register */ |
| 245 | #define PCIE_DLL_DATA_LINK_TEST 0x0000054c /* DATA_LINK_TEST Register */ |
| 246 | #define PCIE_DLL_PACKET_BIST 0x00000550 /* PACKET_BIST Register */ |
| 247 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00000554 /* LINK_PCIE_1_1_CONTROL Register */ |
| 248 | |
| 249 | |
| 250 | /**************************************************************************** |
| 251 | * BCM70012_TGT_TOP_PCIE_PHY |
| 252 | ***************************************************************************/ |
| 253 | #define PCIE_PHY_PHY_MODE 0x00000600 /* TYPE_PHY_MODE Register */ |
| 254 | #define PCIE_PHY_PHY_LINK_STATUS 0x00000604 /* TYPE_PHY_LINK_STATUS Register */ |
| 255 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00000608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ |
| 256 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0000060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ |
| 257 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00000610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ |
| 258 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00000614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ |
| 259 | #define PCIE_PHY_PHY_ATTENTION 0x00000618 /* TYPE_PHY_ATTENTION Register */ |
| 260 | #define PCIE_PHY_PHY_ATTENTION_MASK 0x0000061c /* TYPE_PHY_ATTENTION_MASK Register */ |
| 261 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00000620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ |
| 262 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00000624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ |
| 263 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00000628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ |
| 264 | #define PCIE_PHY_PHY_TEST_CONTROL 0x0000062c /* TYPE_PHY_TEST_CONTROL Register */ |
| 265 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00000630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ |
| 266 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00000634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ |
| 267 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00000638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ |
| 268 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0000063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ |
| 269 | |
| 270 | |
| 271 | /**************************************************************************** |
| 272 | * BCM70012_TGT_TOP_INTR |
| 273 | ***************************************************************************/ |
| 274 | #define INTR_INTR_STATUS 0x00000700 /* Interrupt Status Register */ |
| 275 | #define INTR_INTR_SET 0x00000704 /* Interrupt Set Register */ |
| 276 | #define INTR_INTR_CLR_REG 0x00000708 /* Interrupt Clear Register */ |
| 277 | #define INTR_INTR_MSK_STS_REG 0x0000070c /* Interrupt Mask Status Register */ |
| 278 | #define INTR_INTR_MSK_SET_REG 0x00000710 /* Interrupt Mask Set Register */ |
| 279 | #define INTR_INTR_MSK_CLR_REG 0x00000714 /* Interrupt Mask Clear Register */ |
| 280 | #define INTR_EOI_CTRL 0x00000720 /* End of interrupt control register */ |
| 281 | |
| 282 | |
| 283 | /**************************************************************************** |
| 284 | * BCM70012_TGT_TOP_MDIO |
| 285 | ***************************************************************************/ |
| 286 | #define MDIO_CTRL0 0x00000730 /* PCIE Serdes MDIO Control Register 0 */ |
| 287 | #define MDIO_CTRL1 0x00000734 /* PCIE Serdes MDIO Control Register 1 */ |
| 288 | #define MDIO_CTRL2 0x00000738 /* PCIE Serdes MDIO Control Register 2 */ |
| 289 | |
| 290 | |
| 291 | /**************************************************************************** |
| 292 | * BCM70012_TGT_TOP_TGT_RGR_BRIDGE |
| 293 | ***************************************************************************/ |
| 294 | #define TGT_RGR_BRIDGE_REVISION 0x00000740 /* PCIE RGR Bridge Revision Register */ |
| 295 | #define TGT_RGR_BRIDGE_CTRL 0x00000744 /* RGR Bridge Control Register */ |
| 296 | #define TGT_RGR_BRIDGE_RBUS_TIMER 0x00000748 /* RGR Bridge RBUS Timer Register */ |
| 297 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0000074c /* RGR Bridge Spare Software Reset 0 Register */ |
| 298 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00000750 /* RGR Bridge Spare Software Reset 1 Register */ |
| 299 | |
| 300 | |
| 301 | /**************************************************************************** |
| 302 | * BCM70012_I2C_TOP_I2C |
| 303 | ***************************************************************************/ |
| 304 | #define I2C_CHIP_ADDRESS 0x00000800 /* I2C Chip Address And Read/Write Control */ |
| 305 | #define I2C_DATA_IN0 0x00000804 /* I2C Write Data Byte 0 */ |
| 306 | #define I2C_DATA_IN1 0x00000808 /* I2C Write Data Byte 1 */ |
| 307 | #define I2C_DATA_IN2 0x0000080c /* I2C Write Data Byte 2 */ |
| 308 | #define I2C_DATA_IN3 0x00000810 /* I2C Write Data Byte 3 */ |
| 309 | #define I2C_DATA_IN4 0x00000814 /* I2C Write Data Byte 4 */ |
| 310 | #define I2C_DATA_IN5 0x00000818 /* I2C Write Data Byte 5 */ |
| 311 | #define I2C_DATA_IN6 0x0000081c /* I2C Write Data Byte 6 */ |
| 312 | #define I2C_DATA_IN7 0x00000820 /* I2C Write Data Byte 7 */ |
| 313 | #define I2C_CNT_REG 0x00000824 /* I2C Transfer Count Register */ |
| 314 | #define I2C_CTL_REG 0x00000828 /* I2C Control Register */ |
| 315 | #define I2C_IIC_ENABLE 0x0000082c /* I2C Read/Write Enable And Interrupt */ |
| 316 | #define I2C_DATA_OUT0 0x00000830 /* I2C Read Data Byte 0 */ |
| 317 | #define I2C_DATA_OUT1 0x00000834 /* I2C Read Data Byte 1 */ |
| 318 | #define I2C_DATA_OUT2 0x00000838 /* I2C Read Data Byte 2 */ |
| 319 | #define I2C_DATA_OUT3 0x0000083c /* I2C Read Data Byte 3 */ |
| 320 | #define I2C_DATA_OUT4 0x00000840 /* I2C Read Data Byte 4 */ |
| 321 | #define I2C_DATA_OUT5 0x00000844 /* I2C Read Data Byte 5 */ |
| 322 | #define I2C_DATA_OUT6 0x00000848 /* I2C Read Data Byte 6 */ |
| 323 | #define I2C_DATA_OUT7 0x0000084c /* I2C Read Data Byte 7 */ |
| 324 | #define I2C_CTLHI_REG 0x00000850 /* I2C Control Register */ |
| 325 | #define I2C_SCL_PARAM 0x00000854 /* I2C SCL Parameter Register */ |
| 326 | |
| 327 | |
| 328 | /**************************************************************************** |
| 329 | * BCM70012_I2C_TOP_I2C_GR_BRIDGE |
| 330 | ***************************************************************************/ |
| 331 | #define I2C_GR_BRIDGE_REVISION 0x00000be0 /* GR Bridge Revision */ |
| 332 | #define I2C_GR_BRIDGE_CTRL 0x00000be4 /* GR Bridge Control Register */ |
| 333 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x00000be8 /* GR Bridge Software Reset 0 Register */ |
| 334 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x00000bec /* GR Bridge Software Reset 1 Register */ |
| 335 | |
| 336 | |
| 337 | /**************************************************************************** |
| 338 | * BCM70012_MISC_TOP_MISC1 |
| 339 | ***************************************************************************/ |
| 340 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */ |
| 341 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00000c04 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ |
| 342 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00000c08 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ |
| 343 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x00000c0c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ |
| 344 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00000c10 /* Tx DMA Software Descriptor List Control and Status */ |
| 345 | #define MISC1_TX_DMA_ERROR_STATUS 0x00000c18 /* Tx DMA Engine Error Status */ |
| 346 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR 0x00000c1c /* Tx DMA List0 Current Descriptor Lower Address */ |
| 347 | #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR 0x00000c20 /* Tx DMA List0 Current Descriptor Upper Address */ |
| 348 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM 0x00000c24 /* Tx DMA List0 Current Descriptor Upper Address */ |
| 349 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR 0x00000c28 /* Tx DMA List1 Current Descriptor Lower Address */ |
| 350 | #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR 0x00000c2c /* Tx DMA List1 Current Descriptor Upper Address */ |
| 351 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM 0x00000c30 /* Tx DMA List1 Current Descriptor Upper Address */ |
| 352 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c34 /* Y Rx Descriptor List0 First Descriptor Lower Address */ |
| 353 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c38 /* Y Rx Descriptor List0 First Descriptor Upper Address */ |
| 354 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c3c /* Y Rx Descriptor List1 First Descriptor Lower Address */ |
| 355 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c40 /* Y Rx Descriptor List1 First Descriptor Upper Address */ |
| 356 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00000c44 /* Y Rx Software Descriptor List Control and Status */ |
| 357 | #define MISC1_Y_RX_ERROR_STATUS 0x00000c4c /* Y Rx Engine Error Status */ |
| 358 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR 0x00000c50 /* Y Rx List0 Current Descriptor Lower Address */ |
| 359 | #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR 0x00000c54 /* Y Rx List0 Current Descriptor Upper Address */ |
| 360 | #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00000c58 /* Y Rx List0 Current Descriptor Byte Count */ |
| 361 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR 0x00000c5c /* Y Rx List1 Current Descriptor Lower address */ |
| 362 | #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR 0x00000c60 /* Y Rx List1 Current Descriptor Upper address */ |
| 363 | #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x00000c64 /* Y Rx List1 Current Descriptor Byte Count */ |
| 364 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c68 /* UV Rx Descriptor List0 First Descriptor lower Address */ |
| 365 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c6c /* UV Rx Descriptor List0 First Descriptor Upper Address */ |
| 366 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c70 /* UV Rx Descriptor List1 First Descriptor Lower Address */ |
| 367 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c74 /* UV Rx Descriptor List1 First Descriptor Upper Address */ |
| 368 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS 0x00000c78 /* UV Rx Software Descriptor List Control and Status */ |
| 369 | #define MISC1_UV_RX_ERROR_STATUS 0x00000c7c /* UV Rx Engine Error Status */ |
| 370 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR 0x00000c80 /* UV Rx List0 Current Descriptor Lower Address */ |
| 371 | #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR 0x00000c84 /* UV Rx List0 Current Descriptor Upper Address */ |
| 372 | #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT 0x00000c88 /* UV Rx List0 Current Descriptor Byte Count */ |
| 373 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR 0x00000c8c /* UV Rx List1 Current Descriptor Lower Address */ |
| 374 | #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR 0x00000c90 /* UV Rx List1 Current Descriptor Upper Address */ |
| 375 | #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT 0x00000c94 /* UV Rx List1 Current Descriptor Byte Count */ |
| 376 | #define MISC1_DMA_DEBUG_OPTIONS_REG 0x00000c98 /* DMA Debug Options Register */ |
| 377 | #define MISC1_READ_CHANNEL_ERROR_STATUS 0x00000c9c /* Read Channel Error Status */ |
| 378 | #define MISC1_PCIE_DMA_CTRL 0x00000ca0 /* PCIE DMA Control Register */ |
| 379 | |
| 380 | |
| 381 | /**************************************************************************** |
| 382 | * BCM70012_MISC_TOP_MISC2 |
| 383 | ***************************************************************************/ |
| 384 | #define MISC2_GLOBAL_CTRL 0x00000d00 /* Global Control Register */ |
| 385 | #define MISC2_INTERNAL_STATUS 0x00000d04 /* Internal Status Register */ |
| 386 | #define MISC2_INTERNAL_STATUS_MUX_CTRL 0x00000d08 /* Internal Debug Mux Control */ |
| 387 | #define MISC2_DEBUG_FIFO_LENGTH 0x00000d0c /* Debug FIFO Length */ |
| 388 | |
| 389 | |
| 390 | /**************************************************************************** |
| 391 | * BCM70012_MISC_TOP_MISC3 |
| 392 | ***************************************************************************/ |
| 393 | #define MISC3_RESET_CTRL 0x00000e00 /* Reset Control Register */ |
| 394 | #define MISC3_BIST_CTRL 0x00000e04 /* BIST Control Register */ |
| 395 | #define MISC3_BIST_STATUS 0x00000e08 /* BIST Status Register */ |
| 396 | #define MISC3_RX_CHECKSUM 0x00000e0c /* Receive Checksum */ |
| 397 | #define MISC3_TX_CHECKSUM 0x00000e10 /* Transmit Checksum */ |
| 398 | #define MISC3_ECO_CTRL_CORE 0x00000e14 /* ECO Core Reset Control Register */ |
| 399 | #define MISC3_CSI_TEST_CTRL 0x00000e18 /* CSI Test Control Register */ |
| 400 | #define MISC3_HD_DVI_TEST_CTRL 0x00000e1c /* HD DVI Test Control Register */ |
| 401 | |
| 402 | |
| 403 | /**************************************************************************** |
| 404 | * BCM70012_MISC_TOP_MISC_PERST |
| 405 | ***************************************************************************/ |
| 406 | #define MISC_PERST_ECO_CTRL_PERST 0x00000e80 /* ECO PCIE Reset Control Register */ |
| 407 | #define MISC_PERST_DECODER_CTRL 0x00000e84 /* Decoder Control Register */ |
| 408 | #define MISC_PERST_CCE_STATUS 0x00000e88 /* Config Copy Engine Status */ |
| 409 | #define MISC_PERST_PCIE_DEBUG 0x00000e8c /* PCIE Debug Control Register */ |
| 410 | #define MISC_PERST_PCIE_DEBUG_STATUS 0x00000e90 /* PCIE Debug Status Register */ |
| 411 | #define MISC_PERST_VREG_CTRL 0x00000e94 /* Voltage Regulator Control Register */ |
| 412 | #define MISC_PERST_MEM_CTRL 0x00000e98 /* Memory Control Register */ |
| 413 | #define MISC_PERST_CLOCK_CTRL 0x00000e9c /* Clock Control Register */ |
| 414 | |
| 415 | |
| 416 | /**************************************************************************** |
| 417 | * BCM70012_MISC_TOP_GISB_ARBITER |
| 418 | ***************************************************************************/ |
| 419 | #define GISB_ARBITER_REVISION 0x00000f00 /* GISB ARBITER REVISION */ |
| 420 | #define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ |
| 421 | #define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ |
| 422 | #define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ |
| 423 | #define GISB_ARBITER_BP_CTRL 0x00000f10 /* GISB ARBITER Breakpoint Control Register */ |
| 424 | #define GISB_ARBITER_BP_CAP_CLR 0x00000f14 /* GISB ARBITER Breakpoint Capture Clear Register */ |
| 425 | #define GISB_ARBITER_BP_START_ADDR_0 0x00000f18 /* GISB ARBITER Breakpoint Start Address 0 Register */ |
| 426 | #define GISB_ARBITER_BP_END_ADDR_0 0x00000f1c /* GISB ARBITER Breakpoint End Address 0 Register */ |
| 427 | #define GISB_ARBITER_BP_READ_0 0x00000f20 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ |
| 428 | #define GISB_ARBITER_BP_WRITE_0 0x00000f24 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ |
| 429 | #define GISB_ARBITER_BP_ENABLE_0 0x00000f28 /* GISB ARBITER Breakpoint Enable 0 Register */ |
| 430 | #define GISB_ARBITER_BP_START_ADDR_1 0x00000f2c /* GISB ARBITER Breakpoint Start Address 1 Register */ |
| 431 | #define GISB_ARBITER_BP_END_ADDR_1 0x00000f30 /* GISB ARBITER Breakpoint End Address 1 Register */ |
| 432 | #define GISB_ARBITER_BP_READ_1 0x00000f34 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ |
| 433 | #define GISB_ARBITER_BP_WRITE_1 0x00000f38 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ |
| 434 | #define GISB_ARBITER_BP_ENABLE_1 0x00000f3c /* GISB ARBITER Breakpoint Enable 1 Register */ |
| 435 | #define GISB_ARBITER_BP_START_ADDR_2 0x00000f40 /* GISB ARBITER Breakpoint Start Address 2 Register */ |
| 436 | #define GISB_ARBITER_BP_END_ADDR_2 0x00000f44 /* GISB ARBITER Breakpoint End Address 2 Register */ |
| 437 | #define GISB_ARBITER_BP_READ_2 0x00000f48 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ |
| 438 | #define GISB_ARBITER_BP_WRITE_2 0x00000f4c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ |
| 439 | #define GISB_ARBITER_BP_ENABLE_2 0x00000f50 /* GISB ARBITER Breakpoint Enable 2 Register */ |
| 440 | #define GISB_ARBITER_BP_START_ADDR_3 0x00000f54 /* GISB ARBITER Breakpoint Start Address 3 Register */ |
| 441 | #define GISB_ARBITER_BP_END_ADDR_3 0x00000f58 /* GISB ARBITER Breakpoint End Address 3 Register */ |
| 442 | #define GISB_ARBITER_BP_READ_3 0x00000f5c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ |
| 443 | #define GISB_ARBITER_BP_WRITE_3 0x00000f60 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ |
| 444 | #define GISB_ARBITER_BP_ENABLE_3 0x00000f64 /* GISB ARBITER Breakpoint Enable 3 Register */ |
| 445 | #define GISB_ARBITER_BP_START_ADDR_4 0x00000f68 /* GISB ARBITER Breakpoint Start Address 4 Register */ |
| 446 | #define GISB_ARBITER_BP_END_ADDR_4 0x00000f6c /* GISB ARBITER Breakpoint End Address 4 Register */ |
| 447 | #define GISB_ARBITER_BP_READ_4 0x00000f70 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ |
| 448 | #define GISB_ARBITER_BP_WRITE_4 0x00000f74 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ |
| 449 | #define GISB_ARBITER_BP_ENABLE_4 0x00000f78 /* GISB ARBITER Breakpoint Enable 4 Register */ |
| 450 | #define GISB_ARBITER_BP_START_ADDR_5 0x00000f7c /* GISB ARBITER Breakpoint Start Address 5 Register */ |
| 451 | #define GISB_ARBITER_BP_END_ADDR_5 0x00000f80 /* GISB ARBITER Breakpoint End Address 5 Register */ |
| 452 | #define GISB_ARBITER_BP_READ_5 0x00000f84 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ |
| 453 | #define GISB_ARBITER_BP_WRITE_5 0x00000f88 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ |
| 454 | #define GISB_ARBITER_BP_ENABLE_5 0x00000f8c /* GISB ARBITER Breakpoint Enable 5 Register */ |
| 455 | #define GISB_ARBITER_BP_START_ADDR_6 0x00000f90 /* GISB ARBITER Breakpoint Start Address 6 Register */ |
| 456 | #define GISB_ARBITER_BP_END_ADDR_6 0x00000f94 /* GISB ARBITER Breakpoint End Address 6 Register */ |
| 457 | #define GISB_ARBITER_BP_READ_6 0x00000f98 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ |
| 458 | #define GISB_ARBITER_BP_WRITE_6 0x00000f9c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ |
| 459 | #define GISB_ARBITER_BP_ENABLE_6 0x00000fa0 /* GISB ARBITER Breakpoint Enable 6 Register */ |
| 460 | #define GISB_ARBITER_BP_START_ADDR_7 0x00000fa4 /* GISB ARBITER Breakpoint Start Address 7 Register */ |
| 461 | #define GISB_ARBITER_BP_END_ADDR_7 0x00000fa8 /* GISB ARBITER Breakpoint End Address 7 Register */ |
| 462 | #define GISB_ARBITER_BP_READ_7 0x00000fac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ |
| 463 | #define GISB_ARBITER_BP_WRITE_7 0x00000fb0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ |
| 464 | #define GISB_ARBITER_BP_ENABLE_7 0x00000fb4 /* GISB ARBITER Breakpoint Enable 7 Register */ |
| 465 | #define GISB_ARBITER_BP_CAP_ADDR 0x00000fb8 /* GISB ARBITER Breakpoint Capture Address Register */ |
| 466 | #define GISB_ARBITER_BP_CAP_DATA 0x00000fbc /* GISB ARBITER Breakpoint Capture Data Register */ |
| 467 | #define GISB_ARBITER_BP_CAP_STATUS 0x00000fc0 /* GISB ARBITER Breakpoint Capture Status Register */ |
| 468 | #define GISB_ARBITER_BP_CAP_MASTER 0x00000fc4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ |
| 469 | #define GISB_ARBITER_ERR_CAP_CLR 0x00000fc8 /* GISB ARBITER Error Capture Clear Register */ |
| 470 | #define GISB_ARBITER_ERR_CAP_ADDR 0x00000fcc /* GISB ARBITER Error Capture Address Register */ |
| 471 | #define GISB_ARBITER_ERR_CAP_DATA 0x00000fd0 /* GISB ARBITER Error Capture Data Register */ |
| 472 | #define GISB_ARBITER_ERR_CAP_STATUS 0x00000fd4 /* GISB ARBITER Error Capture Status Register */ |
| 473 | #define GISB_ARBITER_ERR_CAP_MASTER 0x00000fd8 /* GISB ARBITER Error Capture GISB MASTER Register */ |
| 474 | |
| 475 | |
| 476 | /**************************************************************************** |
| 477 | * BCM70012_MISC_TOP_MISC_GR_BRIDGE |
| 478 | ***************************************************************************/ |
| 479 | #define MISC_GR_BRIDGE_REVISION 0x00000fe0 /* GR Bridge Revision */ |
| 480 | #define MISC_GR_BRIDGE_CTRL 0x00000fe4 /* GR Bridge Control Register */ |
| 481 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x00000fe8 /* GR Bridge Software Reset 0 Register */ |
| 482 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x00000fec /* GR Bridge Software Reset 1 Register */ |
| 483 | |
| 484 | |
| 485 | /**************************************************************************** |
| 486 | * BCM70012_DBU_TOP_DBU |
| 487 | ***************************************************************************/ |
| 488 | #define DBU_DBU_CMD 0x00001000 /* DBU (Debug UART) command register */ |
| 489 | #define DBU_DBU_STATUS 0x00001004 /* DBU (Debug UART) status register */ |
| 490 | #define DBU_DBU_CONFIG 0x00001008 /* DBU (Debug UART) configuration register */ |
| 491 | #define DBU_DBU_TIMING 0x0000100c /* DBU (Debug UART) timing register */ |
| 492 | #define DBU_DBU_RXDATA 0x00001010 /* DBU (Debug UART) recieve data register */ |
| 493 | #define DBU_DBU_TXDATA 0x00001014 /* DBU (Debug UART) transmit data register */ |
| 494 | |
| 495 | |
| 496 | /**************************************************************************** |
| 497 | * BCM70012_DBU_TOP_DBU_RGR_BRIDGE |
| 498 | ***************************************************************************/ |
| 499 | #define DBU_RGR_BRIDGE_REVISION 0x000013e0 /* RGR Bridge Revision */ |
| 500 | #define DBU_RGR_BRIDGE_CTRL 0x000013e4 /* RGR Bridge Control Register */ |
| 501 | #define DBU_RGR_BRIDGE_RBUS_TIMER 0x000013e8 /* RGR Bridge RBUS Timer Register */ |
| 502 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0 0x000013ec /* RGR Bridge Software Reset 0 Register */ |
| 503 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1 0x000013f0 /* RGR Bridge Software Reset 1 Register */ |
| 504 | |
| 505 | |
| 506 | /**************************************************************************** |
| 507 | * BCM70012_OTP_TOP_OTP |
| 508 | ***************************************************************************/ |
| 509 | #define OTP_CONFIG_INFO 0x00001400 /* OTP Configuration Register */ |
| 510 | #define OTP_CMD 0x00001404 /* OTP Command Register */ |
| 511 | #define OTP_STATUS 0x00001408 /* OTP Status Register */ |
| 512 | #define OTP_CONTENT_MISC 0x0000140c /* Content : Miscellaneous Register */ |
| 513 | #define OTP_CONTENT_AES_0 0x00001410 /* Content : AES Key 0 Register */ |
| 514 | #define OTP_CONTENT_AES_1 0x00001414 /* Content : AES Key 1 Register */ |
| 515 | #define OTP_CONTENT_AES_2 0x00001418 /* Content : AES Key 2 Register */ |
| 516 | #define OTP_CONTENT_AES_3 0x0000141c /* Content : AES Key 3 Register */ |
| 517 | #define OTP_CONTENT_SHA_0 0x00001420 /* Content : SHA Key 0 Register */ |
| 518 | #define OTP_CONTENT_SHA_1 0x00001424 /* Content : SHA Key 1 Register */ |
| 519 | #define OTP_CONTENT_SHA_2 0x00001428 /* Content : SHA Key 2 Register */ |
| 520 | #define OTP_CONTENT_SHA_3 0x0000142c /* Content : SHA Key 3 Register */ |
| 521 | #define OTP_CONTENT_SHA_4 0x00001430 /* Content : SHA Key 4 Register */ |
| 522 | #define OTP_CONTENT_SHA_5 0x00001434 /* Content : SHA Key 5 Register */ |
| 523 | #define OTP_CONTENT_SHA_6 0x00001438 /* Content : SHA Key 6 Register */ |
| 524 | #define OTP_CONTENT_SHA_7 0x0000143c /* Content : SHA Key 7 Register */ |
| 525 | #define OTP_CONTENT_CHECKSUM 0x00001440 /* Content : Checksum Register */ |
| 526 | #define OTP_PROG_CTRL 0x00001444 /* Programming Control Register */ |
| 527 | #define OTP_PROG_STATUS 0x00001448 /* Programming Status Register */ |
| 528 | #define OTP_PROG_PULSE 0x0000144c /* Program Pulse Width Register */ |
| 529 | #define OTP_VERIFY_PULSE 0x00001450 /* Verify Pulse Width Register */ |
| 530 | #define OTP_PROG_MASK 0x00001454 /* Program Mask Register */ |
| 531 | #define OTP_DATA_INPUT 0x00001458 /* Data Input Register */ |
| 532 | #define OTP_DATA_OUTPUT 0x0000145c /* Data Output Register */ |
| 533 | |
| 534 | |
| 535 | /**************************************************************************** |
| 536 | * BCM70012_OTP_TOP_OTP_GR_BRIDGE |
| 537 | ***************************************************************************/ |
| 538 | #define OTP_GR_BRIDGE_REVISION 0x000017e0 /* GR Bridge Revision */ |
| 539 | #define OTP_GR_BRIDGE_CTRL 0x000017e4 /* GR Bridge Control Register */ |
| 540 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0 0x000017e8 /* GR Bridge Software Reset 0 Register */ |
| 541 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1 0x000017ec /* GR Bridge Software Reset 1 Register */ |
| 542 | |
| 543 | |
| 544 | /**************************************************************************** |
| 545 | * BCM70012_AES_TOP_AES |
| 546 | ***************************************************************************/ |
| 547 | #define AES_CONFIG_INFO 0x00001800 /* AES Configuration Information Register */ |
| 548 | #define AES_CMD 0x00001804 /* AES Command Register */ |
| 549 | #define AES_STATUS 0x00001808 /* AES Status Register */ |
| 550 | #define AES_EEPROM_CONFIG 0x0000180c /* AES EEPROM Configuration Register */ |
| 551 | #define AES_EEPROM_DATA_0 0x00001810 /* AES EEPROM Data Register 0 */ |
| 552 | #define AES_EEPROM_DATA_1 0x00001814 /* AES EEPROM Data Register 1 */ |
| 553 | #define AES_EEPROM_DATA_2 0x00001818 /* AES EEPROM Data Register 2 */ |
| 554 | #define AES_EEPROM_DATA_3 0x0000181c /* AES EEPROM Data Register 3 */ |
| 555 | |
| 556 | |
| 557 | /**************************************************************************** |
| 558 | * BCM70012_AES_TOP_AES_RGR_BRIDGE |
| 559 | ***************************************************************************/ |
| 560 | #define AES_RGR_BRIDGE_REVISION 0x00001be0 /* RGR Bridge Revision */ |
| 561 | #define AES_RGR_BRIDGE_CTRL 0x00001be4 /* RGR Bridge Control Register */ |
| 562 | #define AES_RGR_BRIDGE_RBUS_TIMER 0x00001be8 /* RGR Bridge RBUS Timer Register */ |
| 563 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001bec /* RGR Bridge Software Reset 0 Register */ |
| 564 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001bf0 /* RGR Bridge Software Reset 1 Register */ |
| 565 | |
| 566 | |
| 567 | /**************************************************************************** |
| 568 | * BCM70012_DCI_TOP_DCI |
| 569 | ***************************************************************************/ |
| 570 | #define DCI_CMD 0x00001c00 /* DCI Command Register */ |
| 571 | #define DCI_STATUS 0x00001c04 /* DCI Status Register */ |
| 572 | #define DCI_DRAM_BASE_ADDR 0x00001c08 /* DRAM Base Address Register */ |
| 573 | #define DCI_FIRMWARE_ADDR 0x00001c0c /* Firmware Address Register */ |
| 574 | #define DCI_FIRMWARE_DATA 0x00001c10 /* Firmware Data Register */ |
| 575 | #define DCI_SIGNATURE_DATA_0 0x00001c14 /* Signature Data Register 0 */ |
| 576 | #define DCI_SIGNATURE_DATA_1 0x00001c18 /* Signature Data Register 1 */ |
| 577 | #define DCI_SIGNATURE_DATA_2 0x00001c1c /* Signature Data Register 2 */ |
| 578 | #define DCI_SIGNATURE_DATA_3 0x00001c20 /* Signature Data Register 3 */ |
| 579 | #define DCI_SIGNATURE_DATA_4 0x00001c24 /* Signature Data Register 4 */ |
| 580 | #define DCI_SIGNATURE_DATA_5 0x00001c28 /* Signature Data Register 5 */ |
| 581 | #define DCI_SIGNATURE_DATA_6 0x00001c2c /* Signature Data Register 6 */ |
| 582 | #define DCI_SIGNATURE_DATA_7 0x00001c30 /* Signature Data Register 7 */ |
| 583 | |
| 584 | |
| 585 | /**************************************************************************** |
| 586 | * BCM70012_DCI_TOP_DCI_RGR_BRIDGE |
| 587 | ***************************************************************************/ |
| 588 | #define DCI_RGR_BRIDGE_REVISION 0x00001fe0 /* RGR Bridge Revision */ |
| 589 | #define DCI_RGR_BRIDGE_CTRL 0x00001fe4 /* RGR Bridge Control Register */ |
| 590 | #define DCI_RGR_BRIDGE_RBUS_TIMER 0x00001fe8 /* RGR Bridge RBUS Timer Register */ |
| 591 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001fec /* RGR Bridge Software Reset 0 Register */ |
| 592 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001ff0 /* RGR Bridge Software Reset 1 Register */ |
| 593 | |
| 594 | |
| 595 | /**************************************************************************** |
| 596 | * BCM70012_CCE_TOP_CCE_RGR_BRIDGE |
| 597 | ***************************************************************************/ |
| 598 | #define CCE_RGR_BRIDGE_REVISION 0x000023e0 /* RGR Bridge Revision */ |
| 599 | #define CCE_RGR_BRIDGE_CTRL 0x000023e4 /* RGR Bridge Control Register */ |
| 600 | #define CCE_RGR_BRIDGE_RBUS_TIMER 0x000023e8 /* RGR Bridge RBUS Timer Register */ |
| 601 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x000023ec /* RGR Bridge Software Reset 0 Register */ |
| 602 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x000023f0 /* RGR Bridge Software Reset 1 Register */ |
| 603 | |
| 604 | |
| 605 | /**************************************************************************** |
| 606 | * BCM70012_TGT_TOP_PCIE_CFG |
| 607 | ***************************************************************************/ |
| 608 | /**************************************************************************** |
| 609 | * PCIE_CFG :: DEVICE_VENDOR_ID |
| 610 | ***************************************************************************/ |
| 611 | /* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ |
| 612 | #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 |
| 613 | #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_ALIGN 0 |
| 614 | #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_BITS 16 |
| 615 | #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 |
| 616 | |
| 617 | /* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ |
| 618 | #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff |
| 619 | #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_ALIGN 0 |
| 620 | #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_BITS 16 |
| 621 | #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 |
| 622 | |
| 623 | |
| 624 | /**************************************************************************** |
| 625 | * PCIE_CFG :: STATUS_COMMAND |
| 626 | ***************************************************************************/ |
| 627 | /* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ |
| 628 | #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 |
| 629 | #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_ALIGN 0 |
| 630 | #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_BITS 1 |
| 631 | #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 |
| 632 | |
| 633 | /* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ |
| 634 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 |
| 635 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_ALIGN 0 |
| 636 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_BITS 1 |
| 637 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 |
| 638 | |
| 639 | /* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ |
| 640 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 |
| 641 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_ALIGN 0 |
| 642 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_BITS 1 |
| 643 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 |
| 644 | |
| 645 | /* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ |
| 646 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 |
| 647 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_ALIGN 0 |
| 648 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_BITS 1 |
| 649 | #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 |
| 650 | |
| 651 | /* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ |
| 652 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 |
| 653 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_ALIGN 0 |
| 654 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_BITS 1 |
| 655 | #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 |
| 656 | |
| 657 | /* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ |
| 658 | #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 |
| 659 | #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_ALIGN 0 |
| 660 | #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_BITS 2 |
| 661 | #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 |
| 662 | |
| 663 | /* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ |
| 664 | #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 |
| 665 | #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_ALIGN 0 |
| 666 | #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_BITS 1 |
| 667 | #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 |
| 668 | |
| 669 | /* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ |
| 670 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 |
| 671 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_ALIGN 0 |
| 672 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_BITS 1 |
| 673 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 |
| 674 | |
| 675 | /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ |
| 676 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 |
| 677 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_ALIGN 0 |
| 678 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_BITS 1 |
| 679 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 |
| 680 | |
| 681 | /* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ |
| 682 | #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 |
| 683 | #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_ALIGN 0 |
| 684 | #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_BITS 1 |
| 685 | #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 |
| 686 | |
| 687 | /* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ |
| 688 | #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 |
| 689 | #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_ALIGN 0 |
| 690 | #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_BITS 1 |
| 691 | #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 |
| 692 | |
| 693 | /* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ |
| 694 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 |
| 695 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_ALIGN 0 |
| 696 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_BITS 1 |
| 697 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 |
| 698 | |
| 699 | /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ |
| 700 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 |
| 701 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_ALIGN 0 |
| 702 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_BITS 3 |
| 703 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 |
| 704 | |
| 705 | /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ |
| 706 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 |
| 707 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_ALIGN 0 |
| 708 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_BITS 5 |
| 709 | #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 |
| 710 | |
| 711 | /* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ |
| 712 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 |
| 713 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_ALIGN 0 |
| 714 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_BITS 1 |
| 715 | #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 |
| 716 | |
| 717 | /* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ |
| 718 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 |
| 719 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_ALIGN 0 |
| 720 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_BITS 1 |
| 721 | #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 |
| 722 | |
| 723 | /* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ |
| 724 | #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 |
| 725 | #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_ALIGN 0 |
| 726 | #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_BITS 1 |
| 727 | #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 |
| 728 | |
| 729 | /* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ |
| 730 | #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 |
| 731 | #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_ALIGN 0 |
| 732 | #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_BITS 1 |
| 733 | #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 |
| 734 | |
| 735 | /* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ |
| 736 | #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 |
| 737 | #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_ALIGN 0 |
| 738 | #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_BITS 1 |
| 739 | #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 |
| 740 | |
| 741 | /* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ |
| 742 | #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 |
| 743 | #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_ALIGN 0 |
| 744 | #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_BITS 1 |
| 745 | #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 |
| 746 | |
| 747 | /* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ |
| 748 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 |
| 749 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_ALIGN 0 |
| 750 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_BITS 1 |
| 751 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 |
| 752 | |
| 753 | /* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ |
| 754 | #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 |
| 755 | #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_ALIGN 0 |
| 756 | #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_BITS 1 |
| 757 | #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 |
| 758 | |
| 759 | /* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ |
| 760 | #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 |
| 761 | #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_ALIGN 0 |
| 762 | #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_BITS 1 |
| 763 | #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 |
| 764 | |
| 765 | /* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ |
| 766 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 |
| 767 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_ALIGN 0 |
| 768 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_BITS 1 |
| 769 | #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 |
| 770 | |
| 771 | /* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ |
| 772 | #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 |
| 773 | #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_ALIGN 0 |
| 774 | #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_BITS 1 |
| 775 | #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 |
| 776 | |
| 777 | |
| 778 | /**************************************************************************** |
| 779 | * PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID |
| 780 | ***************************************************************************/ |
| 781 | /* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ |
| 782 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 |
| 783 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_ALIGN 0 |
| 784 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_BITS 24 |
| 785 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 |
| 786 | |
| 787 | /* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ |
| 788 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff |
| 789 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_ALIGN 0 |
| 790 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_BITS 8 |
| 791 | #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 |
| 792 | |
| 793 | |
| 794 | /**************************************************************************** |
| 795 | * PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE |
| 796 | ***************************************************************************/ |
| 797 | /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ |
| 798 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 |
| 799 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_ALIGN 0 |
| 800 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_BITS 8 |
| 801 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 |
| 802 | |
| 803 | /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ |
| 804 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 |
| 805 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_ALIGN 0 |
| 806 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_BITS 8 |
| 807 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 |
| 808 | |
| 809 | /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ |
| 810 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 |
| 811 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_ALIGN 0 |
| 812 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_BITS 8 |
| 813 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 |
| 814 | |
| 815 | /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ |
| 816 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff |
| 817 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_ALIGN 0 |
| 818 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_BITS 8 |
| 819 | #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 |
| 820 | |
| 821 | |
| 822 | /**************************************************************************** |
| 823 | * PCIE_CFG :: BASE_ADDRESS_1 |
| 824 | ***************************************************************************/ |
| 825 | /* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ |
| 826 | #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 |
| 827 | #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_ALIGN 0 |
| 828 | #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_BITS 16 |
| 829 | #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 |
| 830 | |
| 831 | /* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ |
| 832 | #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 |
| 833 | #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_ALIGN 0 |
| 834 | #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_BITS 12 |
| 835 | #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 |
| 836 | |
| 837 | /* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ |
| 838 | #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 |
| 839 | #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_ALIGN 0 |
| 840 | #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_BITS 1 |
| 841 | #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 |
| 842 | |
| 843 | /* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ |
| 844 | #define PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 |
| 845 | #define PCIE_CFG_BASE_ADDRESS_1_TYPE_ALIGN 0 |
| 846 | #define PCIE_CFG_BASE_ADDRESS_1_TYPE_BITS 2 |
| 847 | #define PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 |
| 848 | |
| 849 | /* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ |
| 850 | #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 |
| 851 | #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_ALIGN 0 |
| 852 | #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_BITS 1 |
| 853 | #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 |
| 854 | |
| 855 | |
| 856 | /**************************************************************************** |
| 857 | * PCIE_CFG :: BASE_ADDRESS_2 |
| 858 | ***************************************************************************/ |
| 859 | /* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ |
| 860 | #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff |
| 861 | #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_ALIGN 0 |
| 862 | #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_BITS 32 |
| 863 | #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 |
| 864 | |
| 865 | |
| 866 | /**************************************************************************** |
| 867 | * PCIE_CFG :: BASE_ADDRESS_3 |
| 868 | ***************************************************************************/ |
| 869 | /* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS_2 [31:22] */ |
| 870 | #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_MASK 0xffc00000 |
| 871 | #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_ALIGN 0 |
| 872 | #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_BITS 10 |
| 873 | #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_SHIFT 22 |
| 874 | |
| 875 | /* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [21:04] */ |
| 876 | #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x003ffff0 |
| 877 | #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_ALIGN 0 |
| 878 | #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_BITS 18 |
| 879 | #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 |
| 880 | |
| 881 | /* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ |
| 882 | #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 |
| 883 | #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_ALIGN 0 |
| 884 | #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_BITS 1 |
| 885 | #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 |
| 886 | |
| 887 | /* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ |
| 888 | #define PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 |
| 889 | #define PCIE_CFG_BASE_ADDRESS_3_TYPE_ALIGN 0 |
| 890 | #define PCIE_CFG_BASE_ADDRESS_3_TYPE_BITS 2 |
| 891 | #define PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 |
| 892 | |
| 893 | /* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ |
| 894 | #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 |
| 895 | #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_ALIGN 0 |
| 896 | #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_BITS 1 |
| 897 | #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 |
| 898 | |
| 899 | |
| 900 | /**************************************************************************** |
| 901 | * PCIE_CFG :: BASE_ADDRESS_4 |
| 902 | ***************************************************************************/ |
| 903 | /* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS_2 [31:00] */ |
| 904 | #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_MASK 0xffffffff |
| 905 | #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_ALIGN 0 |
| 906 | #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_BITS 32 |
| 907 | #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_SHIFT 0 |
| 908 | |
| 909 | |
| 910 | /**************************************************************************** |
| 911 | * PCIE_CFG :: CARDBUS_CIS_POINTER |
| 912 | ***************************************************************************/ |
| 913 | /* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ |
| 914 | #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff |
| 915 | #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_ALIGN 0 |
| 916 | #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_BITS 32 |
| 917 | #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 |
| 918 | |
| 919 | |
| 920 | /**************************************************************************** |
| 921 | * PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID |
| 922 | ***************************************************************************/ |
| 923 | /* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ |
| 924 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 |
| 925 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_ALIGN 0 |
| 926 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_BITS 16 |
| 927 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 |
| 928 | |
| 929 | /* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ |
| 930 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff |
| 931 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_ALIGN 0 |
| 932 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BITS 16 |
| 933 | #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 |
| 934 | |
| 935 | |
| 936 | /**************************************************************************** |
| 937 | * PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS |
| 938 | ***************************************************************************/ |
| 939 | /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ |
| 940 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 |
| 941 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_ALIGN 0 |
| 942 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_BITS 16 |
| 943 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 |
| 944 | |
| 945 | /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ |
| 946 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 |
| 947 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_ALIGN 0 |
| 948 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_BITS 5 |
| 949 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 |
| 950 | |
| 951 | /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ |
| 952 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe |
| 953 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_ALIGN 0 |
| 954 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_BITS 10 |
| 955 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 |
| 956 | |
| 957 | /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ |
| 958 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 |
| 959 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_ALIGN 0 |
| 960 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_BITS 1 |
| 961 | #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 |
| 962 | |
| 963 | |
| 964 | /**************************************************************************** |
| 965 | * PCIE_CFG :: CAPABILITIES_POINTER |
| 966 | ***************************************************************************/ |
| 967 | /* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ |
| 968 | #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff |
| 969 | #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_ALIGN 0 |
| 970 | #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_BITS 32 |
| 971 | #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 |
| 972 | |
| 973 | |
| 974 | /**************************************************************************** |
| 975 | * PCIE_CFG :: INTERRUPT |
| 976 | ***************************************************************************/ |
| 977 | /* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ |
| 978 | #define PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 |
| 979 | #define PCIE_CFG_INTERRUPT_RESERVED_0_ALIGN 0 |
| 980 | #define PCIE_CFG_INTERRUPT_RESERVED_0_BITS 16 |
| 981 | #define PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 |
| 982 | |
| 983 | /* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ |
| 984 | #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 |
| 985 | #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_ALIGN 0 |
| 986 | #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_BITS 8 |
| 987 | #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 |
| 988 | |
| 989 | /* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ |
| 990 | #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff |
| 991 | #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_ALIGN 0 |
| 992 | #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_BITS 8 |
| 993 | #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 |
| 994 | |
| 995 | |
| 996 | /**************************************************************************** |
| 997 | * PCIE_CFG :: VPD_CAPABILITIES |
| 998 | ***************************************************************************/ |
| 999 | /* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ |
| 1000 | #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff |
| 1001 | #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_ALIGN 0 |
| 1002 | #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_BITS 32 |
| 1003 | #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 |
| 1004 | |
| 1005 | |
| 1006 | /**************************************************************************** |
| 1007 | * PCIE_CFG :: VPD_DATA |
| 1008 | ***************************************************************************/ |
| 1009 | /* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ |
| 1010 | #define PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff |
| 1011 | #define PCIE_CFG_VPD_DATA_RESERVED_0_ALIGN 0 |
| 1012 | #define PCIE_CFG_VPD_DATA_RESERVED_0_BITS 32 |
| 1013 | #define PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 |
| 1014 | |
| 1015 | |
| 1016 | /**************************************************************************** |
| 1017 | * PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY |
| 1018 | ***************************************************************************/ |
| 1019 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ |
| 1020 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 |
| 1021 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_ALIGN 0 |
| 1022 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_BITS 5 |
| 1023 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 |
| 1024 | |
| 1025 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ |
| 1026 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 |
| 1027 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_ALIGN 0 |
| 1028 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_BITS 1 |
| 1029 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 |
| 1030 | |
| 1031 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ |
| 1032 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 |
| 1033 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_ALIGN 0 |
| 1034 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_BITS 1 |
| 1035 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 |
| 1036 | |
| 1037 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ |
| 1038 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 |
| 1039 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_ALIGN 0 |
| 1040 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_BITS 3 |
| 1041 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 |
| 1042 | |
| 1043 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ |
| 1044 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 |
| 1045 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_ALIGN 0 |
| 1046 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_BITS 1 |
| 1047 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 |
| 1048 | |
| 1049 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ |
| 1050 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 |
| 1051 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_ALIGN 0 |
| 1052 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_BITS 1 |
| 1053 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 |
| 1054 | |
| 1055 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ |
| 1056 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 |
| 1057 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_ALIGN 0 |
| 1058 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_BITS 1 |
| 1059 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 |
| 1060 | |
| 1061 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ |
| 1062 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 |
| 1063 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_ALIGN 0 |
| 1064 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_BITS 3 |
| 1065 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 |
| 1066 | |
| 1067 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ |
| 1068 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 |
| 1069 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_ALIGN 0 |
| 1070 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_BITS 8 |
| 1071 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 |
| 1072 | |
| 1073 | /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ |
| 1074 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff |
| 1075 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_ALIGN 0 |
| 1076 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_BITS 8 |
| 1077 | #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 |
| 1078 | |
| 1079 | |
| 1080 | /**************************************************************************** |
| 1081 | * PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS |
| 1082 | ***************************************************************************/ |
| 1083 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ |
| 1084 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 |
| 1085 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_ALIGN 0 |
| 1086 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_BITS 8 |
| 1087 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 |
| 1088 | |
| 1089 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ |
| 1090 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 |
| 1091 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_ALIGN 0 |
| 1092 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_BITS 8 |
| 1093 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 |
| 1094 | |
| 1095 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ |
| 1096 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 |
| 1097 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_ALIGN 0 |
| 1098 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_BITS 1 |
| 1099 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 |
| 1100 | |
| 1101 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ |
| 1102 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 |
| 1103 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_ALIGN 0 |
| 1104 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_BITS 2 |
| 1105 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 |
| 1106 | |
| 1107 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ |
| 1108 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 |
| 1109 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_ALIGN 0 |
| 1110 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_BITS 4 |
| 1111 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 |
| 1112 | |
| 1113 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ |
| 1114 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 |
| 1115 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_ALIGN 0 |
| 1116 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_BITS 1 |
| 1117 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 |
| 1118 | |
| 1119 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ |
| 1120 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 |
| 1121 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_ALIGN 0 |
| 1122 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_BITS 4 |
| 1123 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 |
| 1124 | |
| 1125 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ |
| 1126 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 |
| 1127 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_ALIGN 0 |
| 1128 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_BITS 1 |
| 1129 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 |
| 1130 | |
| 1131 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ |
| 1132 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 |
| 1133 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_ALIGN 0 |
| 1134 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_BITS 1 |
| 1135 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 |
| 1136 | |
| 1137 | /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ |
| 1138 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 |
| 1139 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_ALIGN 0 |
| 1140 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_BITS 2 |
| 1141 | #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 |
| 1142 | |
| 1143 | |
| 1144 | /**************************************************************************** |
| 1145 | * PCIE_CFG :: MSI_CAPABILITY_HEADER |
| 1146 | ***************************************************************************/ |
| 1147 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ |
| 1148 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 |
| 1149 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_ALIGN 0 |
| 1150 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_BITS 8 |
| 1151 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 |
| 1152 | |
| 1153 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ |
| 1154 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 |
| 1155 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_ALIGN 0 |
| 1156 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_BITS 1 |
| 1157 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 |
| 1158 | |
| 1159 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ |
| 1160 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 |
| 1161 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_ALIGN 0 |
| 1162 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_BITS 3 |
| 1163 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 |
| 1164 | |
| 1165 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ |
| 1166 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 |
| 1167 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_ALIGN 0 |
| 1168 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_BITS 3 |
| 1169 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 |
| 1170 | |
| 1171 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ |
| 1172 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 |
| 1173 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_ALIGN 0 |
| 1174 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_BITS 1 |
| 1175 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 |
| 1176 | |
| 1177 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ |
| 1178 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 |
| 1179 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 |
| 1180 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 |
| 1181 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 |
| 1182 | |
| 1183 | /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ |
| 1184 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff |
| 1185 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 |
| 1186 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 |
| 1187 | #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 |
| 1188 | |
| 1189 | |
| 1190 | /**************************************************************************** |
| 1191 | * PCIE_CFG :: MSI_LOWER_ADDRESS |
| 1192 | ***************************************************************************/ |
| 1193 | /* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ |
| 1194 | #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc |
| 1195 | #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_ALIGN 0 |
| 1196 | #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_BITS 30 |
| 1197 | #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 |
| 1198 | |
| 1199 | /* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ |
| 1200 | #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 |
| 1201 | #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_ALIGN 0 |
| 1202 | #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_BITS 2 |
| 1203 | #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 |
| 1204 | |
| 1205 | |
| 1206 | /**************************************************************************** |
| 1207 | * PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER |
| 1208 | ***************************************************************************/ |
| 1209 | /* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ |
| 1210 | #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff |
| 1211 | #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_ALIGN 0 |
| 1212 | #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_BITS 32 |
| 1213 | #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 |
| 1214 | |
| 1215 | |
| 1216 | /**************************************************************************** |
| 1217 | * PCIE_CFG :: MSI_DATA |
| 1218 | ***************************************************************************/ |
| 1219 | /* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ |
| 1220 | #define PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 |
| 1221 | #define PCIE_CFG_MSI_DATA_RESERVED_0_ALIGN 0 |
| 1222 | #define PCIE_CFG_MSI_DATA_RESERVED_0_BITS 16 |
| 1223 | #define PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 |
| 1224 | |
| 1225 | /* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ |
| 1226 | #define PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff |
| 1227 | #define PCIE_CFG_MSI_DATA_MSI_DATA_ALIGN 0 |
| 1228 | #define PCIE_CFG_MSI_DATA_MSI_DATA_BITS 16 |
| 1229 | #define PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 |
| 1230 | |
| 1231 | |
| 1232 | /**************************************************************************** |
| 1233 | * PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER |
| 1234 | ***************************************************************************/ |
| 1235 | /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ |
| 1236 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 |
| 1237 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_ALIGN 0 |
| 1238 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_BITS 8 |
| 1239 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 |
| 1240 | |
| 1241 | /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ |
| 1242 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 |
| 1243 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_ALIGN 0 |
| 1244 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_BITS 8 |
| 1245 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 |
| 1246 | |
| 1247 | /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ |
| 1248 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 |
| 1249 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 |
| 1250 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 |
| 1251 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 |
| 1252 | |
| 1253 | /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ |
| 1254 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff |
| 1255 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 |
| 1256 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 |
| 1257 | #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 |
| 1258 | |
| 1259 | |
| 1260 | /**************************************************************************** |
| 1261 | * PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES |
| 1262 | ***************************************************************************/ |
| 1263 | /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ |
| 1264 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 |
| 1265 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_ALIGN 0 |
| 1266 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_BITS 4 |
| 1267 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 |
| 1268 | |
| 1269 | /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ |
| 1270 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 |
| 1271 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_ALIGN 0 |
| 1272 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_BITS 4 |
| 1273 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 |
| 1274 | |
| 1275 | /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ |
| 1276 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 |
| 1277 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_ALIGN 0 |
| 1278 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_BITS 8 |
| 1279 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 |
| 1280 | |
| 1281 | /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ |
| 1282 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 |
| 1283 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_ALIGN 0 |
| 1284 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_BITS 8 |
| 1285 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 |
| 1286 | |
| 1287 | /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ |
| 1288 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff |
| 1289 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_ALIGN 0 |
| 1290 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_BITS 8 |
| 1291 | #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 |
| 1292 | |
| 1293 | |
| 1294 | /**************************************************************************** |
| 1295 | * PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL |
| 1296 | ***************************************************************************/ |
| 1297 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ |
| 1298 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 |
| 1299 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_ALIGN 0 |
| 1300 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_BITS 8 |
| 1301 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 |
| 1302 | |
| 1303 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ |
| 1304 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 |
| 1305 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_ALIGN 0 |
| 1306 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_BITS 8 |
| 1307 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 |
| 1308 | |
| 1309 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ |
| 1310 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 |
| 1311 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_ALIGN 0 |
| 1312 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_BITS 1 |
| 1313 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 |
| 1314 | |
| 1315 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ |
| 1316 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 |
| 1317 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_ALIGN 0 |
| 1318 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_BITS 1 |
| 1319 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 |
| 1320 | |
| 1321 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ |
| 1322 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 |
| 1323 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_ALIGN 0 |
| 1324 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_BITS 1 |
| 1325 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 |
| 1326 | |
| 1327 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ |
| 1328 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 |
| 1329 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_ALIGN 0 |
| 1330 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_BITS 1 |
| 1331 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 |
| 1332 | |
| 1333 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ |
| 1334 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 |
| 1335 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_ALIGN 0 |
| 1336 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_BITS 1 |
| 1337 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 |
| 1338 | |
| 1339 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ |
| 1340 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 |
| 1341 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_ALIGN 0 |
| 1342 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_BITS 1 |
| 1343 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 |
| 1344 | |
| 1345 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ |
| 1346 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 |
| 1347 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_ALIGN 0 |
| 1348 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_BITS 1 |
| 1349 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 |
| 1350 | |
| 1351 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ |
| 1352 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 |
| 1353 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_ALIGN 0 |
| 1354 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_BITS 1 |
| 1355 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 |
| 1356 | |
| 1357 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ |
| 1358 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 |
| 1359 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_ALIGN 0 |
| 1360 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_BITS 1 |
| 1361 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 |
| 1362 | |
| 1363 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ |
| 1364 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 |
| 1365 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_ALIGN 0 |
| 1366 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_BITS 1 |
| 1367 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 |
| 1368 | |
| 1369 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ |
| 1370 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 |
| 1371 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 |
| 1372 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_BITS 1 |
| 1373 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 |
| 1374 | |
| 1375 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ |
| 1376 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 |
| 1377 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 |
| 1378 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_BITS 1 |
| 1379 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 |
| 1380 | |
| 1381 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ |
| 1382 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 |
| 1383 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_ALIGN 0 |
| 1384 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_BITS 1 |
| 1385 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 |
| 1386 | |
| 1387 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ |
| 1388 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 |
| 1389 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_ALIGN 0 |
| 1390 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_BITS 1 |
| 1391 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 |
| 1392 | |
| 1393 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ |
| 1394 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 |
| 1395 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_ALIGN 0 |
| 1396 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_BITS 1 |
| 1397 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 |
| 1398 | |
| 1399 | /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ |
| 1400 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 |
| 1401 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_ALIGN 0 |
| 1402 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_BITS 1 |
| 1403 | #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 |
| 1404 | |
| 1405 | |
| 1406 | /**************************************************************************** |
| 1407 | * PCIE_CFG :: SPARE |
| 1408 | ***************************************************************************/ |
| 1409 | /* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ |
| 1410 | #define PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 |
| 1411 | #define PCIE_CFG_SPARE_UNUSED_0_ALIGN 0 |
| 1412 | #define PCIE_CFG_SPARE_UNUSED_0_BITS 16 |
| 1413 | #define PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 |
| 1414 | |
| 1415 | /* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ |
| 1416 | #define PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 |
| 1417 | #define PCIE_CFG_SPARE_RESERVED_0_ALIGN 0 |
| 1418 | #define PCIE_CFG_SPARE_RESERVED_0_BITS 1 |
| 1419 | #define PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 |
| 1420 | |
| 1421 | /* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ |
| 1422 | #define PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc |
| 1423 | #define PCIE_CFG_SPARE_UNUSED_1_ALIGN 0 |
| 1424 | #define PCIE_CFG_SPARE_UNUSED_1_BITS 13 |
| 1425 | #define PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 |
| 1426 | |
| 1427 | /* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ |
| 1428 | #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 |
| 1429 | #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_ALIGN 0 |
| 1430 | #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_BITS 1 |
| 1431 | #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 |
| 1432 | |
| 1433 | /* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ |
| 1434 | #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 |
| 1435 | #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_ALIGN 0 |
| 1436 | #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_BITS 1 |
| 1437 | #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 |
| 1438 | |
| 1439 | |
| 1440 | /**************************************************************************** |
| 1441 | * PCIE_CFG :: PCI_STATE |
| 1442 | ***************************************************************************/ |
| 1443 | /* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ |
| 1444 | #define PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 |
| 1445 | #define PCIE_CFG_PCI_STATE_RESERVED_0_ALIGN 0 |
| 1446 | #define PCIE_CFG_PCI_STATE_RESERVED_0_BITS 16 |
| 1447 | #define PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 |
| 1448 | |
| 1449 | /* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ |
| 1450 | #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 |
| 1451 | #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_ALIGN 0 |
| 1452 | #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_BITS 1 |
| 1453 | #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 |
| 1454 | |
| 1455 | /* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ |
| 1456 | #define PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 |
| 1457 | #define PCIE_CFG_PCI_STATE_RESERVED_1_ALIGN 0 |
| 1458 | #define PCIE_CFG_PCI_STATE_RESERVED_1_BITS 3 |
| 1459 | #define PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 |
| 1460 | |
| 1461 | /* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ |
| 1462 | #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 |
| 1463 | #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_ALIGN 0 |
| 1464 | #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_BITS 3 |
| 1465 | #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 |
| 1466 | |
| 1467 | /* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ |
| 1468 | #define PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 |
| 1469 | #define PCIE_CFG_PCI_STATE_FLAT_VIEW_ALIGN 0 |
| 1470 | #define PCIE_CFG_PCI_STATE_FLAT_VIEW_BITS 1 |
| 1471 | #define PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 |
| 1472 | |
| 1473 | /* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ |
| 1474 | #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 |
| 1475 | #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_ALIGN 0 |
| 1476 | #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_BITS 1 |
| 1477 | #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 |
| 1478 | |
| 1479 | /* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ |
| 1480 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 |
| 1481 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_ALIGN 0 |
| 1482 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_BITS 1 |
| 1483 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 |
| 1484 | |
| 1485 | /* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ |
| 1486 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 |
| 1487 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_ALIGN 0 |
| 1488 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_BITS 1 |
| 1489 | #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 |
| 1490 | |
| 1491 | /* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ |
| 1492 | #define PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f |
| 1493 | #define PCIE_CFG_PCI_STATE_RESERVED_2_ALIGN 0 |
| 1494 | #define PCIE_CFG_PCI_STATE_RESERVED_2_BITS 5 |
| 1495 | #define PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 |
| 1496 | |
| 1497 | |
| 1498 | /**************************************************************************** |
| 1499 | * PCIE_CFG :: CLOCK_CONTROL |
| 1500 | ***************************************************************************/ |
| 1501 | /* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ |
| 1502 | #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 |
| 1503 | #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_ALIGN 0 |
| 1504 | #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_BITS 1 |
| 1505 | #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 |
| 1506 | |
| 1507 | /* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ |
| 1508 | #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 |
| 1509 | #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_ALIGN 0 |
| 1510 | #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_BITS 1 |
| 1511 | #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 |
| 1512 | |
| 1513 | /* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ |
| 1514 | #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 |
| 1515 | #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_ALIGN 0 |
| 1516 | #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_BITS 1 |
| 1517 | #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 |
| 1518 | |
| 1519 | /* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ |
| 1520 | #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 |
| 1521 | #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_ALIGN 0 |
| 1522 | #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_BITS 1 |
| 1523 | #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 |
| 1524 | |
| 1525 | /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ |
| 1526 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 |
| 1527 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_ALIGN 0 |
| 1528 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_BITS 7 |
| 1529 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 |
| 1530 | |
| 1531 | /* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ |
| 1532 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 |
| 1533 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_ALIGN 0 |
| 1534 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_BITS 1 |
| 1535 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 |
| 1536 | |
| 1537 | /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ |
| 1538 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 |
| 1539 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_ALIGN 0 |
| 1540 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_BITS 7 |
| 1541 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 |
| 1542 | |
| 1543 | /* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ |
| 1544 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 |
| 1545 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_ALIGN 0 |
| 1546 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_BITS 1 |
| 1547 | #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 |
| 1548 | |
| 1549 | /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ |
| 1550 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 |
| 1551 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_ALIGN 0 |
| 1552 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_BITS 4 |
| 1553 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 |
| 1554 | |
| 1555 | /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ |
| 1556 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff |
| 1557 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_ALIGN 0 |
| 1558 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_BITS 8 |
| 1559 | #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 |
| 1560 | |
| 1561 | |
| 1562 | /**************************************************************************** |
| 1563 | * PCIE_CFG :: REGISTER_BASE |
| 1564 | ***************************************************************************/ |
| 1565 | /* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ |
| 1566 | #define PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 |
| 1567 | #define PCIE_CFG_REGISTER_BASE_RESERVED_0_ALIGN 0 |
| 1568 | #define PCIE_CFG_REGISTER_BASE_RESERVED_0_BITS 14 |
| 1569 | #define PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 |
| 1570 | |
| 1571 | /* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ |
| 1572 | #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc |
| 1573 | #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_ALIGN 0 |
| 1574 | #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_BITS 16 |
| 1575 | #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 |
| 1576 | |
| 1577 | /* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ |
| 1578 | #define PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 |
| 1579 | #define PCIE_CFG_REGISTER_BASE_RESERVED_1_ALIGN 0 |
| 1580 | #define PCIE_CFG_REGISTER_BASE_RESERVED_1_BITS 2 |
| 1581 | #define PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 |
| 1582 | |
| 1583 | |
| 1584 | /**************************************************************************** |
| 1585 | * PCIE_CFG :: MEMORY_BASE |
| 1586 | ***************************************************************************/ |
| 1587 | /* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ |
| 1588 | #define PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 |
| 1589 | #define PCIE_CFG_MEMORY_BASE_RESERVED_0_ALIGN 0 |
| 1590 | #define PCIE_CFG_MEMORY_BASE_RESERVED_0_BITS 8 |
| 1591 | #define PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 |
| 1592 | |
| 1593 | /* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ |
| 1594 | #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc |
| 1595 | #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_ALIGN 0 |
| 1596 | #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_BITS 22 |
| 1597 | #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 |
| 1598 | |
| 1599 | /* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ |
| 1600 | #define PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 |
| 1601 | #define PCIE_CFG_MEMORY_BASE_RESERVED_1_ALIGN 0 |
| 1602 | #define PCIE_CFG_MEMORY_BASE_RESERVED_1_BITS 2 |
| 1603 | #define PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 |
| 1604 | |
| 1605 | |
| 1606 | /**************************************************************************** |
| 1607 | * PCIE_CFG :: REGISTER_DATA |
| 1608 | ***************************************************************************/ |
| 1609 | /* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ |
| 1610 | #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff |
| 1611 | #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_ALIGN 0 |
| 1612 | #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_BITS 32 |
| 1613 | #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 |
| 1614 | |
| 1615 | |
| 1616 | /**************************************************************************** |
| 1617 | * PCIE_CFG :: MEMORY_DATA |
| 1618 | ***************************************************************************/ |
| 1619 | /* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ |
| 1620 | #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff |
| 1621 | #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_ALIGN 0 |
| 1622 | #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_BITS 32 |
| 1623 | #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 |
| 1624 | |
| 1625 | |
| 1626 | /**************************************************************************** |
| 1627 | * PCIE_CFG :: EXPANSION_ROM_BAR_SIZE |
| 1628 | ***************************************************************************/ |
| 1629 | /* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ |
| 1630 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 |
| 1631 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_ALIGN 0 |
| 1632 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_BITS 28 |
| 1633 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 |
| 1634 | |
| 1635 | /* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ |
| 1636 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f |
| 1637 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_ALIGN 0 |
| 1638 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_BITS 4 |
| 1639 | #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 |
| 1640 | |
| 1641 | |
| 1642 | /**************************************************************************** |
| 1643 | * PCIE_CFG :: EXPANSION_ROM_ADDRESS |
| 1644 | ***************************************************************************/ |
| 1645 | /* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ |
| 1646 | #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff |
| 1647 | #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_ALIGN 0 |
| 1648 | #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_BITS 32 |
| 1649 | #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 |
| 1650 | |
| 1651 | |
| 1652 | /**************************************************************************** |
| 1653 | * PCIE_CFG :: EXPANSION_ROM_DATA |
| 1654 | ***************************************************************************/ |
| 1655 | /* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ |
| 1656 | #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff |
| 1657 | #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_ALIGN 0 |
| 1658 | #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_BITS 32 |
| 1659 | #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 |
| 1660 | |
| 1661 | |
| 1662 | /**************************************************************************** |
| 1663 | * PCIE_CFG :: VPD_INTERFACE |
| 1664 | ***************************************************************************/ |
| 1665 | /* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ |
| 1666 | #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe |
| 1667 | #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_ALIGN 0 |
| 1668 | #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_BITS 31 |
| 1669 | #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 |
| 1670 | |
| 1671 | /* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ |
| 1672 | #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 |
| 1673 | #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_ALIGN 0 |
| 1674 | #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_BITS 1 |
| 1675 | #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 |
| 1676 | |
| 1677 | |
| 1678 | /**************************************************************************** |
| 1679 | * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER |
| 1680 | ***************************************************************************/ |
| 1681 | /* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ |
| 1682 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff |
| 1683 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 |
| 1684 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 |
| 1685 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 |
| 1686 | |
| 1687 | |
| 1688 | /**************************************************************************** |
| 1689 | * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER |
| 1690 | ***************************************************************************/ |
| 1691 | /* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ |
| 1692 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff |
| 1693 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 |
| 1694 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 |
| 1695 | #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 |
| 1696 | |
| 1697 | |
| 1698 | /**************************************************************************** |
| 1699 | * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER |
| 1700 | ***************************************************************************/ |
| 1701 | /* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ |
| 1702 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff |
| 1703 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 |
| 1704 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 |
| 1705 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 |
| 1706 | |
| 1707 | |
| 1708 | /**************************************************************************** |
| 1709 | * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER |
| 1710 | ***************************************************************************/ |
| 1711 | /* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ |
| 1712 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff |
| 1713 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 |
| 1714 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 |
| 1715 | #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 |
| 1716 | |
| 1717 | |
| 1718 | /**************************************************************************** |
| 1719 | * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER |
| 1720 | ***************************************************************************/ |
| 1721 | /* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ |
| 1722 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff |
| 1723 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 |
| 1724 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 |
| 1725 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 |
| 1726 | |
| 1727 | |
| 1728 | /**************************************************************************** |
| 1729 | * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER |
| 1730 | ***************************************************************************/ |
| 1731 | /* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ |
| 1732 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff |
| 1733 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 |
| 1734 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 |
| 1735 | #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 |
| 1736 | |
| 1737 | |
| 1738 | /**************************************************************************** |
| 1739 | * PCIE_CFG :: INT_MAILBOX_UPPER |
| 1740 | ***************************************************************************/ |
| 1741 | /* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ |
| 1742 | #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff |
| 1743 | #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 |
| 1744 | #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 |
| 1745 | #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 |
| 1746 | |
| 1747 | |
| 1748 | /**************************************************************************** |
| 1749 | * PCIE_CFG :: INT_MAILBOX_LOWER |
| 1750 | ***************************************************************************/ |
| 1751 | /* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ |
| 1752 | #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff |
| 1753 | #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 |
| 1754 | #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 |
| 1755 | #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 |
| 1756 | |
| 1757 | |
| 1758 | /**************************************************************************** |
| 1759 | * PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION |
| 1760 | ***************************************************************************/ |
| 1761 | /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ |
| 1762 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 |
| 1763 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_ALIGN 0 |
| 1764 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_BITS 4 |
| 1765 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 |
| 1766 | |
| 1767 | /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ |
| 1768 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 |
| 1769 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_ALIGN 0 |
| 1770 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_BITS 20 |
| 1771 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 |
| 1772 | |
| 1773 | /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ |
| 1774 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff |
| 1775 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_ALIGN 0 |
| 1776 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_BITS 8 |
| 1777 | #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 |
| 1778 | |
| 1779 | |
| 1780 | /**************************************************************************** |
| 1781 | * PCIE_CFG :: FUNCTION_EVENT |
| 1782 | ***************************************************************************/ |
| 1783 | /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ |
| 1784 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 |
| 1785 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_ALIGN 0 |
| 1786 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_BITS 16 |
| 1787 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 |
| 1788 | |
| 1789 | /* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ |
| 1790 | #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 |
| 1791 | #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_ALIGN 0 |
| 1792 | #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_BITS 1 |
| 1793 | #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 |
| 1794 | |
| 1795 | /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ |
| 1796 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 |
| 1797 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_ALIGN 0 |
| 1798 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_BITS 10 |
| 1799 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 |
| 1800 | |
| 1801 | /* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ |
| 1802 | #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 |
| 1803 | #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_ALIGN 0 |
| 1804 | #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_BITS 1 |
| 1805 | #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 |
| 1806 | |
| 1807 | /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ |
| 1808 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f |
| 1809 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_ALIGN 0 |
| 1810 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_BITS 4 |
| 1811 | #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 |
| 1812 | |
| 1813 | |
| 1814 | /**************************************************************************** |
| 1815 | * PCIE_CFG :: FUNCTION_EVENT_MASK |
| 1816 | ***************************************************************************/ |
| 1817 | /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ |
| 1818 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 |
| 1819 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_ALIGN 0 |
| 1820 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_BITS 16 |
| 1821 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 |
| 1822 | |
| 1823 | /* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ |
| 1824 | #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 |
| 1825 | #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_ALIGN 0 |
| 1826 | #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_BITS 1 |
| 1827 | #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 |
| 1828 | |
| 1829 | /* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ |
| 1830 | #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 |
| 1831 | #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_ALIGN 0 |
| 1832 | #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_BITS 1 |
| 1833 | #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 |
| 1834 | |
| 1835 | /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ |
| 1836 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 |
| 1837 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_ALIGN 0 |
| 1838 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_BITS 9 |
| 1839 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 |
| 1840 | |
| 1841 | /* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ |
| 1842 | #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 |
| 1843 | #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_ALIGN 0 |
| 1844 | #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_BITS 1 |
| 1845 | #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 |
| 1846 | |
| 1847 | /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ |
| 1848 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f |
| 1849 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_ALIGN 0 |
| 1850 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_BITS 4 |
| 1851 | #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 |
| 1852 | |
| 1853 | |
| 1854 | /**************************************************************************** |
| 1855 | * PCIE_CFG :: FUNCTION_PRESENT |
| 1856 | ***************************************************************************/ |
| 1857 | /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ |
| 1858 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 |
| 1859 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_ALIGN 0 |
| 1860 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_BITS 16 |
| 1861 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 |
| 1862 | |
| 1863 | /* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ |
| 1864 | #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 |
| 1865 | #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_ALIGN 0 |
| 1866 | #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_BITS 1 |
| 1867 | #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 |
| 1868 | |
| 1869 | /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ |
| 1870 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 |
| 1871 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_ALIGN 0 |
| 1872 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_BITS 10 |
| 1873 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 |
| 1874 | |
| 1875 | /* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ |
| 1876 | #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 |
| 1877 | #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_ALIGN 0 |
| 1878 | #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_BITS 1 |
| 1879 | #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 |
| 1880 | |
| 1881 | /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ |
| 1882 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f |
| 1883 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_ALIGN 0 |
| 1884 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_BITS 4 |
| 1885 | #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 |
| 1886 | |
| 1887 | |
| 1888 | /**************************************************************************** |
| 1889 | * PCIE_CFG :: PCIE_CAPABILITIES |
| 1890 | ***************************************************************************/ |
| 1891 | /* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ |
| 1892 | #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 |
| 1893 | #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_ALIGN 0 |
| 1894 | #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_BITS 2 |
| 1895 | #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 |
| 1896 | |
| 1897 | /* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ |
| 1898 | #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 |
| 1899 | #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_ALIGN 0 |
| 1900 | #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_BITS 5 |
| 1901 | #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 |
| 1902 | |
| 1903 | /* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ |
| 1904 | #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 |
| 1905 | #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_ALIGN 0 |
| 1906 | #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_BITS 1 |
| 1907 | #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 |
| 1908 | |
| 1909 | /* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ |
| 1910 | #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 |
| 1911 | #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_ALIGN 0 |
| 1912 | #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_BITS 4 |
| 1913 | #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 |
| 1914 | |
| 1915 | /* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ |
| 1916 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 |
| 1917 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_ALIGN 0 |
| 1918 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_BITS 4 |
| 1919 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 |
| 1920 | |
| 1921 | /* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ |
| 1922 | #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 |
| 1923 | #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_ALIGN 0 |
| 1924 | #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_BITS 8 |
| 1925 | #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 |
| 1926 | |
| 1927 | /* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ |
| 1928 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff |
| 1929 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_ALIGN 0 |
| 1930 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_BITS 8 |
| 1931 | #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 |
| 1932 | |
| 1933 | |
| 1934 | /**************************************************************************** |
| 1935 | * PCIE_CFG :: DEVICE_CAPABILITIES |
| 1936 | ***************************************************************************/ |
| 1937 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ |
| 1938 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 |
| 1939 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_ALIGN 0 |
| 1940 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_BITS 4 |
| 1941 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 |
| 1942 | |
| 1943 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ |
| 1944 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 |
| 1945 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_ALIGN 0 |
| 1946 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_BITS 2 |
| 1947 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 |
| 1948 | |
| 1949 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ |
| 1950 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 |
| 1951 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_ALIGN 0 |
| 1952 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_BITS 8 |
| 1953 | #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 |
| 1954 | |
| 1955 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ |
| 1956 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 |
| 1957 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_ALIGN 0 |
| 1958 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_BITS 2 |
| 1959 | #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 |
| 1960 | |
| 1961 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ |
| 1962 | #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 |
| 1963 | #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_ALIGN 0 |
| 1964 | #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_BITS 1 |
| 1965 | #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 |
| 1966 | |
| 1967 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ |
| 1968 | #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 |
| 1969 | #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_ALIGN 0 |
| 1970 | #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_BITS 1 |
| 1971 | #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 |
| 1972 | |
| 1973 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ |
| 1974 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 |
| 1975 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_ALIGN 0 |
| 1976 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_BITS 1 |
| 1977 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 |
| 1978 | |
| 1979 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ |
| 1980 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 |
| 1981 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_ALIGN 0 |
| 1982 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_BITS 1 |
| 1983 | #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 |
| 1984 | |
| 1985 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ |
| 1986 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 |
| 1987 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_ALIGN 0 |
| 1988 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_BITS 3 |
| 1989 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 |
| 1990 | |
| 1991 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ |
| 1992 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 |
| 1993 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_ALIGN 0 |
| 1994 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_BITS 3 |
| 1995 | #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 |
| 1996 | |
| 1997 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ |
| 1998 | #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 |
| 1999 | #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_ALIGN 0 |
| 2000 | #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_BITS 1 |
| 2001 | #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 |
| 2002 | |
| 2003 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ |
| 2004 | #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 |
| 2005 | #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_ALIGN 0 |
| 2006 | #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_BITS 2 |
| 2007 | #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 |
| 2008 | |
| 2009 | /* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ |
| 2010 | #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 |
| 2011 | #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_ALIGN 0 |
| 2012 | #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_BITS 3 |
| 2013 | #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 |
| 2014 | |
| 2015 | |
| 2016 | /**************************************************************************** |
| 2017 | * PCIE_CFG :: DEVICE_STATUS_CONTROL |
| 2018 | ***************************************************************************/ |
| 2019 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ |
| 2020 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 |
| 2021 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_ALIGN 0 |
| 2022 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_BITS 10 |
| 2023 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 |
| 2024 | |
| 2025 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ |
| 2026 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 |
| 2027 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_ALIGN 0 |
| 2028 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_BITS 1 |
| 2029 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 |
| 2030 | |
| 2031 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ |
| 2032 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 |
| 2033 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_ALIGN 0 |
| 2034 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_BITS 1 |
| 2035 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 |
| 2036 | |
| 2037 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ |
| 2038 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 |
| 2039 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_ALIGN 0 |
| 2040 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_BITS 1 |
| 2041 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 |
| 2042 | |
| 2043 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ |
| 2044 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 |
| 2045 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_ALIGN 0 |
| 2046 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_BITS 1 |
| 2047 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 |
| 2048 | |
| 2049 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ |
| 2050 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 |
| 2051 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_ALIGN 0 |
| 2052 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_BITS 1 |
| 2053 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 |
| 2054 | |
| 2055 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ |
| 2056 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 |
| 2057 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_ALIGN 0 |
| 2058 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_BITS 1 |
| 2059 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 |
| 2060 | |
| 2061 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ |
| 2062 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 |
| 2063 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_ALIGN 0 |
| 2064 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_BITS 1 |
| 2065 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 |
| 2066 | |
| 2067 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ |
| 2068 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 |
| 2069 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_ALIGN 0 |
| 2070 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_BITS 3 |
| 2071 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 |
| 2072 | |
| 2073 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ |
| 2074 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 |
| 2075 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_ALIGN 0 |
| 2076 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_BITS 1 |
| 2077 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 |
| 2078 | |
| 2079 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ |
| 2080 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 |
| 2081 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_ALIGN 0 |
| 2082 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_BITS 1 |
| 2083 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 |
| 2084 | |
| 2085 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ |
| 2086 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 |
| 2087 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_ALIGN 0 |
| 2088 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_BITS 1 |
| 2089 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 |
| 2090 | |
| 2091 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ |
| 2092 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 |
| 2093 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_ALIGN 0 |
| 2094 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_BITS 1 |
| 2095 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 |
| 2096 | |
| 2097 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ |
| 2098 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 |
| 2099 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_ALIGN 0 |
| 2100 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BITS 3 |
| 2101 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 |
| 2102 | |
| 2103 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ |
| 2104 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 |
| 2105 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_ALIGN 0 |
| 2106 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_BITS 1 |
| 2107 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 |
| 2108 | |
| 2109 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ |
| 2110 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 |
| 2111 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_ALIGN 0 |
| 2112 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_BITS 1 |
| 2113 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 |
| 2114 | |
| 2115 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ |
| 2116 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 |
| 2117 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 |
| 2118 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_BITS 1 |
| 2119 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 |
| 2120 | |
| 2121 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ |
| 2122 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 |
| 2123 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 |
| 2124 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_BITS 1 |
| 2125 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 |
| 2126 | |
| 2127 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ |
| 2128 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 |
| 2129 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_ALIGN 0 |
| 2130 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_BITS 1 |
| 2131 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 |
| 2132 | |
| 2133 | |
| 2134 | /**************************************************************************** |
| 2135 | * PCIE_CFG :: LINK_CAPABILITY |
| 2136 | ***************************************************************************/ |
| 2137 | /* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ |
| 2138 | #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 |
| 2139 | #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_ALIGN 0 |
| 2140 | #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_BITS 8 |
| 2141 | #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 |
| 2142 | |
| 2143 | /* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ |
| 2144 | #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 |
| 2145 | #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_ALIGN 0 |
| 2146 | #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_BITS 5 |
| 2147 | #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 |
| 2148 | |
| 2149 | /* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ |
| 2150 | #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 |
| 2151 | #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_ALIGN 0 |
| 2152 | #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_BITS 1 |
| 2153 | #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 |
| 2154 | |
| 2155 | /* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ |
| 2156 | #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 |
| 2157 | #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_ALIGN 0 |
| 2158 | #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_BITS 3 |
| 2159 | #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 |
| 2160 | |
| 2161 | /* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ |
| 2162 | #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 |
| 2163 | #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_ALIGN 0 |
| 2164 | #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_BITS 3 |
| 2165 | #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 |
| 2166 | |
| 2167 | /* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ |
| 2168 | #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 |
| 2169 | #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_ALIGN 0 |
| 2170 | #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_BITS 2 |
| 2171 | #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 |
| 2172 | |
| 2173 | /* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ |
| 2174 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 |
| 2175 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_ALIGN 0 |
| 2176 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_BITS 6 |
| 2177 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 |
| 2178 | |
| 2179 | /* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ |
| 2180 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f |
| 2181 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_ALIGN 0 |
| 2182 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_BITS 4 |
| 2183 | #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 |
| 2184 | |
| 2185 | |
| 2186 | /**************************************************************************** |
| 2187 | * PCIE_CFG :: LINK_STATUS_CONTROL |
| 2188 | ***************************************************************************/ |
| 2189 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ |
| 2190 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 |
| 2191 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_ALIGN 0 |
| 2192 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_BITS 3 |
| 2193 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 |
| 2194 | |
| 2195 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ |
| 2196 | #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 |
| 2197 | #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_ALIGN 0 |
| 2198 | #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_BITS 1 |
| 2199 | #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 |
| 2200 | |
| 2201 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ |
| 2202 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 |
| 2203 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_ALIGN 0 |
| 2204 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_BITS 2 |
| 2205 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 |
| 2206 | |
| 2207 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ |
| 2208 | #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 |
| 2209 | #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_ALIGN 0 |
| 2210 | #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_BITS 6 |
| 2211 | #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 |
| 2212 | |
| 2213 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ |
| 2214 | #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 |
| 2215 | #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_ALIGN 0 |
| 2216 | #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_BITS 4 |
| 2217 | #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 |
| 2218 | |
| 2219 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ |
| 2220 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 |
| 2221 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_ALIGN 0 |
| 2222 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_BITS 7 |
| 2223 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 |
| 2224 | |
| 2225 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ |
| 2226 | #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 |
| 2227 | #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_ALIGN 0 |
| 2228 | #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_BITS 1 |
| 2229 | #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 |
| 2230 | |
| 2231 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ |
| 2232 | #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 |
| 2233 | #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_ALIGN 0 |
| 2234 | #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_BITS 1 |
| 2235 | #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 |
| 2236 | |
| 2237 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ |
| 2238 | #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 |
| 2239 | #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_ALIGN 0 |
| 2240 | #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_BITS 1 |
| 2241 | #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 |
| 2242 | |
| 2243 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ |
| 2244 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 |
| 2245 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_ALIGN 0 |
| 2246 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_BITS 1 |
| 2247 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 |
| 2248 | |
| 2249 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ |
| 2250 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 |
| 2251 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_ALIGN 0 |
| 2252 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_BITS 1 |
| 2253 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 |
| 2254 | |
| 2255 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ |
| 2256 | #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 |
| 2257 | #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_ALIGN 0 |
| 2258 | #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_BITS 1 |
| 2259 | #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 |
| 2260 | |
| 2261 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ |
| 2262 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 |
| 2263 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_ALIGN 0 |
| 2264 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_BITS 1 |
| 2265 | #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 |
| 2266 | |
| 2267 | /* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ |
| 2268 | #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 |
| 2269 | #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_ALIGN 0 |
| 2270 | #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_BITS 2 |
| 2271 | #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 |
| 2272 | |
| 2273 | |
| 2274 | /**************************************************************************** |
| 2275 | * PCIE_CFG :: DEVICE_CAPABILITIES_2 |
| 2276 | ***************************************************************************/ |
| 2277 | /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ |
| 2278 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 |
| 2279 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_ALIGN 0 |
| 2280 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_BITS 27 |
| 2281 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 |
| 2282 | |
| 2283 | /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ |
| 2284 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 |
| 2285 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_ALIGN 0 |
| 2286 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_BITS 1 |
| 2287 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 |
| 2288 | |
| 2289 | /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ |
| 2290 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f |
| 2291 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_ALIGN 0 |
| 2292 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_BITS 4 |
| 2293 | #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 |
| 2294 | |
| 2295 | |
| 2296 | /**************************************************************************** |
| 2297 | * PCIE_CFG :: DEVICE_STATUS_CONTROL_2 |
| 2298 | ***************************************************************************/ |
| 2299 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ |
| 2300 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 |
| 2301 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 |
| 2302 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_BITS 27 |
| 2303 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 |
| 2304 | |
| 2305 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ |
| 2306 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 |
| 2307 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_ALIGN 0 |
| 2308 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_BITS 1 |
| 2309 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 |
| 2310 | |
| 2311 | /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ |
| 2312 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f |
| 2313 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_ALIGN 0 |
| 2314 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_BITS 4 |
| 2315 | #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 |
| 2316 | |
| 2317 | |
| 2318 | /**************************************************************************** |
| 2319 | * PCIE_CFG :: LINK_CAPABILITIES_2 |
| 2320 | ***************************************************************************/ |
| 2321 | /* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ |
| 2322 | #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff |
| 2323 | #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_ALIGN 0 |
| 2324 | #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_BITS 32 |
| 2325 | #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 |
| 2326 | |
| 2327 | |
| 2328 | /**************************************************************************** |
| 2329 | * PCIE_CFG :: LINK_STATUS_CONTROL_2 |
| 2330 | ***************************************************************************/ |
| 2331 | /* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ |
| 2332 | #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff |
| 2333 | #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 |
| 2334 | #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_BITS 32 |
| 2335 | #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 |
| 2336 | |
| 2337 | |
| 2338 | /**************************************************************************** |
| 2339 | * PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER |
| 2340 | ***************************************************************************/ |
| 2341 | /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ |
| 2342 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 |
| 2343 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 |
| 2344 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 |
| 2345 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 |
| 2346 | |
| 2347 | /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ |
| 2348 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 |
| 2349 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 |
| 2350 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 |
| 2351 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 |
| 2352 | |
| 2353 | /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ |
| 2354 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff |
| 2355 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 |
| 2356 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 |
| 2357 | #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 |
| 2358 | |
| 2359 | |
| 2360 | /**************************************************************************** |
| 2361 | * PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS |
| 2362 | ***************************************************************************/ |
| 2363 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ |
| 2364 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 |
| 2365 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 |
| 2366 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 11 |
| 2367 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 |
| 2368 | |
| 2369 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ |
| 2370 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 |
| 2371 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_ALIGN 0 |
| 2372 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_BITS 1 |
| 2373 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 |
| 2374 | |
| 2375 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ |
| 2376 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 |
| 2377 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_ALIGN 0 |
| 2378 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_BITS 1 |
| 2379 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 |
| 2380 | |
| 2381 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ |
| 2382 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 |
| 2383 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_ALIGN 0 |
| 2384 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_BITS 1 |
| 2385 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 |
| 2386 | |
| 2387 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ |
| 2388 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 |
| 2389 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_ALIGN 0 |
| 2390 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_BITS 1 |
| 2391 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 |
| 2392 | |
| 2393 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ |
| 2394 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 |
| 2395 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_ALIGN 0 |
| 2396 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_BITS 1 |
| 2397 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 |
| 2398 | |
| 2399 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ |
| 2400 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 |
| 2401 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_ALIGN 0 |
| 2402 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_BITS 1 |
| 2403 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 |
| 2404 | |
| 2405 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ |
| 2406 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 |
| 2407 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_ALIGN 0 |
| 2408 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_BITS 1 |
| 2409 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 |
| 2410 | |
| 2411 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ |
| 2412 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 |
| 2413 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_ALIGN 0 |
| 2414 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_BITS 1 |
| 2415 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 |
| 2416 | |
| 2417 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ |
| 2418 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 |
| 2419 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_ALIGN 0 |
| 2420 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_BITS 1 |
| 2421 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 |
| 2422 | |
| 2423 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ |
| 2424 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 |
| 2425 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 |
| 2426 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 7 |
| 2427 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 |
| 2428 | |
| 2429 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ |
| 2430 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 |
| 2431 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_ALIGN 0 |
| 2432 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_BITS 1 |
| 2433 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 |
| 2434 | |
| 2435 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ |
| 2436 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e |
| 2437 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 |
| 2438 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 3 |
| 2439 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 |
| 2440 | |
| 2441 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ |
| 2442 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 |
| 2443 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_ALIGN 0 |
| 2444 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_BITS 1 |
| 2445 | #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 |
| 2446 | |
| 2447 | |
| 2448 | /**************************************************************************** |
| 2449 | * PCIE_CFG :: UNCORRECTABLE_ERROR_MASK |
| 2450 | ***************************************************************************/ |
| 2451 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ |
| 2452 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 |
| 2453 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 |
| 2454 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_BITS 11 |
| 2455 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 |
| 2456 | |
| 2457 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ |
| 2458 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 |
| 2459 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_ALIGN 0 |
| 2460 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_BITS 1 |
| 2461 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 |
| 2462 | |
| 2463 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ |
| 2464 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 |
| 2465 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_ALIGN 0 |
| 2466 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_BITS 1 |
| 2467 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 |
| 2468 | |
| 2469 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ |
| 2470 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 |
| 2471 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_ALIGN 0 |
| 2472 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_BITS 1 |
| 2473 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 |
| 2474 | |
| 2475 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ |
| 2476 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 |
| 2477 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_ALIGN 0 |
| 2478 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_BITS 1 |
| 2479 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 |
| 2480 | |
| 2481 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ |
| 2482 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 |
| 2483 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_ALIGN 0 |
| 2484 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_BITS 1 |
| 2485 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 |
| 2486 | |
| 2487 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ |
| 2488 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 |
| 2489 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_ALIGN 0 |
| 2490 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_BITS 1 |
| 2491 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 |
| 2492 | |
| 2493 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ |
| 2494 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 |
| 2495 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_ALIGN 0 |
| 2496 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_BITS 1 |
| 2497 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 |
| 2498 | |
| 2499 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ |
| 2500 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 |
| 2501 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_ALIGN 0 |
| 2502 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_BITS 1 |
| 2503 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 |
| 2504 | |
| 2505 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ |
| 2506 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 |
| 2507 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_ALIGN 0 |
| 2508 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_BITS 1 |
| 2509 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 |
| 2510 | |
| 2511 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ |
| 2512 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 |
| 2513 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 |
| 2514 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_BITS 7 |
| 2515 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 |
| 2516 | |
| 2517 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ |
| 2518 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 |
| 2519 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_ALIGN 0 |
| 2520 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_BITS 1 |
| 2521 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 |
| 2522 | |
| 2523 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ |
| 2524 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e |
| 2525 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 |
| 2526 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_BITS 3 |
| 2527 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 |
| 2528 | |
| 2529 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ |
| 2530 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 |
| 2531 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_ALIGN 0 |
| 2532 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_BITS 1 |
| 2533 | #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 |
| 2534 | |
| 2535 | |
| 2536 | /**************************************************************************** |
| 2537 | * PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY |
| 2538 | ***************************************************************************/ |
| 2539 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ |
| 2540 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 |
| 2541 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_ALIGN 0 |
| 2542 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_BITS 11 |
| 2543 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 |
| 2544 | |
| 2545 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ |
| 2546 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 |
| 2547 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_ALIGN 0 |
| 2548 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_BITS 1 |
| 2549 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 |
| 2550 | |
| 2551 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ |
| 2552 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 |
| 2553 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_ALIGN 0 |
| 2554 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_BITS 1 |
| 2555 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 |
| 2556 | |
| 2557 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ |
| 2558 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 |
| 2559 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_ALIGN 0 |
| 2560 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_BITS 1 |
| 2561 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 |
| 2562 | |
| 2563 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ |
| 2564 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 |
| 2565 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_ALIGN 0 |
| 2566 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_BITS 1 |
| 2567 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 |
| 2568 | |
| 2569 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ |
| 2570 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 |
| 2571 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_ALIGN 0 |
| 2572 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_BITS 1 |
| 2573 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 |
| 2574 | |
| 2575 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ |
| 2576 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 |
| 2577 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_ALIGN 0 |
| 2578 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_BITS 1 |
| 2579 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 |
| 2580 | |
| 2581 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ |
| 2582 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 |
| 2583 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_ALIGN 0 |
| 2584 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_BITS 1 |
| 2585 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 |
| 2586 | |
| 2587 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ |
| 2588 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 |
| 2589 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_ALIGN 0 |
| 2590 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_BITS 1 |
| 2591 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 |
| 2592 | |
| 2593 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ |
| 2594 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 |
| 2595 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_ALIGN 0 |
| 2596 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_BITS 1 |
| 2597 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 |
| 2598 | |
| 2599 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ |
| 2600 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 |
| 2601 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_ALIGN 0 |
| 2602 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_BITS 7 |
| 2603 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 |
| 2604 | |
| 2605 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ |
| 2606 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 |
| 2607 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_ALIGN 0 |
| 2608 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_BITS 1 |
| 2609 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 |
| 2610 | |
| 2611 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ |
| 2612 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e |
| 2613 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_ALIGN 0 |
| 2614 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_BITS 3 |
| 2615 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 |
| 2616 | |
| 2617 | /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ |
| 2618 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 |
| 2619 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_ALIGN 0 |
| 2620 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_BITS 1 |
| 2621 | #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 |
| 2622 | |
| 2623 | |
| 2624 | /**************************************************************************** |
| 2625 | * PCIE_CFG :: CORRECTABLE_ERROR_STATUS |
| 2626 | ***************************************************************************/ |
| 2627 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ |
| 2628 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 |
| 2629 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 |
| 2630 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 18 |
| 2631 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 |
| 2632 | |
| 2633 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ |
| 2634 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 |
| 2635 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_ALIGN 0 |
| 2636 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_BITS 1 |
| 2637 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 |
| 2638 | |
| 2639 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ |
| 2640 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 |
| 2641 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_ALIGN 0 |
| 2642 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_BITS 1 |
| 2643 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 |
| 2644 | |
| 2645 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ |
| 2646 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 |
| 2647 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 |
| 2648 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 3 |
| 2649 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 |
| 2650 | |
| 2651 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ |
| 2652 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 |
| 2653 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_ALIGN 0 |
| 2654 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_BITS 1 |
| 2655 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 |
| 2656 | |
| 2657 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ |
| 2658 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 |
| 2659 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_ALIGN 0 |
| 2660 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_BITS 1 |
| 2661 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 |
| 2662 | |
| 2663 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ |
| 2664 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 |
| 2665 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_ALIGN 0 |
| 2666 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_BITS 1 |
| 2667 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 |
| 2668 | |
| 2669 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ |
| 2670 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e |
| 2671 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 |
| 2672 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 5 |
| 2673 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 |
| 2674 | |
| 2675 | /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ |
| 2676 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 |
| 2677 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_ALIGN 0 |
| 2678 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_BITS 1 |
| 2679 | #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 |
| 2680 | |
| 2681 | |
| 2682 | /**************************************************************************** |
| 2683 | * PCIE_CFG :: CORRECTABLE_ERROR_MASK |
| 2684 | ***************************************************************************/ |
| 2685 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ |
| 2686 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 |
| 2687 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 |
| 2688 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_BITS 18 |
| 2689 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 |
| 2690 | |
| 2691 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ |
| 2692 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 |
| 2693 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_ALIGN 0 |
| 2694 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_BITS 1 |
| 2695 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 |
| 2696 | |
| 2697 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ |
| 2698 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 |
| 2699 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_ALIGN 0 |
| 2700 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_BITS 1 |
| 2701 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 |
| 2702 | |
| 2703 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ |
| 2704 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 |
| 2705 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 |
| 2706 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_BITS 3 |
| 2707 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 |
| 2708 | |
| 2709 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ |
| 2710 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 |
| 2711 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_ALIGN 0 |
| 2712 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_BITS 1 |
| 2713 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 |
| 2714 | |
| 2715 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ |
| 2716 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 |
| 2717 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_ALIGN 0 |
| 2718 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_BITS 1 |
| 2719 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 |
| 2720 | |
| 2721 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ |
| 2722 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 |
| 2723 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_ALIGN 0 |
| 2724 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_BITS 1 |
| 2725 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 |
| 2726 | |
| 2727 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ |
| 2728 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e |
| 2729 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 |
| 2730 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_BITS 5 |
| 2731 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 |
| 2732 | |
| 2733 | /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ |
| 2734 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 |
| 2735 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_ALIGN 0 |
| 2736 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_BITS 1 |
| 2737 | #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 |
| 2738 | |
| 2739 | |
| 2740 | /**************************************************************************** |
| 2741 | * PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL |
| 2742 | ***************************************************************************/ |
| 2743 | /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ |
| 2744 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 |
| 2745 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_ALIGN 0 |
| 2746 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_BITS 23 |
| 2747 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 |
| 2748 | |
| 2749 | /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ |
| 2750 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 |
| 2751 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_ALIGN 0 |
| 2752 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_BITS 1 |
| 2753 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 |
| 2754 | |
| 2755 | /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ |
| 2756 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 |
| 2757 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_ALIGN 0 |
| 2758 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_BITS 1 |
| 2759 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 |
| 2760 | |
| 2761 | /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ |
| 2762 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 |
| 2763 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_ALIGN 0 |
| 2764 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_BITS 1 |
| 2765 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 |
| 2766 | |
| 2767 | /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ |
| 2768 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 |
| 2769 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_ALIGN 0 |
| 2770 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_BITS 1 |
| 2771 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 |
| 2772 | |
| 2773 | /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ |
| 2774 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f |
| 2775 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_ALIGN 0 |
| 2776 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_BITS 5 |
| 2777 | #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 |
| 2778 | |
| 2779 | |
| 2780 | /**************************************************************************** |
| 2781 | * PCIE_CFG :: HEADER_LOG_1 |
| 2782 | ***************************************************************************/ |
| 2783 | /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ |
| 2784 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 |
| 2785 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_ALIGN 0 |
| 2786 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_BITS 8 |
| 2787 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 |
| 2788 | |
| 2789 | /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ |
| 2790 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 |
| 2791 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_ALIGN 0 |
| 2792 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_BITS 8 |
| 2793 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 |
| 2794 | |
| 2795 | /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ |
| 2796 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 |
| 2797 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_ALIGN 0 |
| 2798 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_BITS 8 |
| 2799 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 |
| 2800 | |
| 2801 | /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ |
| 2802 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff |
| 2803 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_ALIGN 0 |
| 2804 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_BITS 8 |
| 2805 | #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 |
| 2806 | |
| 2807 | |
| 2808 | /**************************************************************************** |
| 2809 | * PCIE_CFG :: HEADER_LOG_2 |
| 2810 | ***************************************************************************/ |
| 2811 | /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ |
| 2812 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 |
| 2813 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_ALIGN 0 |
| 2814 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_BITS 8 |
| 2815 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 |
| 2816 | |
| 2817 | /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ |
| 2818 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 |
| 2819 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_ALIGN 0 |
| 2820 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_BITS 8 |
| 2821 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 |
| 2822 | |
| 2823 | /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ |
| 2824 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 |
| 2825 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_ALIGN 0 |
| 2826 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_BITS 8 |
| 2827 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 |
| 2828 | |
| 2829 | /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ |
| 2830 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff |
| 2831 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_ALIGN 0 |
| 2832 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_BITS 8 |
| 2833 | #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 |
| 2834 | |
| 2835 | |
| 2836 | /**************************************************************************** |
| 2837 | * PCIE_CFG :: HEADER_LOG_3 |
| 2838 | ***************************************************************************/ |
| 2839 | /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ |
| 2840 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 |
| 2841 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_ALIGN 0 |
| 2842 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_BITS 8 |
| 2843 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 |
| 2844 | |
| 2845 | /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ |
| 2846 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 |
| 2847 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_ALIGN 0 |
| 2848 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_BITS 8 |
| 2849 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 |
| 2850 | |
| 2851 | /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ |
| 2852 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 |
| 2853 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_ALIGN 0 |
| 2854 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_BITS 8 |
| 2855 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 |
| 2856 | |
| 2857 | /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ |
| 2858 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff |
| 2859 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_ALIGN 0 |
| 2860 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_BITS 8 |
| 2861 | #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 |
| 2862 | |
| 2863 | |
| 2864 | /**************************************************************************** |
| 2865 | * PCIE_CFG :: HEADER_LOG_4 |
| 2866 | ***************************************************************************/ |
| 2867 | /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ |
| 2868 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 |
| 2869 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_ALIGN 0 |
| 2870 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_BITS 8 |
| 2871 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 |
| 2872 | |
| 2873 | /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ |
| 2874 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 |
| 2875 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_ALIGN 0 |
| 2876 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_BITS 8 |
| 2877 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 |
| 2878 | |
| 2879 | /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ |
| 2880 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 |
| 2881 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_ALIGN 0 |
| 2882 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_BITS 8 |
| 2883 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 |
| 2884 | |
| 2885 | /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ |
| 2886 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff |
| 2887 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_ALIGN 0 |
| 2888 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_BITS 8 |
| 2889 | #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 |
| 2890 | |
| 2891 | |
| 2892 | /**************************************************************************** |
| 2893 | * PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER |
| 2894 | ***************************************************************************/ |
| 2895 | /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ |
| 2896 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 |
| 2897 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 |
| 2898 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 |
| 2899 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 |
| 2900 | |
| 2901 | /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ |
| 2902 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 |
| 2903 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 |
| 2904 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 |
| 2905 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 |
| 2906 | |
| 2907 | /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ |
| 2908 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff |
| 2909 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 |
| 2910 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 |
| 2911 | #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 |
| 2912 | |
| 2913 | |
| 2914 | /**************************************************************************** |
| 2915 | * PCIE_CFG :: PORT_VC_CAPABILITY |
| 2916 | ***************************************************************************/ |
| 2917 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ |
| 2918 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 |
| 2919 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_ALIGN 0 |
| 2920 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_BITS 20 |
| 2921 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 |
| 2922 | |
| 2923 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ |
| 2924 | #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 |
| 2925 | #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_ALIGN 0 |
| 2926 | #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_BITS 2 |
| 2927 | #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 |
| 2928 | |
| 2929 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ |
| 2930 | #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 |
| 2931 | #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_ALIGN 0 |
| 2932 | #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_BITS 2 |
| 2933 | #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 |
| 2934 | |
| 2935 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ |
| 2936 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 |
| 2937 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_ALIGN 0 |
| 2938 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_BITS 1 |
| 2939 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 |
| 2940 | |
| 2941 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ |
| 2942 | #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 |
| 2943 | #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_ALIGN 0 |
| 2944 | #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_BITS 3 |
| 2945 | #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 |
| 2946 | |
| 2947 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ |
| 2948 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 |
| 2949 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_ALIGN 0 |
| 2950 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_BITS 1 |
| 2951 | #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 |
| 2952 | |
| 2953 | /* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ |
| 2954 | #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 |
| 2955 | #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_ALIGN 0 |
| 2956 | #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_BITS 3 |
| 2957 | #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 |
| 2958 | |
| 2959 | |
| 2960 | /**************************************************************************** |
| 2961 | * PCIE_CFG :: PORT_VC_CAPABILITY_2 |
| 2962 | ***************************************************************************/ |
| 2963 | /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ |
| 2964 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 |
| 2965 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_ALIGN 0 |
| 2966 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_BITS 8 |
| 2967 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 |
| 2968 | |
| 2969 | /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ |
| 2970 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 |
| 2971 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_ALIGN 0 |
| 2972 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_BITS 16 |
| 2973 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 |
| 2974 | |
| 2975 | /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ |
| 2976 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff |
| 2977 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_ALIGN 0 |
| 2978 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_BITS 8 |
| 2979 | #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 |
| 2980 | |
| 2981 | |
| 2982 | /**************************************************************************** |
| 2983 | * PCIE_CFG :: PORT_VC_STATUS_CONTROL |
| 2984 | ***************************************************************************/ |
| 2985 | /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ |
| 2986 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 |
| 2987 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_ALIGN 0 |
| 2988 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_BITS 15 |
| 2989 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 |
| 2990 | |
| 2991 | /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ |
| 2992 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 |
| 2993 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_ALIGN 0 |
| 2994 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_BITS 1 |
| 2995 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 |
| 2996 | |
| 2997 | /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ |
| 2998 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 |
| 2999 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_ALIGN 0 |
| 3000 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_BITS 12 |
| 3001 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 |
| 3002 | |
| 3003 | /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ |
| 3004 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e |
| 3005 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_ALIGN 0 |
| 3006 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_BITS 3 |
| 3007 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 |
| 3008 | |
| 3009 | /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ |
| 3010 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 |
| 3011 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_ALIGN 0 |
| 3012 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_BITS 1 |
| 3013 | #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 |
| 3014 | |
| 3015 | |
| 3016 | /**************************************************************************** |
| 3017 | * PCIE_CFG :: VC_RESOURCE_CAPABILITY |
| 3018 | ***************************************************************************/ |
| 3019 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ |
| 3020 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 |
| 3021 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_ALIGN 0 |
| 3022 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_BITS 8 |
| 3023 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 |
| 3024 | |
| 3025 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ |
| 3026 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 |
| 3027 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_ALIGN 0 |
| 3028 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_BITS 1 |
| 3029 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 |
| 3030 | |
| 3031 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ |
| 3032 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 |
| 3033 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_ALIGN 0 |
| 3034 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_BITS 7 |
| 3035 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 |
| 3036 | |
| 3037 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ |
| 3038 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 |
| 3039 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_ALIGN 0 |
| 3040 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_BITS 1 |
| 3041 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 |
| 3042 | |
| 3043 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ |
| 3044 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 |
| 3045 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_ALIGN 0 |
| 3046 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_BITS 1 |
| 3047 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 |
| 3048 | |
| 3049 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ |
| 3050 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 |
| 3051 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_ALIGN 0 |
| 3052 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_BITS 6 |
| 3053 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 |
| 3054 | |
| 3055 | /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ |
| 3056 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff |
| 3057 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_ALIGN 0 |
| 3058 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_BITS 8 |
| 3059 | #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 |
| 3060 | |
| 3061 | |
| 3062 | /**************************************************************************** |
| 3063 | * PCIE_CFG :: VC_RESOURCE_CONTROL |
| 3064 | ***************************************************************************/ |
| 3065 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ |
| 3066 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 |
| 3067 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_ALIGN 0 |
| 3068 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_BITS 1 |
| 3069 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 |
| 3070 | |
| 3071 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ |
| 3072 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 |
| 3073 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_ALIGN 0 |
| 3074 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_BITS 4 |
| 3075 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 |
| 3076 | |
| 3077 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ |
| 3078 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 |
| 3079 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_ALIGN 0 |
| 3080 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_BITS 3 |
| 3081 | #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 |
| 3082 | |
| 3083 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ |
| 3084 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 |
| 3085 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_ALIGN 0 |
| 3086 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_BITS 4 |
| 3087 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 |
| 3088 | |
| 3089 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ |
| 3090 | #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 |
| 3091 | #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_ALIGN 0 |
| 3092 | #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_BITS 3 |
| 3093 | #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 |
| 3094 | |
| 3095 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ |
| 3096 | #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 |
| 3097 | #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_ALIGN 0 |
| 3098 | #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_BITS 1 |
| 3099 | #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 |
| 3100 | |
| 3101 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ |
| 3102 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 |
| 3103 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_ALIGN 0 |
| 3104 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_BITS 8 |
| 3105 | #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 |
| 3106 | |
| 3107 | /* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ |
| 3108 | #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff |
| 3109 | #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_ALIGN 0 |
| 3110 | #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_BITS 8 |
| 3111 | #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 |
| 3112 | |
| 3113 | |
| 3114 | /**************************************************************************** |
| 3115 | * PCIE_CFG :: VC_RESOURCE_STATUS |
| 3116 | ***************************************************************************/ |
| 3117 | /* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ |
| 3118 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 |
| 3119 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_ALIGN 0 |
| 3120 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_BITS 14 |
| 3121 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 |
| 3122 | |
| 3123 | /* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ |
| 3124 | #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 |
| 3125 | #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_ALIGN 0 |
| 3126 | #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_BITS 1 |
| 3127 | #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 |
| 3128 | |
| 3129 | /* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ |
| 3130 | #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 |
| 3131 | #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_ALIGN 0 |
| 3132 | #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_BITS 1 |
| 3133 | #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 |
| 3134 | |
| 3135 | /* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ |
| 3136 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff |
| 3137 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_ALIGN 0 |
| 3138 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_BITS 16 |
| 3139 | #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 |
| 3140 | |
| 3141 | |
| 3142 | /**************************************************************************** |
| 3143 | * PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER |
| 3144 | ***************************************************************************/ |
| 3145 | /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ |
| 3146 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 |
| 3147 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 |
| 3148 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 |
| 3149 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 |
| 3150 | |
| 3151 | /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ |
| 3152 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 |
| 3153 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 |
| 3154 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 |
| 3155 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 |
| 3156 | |
| 3157 | /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ |
| 3158 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff |
| 3159 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 |
| 3160 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 |
| 3161 | #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 |
| 3162 | |
| 3163 | |
| 3164 | /**************************************************************************** |
| 3165 | * PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW |
| 3166 | ***************************************************************************/ |
| 3167 | /* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ |
| 3168 | #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff |
| 3169 | #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_ALIGN 0 |
| 3170 | #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_BITS 32 |
| 3171 | #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 |
| 3172 | |
| 3173 | |
| 3174 | /**************************************************************************** |
| 3175 | * PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW |
| 3176 | ***************************************************************************/ |
| 3177 | /* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ |
| 3178 | #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff |
| 3179 | #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_ALIGN 0 |
| 3180 | #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_BITS 32 |
| 3181 | #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 |
| 3182 | |
| 3183 | |
| 3184 | /**************************************************************************** |
| 3185 | * PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER |
| 3186 | ***************************************************************************/ |
| 3187 | /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ |
| 3188 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 |
| 3189 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 |
| 3190 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 |
| 3191 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 |
| 3192 | |
| 3193 | /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ |
| 3194 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 |
| 3195 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 |
| 3196 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 |
| 3197 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 |
| 3198 | |
| 3199 | /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ |
| 3200 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff |
| 3201 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 |
| 3202 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 |
| 3203 | #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 |
| 3204 | |
| 3205 | |
| 3206 | /**************************************************************************** |
| 3207 | * PCIE_CFG :: POWER_BUDGETING_DATA_SELECT |
| 3208 | ***************************************************************************/ |
| 3209 | /* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ |
| 3210 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 |
| 3211 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_ALIGN 0 |
| 3212 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_BITS 24 |
| 3213 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 |
| 3214 | |
| 3215 | /* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ |
| 3216 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff |
| 3217 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_ALIGN 0 |
| 3218 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_BITS 8 |
| 3219 | #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 |
| 3220 | |
| 3221 | |
| 3222 | /**************************************************************************** |
| 3223 | * PCIE_CFG :: POWER_BUDGETING_DATA |
| 3224 | ***************************************************************************/ |
| 3225 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ |
| 3226 | #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 |
| 3227 | #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_ALIGN 0 |
| 3228 | #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_BITS 11 |
| 3229 | #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 |
| 3230 | |
| 3231 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ |
| 3232 | #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 |
| 3233 | #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_ALIGN 0 |
| 3234 | #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_BITS 3 |
| 3235 | #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 |
| 3236 | |
| 3237 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ |
| 3238 | #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 |
| 3239 | #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_ALIGN 0 |
| 3240 | #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_BITS 3 |
| 3241 | #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 |
| 3242 | |
| 3243 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ |
| 3244 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 |
| 3245 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_ALIGN 0 |
| 3246 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_BITS 2 |
| 3247 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 |
| 3248 | |
| 3249 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ |
| 3250 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 |
| 3251 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_ALIGN 0 |
| 3252 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_BITS 3 |
| 3253 | #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 |
| 3254 | |
| 3255 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ |
| 3256 | #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 |
| 3257 | #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_ALIGN 0 |
| 3258 | #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_BITS 2 |
| 3259 | #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 |
| 3260 | |
| 3261 | /* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ |
| 3262 | #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff |
| 3263 | #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_ALIGN 0 |
| 3264 | #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_BITS 8 |
| 3265 | #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 |
| 3266 | |
| 3267 | |
| 3268 | /**************************************************************************** |
| 3269 | * PCIE_CFG :: POWER_BUDGETING_CAPABILITY |
| 3270 | ***************************************************************************/ |
| 3271 | /* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ |
| 3272 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe |
| 3273 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_ALIGN 0 |
| 3274 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_BITS 31 |
| 3275 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 |
| 3276 | |
| 3277 | /* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ |
| 3278 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 |
| 3279 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_ALIGN 0 |
| 3280 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_BITS 1 |
| 3281 | #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 |
| 3282 | |
| 3283 | |
| 3284 | /**************************************************************************** |
| 3285 | * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 |
| 3286 | ***************************************************************************/ |
| 3287 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ |
| 3288 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 |
| 3289 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_ALIGN 0 |
| 3290 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_BITS 3 |
| 3291 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 |
| 3292 | |
| 3293 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ |
| 3294 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 |
| 3295 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_ALIGN 0 |
| 3296 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_BITS 3 |
| 3297 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 |
| 3298 | |
| 3299 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ |
| 3300 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 |
| 3301 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_ALIGN 0 |
| 3302 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_BITS 2 |
| 3303 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 |
| 3304 | |
| 3305 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ |
| 3306 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 |
| 3307 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_ALIGN 0 |
| 3308 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_BITS 8 |
| 3309 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 |
| 3310 | |
| 3311 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ |
| 3312 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 |
| 3313 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_ALIGN 0 |
| 3314 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_BITS 3 |
| 3315 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 |
| 3316 | |
| 3317 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ |
| 3318 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 |
| 3319 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_ALIGN 0 |
| 3320 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_BITS 3 |
| 3321 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 |
| 3322 | |
| 3323 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ |
| 3324 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 |
| 3325 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_ALIGN 0 |
| 3326 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_BITS 2 |
| 3327 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 |
| 3328 | |
| 3329 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ |
| 3330 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff |
| 3331 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_ALIGN 0 |
| 3332 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_BITS 8 |
| 3333 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 |
| 3334 | |
| 3335 | |
| 3336 | /**************************************************************************** |
| 3337 | * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 |
| 3338 | ***************************************************************************/ |
| 3339 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ |
| 3340 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 |
| 3341 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_ALIGN 0 |
| 3342 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_BITS 3 |
| 3343 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 |
| 3344 | |
| 3345 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ |
| 3346 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 |
| 3347 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_ALIGN 0 |
| 3348 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_BITS 3 |
| 3349 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 |
| 3350 | |
| 3351 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ |
| 3352 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 |
| 3353 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_ALIGN 0 |
| 3354 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_BITS 2 |
| 3355 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 |
| 3356 | |
| 3357 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ |
| 3358 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 |
| 3359 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_ALIGN 0 |
| 3360 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_BITS 8 |
| 3361 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 |
| 3362 | |
| 3363 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ |
| 3364 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 |
| 3365 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_ALIGN 0 |
| 3366 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_BITS 3 |
| 3367 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 |
| 3368 | |
| 3369 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ |
| 3370 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 |
| 3371 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_ALIGN 0 |
| 3372 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_BITS 3 |
| 3373 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 |
| 3374 | |
| 3375 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ |
| 3376 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 |
| 3377 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_ALIGN 0 |
| 3378 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_BITS 2 |
| 3379 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 |
| 3380 | |
| 3381 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ |
| 3382 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff |
| 3383 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_ALIGN 0 |
| 3384 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_BITS 8 |
| 3385 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 |
| 3386 | |
| 3387 | |
| 3388 | /**************************************************************************** |
| 3389 | * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 |
| 3390 | ***************************************************************************/ |
| 3391 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ |
| 3392 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 |
| 3393 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_ALIGN 0 |
| 3394 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_BITS 3 |
| 3395 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 |
| 3396 | |
| 3397 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ |
| 3398 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 |
| 3399 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_ALIGN 0 |
| 3400 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_BITS 3 |
| 3401 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 |
| 3402 | |
| 3403 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ |
| 3404 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 |
| 3405 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_ALIGN 0 |
| 3406 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_BITS 2 |
| 3407 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 |
| 3408 | |
| 3409 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ |
| 3410 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 |
| 3411 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_ALIGN 0 |
| 3412 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_BITS 8 |
| 3413 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 |
| 3414 | |
| 3415 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ |
| 3416 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 |
| 3417 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_ALIGN 0 |
| 3418 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_BITS 3 |
| 3419 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 |
| 3420 | |
| 3421 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ |
| 3422 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 |
| 3423 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_ALIGN 0 |
| 3424 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_BITS 3 |
| 3425 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 |
| 3426 | |
| 3427 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ |
| 3428 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 |
| 3429 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_ALIGN 0 |
| 3430 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_BITS 2 |
| 3431 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 |
| 3432 | |
| 3433 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ |
| 3434 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff |
| 3435 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_ALIGN 0 |
| 3436 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_BITS 8 |
| 3437 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 |
| 3438 | |
| 3439 | |
| 3440 | /**************************************************************************** |
| 3441 | * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 |
| 3442 | ***************************************************************************/ |
| 3443 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ |
| 3444 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 |
| 3445 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_ALIGN 0 |
| 3446 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_BITS 3 |
| 3447 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 |
| 3448 | |
| 3449 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ |
| 3450 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 |
| 3451 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_ALIGN 0 |
| 3452 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_BITS 3 |
| 3453 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 |
| 3454 | |
| 3455 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ |
| 3456 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 |
| 3457 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_ALIGN 0 |
| 3458 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_BITS 2 |
| 3459 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 |
| 3460 | |
| 3461 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ |
| 3462 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 |
| 3463 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_ALIGN 0 |
| 3464 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_BITS 8 |
| 3465 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 |
| 3466 | |
| 3467 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ |
| 3468 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 |
| 3469 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_ALIGN 0 |
| 3470 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_BITS 3 |
| 3471 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 |
| 3472 | |
| 3473 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ |
| 3474 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 |
| 3475 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_ALIGN 0 |
| 3476 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_BITS 3 |
| 3477 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 |
| 3478 | |
| 3479 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ |
| 3480 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 |
| 3481 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_ALIGN 0 |
| 3482 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_BITS 2 |
| 3483 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 |
| 3484 | |
| 3485 | /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ |
| 3486 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff |
| 3487 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_ALIGN 0 |
| 3488 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_BITS 8 |
| 3489 | #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 |
| 3490 | |
| 3491 | |
| 3492 | /**************************************************************************** |
| 3493 | * PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING |
| 3494 | ***************************************************************************/ |
| 3495 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ |
| 3496 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 |
| 3497 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_ALIGN 0 |
| 3498 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_BITS 25 |
| 3499 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 |
| 3500 | |
| 3501 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ |
| 3502 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 |
| 3503 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_ALIGN 0 |
| 3504 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_BITS 1 |
| 3505 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 |
| 3506 | |
| 3507 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ |
| 3508 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 |
| 3509 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_ALIGN 0 |
| 3510 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_BITS 1 |
| 3511 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 |
| 3512 | |
| 3513 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ |
| 3514 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 |
| 3515 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 |
| 3516 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_BITS 1 |
| 3517 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 |
| 3518 | |
| 3519 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ |
| 3520 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 |
| 3521 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 |
| 3522 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_BITS 1 |
| 3523 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 |
| 3524 | |
| 3525 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ |
| 3526 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 |
| 3527 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 |
| 3528 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_BITS 1 |
| 3529 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 |
| 3530 | |
| 3531 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ |
| 3532 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 |
| 3533 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 |
| 3534 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 |
| 3535 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 |
| 3536 | |
| 3537 | /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ |
| 3538 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 |
| 3539 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 |
| 3540 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 |
| 3541 | #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 |
| 3542 | |
| 3543 | |
| 3544 | /**************************************************************************** |
| 3545 | * BCM70012_TGT_TOP_PCIE_TL |
| 3546 | ***************************************************************************/ |
| 3547 | /**************************************************************************** |
| 3548 | * PCIE_TL :: TL_CONTROL |
| 3549 | ***************************************************************************/ |
| 3550 | /* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ |
| 3551 | #define PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 |
| 3552 | #define PCIE_TL_TL_CONTROL_RESERVED_0_ALIGN 0 |
| 3553 | #define PCIE_TL_TL_CONTROL_RESERVED_0_BITS 1 |
| 3554 | #define PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 |
| 3555 | |
| 3556 | /* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ |
| 3557 | #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 |
| 3558 | #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_ALIGN 0 |
| 3559 | #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_BITS 1 |
| 3560 | #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 |
| 3561 | |
| 3562 | /* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ |
| 3563 | #define PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 |
| 3564 | #define PCIE_TL_TL_CONTROL_RESERVED_1_ALIGN 0 |
| 3565 | #define PCIE_TL_TL_CONTROL_RESERVED_1_BITS 1 |
| 3566 | #define PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 |
| 3567 | |
| 3568 | /* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ |
| 3569 | #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 |
| 3570 | #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_ALIGN 0 |
| 3571 | #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_BITS 1 |
| 3572 | #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 |
| 3573 | |
| 3574 | /* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ |
| 3575 | #define PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 |
| 3576 | #define PCIE_TL_TL_CONTROL_RESERVED_2_ALIGN 0 |
| 3577 | #define PCIE_TL_TL_CONTROL_RESERVED_2_BITS 1 |
| 3578 | #define PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 |
| 3579 | |
| 3580 | /* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ |
| 3581 | #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 |
| 3582 | #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_ALIGN 0 |
| 3583 | #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_BITS 1 |
| 3584 | #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 |
| 3585 | |
| 3586 | /* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ |
| 3587 | #define PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 |
| 3588 | #define PCIE_TL_TL_CONTROL_RESERVED_3_ALIGN 0 |
| 3589 | #define PCIE_TL_TL_CONTROL_RESERVED_3_BITS 1 |
| 3590 | #define PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 |
| 3591 | |
| 3592 | /* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ |
| 3593 | #define PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 |
| 3594 | #define PCIE_TL_TL_CONTROL_RESERVED_4_ALIGN 0 |
| 3595 | #define PCIE_TL_TL_CONTROL_RESERVED_4_BITS 1 |
| 3596 | #define PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 |
| 3597 | |
| 3598 | /* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ |
| 3599 | #define PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 |
| 3600 | #define PCIE_TL_TL_CONTROL_RESERVED_5_ALIGN 0 |
| 3601 | #define PCIE_TL_TL_CONTROL_RESERVED_5_BITS 1 |
| 3602 | #define PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 |
| 3603 | |
| 3604 | /* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ |
| 3605 | #define PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 |
| 3606 | #define PCIE_TL_TL_CONTROL_CRC_SWAP_ALIGN 0 |
| 3607 | #define PCIE_TL_TL_CONTROL_CRC_SWAP_BITS 1 |
| 3608 | #define PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 |
| 3609 | |
| 3610 | /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ |
| 3611 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 |
| 3612 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_ALIGN 0 |
| 3613 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_BITS 1 |
| 3614 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 |
| 3615 | |
| 3616 | /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ |
| 3617 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 |
| 3618 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_ALIGN 0 |
| 3619 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_BITS 1 |
| 3620 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 |
| 3621 | |
| 3622 | /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ |
| 3623 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 |
| 3624 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_ALIGN 0 |
| 3625 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_BITS 1 |
| 3626 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 |
| 3627 | |
| 3628 | /* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ |
| 3629 | #define PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 |
| 3630 | #define PCIE_TL_TL_CONTROL_RESERVED_6_ALIGN 0 |
| 3631 | #define PCIE_TL_TL_CONTROL_RESERVED_6_BITS 1 |
| 3632 | #define PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 |
| 3633 | |
| 3634 | /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ |
| 3635 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 |
| 3636 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_ALIGN 0 |
| 3637 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_BITS 1 |
| 3638 | #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 |
| 3639 | |
| 3640 | /* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ |
| 3641 | #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 |
| 3642 | #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_ALIGN 0 |
| 3643 | #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_BITS 1 |
| 3644 | #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 |
| 3645 | |
| 3646 | /* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ |
| 3647 | #define PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 |
| 3648 | #define PCIE_TL_TL_CONTROL_NOT_USED_ALIGN 0 |
| 3649 | #define PCIE_TL_TL_CONTROL_NOT_USED_BITS 2 |
| 3650 | #define PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 |
| 3651 | |
| 3652 | /* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ |
| 3653 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 |
| 3654 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_ALIGN 0 |
| 3655 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_BITS 3 |
| 3656 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 |
| 3657 | |
| 3658 | /* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ |
| 3659 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 |
| 3660 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_ALIGN 0 |
| 3661 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_BITS 3 |
| 3662 | #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 |
| 3663 | |
| 3664 | /* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ |
| 3665 | #define PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 |
| 3666 | #define PCIE_TL_TL_CONTROL_NOT_USED_0_ALIGN 0 |
| 3667 | #define PCIE_TL_TL_CONTROL_NOT_USED_0_BITS 2 |
| 3668 | #define PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 |
| 3669 | |
| 3670 | /* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ |
| 3671 | #define PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f |
| 3672 | #define PCIE_TL_TL_CONTROL_NOT_USED_1_ALIGN 0 |
| 3673 | #define PCIE_TL_TL_CONTROL_NOT_USED_1_BITS 6 |
| 3674 | #define PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 |
| 3675 | |
| 3676 | |
| 3677 | /**************************************************************************** |
| 3678 | * PCIE_TL :: TRANSACTION_CONFIGURATION |
| 3679 | ***************************************************************************/ |
| 3680 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ |
| 3681 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 |
| 3682 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_ALIGN 0 |
| 3683 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_BITS 1 |
| 3684 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 |
| 3685 | |
| 3686 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ |
| 3687 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 |
| 3688 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_ALIGN 0 |
| 3689 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_BITS 1 |
| 3690 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 |
| 3691 | |
| 3692 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ |
| 3693 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 |
| 3694 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_ALIGN 0 |
| 3695 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_BITS 1 |
| 3696 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 |
| 3697 | |
| 3698 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ |
| 3699 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 |
| 3700 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_ALIGN 0 |
| 3701 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_BITS 1 |
| 3702 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 |
| 3703 | |
| 3704 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ |
| 3705 | #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 |
| 3706 | #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_ALIGN 0 |
| 3707 | #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_BITS 1 |
| 3708 | #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 |
| 3709 | |
| 3710 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ |
| 3711 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 |
| 3712 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_ALIGN 0 |
| 3713 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_BITS 1 |
| 3714 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 |
| 3715 | |
| 3716 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ |
| 3717 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 |
| 3718 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_ALIGN 0 |
| 3719 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_BITS 1 |
| 3720 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 |
| 3721 | |
| 3722 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ |
| 3723 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 |
| 3724 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_ALIGN 0 |
| 3725 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_BITS 1 |
| 3726 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 |
| 3727 | |
| 3728 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ |
| 3729 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 |
| 3730 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_ALIGN 0 |
| 3731 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_BITS 1 |
| 3732 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 |
| 3733 | |
| 3734 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ |
| 3735 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 |
| 3736 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_ALIGN 0 |
| 3737 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_BITS 1 |
| 3738 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 |
| 3739 | |
| 3740 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ |
| 3741 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 |
| 3742 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_ALIGN 0 |
| 3743 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_BITS 1 |
| 3744 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 |
| 3745 | |
| 3746 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ |
| 3747 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 |
| 3748 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_ALIGN 0 |
| 3749 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_BITS 1 |
| 3750 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 |
| 3751 | |
| 3752 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ |
| 3753 | #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 |
| 3754 | #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_ALIGN 0 |
| 3755 | #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_BITS 1 |
| 3756 | #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 |
| 3757 | |
| 3758 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ |
| 3759 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 |
| 3760 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_ALIGN 0 |
| 3761 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_BITS 3 |
| 3762 | #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 |
| 3763 | |
| 3764 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ |
| 3765 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 |
| 3766 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_ALIGN 0 |
| 3767 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_BITS 4 |
| 3768 | #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 |
| 3769 | |
| 3770 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ |
| 3771 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 |
| 3772 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_ALIGN 0 |
| 3773 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_BITS 1 |
| 3774 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 |
| 3775 | |
| 3776 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ |
| 3777 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 |
| 3778 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_ALIGN 0 |
| 3779 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_BITS 1 |
| 3780 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 |
| 3781 | |
| 3782 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ |
| 3783 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 |
| 3784 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_ALIGN 0 |
| 3785 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_BITS 1 |
| 3786 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 |
| 3787 | |
| 3788 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:07] */ |
| 3789 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000180 |
| 3790 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_ALIGN 0 |
| 3791 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_BITS 2 |
| 3792 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 7 |
| 3793 | |
| 3794 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ |
| 3795 | #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 |
| 3796 | #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_ALIGN 0 |
| 3797 | #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_BITS 1 |
| 3798 | #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 |
| 3799 | |
| 3800 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ |
| 3801 | #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 |
| 3802 | #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_ALIGN 0 |
| 3803 | #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_BITS 1 |
| 3804 | #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 |
| 3805 | |
| 3806 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ |
| 3807 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 |
| 3808 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_ALIGN 0 |
| 3809 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_BITS 1 |
| 3810 | #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 |
| 3811 | |
| 3812 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ |
| 3813 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 |
| 3814 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_ALIGN 0 |
| 3815 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_BITS 1 |
| 3816 | #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 |
| 3817 | |
| 3818 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ |
| 3819 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 |
| 3820 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_ALIGN 0 |
| 3821 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_BITS 1 |
| 3822 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 |
| 3823 | |
| 3824 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ |
| 3825 | #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 |
| 3826 | #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_ALIGN 0 |
| 3827 | #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_BITS 1 |
| 3828 | #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 |
| 3829 | |
| 3830 | /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ |
| 3831 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 |
| 3832 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_ALIGN 0 |
| 3833 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_BITS 1 |
| 3834 | #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 |
| 3835 | |
| 3836 | |
| 3837 | /**************************************************************************** |
| 3838 | * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC |
| 3839 | ***************************************************************************/ |
| 3840 | /* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ |
| 3841 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff |
| 3842 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 3843 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_BITS 32 |
| 3844 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 |
| 3845 | |
| 3846 | |
| 3847 | /**************************************************************************** |
| 3848 | * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 |
| 3849 | ***************************************************************************/ |
| 3850 | /* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ |
| 3851 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff |
| 3852 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_ALIGN 0 |
| 3853 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_BITS 32 |
| 3854 | #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 |
| 3855 | |
| 3856 | |
| 3857 | /**************************************************************************** |
| 3858 | * PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC |
| 3859 | ***************************************************************************/ |
| 3860 | /* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ |
| 3861 | #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff |
| 3862 | #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_ALIGN 0 |
| 3863 | #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_BITS 32 |
| 3864 | #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 |
| 3865 | |
| 3866 | |
| 3867 | /**************************************************************************** |
| 3868 | * PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 |
| 3869 | ***************************************************************************/ |
| 3870 | /* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ |
| 3871 | #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff |
| 3872 | #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_ALIGN 0 |
| 3873 | #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_BITS 32 |
| 3874 | #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 |
| 3875 | |
| 3876 | |
| 3877 | /**************************************************************************** |
| 3878 | * PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC |
| 3879 | ***************************************************************************/ |
| 3880 | /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ |
| 3881 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 |
| 3882 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_ALIGN 0 |
| 3883 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_BITS 8 |
| 3884 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 |
| 3885 | |
| 3886 | /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ |
| 3887 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 |
| 3888 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_ALIGN 0 |
| 3889 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_BITS 4 |
| 3890 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 |
| 3891 | |
| 3892 | /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ |
| 3893 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 |
| 3894 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_ALIGN 0 |
| 3895 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_BITS 4 |
| 3896 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 |
| 3897 | |
| 3898 | /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ |
| 3899 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 |
| 3900 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 3901 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_BITS 5 |
| 3902 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 |
| 3903 | |
| 3904 | /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ |
| 3905 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff |
| 3906 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_ALIGN 0 |
| 3907 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_BITS 11 |
| 3908 | #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 |
| 3909 | |
| 3910 | |
| 3911 | /**************************************************************************** |
| 3912 | * PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC |
| 3913 | ***************************************************************************/ |
| 3914 | /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ |
| 3915 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 |
| 3916 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_ALIGN 0 |
| 3917 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_BITS 13 |
| 3918 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 |
| 3919 | |
| 3920 | /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ |
| 3921 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 |
| 3922 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_ALIGN 0 |
| 3923 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_BITS 3 |
| 3924 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 |
| 3925 | |
| 3926 | /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ |
| 3927 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 |
| 3928 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 3929 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_BITS 3 |
| 3930 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 |
| 3931 | |
| 3932 | /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ |
| 3933 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 |
| 3934 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_ALIGN 0 |
| 3935 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_BITS 5 |
| 3936 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 |
| 3937 | |
| 3938 | /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ |
| 3939 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 |
| 3940 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_ALIGN 0 |
| 3941 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_BITS 3 |
| 3942 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 |
| 3943 | |
| 3944 | /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ |
| 3945 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f |
| 3946 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_ALIGN 0 |
| 3947 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_BITS 5 |
| 3948 | #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 |
| 3949 | |
| 3950 | |
| 3951 | /**************************************************************************** |
| 3952 | * PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC |
| 3953 | ***************************************************************************/ |
| 3954 | /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ |
| 3955 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 |
| 3956 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_ALIGN 0 |
| 3957 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_BITS 16 |
| 3958 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 |
| 3959 | |
| 3960 | /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ |
| 3961 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 |
| 3962 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 3963 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_BITS 3 |
| 3964 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 |
| 3965 | |
| 3966 | /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ |
| 3967 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 |
| 3968 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_ALIGN 0 |
| 3969 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_BITS 2 |
| 3970 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 |
| 3971 | |
| 3972 | /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ |
| 3973 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 |
| 3974 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_ALIGN 0 |
| 3975 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_BITS 3 |
| 3976 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 |
| 3977 | |
| 3978 | /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ |
| 3979 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 |
| 3980 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_ALIGN 0 |
| 3981 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_BITS 3 |
| 3982 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 |
| 3983 | |
| 3984 | /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ |
| 3985 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f |
| 3986 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_ALIGN 0 |
| 3987 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_BITS 5 |
| 3988 | #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 |
| 3989 | |
| 3990 | |
| 3991 | /**************************************************************************** |
| 3992 | * PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC |
| 3993 | ***************************************************************************/ |
| 3994 | /* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ |
| 3995 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 |
| 3996 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_ALIGN 0 |
| 3997 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_BITS 19 |
| 3998 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 |
| 3999 | |
| 4000 | /* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ |
| 4001 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff |
| 4002 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_ALIGN 0 |
| 4003 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_BITS 13 |
| 4004 | #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 |
| 4005 | |
| 4006 | |
| 4007 | /**************************************************************************** |
| 4008 | * PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC |
| 4009 | ***************************************************************************/ |
| 4010 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ |
| 4011 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 |
| 4012 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_ALIGN 0 |
| 4013 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_BITS 1 |
| 4014 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 |
| 4015 | |
| 4016 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ |
| 4017 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 |
| 4018 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_ALIGN 0 |
| 4019 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_BITS 3 |
| 4020 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 |
| 4021 | |
| 4022 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ |
| 4023 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 |
| 4024 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_ALIGN 0 |
| 4025 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_BITS 5 |
| 4026 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 |
| 4027 | |
| 4028 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ |
| 4029 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 |
| 4030 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 4031 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_BITS 16 |
| 4032 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 |
| 4033 | |
| 4034 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ |
| 4035 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 |
| 4036 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_ALIGN 0 |
| 4037 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_BITS 1 |
| 4038 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 |
| 4039 | |
| 4040 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ |
| 4041 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 |
| 4042 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_ALIGN 0 |
| 4043 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_BITS 1 |
| 4044 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 |
| 4045 | |
| 4046 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ |
| 4047 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 |
| 4048 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_ALIGN 0 |
| 4049 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_BITS 1 |
| 4050 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 |
| 4051 | |
| 4052 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ |
| 4053 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 |
| 4054 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_ALIGN 0 |
| 4055 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_BITS 1 |
| 4056 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 |
| 4057 | |
| 4058 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ |
| 4059 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 |
| 4060 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_ALIGN 0 |
| 4061 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_BITS 1 |
| 4062 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 |
| 4063 | |
| 4064 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ |
| 4065 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 |
| 4066 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_ALIGN 0 |
| 4067 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_BITS 1 |
| 4068 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 |
| 4069 | |
| 4070 | /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ |
| 4071 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 |
| 4072 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_ALIGN 0 |
| 4073 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_BITS 1 |
| 4074 | #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 |
| 4075 | |
| 4076 | |
| 4077 | /**************************************************************************** |
| 4078 | * PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC |
| 4079 | ***************************************************************************/ |
| 4080 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ |
| 4081 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 |
| 4082 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_ALIGN 0 |
| 4083 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_BITS 3 |
| 4084 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 |
| 4085 | |
| 4086 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ |
| 4087 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 |
| 4088 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_ALIGN 0 |
| 4089 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_BITS 13 |
| 4090 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 |
| 4091 | |
| 4092 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ |
| 4093 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 |
| 4094 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_ALIGN 0 |
| 4095 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_BITS 1 |
| 4096 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 |
| 4097 | |
| 4098 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ |
| 4099 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 |
| 4100 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_ALIGN 0 |
| 4101 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_BITS 1 |
| 4102 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 |
| 4103 | |
| 4104 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ |
| 4105 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 |
| 4106 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_ALIGN 0 |
| 4107 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_BITS 1 |
| 4108 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 |
| 4109 | |
| 4110 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ |
| 4111 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 |
| 4112 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_ALIGN 0 |
| 4113 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_BITS 1 |
| 4114 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 |
| 4115 | |
| 4116 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ |
| 4117 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 |
| 4118 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_ALIGN 0 |
| 4119 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_BITS 1 |
| 4120 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 |
| 4121 | |
| 4122 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ |
| 4123 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 |
| 4124 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_ALIGN 0 |
| 4125 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_BITS 1 |
| 4126 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 |
| 4127 | |
| 4128 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ |
| 4129 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 |
| 4130 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_ALIGN 0 |
| 4131 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_BITS 1 |
| 4132 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 |
| 4133 | |
| 4134 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ |
| 4135 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 |
| 4136 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_ALIGN 0 |
| 4137 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_BITS 1 |
| 4138 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 |
| 4139 | |
| 4140 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ |
| 4141 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 |
| 4142 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_ALIGN 0 |
| 4143 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_BITS 4 |
| 4144 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 |
| 4145 | |
| 4146 | /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ |
| 4147 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f |
| 4148 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_ALIGN 0 |
| 4149 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_BITS 4 |
| 4150 | #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 |
| 4151 | |
| 4152 | |
| 4153 | /**************************************************************************** |
| 4154 | * PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC |
| 4155 | ***************************************************************************/ |
| 4156 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ |
| 4157 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 |
| 4158 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_ALIGN 0 |
| 4159 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_BITS 3 |
| 4160 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 |
| 4161 | |
| 4162 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ |
| 4163 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 |
| 4164 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_ALIGN 0 |
| 4165 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_BITS 13 |
| 4166 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 |
| 4167 | |
| 4168 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ |
| 4169 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff |
| 4170 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_ALIGN 0 |
| 4171 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_BITS 16 |
| 4172 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 |
| 4173 | |
| 4174 | |
| 4175 | /**************************************************************************** |
| 4176 | * PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC |
| 4177 | ***************************************************************************/ |
| 4178 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ |
| 4179 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 |
| 4180 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_ALIGN 0 |
| 4181 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_BITS 16 |
| 4182 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 |
| 4183 | |
| 4184 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ |
| 4185 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 |
| 4186 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 4187 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_BITS 1 |
| 4188 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 |
| 4189 | |
| 4190 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ |
| 4191 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 |
| 4192 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_ALIGN 0 |
| 4193 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_BITS 7 |
| 4194 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 |
| 4195 | |
| 4196 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ |
| 4197 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 |
| 4198 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_ALIGN 0 |
| 4199 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_BITS 1 |
| 4200 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 |
| 4201 | |
| 4202 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ |
| 4203 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 |
| 4204 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_ALIGN 0 |
| 4205 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_BITS 2 |
| 4206 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 |
| 4207 | |
| 4208 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ |
| 4209 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f |
| 4210 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_ALIGN 0 |
| 4211 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_BITS 5 |
| 4212 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 |
| 4213 | |
| 4214 | |
| 4215 | /**************************************************************************** |
| 4216 | * PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC |
| 4217 | ***************************************************************************/ |
| 4218 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ |
| 4219 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 |
| 4220 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_ALIGN 0 |
| 4221 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_BITS 1 |
| 4222 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 |
| 4223 | |
| 4224 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ |
| 4225 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 |
| 4226 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_ALIGN 0 |
| 4227 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_BITS 1 |
| 4228 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 |
| 4229 | |
| 4230 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ |
| 4231 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 |
| 4232 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_ALIGN 0 |
| 4233 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_BITS 1 |
| 4234 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 |
| 4235 | |
| 4236 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ |
| 4237 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 |
| 4238 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_ALIGN 0 |
| 4239 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_BITS 13 |
| 4240 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 |
| 4241 | |
| 4242 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ |
| 4243 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 |
| 4244 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_ALIGN 0 |
| 4245 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_BITS 8 |
| 4246 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 |
| 4247 | |
| 4248 | /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ |
| 4249 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff |
| 4250 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_ALIGN 0 |
| 4251 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_BITS 8 |
| 4252 | #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 |
| 4253 | |
| 4254 | |
| 4255 | /**************************************************************************** |
| 4256 | * PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO |
| 4257 | ***************************************************************************/ |
| 4258 | /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ |
| 4259 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 |
| 4260 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_ALIGN 0 |
| 4261 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_BITS 15 |
| 4262 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 |
| 4263 | |
| 4264 | /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ |
| 4265 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 |
| 4266 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_ALIGN 0 |
| 4267 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_BITS 1 |
| 4268 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 |
| 4269 | |
| 4270 | /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ |
| 4271 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 |
| 4272 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_ALIGN 0 |
| 4273 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_BITS 8 |
| 4274 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 |
| 4275 | |
| 4276 | /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ |
| 4277 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 |
| 4278 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_ALIGN 0 |
| 4279 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_BITS 5 |
| 4280 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 |
| 4281 | |
| 4282 | /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ |
| 4283 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 |
| 4284 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_ALIGN 0 |
| 4285 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_BITS 3 |
| 4286 | #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 |
| 4287 | |
| 4288 | |
| 4289 | /**************************************************************************** |
| 4290 | * PCIE_TL :: TL_DEBUG |
| 4291 | ***************************************************************************/ |
| 4292 | /* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ |
| 4293 | #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 |
| 4294 | #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_ALIGN 0 |
| 4295 | #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_BITS 1 |
| 4296 | #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 |
| 4297 | |
| 4298 | /* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ |
| 4299 | #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 |
| 4300 | #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_ALIGN 0 |
| 4301 | #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_BITS 1 |
| 4302 | #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 |
| 4303 | |
| 4304 | /* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ |
| 4305 | #define PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff |
| 4306 | #define PCIE_TL_TL_DEBUG_RESERVED_0_ALIGN 0 |
| 4307 | #define PCIE_TL_TL_DEBUG_RESERVED_0_BITS 30 |
| 4308 | #define PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 |
| 4309 | |
| 4310 | |
| 4311 | /**************************************************************************** |
| 4312 | * BCM70012_TGT_TOP_PCIE_DLL |
| 4313 | ***************************************************************************/ |
| 4314 | /**************************************************************************** |
| 4315 | * PCIE_DLL :: DATA_LINK_CONTROL |
| 4316 | ***************************************************************************/ |
| 4317 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:30] */ |
| 4318 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0xc0000000 |
| 4319 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_ALIGN 0 |
| 4320 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_BITS 2 |
| 4321 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 30 |
| 4322 | |
| 4323 | /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ |
| 4324 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 |
| 4325 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_ALIGN 0 |
| 4326 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_BITS 1 |
| 4327 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 |
| 4328 | |
| 4329 | /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ |
| 4330 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 |
| 4331 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_ALIGN 0 |
| 4332 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_BITS 1 |
| 4333 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 |
| 4334 | |
| 4335 | /* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ |
| 4336 | #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 |
| 4337 | #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_ALIGN 0 |
| 4338 | #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_BITS 1 |
| 4339 | #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 |
| 4340 | |
| 4341 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ |
| 4342 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 |
| 4343 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_ALIGN 0 |
| 4344 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_BITS 2 |
| 4345 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 |
| 4346 | |
| 4347 | /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ |
| 4348 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 |
| 4349 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_ALIGN 0 |
| 4350 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_BITS 1 |
| 4351 | #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 |
| 4352 | |
| 4353 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ |
| 4354 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 |
| 4355 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_ALIGN 0 |
| 4356 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_BITS 1 |
| 4357 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 |
| 4358 | |
| 4359 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ |
| 4360 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 |
| 4361 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_ALIGN 0 |
| 4362 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_BITS 1 |
| 4363 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 |
| 4364 | |
| 4365 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ |
| 4366 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 |
| 4367 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_ALIGN 0 |
| 4368 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_BITS 1 |
| 4369 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 |
| 4370 | |
| 4371 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ |
| 4372 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 |
| 4373 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_ALIGN 0 |
| 4374 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_BITS 1 |
| 4375 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 |
| 4376 | |
| 4377 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ |
| 4378 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 |
| 4379 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_ALIGN 0 |
| 4380 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_BITS 1 |
| 4381 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 |
| 4382 | |
| 4383 | /* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ |
| 4384 | #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 |
| 4385 | #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_ALIGN 0 |
| 4386 | #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_BITS 1 |
| 4387 | #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 |
| 4388 | |
| 4389 | /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ |
| 4390 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 |
| 4391 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_ALIGN 0 |
| 4392 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_BITS 1 |
| 4393 | #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 |
| 4394 | |
| 4395 | /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ |
| 4396 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 |
| 4397 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_ALIGN 0 |
| 4398 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_BITS 1 |
| 4399 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 |
| 4400 | |
| 4401 | /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ |
| 4402 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 |
| 4403 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_ALIGN 0 |
| 4404 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_BITS 1 |
| 4405 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 |
| 4406 | |
| 4407 | /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ |
| 4408 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 |
| 4409 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_ALIGN 0 |
| 4410 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_BITS 1 |
| 4411 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 |
| 4412 | |
| 4413 | /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ |
| 4414 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 |
| 4415 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_ALIGN 0 |
| 4416 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_BITS 1 |
| 4417 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 |
| 4418 | |
| 4419 | /* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ |
| 4420 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 |
| 4421 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_ALIGN 0 |
| 4422 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_BITS 1 |
| 4423 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 |
| 4424 | |
| 4425 | /* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ |
| 4426 | #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 |
| 4427 | #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_ALIGN 0 |
| 4428 | #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_BITS 1 |
| 4429 | #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 |
| 4430 | |
| 4431 | /* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ |
| 4432 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 |
| 4433 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_ALIGN 0 |
| 4434 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_BITS 1 |
| 4435 | #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 |
| 4436 | |
| 4437 | /* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ |
| 4438 | #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 |
| 4439 | #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_ALIGN 0 |
| 4440 | #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_BITS 1 |
| 4441 | #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 |
| 4442 | |
| 4443 | /* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ |
| 4444 | #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 |
| 4445 | #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_ALIGN 0 |
| 4446 | #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_BITS 1 |
| 4447 | #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 |
| 4448 | |
| 4449 | /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ |
| 4450 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff |
| 4451 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_ALIGN 0 |
| 4452 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_BITS 8 |
| 4453 | #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 |
| 4454 | |
| 4455 | |
| 4456 | /**************************************************************************** |
| 4457 | * PCIE_DLL :: DATA_LINK_STATUS |
| 4458 | ***************************************************************************/ |
| 4459 | /* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ |
| 4460 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 |
| 4461 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_ALIGN 0 |
| 4462 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_BITS 6 |
| 4463 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 |
| 4464 | |
| 4465 | /* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ |
| 4466 | #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 |
| 4467 | #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_ALIGN 0 |
| 4468 | #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_BITS 3 |
| 4469 | #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 |
| 4470 | |
| 4471 | /* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ |
| 4472 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 |
| 4473 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_ALIGN 0 |
| 4474 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_BITS 4 |
| 4475 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 |
| 4476 | |
| 4477 | /* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ |
| 4478 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 |
| 4479 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_ALIGN 0 |
| 4480 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_BITS 2 |
| 4481 | #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 |
| 4482 | |
| 4483 | /* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ |
| 4484 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 |
| 4485 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_ALIGN 0 |
| 4486 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_BITS 1 |
| 4487 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 |
| 4488 | |
| 4489 | /* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ |
| 4490 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 |
| 4491 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_ALIGN 0 |
| 4492 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_BITS 5 |
| 4493 | #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 |
| 4494 | |
| 4495 | /* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ |
| 4496 | #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 |
| 4497 | #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_ALIGN 0 |
| 4498 | #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_BITS 1 |
| 4499 | #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 |
| 4500 | |
| 4501 | /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ |
| 4502 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 |
| 4503 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_ALIGN 0 |
| 4504 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_BITS 1 |
| 4505 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 |
| 4506 | |
| 4507 | /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ |
| 4508 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 |
| 4509 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_ALIGN 0 |
| 4510 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_BITS 1 |
| 4511 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 |
| 4512 | |
| 4513 | /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ |
| 4514 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 |
| 4515 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_ALIGN 0 |
| 4516 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_BITS 1 |
| 4517 | #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 |
| 4518 | |
| 4519 | /* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ |
| 4520 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 |
| 4521 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_ALIGN 0 |
| 4522 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_BITS 1 |
| 4523 | #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 |
| 4524 | |
| 4525 | /* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ |
| 4526 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 |
| 4527 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_ALIGN 0 |
| 4528 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_BITS 1 |
| 4529 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 |
| 4530 | |
| 4531 | /* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ |
| 4532 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 |
| 4533 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_ALIGN 0 |
| 4534 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_BITS 1 |
| 4535 | #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 |
| 4536 | |
| 4537 | /* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ |
| 4538 | #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 |
| 4539 | #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_ALIGN 0 |
| 4540 | #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_BITS 1 |
| 4541 | #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 |
| 4542 | |
| 4543 | /* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ |
| 4544 | #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 |
| 4545 | #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_ALIGN 0 |
| 4546 | #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_BITS 1 |
| 4547 | #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 |
| 4548 | |
| 4549 | /* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ |
| 4550 | #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 |
| 4551 | #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_ALIGN 0 |
| 4552 | #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_BITS 1 |
| 4553 | #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 |
| 4554 | |
| 4555 | /* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ |
| 4556 | #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 |
| 4557 | #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_ALIGN 0 |
| 4558 | #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_BITS 1 |
| 4559 | #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 |
| 4560 | |
| 4561 | |
| 4562 | /**************************************************************************** |
| 4563 | * PCIE_DLL :: DATA_LINK_ATTENTION |
| 4564 | ***************************************************************************/ |
| 4565 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ |
| 4566 | #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 |
| 4567 | #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_ALIGN 0 |
| 4568 | #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_BITS 26 |
| 4569 | #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 |
| 4570 | |
| 4571 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ |
| 4572 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 |
| 4573 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_ALIGN 0 |
| 4574 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_BITS 1 |
| 4575 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 |
| 4576 | |
| 4577 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ |
| 4578 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 |
| 4579 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_ALIGN 0 |
| 4580 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_BITS 1 |
| 4581 | #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 |
| 4582 | |
| 4583 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ |
| 4584 | #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 |
| 4585 | #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_ALIGN 0 |
| 4586 | #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_BITS 1 |
| 4587 | #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 |
| 4588 | |
| 4589 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ |
| 4590 | #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 |
| 4591 | #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 |
| 4592 | #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 |
| 4593 | #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 |
| 4594 | |
| 4595 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ |
| 4596 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 |
| 4597 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_ALIGN 0 |
| 4598 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_BITS 1 |
| 4599 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 |
| 4600 | |
| 4601 | /* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ |
| 4602 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 |
| 4603 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 |
| 4604 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 |
| 4605 | #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 |
| 4606 | |
| 4607 | |
| 4608 | /**************************************************************************** |
| 4609 | * PCIE_DLL :: DATA_LINK_ATTENTION_MASK |
| 4610 | ***************************************************************************/ |
| 4611 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ |
| 4612 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 |
| 4613 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_ALIGN 0 |
| 4614 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_BITS 24 |
| 4615 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 |
| 4616 | |
| 4617 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ |
| 4618 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 |
| 4619 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_ALIGN 0 |
| 4620 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_BITS 2 |
| 4621 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 |
| 4622 | |
| 4623 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ |
| 4624 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 |
| 4625 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_ALIGN 0 |
| 4626 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_BITS 1 |
| 4627 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 |
| 4628 | |
| 4629 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ |
| 4630 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 |
| 4631 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_ALIGN 0 |
| 4632 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_BITS 1 |
| 4633 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 |
| 4634 | |
| 4635 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ |
| 4636 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 |
| 4637 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_ALIGN 0 |
| 4638 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_BITS 1 |
| 4639 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 |
| 4640 | |
| 4641 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ |
| 4642 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 |
| 4643 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 |
| 4644 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 |
| 4645 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 |
| 4646 | |
| 4647 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ |
| 4648 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 |
| 4649 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_ALIGN 0 |
| 4650 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_BITS 1 |
| 4651 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 |
| 4652 | |
| 4653 | /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ |
| 4654 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 |
| 4655 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 |
| 4656 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 |
| 4657 | #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 |
| 4658 | |
| 4659 | |
| 4660 | /**************************************************************************** |
| 4661 | * PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG |
| 4662 | ***************************************************************************/ |
| 4663 | /* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ |
| 4664 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 |
| 4665 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 |
| 4666 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 |
| 4667 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 |
| 4668 | |
| 4669 | /* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ |
| 4670 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff |
| 4671 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 |
| 4672 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_BITS 12 |
| 4673 | #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 |
| 4674 | |
| 4675 | |
| 4676 | /**************************************************************************** |
| 4677 | * PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG |
| 4678 | ***************************************************************************/ |
| 4679 | /* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ |
| 4680 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 |
| 4681 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 |
| 4682 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 |
| 4683 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 |
| 4684 | |
| 4685 | /* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ |
| 4686 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff |
| 4687 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 |
| 4688 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 |
| 4689 | #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 |
| 4690 | |
| 4691 | |
| 4692 | /**************************************************************************** |
| 4693 | * PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG |
| 4694 | ***************************************************************************/ |
| 4695 | /* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ |
| 4696 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 |
| 4697 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 |
| 4698 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 |
| 4699 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 |
| 4700 | |
| 4701 | /* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ |
| 4702 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff |
| 4703 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 |
| 4704 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 |
| 4705 | #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 |
| 4706 | |
| 4707 | |
| 4708 | /**************************************************************************** |
| 4709 | * PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG |
| 4710 | ***************************************************************************/ |
| 4711 | /* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ |
| 4712 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 |
| 4713 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 |
| 4714 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 |
| 4715 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 |
| 4716 | |
| 4717 | /* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ |
| 4718 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff |
| 4719 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_ALIGN 0 |
| 4720 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_BITS 12 |
| 4721 | #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 |
| 4722 | |
| 4723 | |
| 4724 | /**************************************************************************** |
| 4725 | * PCIE_DLL :: DATA_LINK_REPLAY |
| 4726 | ***************************************************************************/ |
| 4727 | /* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ |
| 4728 | #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 |
| 4729 | #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_ALIGN 0 |
| 4730 | #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_BITS 9 |
| 4731 | #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 |
| 4732 | |
| 4733 | /* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ |
| 4734 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 |
| 4735 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_ALIGN 0 |
| 4736 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_BITS 13 |
| 4737 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 |
| 4738 | |
| 4739 | /* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ |
| 4740 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff |
| 4741 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_ALIGN 0 |
| 4742 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_BITS 10 |
| 4743 | #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 |
| 4744 | |
| 4745 | |
| 4746 | /**************************************************************************** |
| 4747 | * PCIE_DLL :: DATA_LINK_ACK_TIMEOUT |
| 4748 | ***************************************************************************/ |
| 4749 | /* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ |
| 4750 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 |
| 4751 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_ALIGN 0 |
| 4752 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_BITS 21 |
| 4753 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 |
| 4754 | |
| 4755 | /* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ |
| 4756 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff |
| 4757 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_ALIGN 0 |
| 4758 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_BITS 11 |
| 4759 | #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 |
| 4760 | |
| 4761 | |
| 4762 | /**************************************************************************** |
| 4763 | * PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD |
| 4764 | ***************************************************************************/ |
| 4765 | /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ |
| 4766 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 |
| 4767 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_ALIGN 0 |
| 4768 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_BITS 8 |
| 4769 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 |
| 4770 | |
| 4771 | /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ |
| 4772 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 |
| 4773 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_ALIGN 0 |
| 4774 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_BITS 4 |
| 4775 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 |
| 4776 | |
| 4777 | /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ |
| 4778 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 |
| 4779 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_ALIGN 0 |
| 4780 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_BITS 4 |
| 4781 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 |
| 4782 | |
| 4783 | /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ |
| 4784 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 |
| 4785 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_ALIGN 0 |
| 4786 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_BITS 8 |
| 4787 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 |
| 4788 | |
| 4789 | /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ |
| 4790 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff |
| 4791 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_ALIGN 0 |
| 4792 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_BITS 8 |
| 4793 | #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 |
| 4794 | |
| 4795 | |
| 4796 | /**************************************************************************** |
| 4797 | * PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG |
| 4798 | ***************************************************************************/ |
| 4799 | /* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ |
| 4800 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 |
| 4801 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_ALIGN 0 |
| 4802 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_BITS 21 |
| 4803 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 |
| 4804 | |
| 4805 | /* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ |
| 4806 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff |
| 4807 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_ALIGN 0 |
| 4808 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_BITS 11 |
| 4809 | #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 |
| 4810 | |
| 4811 | |
| 4812 | /**************************************************************************** |
| 4813 | * PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG |
| 4814 | ***************************************************************************/ |
| 4815 | /* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ |
| 4816 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 |
| 4817 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_ALIGN 0 |
| 4818 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_BITS 21 |
| 4819 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 |
| 4820 | |
| 4821 | /* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ |
| 4822 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff |
| 4823 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_ALIGN 0 |
| 4824 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_BITS 11 |
| 4825 | #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 |
| 4826 | |
| 4827 | |
| 4828 | /**************************************************************************** |
| 4829 | * PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG |
| 4830 | ***************************************************************************/ |
| 4831 | /* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ |
| 4832 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 |
| 4833 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_ALIGN 0 |
| 4834 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_BITS 21 |
| 4835 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 |
| 4836 | |
| 4837 | /* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ |
| 4838 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff |
| 4839 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_ALIGN 0 |
| 4840 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_BITS 11 |
| 4841 | #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 |
| 4842 | |
| 4843 | |
| 4844 | /**************************************************************************** |
| 4845 | * PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT |
| 4846 | ***************************************************************************/ |
| 4847 | /* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ |
| 4848 | #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff |
| 4849 | #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_ALIGN 0 |
| 4850 | #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_BITS 32 |
| 4851 | #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 |
| 4852 | |
| 4853 | |
| 4854 | /**************************************************************************** |
| 4855 | * PCIE_DLL :: ERROR_COUNT_THRESHOLD |
| 4856 | ***************************************************************************/ |
| 4857 | /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ |
| 4858 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 |
| 4859 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_ALIGN 0 |
| 4860 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_BITS 17 |
| 4861 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 |
| 4862 | |
| 4863 | /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ |
| 4864 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 |
| 4865 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_ALIGN 0 |
| 4866 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_BITS 3 |
| 4867 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 |
| 4868 | |
| 4869 | /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ |
| 4870 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 |
| 4871 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_ALIGN 0 |
| 4872 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_BITS 4 |
| 4873 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 |
| 4874 | |
| 4875 | /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ |
| 4876 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 |
| 4877 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_ALIGN 0 |
| 4878 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_BITS 4 |
| 4879 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 |
| 4880 | |
| 4881 | /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ |
| 4882 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f |
| 4883 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_ALIGN 0 |
| 4884 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_BITS 4 |
| 4885 | #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 |
| 4886 | |
| 4887 | |
| 4888 | /**************************************************************************** |
| 4889 | * PCIE_DLL :: TL_ERROR_COUNTER |
| 4890 | ***************************************************************************/ |
| 4891 | /* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ |
| 4892 | #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 |
| 4893 | #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_ALIGN 0 |
| 4894 | #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_BITS 8 |
| 4895 | #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 |
| 4896 | |
| 4897 | /* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ |
| 4898 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 |
| 4899 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_ALIGN 0 |
| 4900 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_BITS 8 |
| 4901 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 |
| 4902 | |
| 4903 | /* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ |
| 4904 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff |
| 4905 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_ALIGN 0 |
| 4906 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_BITS 16 |
| 4907 | #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 |
| 4908 | |
| 4909 | |
| 4910 | /**************************************************************************** |
| 4911 | * PCIE_DLL :: DLLP_ERROR_COUNTER |
| 4912 | ***************************************************************************/ |
| 4913 | /* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ |
| 4914 | #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 |
| 4915 | #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_ALIGN 0 |
| 4916 | #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_BITS 16 |
| 4917 | #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 |
| 4918 | |
| 4919 | /* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ |
| 4920 | #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff |
| 4921 | #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_ALIGN 0 |
| 4922 | #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_BITS 16 |
| 4923 | #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 |
| 4924 | |
| 4925 | |
| 4926 | /**************************************************************************** |
| 4927 | * PCIE_DLL :: NAK_RECEIVED_COUNTER |
| 4928 | ***************************************************************************/ |
| 4929 | /* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ |
| 4930 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 |
| 4931 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_ALIGN 0 |
| 4932 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_BITS 16 |
| 4933 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 |
| 4934 | |
| 4935 | /* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ |
| 4936 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff |
| 4937 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_ALIGN 0 |
| 4938 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_BITS 16 |
| 4939 | #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 |
| 4940 | |
| 4941 | |
| 4942 | /**************************************************************************** |
| 4943 | * PCIE_DLL :: DATA_LINK_TEST |
| 4944 | ***************************************************************************/ |
| 4945 | /* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ |
| 4946 | #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 |
| 4947 | #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_ALIGN 0 |
| 4948 | #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_BITS 16 |
| 4949 | #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 |
| 4950 | |
| 4951 | /* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ |
| 4952 | #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 |
| 4953 | #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_ALIGN 0 |
| 4954 | #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_BITS 1 |
| 4955 | #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 |
| 4956 | |
| 4957 | /* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ |
| 4958 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 |
| 4959 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_ALIGN 0 |
| 4960 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_BITS 1 |
| 4961 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 |
| 4962 | |
| 4963 | /* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ |
| 4964 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 |
| 4965 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_ALIGN 0 |
| 4966 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_BITS 1 |
| 4967 | #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 |
| 4968 | |
| 4969 | /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ |
| 4970 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 |
| 4971 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_ALIGN 0 |
| 4972 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_BITS 1 |
| 4973 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 |
| 4974 | |
| 4975 | /* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ |
| 4976 | #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 |
| 4977 | #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_ALIGN 0 |
| 4978 | #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_BITS 1 |
| 4979 | #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 |
| 4980 | |
| 4981 | /* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ |
| 4982 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 |
| 4983 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_ALIGN 0 |
| 4984 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_BITS 1 |
| 4985 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 |
| 4986 | |
| 4987 | /* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ |
| 4988 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 |
| 4989 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_ALIGN 0 |
| 4990 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_BITS 1 |
| 4991 | #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 |
| 4992 | |
| 4993 | /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ |
| 4994 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 |
| 4995 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_ALIGN 0 |
| 4996 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_BITS 1 |
| 4997 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 |
| 4998 | |
| 4999 | /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ |
| 5000 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 |
| 5001 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_ALIGN 0 |
| 5002 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_BITS 1 |
| 5003 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 |
| 5004 | |
| 5005 | /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ |
| 5006 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 |
| 5007 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_ALIGN 0 |
| 5008 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_BITS 1 |
| 5009 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 |
| 5010 | |
| 5011 | /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ |
| 5012 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 |
| 5013 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_ALIGN 0 |
| 5014 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_BITS 1 |
| 5015 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 |
| 5016 | |
| 5017 | /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ |
| 5018 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 |
| 5019 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_ALIGN 0 |
| 5020 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_BITS 1 |
| 5021 | #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 |
| 5022 | |
| 5023 | /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ |
| 5024 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 |
| 5025 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_ALIGN 0 |
| 5026 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_BITS 1 |
| 5027 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 |
| 5028 | |
| 5029 | /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ |
| 5030 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 |
| 5031 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_ALIGN 0 |
| 5032 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_BITS 1 |
| 5033 | #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 |
| 5034 | |
| 5035 | /* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ |
| 5036 | #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 |
| 5037 | #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_ALIGN 0 |
| 5038 | #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_BITS 1 |
| 5039 | #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 |
| 5040 | |
| 5041 | /* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ |
| 5042 | #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 |
| 5043 | #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_ALIGN 0 |
| 5044 | #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_BITS 1 |
| 5045 | #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 |
| 5046 | |
| 5047 | |
| 5048 | /**************************************************************************** |
| 5049 | * PCIE_DLL :: PACKET_BIST |
| 5050 | ***************************************************************************/ |
| 5051 | /* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ |
| 5052 | #define PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 |
| 5053 | #define PCIE_DLL_PACKET_BIST_RESERVED_0_ALIGN 0 |
| 5054 | #define PCIE_DLL_PACKET_BIST_RESERVED_0_BITS 8 |
| 5055 | #define PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 |
| 5056 | |
| 5057 | /* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ |
| 5058 | #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 |
| 5059 | #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_ALIGN 0 |
| 5060 | #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_BITS 1 |
| 5061 | #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 |
| 5062 | |
| 5063 | /* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ |
| 5064 | #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 |
| 5065 | #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_ALIGN 0 |
| 5066 | #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_BITS 1 |
| 5067 | #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 |
| 5068 | |
| 5069 | /* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ |
| 5070 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 |
| 5071 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_ALIGN 0 |
| 5072 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_BITS 1 |
| 5073 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 |
| 5074 | |
| 5075 | /* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ |
| 5076 | #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 |
| 5077 | #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_ALIGN 0 |
| 5078 | #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_BITS 11 |
| 5079 | #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 |
| 5080 | |
| 5081 | /* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ |
| 5082 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 |
| 5083 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_ALIGN 0 |
| 5084 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_BITS 1 |
| 5085 | #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 |
| 5086 | |
| 5087 | /* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ |
| 5088 | #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc |
| 5089 | #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_ALIGN 0 |
| 5090 | #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_BITS 7 |
| 5091 | #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 |
| 5092 | |
| 5093 | /* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ |
| 5094 | #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 |
| 5095 | #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_ALIGN 0 |
| 5096 | #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_BITS 1 |
| 5097 | #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 |
| 5098 | |
| 5099 | /* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ |
| 5100 | #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 |
| 5101 | #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_ALIGN 0 |
| 5102 | #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_BITS 1 |
| 5103 | #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 |
| 5104 | |
| 5105 | |
| 5106 | /**************************************************************************** |
| 5107 | * PCIE_DLL :: LINK_PCIE_1_1_CONTROL |
| 5108 | ***************************************************************************/ |
| 5109 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ |
| 5110 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 |
| 5111 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_ALIGN 0 |
| 5112 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_BITS 3 |
| 5113 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 |
| 5114 | |
| 5115 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ |
| 5116 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 |
| 5117 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_ALIGN 0 |
| 5118 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_BITS 2 |
| 5119 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 |
| 5120 | |
| 5121 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ |
| 5122 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 |
| 5123 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_ALIGN 0 |
| 5124 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_BITS 17 |
| 5125 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 |
| 5126 | |
| 5127 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ |
| 5128 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 |
| 5129 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_ALIGN 0 |
| 5130 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_BITS 1 |
| 5131 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 |
| 5132 | |
| 5133 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ |
| 5134 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 |
| 5135 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_ALIGN 0 |
| 5136 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_BITS 1 |
| 5137 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 |
| 5138 | |
| 5139 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ |
| 5140 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 |
| 5141 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_ALIGN 0 |
| 5142 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_BITS 1 |
| 5143 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 |
| 5144 | |
| 5145 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ |
| 5146 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 |
| 5147 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_ALIGN 0 |
| 5148 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_BITS 1 |
| 5149 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 |
| 5150 | |
| 5151 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ |
| 5152 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 |
| 5153 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_ALIGN 0 |
| 5154 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_BITS 1 |
| 5155 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 |
| 5156 | |
| 5157 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ |
| 5158 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 |
| 5159 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_ALIGN 0 |
| 5160 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_BITS 1 |
| 5161 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 |
| 5162 | |
| 5163 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ |
| 5164 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 |
| 5165 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_ALIGN 0 |
| 5166 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_BITS 1 |
| 5167 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 |
| 5168 | |
| 5169 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ |
| 5170 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 |
| 5171 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_ALIGN 0 |
| 5172 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_BITS 1 |
| 5173 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 |
| 5174 | |
| 5175 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ |
| 5176 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 |
| 5177 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_ALIGN 0 |
| 5178 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_BITS 1 |
| 5179 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 |
| 5180 | |
| 5181 | /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ |
| 5182 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 |
| 5183 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_ALIGN 0 |
| 5184 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_BITS 1 |
| 5185 | #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 |
| 5186 | |
| 5187 | |
| 5188 | /**************************************************************************** |
| 5189 | * BCM70012_TGT_TOP_PCIE_PHY |
| 5190 | ***************************************************************************/ |
| 5191 | /**************************************************************************** |
| 5192 | * PCIE_PHY :: PHY_MODE |
| 5193 | ***************************************************************************/ |
| 5194 | /* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ |
| 5195 | #define PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 |
| 5196 | #define PCIE_PHY_PHY_MODE_RESERVED_0_ALIGN 0 |
| 5197 | #define PCIE_PHY_PHY_MODE_RESERVED_0_BITS 28 |
| 5198 | #define PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 |
| 5199 | |
| 5200 | /* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ |
| 5201 | #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 |
| 5202 | #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_ALIGN 0 |
| 5203 | #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_BITS 1 |
| 5204 | #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 |
| 5205 | |
| 5206 | /* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ |
| 5207 | #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 |
| 5208 | #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_ALIGN 0 |
| 5209 | #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_BITS 1 |
| 5210 | #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 |
| 5211 | |
| 5212 | /* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ |
| 5213 | #define PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 |
| 5214 | #define PCIE_PHY_PHY_MODE_LINK_DISABLE_ALIGN 0 |
| 5215 | #define PCIE_PHY_PHY_MODE_LINK_DISABLE_BITS 1 |
| 5216 | #define PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 |
| 5217 | |
| 5218 | /* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ |
| 5219 | #define PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 |
| 5220 | #define PCIE_PHY_PHY_MODE_SOFT_RESET_ALIGN 0 |
| 5221 | #define PCIE_PHY_PHY_MODE_SOFT_RESET_BITS 1 |
| 5222 | #define PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 |
| 5223 | |
| 5224 | |
| 5225 | /**************************************************************************** |
| 5226 | * PCIE_PHY :: PHY_LINK_STATUS |
| 5227 | ***************************************************************************/ |
| 5228 | /* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ |
| 5229 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 |
| 5230 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_ALIGN 0 |
| 5231 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_BITS 22 |
| 5232 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 |
| 5233 | |
| 5234 | /* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ |
| 5235 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 |
| 5236 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_ALIGN 0 |
| 5237 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_BITS 1 |
| 5238 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 |
| 5239 | |
| 5240 | /* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ |
| 5241 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 |
| 5242 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_ALIGN 0 |
| 5243 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_BITS 1 |
| 5244 | #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 |
| 5245 | |
| 5246 | /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ |
| 5247 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 |
| 5248 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_ALIGN 0 |
| 5249 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_BITS 1 |
| 5250 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 |
| 5251 | |
| 5252 | /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ |
| 5253 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 |
| 5254 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_ALIGN 0 |
| 5255 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_BITS 1 |
| 5256 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 |
| 5257 | |
| 5258 | /* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ |
| 5259 | #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 |
| 5260 | #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_ALIGN 0 |
| 5261 | #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_BITS 1 |
| 5262 | #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 |
| 5263 | |
| 5264 | /* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ |
| 5265 | #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 |
| 5266 | #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_ALIGN 0 |
| 5267 | #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_BITS 1 |
| 5268 | #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 |
| 5269 | |
| 5270 | /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ |
| 5271 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 |
| 5272 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_ALIGN 0 |
| 5273 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_BITS 1 |
| 5274 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 |
| 5275 | |
| 5276 | /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ |
| 5277 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 |
| 5278 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_ALIGN 0 |
| 5279 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_BITS 1 |
| 5280 | #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 |
| 5281 | |
| 5282 | /* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ |
| 5283 | #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 |
| 5284 | #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_ALIGN 0 |
| 5285 | #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_BITS 1 |
| 5286 | #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 |
| 5287 | |
| 5288 | /* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ |
| 5289 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 |
| 5290 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_ALIGN 0 |
| 5291 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_BITS 1 |
| 5292 | #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 |
| 5293 | |
| 5294 | |
| 5295 | /**************************************************************************** |
| 5296 | * PCIE_PHY :: PHY_LINK_LTSSM_CONTROL |
| 5297 | ***************************************************************************/ |
| 5298 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ |
| 5299 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 |
| 5300 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_ALIGN 0 |
| 5301 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_BITS 24 |
| 5302 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 |
| 5303 | |
| 5304 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ |
| 5305 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 |
| 5306 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_ALIGN 0 |
| 5307 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_BITS 1 |
| 5308 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 |
| 5309 | |
| 5310 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ |
| 5311 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 |
| 5312 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_ALIGN 0 |
| 5313 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_BITS 1 |
| 5314 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 |
| 5315 | |
| 5316 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ |
| 5317 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 |
| 5318 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_ALIGN 0 |
| 5319 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_BITS 1 |
| 5320 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 |
| 5321 | |
| 5322 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ |
| 5323 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 |
| 5324 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_ALIGN 0 |
| 5325 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_BITS 1 |
| 5326 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 |
| 5327 | |
| 5328 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ |
| 5329 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 |
| 5330 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_ALIGN 0 |
| 5331 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_BITS 1 |
| 5332 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 |
| 5333 | |
| 5334 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ |
| 5335 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 |
| 5336 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_ALIGN 0 |
| 5337 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_BITS 1 |
| 5338 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 |
| 5339 | |
| 5340 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ |
| 5341 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 |
| 5342 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_ALIGN 0 |
| 5343 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_BITS 1 |
| 5344 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 |
| 5345 | |
| 5346 | /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ |
| 5347 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 |
| 5348 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_ALIGN 0 |
| 5349 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_BITS 1 |
| 5350 | #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 |
| 5351 | |
| 5352 | |
| 5353 | /**************************************************************************** |
| 5354 | * PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER |
| 5355 | ***************************************************************************/ |
| 5356 | /* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ |
| 5357 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 |
| 5358 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_ALIGN 0 |
| 5359 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_BITS 24 |
| 5360 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 |
| 5361 | |
| 5362 | /* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ |
| 5363 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff |
| 5364 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_ALIGN 0 |
| 5365 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_BITS 8 |
| 5366 | #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 |
| 5367 | |
| 5368 | |
| 5369 | /**************************************************************************** |
| 5370 | * PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER |
| 5371 | ***************************************************************************/ |
| 5372 | /* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ |
| 5373 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 |
| 5374 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_ALIGN 0 |
| 5375 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_BITS 24 |
| 5376 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 |
| 5377 | |
| 5378 | /* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ |
| 5379 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff |
| 5380 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_ALIGN 0 |
| 5381 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_BITS 8 |
| 5382 | #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 |
| 5383 | |
| 5384 | |
| 5385 | /**************************************************************************** |
| 5386 | * PCIE_PHY :: PHY_LINK_TRAINING_N_FTS |
| 5387 | ***************************************************************************/ |
| 5388 | /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ |
| 5389 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 |
| 5390 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_ALIGN 0 |
| 5391 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_BITS 7 |
| 5392 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 |
| 5393 | |
| 5394 | /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ |
| 5395 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 |
| 5396 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_ALIGN 0 |
| 5397 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_BITS 1 |
| 5398 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 |
| 5399 | |
| 5400 | /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ |
| 5401 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 |
| 5402 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_ALIGN 0 |
| 5403 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_BITS 8 |
| 5404 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 |
| 5405 | |
| 5406 | /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ |
| 5407 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 |
| 5408 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_ALIGN 0 |
| 5409 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_BITS 8 |
| 5410 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 |
| 5411 | |
| 5412 | /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ |
| 5413 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff |
| 5414 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_ALIGN 0 |
| 5415 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_BITS 8 |
| 5416 | #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 |
| 5417 | |
| 5418 | |
| 5419 | /**************************************************************************** |
| 5420 | * PCIE_PHY :: PHY_ATTENTION |
| 5421 | ***************************************************************************/ |
| 5422 | /* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ |
| 5423 | #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 |
| 5424 | #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_ALIGN 0 |
| 5425 | #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_BITS 24 |
| 5426 | #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 |
| 5427 | |
| 5428 | /* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ |
| 5429 | #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 |
| 5430 | #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_ALIGN 0 |
| 5431 | #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_BITS 1 |
| 5432 | #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 |
| 5433 | |
| 5434 | /* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ |
| 5435 | #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 |
| 5436 | #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_ALIGN 0 |
| 5437 | #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_BITS 1 |
| 5438 | #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 |
| 5439 | |
| 5440 | /* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ |
| 5441 | #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 |
| 5442 | #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_ALIGN 0 |
| 5443 | #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_BITS 1 |
| 5444 | #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 |
| 5445 | |
| 5446 | /* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ |
| 5447 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 |
| 5448 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_ALIGN 0 |
| 5449 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_BITS 1 |
| 5450 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 |
| 5451 | |
| 5452 | /* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ |
| 5453 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 |
| 5454 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_ALIGN 0 |
| 5455 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_BITS 1 |
| 5456 | #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 |
| 5457 | |
| 5458 | /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ |
| 5459 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 |
| 5460 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_ALIGN 0 |
| 5461 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_BITS 1 |
| 5462 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 |
| 5463 | |
| 5464 | /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ |
| 5465 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 |
| 5466 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_ALIGN 0 |
| 5467 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_BITS 1 |
| 5468 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 |
| 5469 | |
| 5470 | /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ |
| 5471 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 |
| 5472 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_ALIGN 0 |
| 5473 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_BITS 1 |
| 5474 | #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 |
| 5475 | |
| 5476 | |
| 5477 | /**************************************************************************** |
| 5478 | * PCIE_PHY :: PHY_ATTENTION_MASK |
| 5479 | ***************************************************************************/ |
| 5480 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ |
| 5481 | #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 |
| 5482 | #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_ALIGN 0 |
| 5483 | #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_BITS 24 |
| 5484 | #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 |
| 5485 | |
| 5486 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ |
| 5487 | #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 |
| 5488 | #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_ALIGN 0 |
| 5489 | #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_BITS 1 |
| 5490 | #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 |
| 5491 | |
| 5492 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ |
| 5493 | #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 |
| 5494 | #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_ALIGN 0 |
| 5495 | #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_BITS 1 |
| 5496 | #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 |
| 5497 | |
| 5498 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ |
| 5499 | #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 |
| 5500 | #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_ALIGN 0 |
| 5501 | #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_BITS 1 |
| 5502 | #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 |
| 5503 | |
| 5504 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ |
| 5505 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 |
| 5506 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_ALIGN 0 |
| 5507 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_BITS 1 |
| 5508 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 |
| 5509 | |
| 5510 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ |
| 5511 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 |
| 5512 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_ALIGN 0 |
| 5513 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_BITS 1 |
| 5514 | #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 |
| 5515 | |
| 5516 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ |
| 5517 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 |
| 5518 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_ALIGN 0 |
| 5519 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_BITS 1 |
| 5520 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 |
| 5521 | |
| 5522 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ |
| 5523 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 |
| 5524 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_ALIGN 0 |
| 5525 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_BITS 1 |
| 5526 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 |
| 5527 | |
| 5528 | /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ |
| 5529 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 |
| 5530 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_ALIGN 0 |
| 5531 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_BITS 1 |
| 5532 | #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 |
| 5533 | |
| 5534 | |
| 5535 | /**************************************************************************** |
| 5536 | * PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER |
| 5537 | ***************************************************************************/ |
| 5538 | /* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ |
| 5539 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 |
| 5540 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_ALIGN 0 |
| 5541 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_BITS 16 |
| 5542 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 |
| 5543 | |
| 5544 | /* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ |
| 5545 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff |
| 5546 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_ALIGN 0 |
| 5547 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_BITS 16 |
| 5548 | #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 |
| 5549 | |
| 5550 | |
| 5551 | /**************************************************************************** |
| 5552 | * PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER |
| 5553 | ***************************************************************************/ |
| 5554 | /* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ |
| 5555 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 |
| 5556 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_ALIGN 0 |
| 5557 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_BITS 16 |
| 5558 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 |
| 5559 | |
| 5560 | /* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ |
| 5561 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff |
| 5562 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_ALIGN 0 |
| 5563 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_BITS 16 |
| 5564 | #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 |
| 5565 | |
| 5566 | |
| 5567 | /**************************************************************************** |
| 5568 | * PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD |
| 5569 | ***************************************************************************/ |
| 5570 | /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ |
| 5571 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 |
| 5572 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_ALIGN 0 |
| 5573 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_BITS 20 |
| 5574 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 |
| 5575 | |
| 5576 | /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ |
| 5577 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 |
| 5578 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_ALIGN 0 |
| 5579 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_BITS 4 |
| 5580 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 |
| 5581 | |
| 5582 | /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ |
| 5583 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 |
| 5584 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_ALIGN 0 |
| 5585 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_BITS 4 |
| 5586 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 |
| 5587 | |
| 5588 | /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ |
| 5589 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f |
| 5590 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_ALIGN 0 |
| 5591 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_BITS 4 |
| 5592 | #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 |
| 5593 | |
| 5594 | |
| 5595 | /**************************************************************************** |
| 5596 | * PCIE_PHY :: PHY_TEST_CONTROL |
| 5597 | ***************************************************************************/ |
| 5598 | /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ |
| 5599 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 |
| 5600 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_ALIGN 0 |
| 5601 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_BITS 1 |
| 5602 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 |
| 5603 | |
| 5604 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ |
| 5605 | #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 |
| 5606 | #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_ALIGN 0 |
| 5607 | #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_BITS 1 |
| 5608 | #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 |
| 5609 | |
| 5610 | /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ |
| 5611 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 |
| 5612 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_ALIGN 0 |
| 5613 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_BITS 1 |
| 5614 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 |
| 5615 | |
| 5616 | /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ |
| 5617 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 |
| 5618 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_ALIGN 0 |
| 5619 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_BITS 1 |
| 5620 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 |
| 5621 | |
| 5622 | /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ |
| 5623 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 |
| 5624 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_ALIGN 0 |
| 5625 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_BITS 1 |
| 5626 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 |
| 5627 | |
| 5628 | /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ |
| 5629 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 |
| 5630 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_ALIGN 0 |
| 5631 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_BITS 1 |
| 5632 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 |
| 5633 | |
| 5634 | /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ |
| 5635 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 |
| 5636 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_ALIGN 0 |
| 5637 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_BITS 3 |
| 5638 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 |
| 5639 | |
| 5640 | /* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ |
| 5641 | #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 |
| 5642 | #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_ALIGN 0 |
| 5643 | #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_BITS 1 |
| 5644 | #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 |
| 5645 | |
| 5646 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ |
| 5647 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 |
| 5648 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_ALIGN 0 |
| 5649 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_BITS 1 |
| 5650 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 |
| 5651 | |
| 5652 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ |
| 5653 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 |
| 5654 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_ALIGN 0 |
| 5655 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_BITS 1 |
| 5656 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 |
| 5657 | |
| 5658 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ |
| 5659 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 |
| 5660 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_ALIGN 0 |
| 5661 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_BITS 1 |
| 5662 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 |
| 5663 | |
| 5664 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ |
| 5665 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 |
| 5666 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_ALIGN 0 |
| 5667 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_BITS 1 |
| 5668 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 |
| 5669 | |
| 5670 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ |
| 5671 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 |
| 5672 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_ALIGN 0 |
| 5673 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_BITS 1 |
| 5674 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 |
| 5675 | |
| 5676 | /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ |
| 5677 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 |
| 5678 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_ALIGN 0 |
| 5679 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_BITS 1 |
| 5680 | #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 |
| 5681 | |
| 5682 | /* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ |
| 5683 | #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 |
| 5684 | #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_ALIGN 0 |
| 5685 | #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_BITS 8 |
| 5686 | #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 |
| 5687 | |
| 5688 | /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ |
| 5689 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 |
| 5690 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_ALIGN 0 |
| 5691 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_BITS 4 |
| 5692 | #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 |
| 5693 | |
| 5694 | /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ |
| 5695 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 |
| 5696 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_ALIGN 0 |
| 5697 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_BITS 1 |
| 5698 | #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 |
| 5699 | |
| 5700 | /* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ |
| 5701 | #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 |
| 5702 | #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_ALIGN 0 |
| 5703 | #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_BITS 1 |
| 5704 | #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 |
| 5705 | |
| 5706 | /* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ |
| 5707 | #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 |
| 5708 | #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_ALIGN 0 |
| 5709 | #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_BITS 1 |
| 5710 | #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 |
| 5711 | |
| 5712 | /* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ |
| 5713 | #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 |
| 5714 | #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_ALIGN 0 |
| 5715 | #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_BITS 1 |
| 5716 | #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 |
| 5717 | |
| 5718 | |
| 5719 | /**************************************************************************** |
| 5720 | * PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE |
| 5721 | ***************************************************************************/ |
| 5722 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ |
| 5723 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 |
| 5724 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_ALIGN 0 |
| 5725 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_BITS 14 |
| 5726 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 |
| 5727 | |
| 5728 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ |
| 5729 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 |
| 5730 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_ALIGN 0 |
| 5731 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_BITS 1 |
| 5732 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 |
| 5733 | |
| 5734 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ |
| 5735 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 |
| 5736 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_ALIGN 0 |
| 5737 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_BITS 1 |
| 5738 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 |
| 5739 | |
| 5740 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ |
| 5741 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 |
| 5742 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_ALIGN 0 |
| 5743 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_BITS 1 |
| 5744 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 |
| 5745 | |
| 5746 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ |
| 5747 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 |
| 5748 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_ALIGN 0 |
| 5749 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_BITS 1 |
| 5750 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 |
| 5751 | |
| 5752 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ |
| 5753 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 |
| 5754 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_ALIGN 0 |
| 5755 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_BITS 1 |
| 5756 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 |
| 5757 | |
| 5758 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ |
| 5759 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 |
| 5760 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_ALIGN 0 |
| 5761 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_BITS 1 |
| 5762 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 |
| 5763 | |
| 5764 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ |
| 5765 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 |
| 5766 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_ALIGN 0 |
| 5767 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_BITS 2 |
| 5768 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 |
| 5769 | |
| 5770 | /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ |
| 5771 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff |
| 5772 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_ALIGN 0 |
| 5773 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_BITS 10 |
| 5774 | #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 |
| 5775 | |
| 5776 | |
| 5777 | /**************************************************************************** |
| 5778 | * PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE |
| 5779 | ***************************************************************************/ |
| 5780 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ |
| 5781 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 |
| 5782 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_ALIGN 0 |
| 5783 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_BITS 1 |
| 5784 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 |
| 5785 | |
| 5786 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ |
| 5787 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 |
| 5788 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_ALIGN 0 |
| 5789 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_BITS 1 |
| 5790 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 |
| 5791 | |
| 5792 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ |
| 5793 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 |
| 5794 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_ALIGN 0 |
| 5795 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_BITS 1 |
| 5796 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 |
| 5797 | |
| 5798 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ |
| 5799 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 |
| 5800 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_ALIGN 0 |
| 5801 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_BITS 1 |
| 5802 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 |
| 5803 | |
| 5804 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ |
| 5805 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 |
| 5806 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_ALIGN 0 |
| 5807 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_BITS 12 |
| 5808 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 |
| 5809 | |
| 5810 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ |
| 5811 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 |
| 5812 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_ALIGN 0 |
| 5813 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_BITS 8 |
| 5814 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 |
| 5815 | |
| 5816 | /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ |
| 5817 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff |
| 5818 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_ALIGN 0 |
| 5819 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_BITS 8 |
| 5820 | #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 |
| 5821 | |
| 5822 | |
| 5823 | /**************************************************************************** |
| 5824 | * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES |
| 5825 | ***************************************************************************/ |
| 5826 | /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ |
| 5827 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 |
| 5828 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_ALIGN 0 |
| 5829 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_BITS 22 |
| 5830 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 |
| 5831 | |
| 5832 | /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ |
| 5833 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 |
| 5834 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_ALIGN 0 |
| 5835 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_BITS 6 |
| 5836 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 |
| 5837 | |
| 5838 | /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ |
| 5839 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f |
| 5840 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_ALIGN 0 |
| 5841 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_BITS 4 |
| 5842 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 |
| 5843 | |
| 5844 | |
| 5845 | /**************************************************************************** |
| 5846 | * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES |
| 5847 | ***************************************************************************/ |
| 5848 | /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ |
| 5849 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff |
| 5850 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_ALIGN 0 |
| 5851 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_BITS 32 |
| 5852 | #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 |
| 5853 | |
| 5854 | |
| 5855 | /**************************************************************************** |
| 5856 | * BCM70012_TGT_TOP_INTR |
| 5857 | ***************************************************************************/ |
| 5858 | /**************************************************************************** |
| 5859 | * INTR :: INTR_STATUS |
| 5860 | ***************************************************************************/ |
| 5861 | /* INTR :: INTR_STATUS :: reserved0 [31:26] */ |
| 5862 | #define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 |
| 5863 | #define INTR_INTR_STATUS_reserved0_ALIGN 0 |
| 5864 | #define INTR_INTR_STATUS_reserved0_BITS 6 |
| 5865 | #define INTR_INTR_STATUS_reserved0_SHIFT 26 |
| 5866 | |
| 5867 | /* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ |
| 5868 | #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 |
| 5869 | #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 |
| 5870 | #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 |
| 5871 | #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 |
| 5872 | |
| 5873 | /* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ |
| 5874 | #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 |
| 5875 | #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 |
| 5876 | #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 |
| 5877 | #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 |
| 5878 | |
| 5879 | /* INTR :: INTR_STATUS :: reserved1 [23:14] */ |
| 5880 | #define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 |
| 5881 | #define INTR_INTR_STATUS_reserved1_ALIGN 0 |
| 5882 | #define INTR_INTR_STATUS_reserved1_BITS 10 |
| 5883 | #define INTR_INTR_STATUS_reserved1_SHIFT 14 |
| 5884 | |
| 5885 | /* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ |
| 5886 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 |
| 5887 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 |
| 5888 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 |
| 5889 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 |
| 5890 | |
| 5891 | /* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ |
| 5892 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 |
| 5893 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 |
| 5894 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 |
| 5895 | #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 |
| 5896 | |
| 5897 | /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ |
| 5898 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 |
| 5899 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 |
| 5900 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 |
| 5901 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 |
| 5902 | |
| 5903 | /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ |
| 5904 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 |
| 5905 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 |
| 5906 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 |
| 5907 | #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 |
| 5908 | |
| 5909 | /* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ |
| 5910 | #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 |
| 5911 | #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 |
| 5912 | #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 |
| 5913 | #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 |
| 5914 | |
| 5915 | /* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ |
| 5916 | #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 |
| 5917 | #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 |
| 5918 | #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 |
| 5919 | #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 |
| 5920 | |
| 5921 | /* INTR :: INTR_STATUS :: reserved2 [07:06] */ |
| 5922 | #define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 |
| 5923 | #define INTR_INTR_STATUS_reserved2_ALIGN 0 |
| 5924 | #define INTR_INTR_STATUS_reserved2_BITS 2 |
| 5925 | #define INTR_INTR_STATUS_reserved2_SHIFT 6 |
| 5926 | |
| 5927 | /* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ |
| 5928 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 |
| 5929 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 |
| 5930 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 |
| 5931 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 |
| 5932 | |
| 5933 | /* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ |
| 5934 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 |
| 5935 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 |
| 5936 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 |
| 5937 | #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 |
| 5938 | |
| 5939 | /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ |
| 5940 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 |
| 5941 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 |
| 5942 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 |
| 5943 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 |
| 5944 | |
| 5945 | /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ |
| 5946 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 |
| 5947 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 |
| 5948 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 |
| 5949 | #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 |
| 5950 | |
| 5951 | /* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ |
| 5952 | #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 |
| 5953 | #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 |
| 5954 | #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 |
| 5955 | #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 |
| 5956 | |
| 5957 | /* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ |
| 5958 | #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 |
| 5959 | #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 |
| 5960 | #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 |
| 5961 | #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 |
| 5962 | |
| 5963 | |
| 5964 | /**************************************************************************** |
| 5965 | * INTR :: INTR_SET |
| 5966 | ***************************************************************************/ |
| 5967 | /* INTR :: INTR_SET :: reserved0 [31:26] */ |
| 5968 | #define INTR_INTR_SET_reserved0_MASK 0xfc000000 |
| 5969 | #define INTR_INTR_SET_reserved0_ALIGN 0 |
| 5970 | #define INTR_INTR_SET_reserved0_BITS 6 |
| 5971 | #define INTR_INTR_SET_reserved0_SHIFT 26 |
| 5972 | |
| 5973 | /* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ |
| 5974 | #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 |
| 5975 | #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_ALIGN 0 |
| 5976 | #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_BITS 1 |
| 5977 | #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 |
| 5978 | |
| 5979 | /* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ |
| 5980 | #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 |
| 5981 | #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_ALIGN 0 |
| 5982 | #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_BITS 1 |
| 5983 | #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 |
| 5984 | |
| 5985 | /* INTR :: INTR_SET :: reserved1 [23:14] */ |
| 5986 | #define INTR_INTR_SET_reserved1_MASK 0x00ffc000 |
| 5987 | #define INTR_INTR_SET_reserved1_ALIGN 0 |
| 5988 | #define INTR_INTR_SET_reserved1_BITS 10 |
| 5989 | #define INTR_INTR_SET_reserved1_SHIFT 14 |
| 5990 | |
| 5991 | /* INTR :: INTR_SET :: UV_RX_DMA_L1_ERR_INTR [13:13] */ |
| 5992 | #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_MASK 0x00002000 |
| 5993 | #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_ALIGN 0 |
| 5994 | #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_BITS 1 |
| 5995 | #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_SHIFT 13 |
| 5996 | |
| 5997 | /* INTR :: INTR_SET :: UV_RX_DMA_L1_DONE_INTR [12:12] */ |
| 5998 | #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_MASK 0x00001000 |
| 5999 | #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_ALIGN 0 |
| 6000 | #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_BITS 1 |
| 6001 | #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_SHIFT 12 |
| 6002 | |
| 6003 | /* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ |
| 6004 | #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 |
| 6005 | #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_ALIGN 0 |
| 6006 | #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_BITS 1 |
| 6007 | #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 |
| 6008 | |
| 6009 | /* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ |
| 6010 | #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 |
| 6011 | #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_ALIGN 0 |
| 6012 | #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_BITS 1 |
| 6013 | #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 |
| 6014 | |
| 6015 | /* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ |
| 6016 | #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 |
| 6017 | #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_ALIGN 0 |
| 6018 | #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_BITS 1 |
| 6019 | #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 |
| 6020 | |
| 6021 | /* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ |
| 6022 | #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 |
| 6023 | #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_ALIGN 0 |
| 6024 | #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_BITS 1 |
| 6025 | #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 |
| 6026 | |
| 6027 | /* INTR :: INTR_SET :: reserved2 [07:06] */ |
| 6028 | #define INTR_INTR_SET_reserved2_MASK 0x000000c0 |
| 6029 | #define INTR_INTR_SET_reserved2_ALIGN 0 |
| 6030 | #define INTR_INTR_SET_reserved2_BITS 2 |
| 6031 | #define INTR_INTR_SET_reserved2_SHIFT 6 |
| 6032 | |
| 6033 | /* INTR :: INTR_SET :: UV_RX_DMA_L0_ERR_INTR [05:05] */ |
| 6034 | #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_MASK 0x00000020 |
| 6035 | #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_ALIGN 0 |
| 6036 | #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_BITS 1 |
| 6037 | #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_SHIFT 5 |
| 6038 | |
| 6039 | /* INTR :: INTR_SET :: UV_RX_DMA_L0_DONE_INTR [04:04] */ |
| 6040 | #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_MASK 0x00000010 |
| 6041 | #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_ALIGN 0 |
| 6042 | #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_BITS 1 |
| 6043 | #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_SHIFT 4 |
| 6044 | |
| 6045 | /* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ |
| 6046 | #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 |
| 6047 | #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_ALIGN 0 |
| 6048 | #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_BITS 1 |
| 6049 | #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 |
| 6050 | |
| 6051 | /* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ |
| 6052 | #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 |
| 6053 | #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_ALIGN 0 |
| 6054 | #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_BITS 1 |
| 6055 | #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 |
| 6056 | |
| 6057 | /* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ |
| 6058 | #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 |
| 6059 | #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_ALIGN 0 |
| 6060 | #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_BITS 1 |
| 6061 | #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 |
| 6062 | |
| 6063 | /* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ |
| 6064 | #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 |
| 6065 | #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_ALIGN 0 |
| 6066 | #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_BITS 1 |
| 6067 | #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 |
| 6068 | |
| 6069 | |
| 6070 | /**************************************************************************** |
| 6071 | * INTR :: INTR_CLR_REG |
| 6072 | ***************************************************************************/ |
| 6073 | /* INTR :: INTR_CLR_REG :: reserved0 [31:26] */ |
| 6074 | #define INTR_INTR_CLR_REG_reserved0_MASK 0xfc000000 |
| 6075 | #define INTR_INTR_CLR_REG_reserved0_ALIGN 0 |
| 6076 | #define INTR_INTR_CLR_REG_reserved0_BITS 6 |
| 6077 | #define INTR_INTR_CLR_REG_reserved0_SHIFT 26 |
| 6078 | |
| 6079 | /* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ |
| 6080 | #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 |
| 6081 | #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 |
| 6082 | #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 |
| 6083 | #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 |
| 6084 | |
| 6085 | /* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ |
| 6086 | #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 |
| 6087 | #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 |
| 6088 | #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 |
| 6089 | #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 |
| 6090 | |
| 6091 | /* INTR :: INTR_CLR_REG :: reserved1 [23:14] */ |
| 6092 | #define INTR_INTR_CLR_REG_reserved1_MASK 0x00ffc000 |
| 6093 | #define INTR_INTR_CLR_REG_reserved1_ALIGN 0 |
| 6094 | #define INTR_INTR_CLR_REG_reserved1_BITS 10 |
| 6095 | #define INTR_INTR_CLR_REG_reserved1_SHIFT 14 |
| 6096 | |
| 6097 | /* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_CLR [13:13] */ |
| 6098 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 |
| 6099 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 |
| 6100 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_BITS 1 |
| 6101 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_SHIFT 13 |
| 6102 | |
| 6103 | /* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_CLR [12:12] */ |
| 6104 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 |
| 6105 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 |
| 6106 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_BITS 1 |
| 6107 | #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_SHIFT 12 |
| 6108 | |
| 6109 | /* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ |
| 6110 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 |
| 6111 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 |
| 6112 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_BITS 1 |
| 6113 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 |
| 6114 | |
| 6115 | /* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ |
| 6116 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 |
| 6117 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 |
| 6118 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_BITS 1 |
| 6119 | #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 |
| 6120 | |
| 6121 | /* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ |
| 6122 | #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 |
| 6123 | #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_ALIGN 0 |
| 6124 | #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_BITS 1 |
| 6125 | #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 |
| 6126 | |
| 6127 | /* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ |
| 6128 | #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 |
| 6129 | #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_ALIGN 0 |
| 6130 | #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_BITS 1 |
| 6131 | #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 |
| 6132 | |
| 6133 | /* INTR :: INTR_CLR_REG :: reserved2 [07:06] */ |
| 6134 | #define INTR_INTR_CLR_REG_reserved2_MASK 0x000000c0 |
| 6135 | #define INTR_INTR_CLR_REG_reserved2_ALIGN 0 |
| 6136 | #define INTR_INTR_CLR_REG_reserved2_BITS 2 |
| 6137 | #define INTR_INTR_CLR_REG_reserved2_SHIFT 6 |
| 6138 | |
| 6139 | /* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_CLR [05:05] */ |
| 6140 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 |
| 6141 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 |
| 6142 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_BITS 1 |
| 6143 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_SHIFT 5 |
| 6144 | |
| 6145 | /* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_CLR [04:04] */ |
| 6146 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 |
| 6147 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 |
| 6148 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_BITS 1 |
| 6149 | #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_SHIFT 4 |
| 6150 | |
| 6151 | /* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ |
| 6152 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 |
| 6153 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 |
| 6154 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_BITS 1 |
| 6155 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 |
| 6156 | |
| 6157 | /* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ |
| 6158 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 |
| 6159 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 |
| 6160 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_BITS 1 |
| 6161 | #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 |
| 6162 | |
| 6163 | /* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ |
| 6164 | #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 |
| 6165 | #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_ALIGN 0 |
| 6166 | #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_BITS 1 |
| 6167 | #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 |
| 6168 | |
| 6169 | /* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ |
| 6170 | #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 |
| 6171 | #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_ALIGN 0 |
| 6172 | #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_BITS 1 |
| 6173 | #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 |
| 6174 | |
| 6175 | |
| 6176 | /**************************************************************************** |
| 6177 | * INTR :: INTR_MSK_STS_REG |
| 6178 | ***************************************************************************/ |
| 6179 | /* INTR :: INTR_MSK_STS_REG :: reserved0 [31:26] */ |
| 6180 | #define INTR_INTR_MSK_STS_REG_reserved0_MASK 0xfc000000 |
| 6181 | #define INTR_INTR_MSK_STS_REG_reserved0_ALIGN 0 |
| 6182 | #define INTR_INTR_MSK_STS_REG_reserved0_BITS 6 |
| 6183 | #define INTR_INTR_MSK_STS_REG_reserved0_SHIFT 26 |
| 6184 | |
| 6185 | /* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ |
| 6186 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 |
| 6187 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_ALIGN 0 |
| 6188 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_BITS 1 |
| 6189 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 |
| 6190 | |
| 6191 | /* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ |
| 6192 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 |
| 6193 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_ALIGN 0 |
| 6194 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_BITS 1 |
| 6195 | #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 |
| 6196 | |
| 6197 | /* INTR :: INTR_MSK_STS_REG :: reserved1 [23:14] */ |
| 6198 | #define INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00ffc000 |
| 6199 | #define INTR_INTR_MSK_STS_REG_reserved1_ALIGN 0 |
| 6200 | #define INTR_INTR_MSK_STS_REG_reserved1_BITS 10 |
| 6201 | #define INTR_INTR_MSK_STS_REG_reserved1_SHIFT 14 |
| 6202 | |
| 6203 | /* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_ERR_INTR_MSK [13:13] */ |
| 6204 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 |
| 6205 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 |
| 6206 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_BITS 1 |
| 6207 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SHIFT 13 |
| 6208 | |
| 6209 | /* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_DONE_INTR_MSK [12:12] */ |
| 6210 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 |
| 6211 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 |
| 6212 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_BITS 1 |
| 6213 | #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SHIFT 12 |
| 6214 | |
| 6215 | /* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ |
| 6216 | #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 |
| 6217 | #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 |
| 6218 | #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_BITS 1 |
| 6219 | #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 |
| 6220 | |
| 6221 | /* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ |
| 6222 | #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 |
| 6223 | #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 |
| 6224 | #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_BITS 1 |
| 6225 | #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 |
| 6226 | |
| 6227 | /* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ |
| 6228 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 |
| 6229 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_ALIGN 0 |
| 6230 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_BITS 1 |
| 6231 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 |
| 6232 | |
| 6233 | /* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ |
| 6234 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 |
| 6235 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_ALIGN 0 |
| 6236 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_BITS 1 |
| 6237 | #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 |
| 6238 | |
| 6239 | /* INTR :: INTR_MSK_STS_REG :: reserved2 [07:06] */ |
| 6240 | #define INTR_INTR_MSK_STS_REG_reserved2_MASK 0x000000c0 |
| 6241 | #define INTR_INTR_MSK_STS_REG_reserved2_ALIGN 0 |
| 6242 | #define INTR_INTR_MSK_STS_REG_reserved2_BITS 2 |
| 6243 | #define INTR_INTR_MSK_STS_REG_reserved2_SHIFT 6 |
| 6244 | |
| 6245 | /* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_ERR_INTR_MSK [05:05] */ |
| 6246 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 |
| 6247 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 |
| 6248 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_BITS 1 |
| 6249 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SHIFT 5 |
| 6250 | |
| 6251 | /* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_DONE_INTR_MSK [04:04] */ |
| 6252 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 |
| 6253 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 |
| 6254 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_BITS 1 |
| 6255 | #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SHIFT 4 |
| 6256 | |
| 6257 | /* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ |
| 6258 | #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 |
| 6259 | #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 |
| 6260 | #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_BITS 1 |
| 6261 | #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 |
| 6262 | |
| 6263 | /* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ |
| 6264 | #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 |
| 6265 | #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 |
| 6266 | #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_BITS 1 |
| 6267 | #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 |
| 6268 | |
| 6269 | /* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ |
| 6270 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 |
| 6271 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_ALIGN 0 |
| 6272 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_BITS 1 |
| 6273 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 |
| 6274 | |
| 6275 | /* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ |
| 6276 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 |
| 6277 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_ALIGN 0 |
| 6278 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_BITS 1 |
| 6279 | #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 |
| 6280 | |
| 6281 | |
| 6282 | /**************************************************************************** |
| 6283 | * INTR :: INTR_MSK_SET_REG |
| 6284 | ***************************************************************************/ |
| 6285 | /* INTR :: INTR_MSK_SET_REG :: reserved0 [31:26] */ |
| 6286 | #define INTR_INTR_MSK_SET_REG_reserved0_MASK 0xfc000000 |
| 6287 | #define INTR_INTR_MSK_SET_REG_reserved0_ALIGN 0 |
| 6288 | #define INTR_INTR_MSK_SET_REG_reserved0_BITS 6 |
| 6289 | #define INTR_INTR_MSK_SET_REG_reserved0_SHIFT 26 |
| 6290 | |
| 6291 | /* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ |
| 6292 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 |
| 6293 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_ALIGN 0 |
| 6294 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_BITS 1 |
| 6295 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 |
| 6296 | |
| 6297 | /* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ |
| 6298 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 |
| 6299 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_ALIGN 0 |
| 6300 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_BITS 1 |
| 6301 | #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 |
| 6302 | |
| 6303 | /* INTR :: INTR_MSK_SET_REG :: reserved1 [23:14] */ |
| 6304 | #define INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00ffc000 |
| 6305 | #define INTR_INTR_MSK_SET_REG_reserved1_ALIGN 0 |
| 6306 | #define INTR_INTR_MSK_SET_REG_reserved1_BITS 10 |
| 6307 | #define INTR_INTR_MSK_SET_REG_reserved1_SHIFT 14 |
| 6308 | |
| 6309 | /* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_SET [13:13] */ |
| 6310 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 |
| 6311 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 |
| 6312 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 |
| 6313 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 |
| 6314 | |
| 6315 | /* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_SET [12:12] */ |
| 6316 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 |
| 6317 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 |
| 6318 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 |
| 6319 | #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 |
| 6320 | |
| 6321 | /* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ |
| 6322 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 |
| 6323 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 |
| 6324 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 |
| 6325 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 |
| 6326 | |
| 6327 | /* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ |
| 6328 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 |
| 6329 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 |
| 6330 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 |
| 6331 | #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 |
| 6332 | |
| 6333 | /* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ |
| 6334 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 |
| 6335 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 |
| 6336 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_BITS 1 |
| 6337 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 |
| 6338 | |
| 6339 | /* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ |
| 6340 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 |
| 6341 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 |
| 6342 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_BITS 1 |
| 6343 | #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 |
| 6344 | |
| 6345 | /* INTR :: INTR_MSK_SET_REG :: reserved2 [07:06] */ |
| 6346 | #define INTR_INTR_MSK_SET_REG_reserved2_MASK 0x000000c0 |
| 6347 | #define INTR_INTR_MSK_SET_REG_reserved2_ALIGN 0 |
| 6348 | #define INTR_INTR_MSK_SET_REG_reserved2_BITS 2 |
| 6349 | #define INTR_INTR_MSK_SET_REG_reserved2_SHIFT 6 |
| 6350 | |
| 6351 | /* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_SET [05:05] */ |
| 6352 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 |
| 6353 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 |
| 6354 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 |
| 6355 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 |
| 6356 | |
| 6357 | /* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_SET [04:04] */ |
| 6358 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 |
| 6359 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 |
| 6360 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 |
| 6361 | #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 |
| 6362 | |
| 6363 | /* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ |
| 6364 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 |
| 6365 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 |
| 6366 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 |
| 6367 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 |
| 6368 | |
| 6369 | /* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ |
| 6370 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 |
| 6371 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 |
| 6372 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 |
| 6373 | #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 |
| 6374 | |
| 6375 | /* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ |
| 6376 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 |
| 6377 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 |
| 6378 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_BITS 1 |
| 6379 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 |
| 6380 | |
| 6381 | /* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ |
| 6382 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 |
| 6383 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 |
| 6384 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_BITS 1 |
| 6385 | #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 |
| 6386 | |
| 6387 | |
| 6388 | /**************************************************************************** |
| 6389 | * INTR :: INTR_MSK_CLR_REG |
| 6390 | ***************************************************************************/ |
| 6391 | /* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:26] */ |
| 6392 | #define INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xfc000000 |
| 6393 | #define INTR_INTR_MSK_CLR_REG_reserved0_ALIGN 0 |
| 6394 | #define INTR_INTR_MSK_CLR_REG_reserved0_BITS 6 |
| 6395 | #define INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 26 |
| 6396 | |
| 6397 | /* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ |
| 6398 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 |
| 6399 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 |
| 6400 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 |
| 6401 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 |
| 6402 | |
| 6403 | /* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ |
| 6404 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 |
| 6405 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 |
| 6406 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 |
| 6407 | #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 |
| 6408 | |
| 6409 | /* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:14] */ |
| 6410 | #define INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00ffc000 |
| 6411 | #define INTR_INTR_MSK_CLR_REG_reserved1_ALIGN 0 |
| 6412 | #define INTR_INTR_MSK_CLR_REG_reserved1_BITS 10 |
| 6413 | #define INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 14 |
| 6414 | |
| 6415 | /* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ |
| 6416 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 |
| 6417 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 |
| 6418 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 |
| 6419 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 |
| 6420 | |
| 6421 | /* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ |
| 6422 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 |
| 6423 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 |
| 6424 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 |
| 6425 | #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 |
| 6426 | |
| 6427 | /* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ |
| 6428 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 |
| 6429 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 |
| 6430 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 |
| 6431 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 |
| 6432 | |
| 6433 | /* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ |
| 6434 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 |
| 6435 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 |
| 6436 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 |
| 6437 | #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 |
| 6438 | |
| 6439 | /* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ |
| 6440 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 |
| 6441 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 |
| 6442 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 |
| 6443 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 |
| 6444 | |
| 6445 | /* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ |
| 6446 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 |
| 6447 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 |
| 6448 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 |
| 6449 | #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 |
| 6450 | |
| 6451 | /* INTR :: INTR_MSK_CLR_REG :: reserved2 [07:06] */ |
| 6452 | #define INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x000000c0 |
| 6453 | #define INTR_INTR_MSK_CLR_REG_reserved2_ALIGN 0 |
| 6454 | #define INTR_INTR_MSK_CLR_REG_reserved2_BITS 2 |
| 6455 | #define INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 6 |
| 6456 | |
| 6457 | /* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ |
| 6458 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 |
| 6459 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 |
| 6460 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 |
| 6461 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 |
| 6462 | |
| 6463 | /* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ |
| 6464 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 |
| 6465 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 |
| 6466 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 |
| 6467 | #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 |
| 6468 | |
| 6469 | /* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ |
| 6470 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 |
| 6471 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 |
| 6472 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 |
| 6473 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 |
| 6474 | |
| 6475 | /* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ |
| 6476 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 |
| 6477 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 |
| 6478 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 |
| 6479 | #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 |
| 6480 | |
| 6481 | /* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ |
| 6482 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 |
| 6483 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 |
| 6484 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 |
| 6485 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 |
| 6486 | |
| 6487 | /* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ |
| 6488 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 |
| 6489 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 |
| 6490 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 |
| 6491 | #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 |
| 6492 | |
| 6493 | |
| 6494 | /**************************************************************************** |
| 6495 | * INTR :: EOI_CTRL |
| 6496 | ***************************************************************************/ |
| 6497 | /* INTR :: EOI_CTRL :: reserved0 [31:01] */ |
| 6498 | #define INTR_EOI_CTRL_reserved0_MASK 0xfffffffe |
| 6499 | #define INTR_EOI_CTRL_reserved0_ALIGN 0 |
| 6500 | #define INTR_EOI_CTRL_reserved0_BITS 31 |
| 6501 | #define INTR_EOI_CTRL_reserved0_SHIFT 1 |
| 6502 | |
| 6503 | /* INTR :: EOI_CTRL :: EOI [00:00] */ |
| 6504 | #define INTR_EOI_CTRL_EOI_MASK 0x00000001 |
| 6505 | #define INTR_EOI_CTRL_EOI_ALIGN 0 |
| 6506 | #define INTR_EOI_CTRL_EOI_BITS 1 |
| 6507 | #define INTR_EOI_CTRL_EOI_SHIFT 0 |
| 6508 | |
| 6509 | |
| 6510 | /**************************************************************************** |
| 6511 | * BCM70012_TGT_TOP_MDIO |
| 6512 | ***************************************************************************/ |
| 6513 | /**************************************************************************** |
| 6514 | * MDIO :: CTRL0 |
| 6515 | ***************************************************************************/ |
| 6516 | /* MDIO :: CTRL0 :: reserved0 [31:22] */ |
| 6517 | #define MDIO_CTRL0_reserved0_MASK 0xffc00000 |
| 6518 | #define MDIO_CTRL0_reserved0_ALIGN 0 |
| 6519 | #define MDIO_CTRL0_reserved0_BITS 10 |
| 6520 | #define MDIO_CTRL0_reserved0_SHIFT 22 |
| 6521 | |
| 6522 | /* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ |
| 6523 | #define MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 |
| 6524 | #define MDIO_CTRL0_WRITE_READ_COMMAND_ALIGN 0 |
| 6525 | #define MDIO_CTRL0_WRITE_READ_COMMAND_BITS 1 |
| 6526 | #define MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 |
| 6527 | |
| 6528 | /* MDIO :: CTRL0 :: PHYAD [20:16] */ |
| 6529 | #define MDIO_CTRL0_PHYAD_MASK 0x001f0000 |
| 6530 | #define MDIO_CTRL0_PHYAD_ALIGN 0 |
| 6531 | #define MDIO_CTRL0_PHYAD_BITS 5 |
| 6532 | #define MDIO_CTRL0_PHYAD_SHIFT 16 |
| 6533 | |
| 6534 | /* MDIO :: CTRL0 :: reserved1 [15:05] */ |
| 6535 | #define MDIO_CTRL0_reserved1_MASK 0x0000ffe0 |
| 6536 | #define MDIO_CTRL0_reserved1_ALIGN 0 |
| 6537 | #define MDIO_CTRL0_reserved1_BITS 11 |
| 6538 | #define MDIO_CTRL0_reserved1_SHIFT 5 |
| 6539 | |
| 6540 | /* MDIO :: CTRL0 :: REGAD [04:00] */ |
| 6541 | #define MDIO_CTRL0_REGAD_MASK 0x0000001f |
| 6542 | #define MDIO_CTRL0_REGAD_ALIGN 0 |
| 6543 | #define MDIO_CTRL0_REGAD_BITS 5 |
| 6544 | #define MDIO_CTRL0_REGAD_SHIFT 0 |
| 6545 | |
| 6546 | |
| 6547 | /**************************************************************************** |
| 6548 | * MDIO :: CTRL1 |
| 6549 | ***************************************************************************/ |
| 6550 | /* MDIO :: CTRL1 :: WR_STATUS [31:31] */ |
| 6551 | #define MDIO_CTRL1_WR_STATUS_MASK 0x80000000 |
| 6552 | #define MDIO_CTRL1_WR_STATUS_ALIGN 0 |
| 6553 | #define MDIO_CTRL1_WR_STATUS_BITS 1 |
| 6554 | #define MDIO_CTRL1_WR_STATUS_SHIFT 31 |
| 6555 | |
| 6556 | /* MDIO :: CTRL1 :: reserved0 [30:16] */ |
| 6557 | #define MDIO_CTRL1_reserved0_MASK 0x7fff0000 |
| 6558 | #define MDIO_CTRL1_reserved0_ALIGN 0 |
| 6559 | #define MDIO_CTRL1_reserved0_BITS 15 |
| 6560 | #define MDIO_CTRL1_reserved0_SHIFT 16 |
| 6561 | |
| 6562 | /* MDIO :: CTRL1 :: Write_Data [15:00] */ |
| 6563 | #define MDIO_CTRL1_Write_Data_MASK 0x0000ffff |
| 6564 | #define MDIO_CTRL1_Write_Data_ALIGN 0 |
| 6565 | #define MDIO_CTRL1_Write_Data_BITS 16 |
| 6566 | #define MDIO_CTRL1_Write_Data_SHIFT 0 |
| 6567 | |
| 6568 | |
| 6569 | /**************************************************************************** |
| 6570 | * MDIO :: CTRL2 |
| 6571 | ***************************************************************************/ |
| 6572 | /* MDIO :: CTRL2 :: RD_STATUS [31:31] */ |
| 6573 | #define MDIO_CTRL2_RD_STATUS_MASK 0x80000000 |
| 6574 | #define MDIO_CTRL2_RD_STATUS_ALIGN 0 |
| 6575 | #define MDIO_CTRL2_RD_STATUS_BITS 1 |
| 6576 | #define MDIO_CTRL2_RD_STATUS_SHIFT 31 |
| 6577 | |
| 6578 | /* MDIO :: CTRL2 :: reserved0 [30:16] */ |
| 6579 | #define MDIO_CTRL2_reserved0_MASK 0x7fff0000 |
| 6580 | #define MDIO_CTRL2_reserved0_ALIGN 0 |
| 6581 | #define MDIO_CTRL2_reserved0_BITS 15 |
| 6582 | #define MDIO_CTRL2_reserved0_SHIFT 16 |
| 6583 | |
| 6584 | /* MDIO :: CTRL2 :: Read_Data [15:00] */ |
| 6585 | #define MDIO_CTRL2_Read_Data_MASK 0x0000ffff |
| 6586 | #define MDIO_CTRL2_Read_Data_ALIGN 0 |
| 6587 | #define MDIO_CTRL2_Read_Data_BITS 16 |
| 6588 | #define MDIO_CTRL2_Read_Data_SHIFT 0 |
| 6589 | |
| 6590 | |
| 6591 | /**************************************************************************** |
| 6592 | * BCM70012_TGT_TOP_TGT_RGR_BRIDGE |
| 6593 | ***************************************************************************/ |
| 6594 | /**************************************************************************** |
| 6595 | * TGT_RGR_BRIDGE :: REVISION |
| 6596 | ***************************************************************************/ |
| 6597 | /* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 6598 | #define TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 6599 | #define TGT_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 6600 | #define TGT_RGR_BRIDGE_REVISION_reserved0_BITS 16 |
| 6601 | #define TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 6602 | |
| 6603 | /* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 6604 | #define TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 6605 | #define TGT_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 6606 | #define TGT_RGR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 6607 | #define TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 6608 | |
| 6609 | /* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 6610 | #define TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 6611 | #define TGT_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 6612 | #define TGT_RGR_BRIDGE_REVISION_MINOR_BITS 8 |
| 6613 | #define TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 6614 | |
| 6615 | |
| 6616 | /**************************************************************************** |
| 6617 | * TGT_RGR_BRIDGE :: CTRL |
| 6618 | ***************************************************************************/ |
| 6619 | /* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ |
| 6620 | #define TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc |
| 6621 | #define TGT_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 6622 | #define TGT_RGR_BRIDGE_CTRL_reserved0_BITS 30 |
| 6623 | #define TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 |
| 6624 | |
| 6625 | /* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ |
| 6626 | #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 |
| 6627 | #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_ALIGN 0 |
| 6628 | #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_BITS 1 |
| 6629 | #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 |
| 6630 | |
| 6631 | /* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ |
| 6632 | #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 |
| 6633 | #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_ALIGN 0 |
| 6634 | #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_BITS 1 |
| 6635 | #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 |
| 6636 | |
| 6637 | |
| 6638 | /**************************************************************************** |
| 6639 | * TGT_RGR_BRIDGE :: RBUS_TIMER |
| 6640 | ***************************************************************************/ |
| 6641 | /* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ |
| 6642 | #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 |
| 6643 | #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 |
| 6644 | #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 |
| 6645 | #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 |
| 6646 | |
| 6647 | /* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ |
| 6648 | #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff |
| 6649 | #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_ALIGN 0 |
| 6650 | #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_BITS 16 |
| 6651 | #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 |
| 6652 | |
| 6653 | |
| 6654 | /**************************************************************************** |
| 6655 | * TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 |
| 6656 | ***************************************************************************/ |
| 6657 | /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 6658 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 6659 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 6660 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 6661 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 6662 | |
| 6663 | /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 6664 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 6665 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 6666 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 6667 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 6668 | |
| 6669 | |
| 6670 | /**************************************************************************** |
| 6671 | * TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 |
| 6672 | ***************************************************************************/ |
| 6673 | /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 6674 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 6675 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 6676 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 6677 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 6678 | |
| 6679 | /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 6680 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 6681 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 6682 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 6683 | #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 6684 | |
| 6685 | |
| 6686 | /**************************************************************************** |
| 6687 | * BCM70012_I2C_TOP_I2C |
| 6688 | ***************************************************************************/ |
| 6689 | /**************************************************************************** |
| 6690 | * I2C :: CHIP_ADDRESS |
| 6691 | ***************************************************************************/ |
| 6692 | /* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ |
| 6693 | #define I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 |
| 6694 | #define I2C_CHIP_ADDRESS_reserved0_ALIGN 0 |
| 6695 | #define I2C_CHIP_ADDRESS_reserved0_BITS 24 |
| 6696 | #define I2C_CHIP_ADDRESS_reserved0_SHIFT 8 |
| 6697 | |
| 6698 | /* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ |
| 6699 | #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe |
| 6700 | #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_ALIGN 0 |
| 6701 | #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_BITS 7 |
| 6702 | #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 |
| 6703 | |
| 6704 | /* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ |
| 6705 | #define I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 |
| 6706 | #define I2C_CHIP_ADDRESS_RESERVED_ALIGN 0 |
| 6707 | #define I2C_CHIP_ADDRESS_RESERVED_BITS 1 |
| 6708 | #define I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 |
| 6709 | |
| 6710 | |
| 6711 | /**************************************************************************** |
| 6712 | * I2C :: DATA_IN0 |
| 6713 | ***************************************************************************/ |
| 6714 | /* I2C :: DATA_IN0 :: reserved0 [31:08] */ |
| 6715 | #define I2C_DATA_IN0_reserved0_MASK 0xffffff00 |
| 6716 | #define I2C_DATA_IN0_reserved0_ALIGN 0 |
| 6717 | #define I2C_DATA_IN0_reserved0_BITS 24 |
| 6718 | #define I2C_DATA_IN0_reserved0_SHIFT 8 |
| 6719 | |
| 6720 | /* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ |
| 6721 | #define I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff |
| 6722 | #define I2C_DATA_IN0_DATA_IN0_ALIGN 0 |
| 6723 | #define I2C_DATA_IN0_DATA_IN0_BITS 8 |
| 6724 | #define I2C_DATA_IN0_DATA_IN0_SHIFT 0 |
| 6725 | |
| 6726 | |
| 6727 | /**************************************************************************** |
| 6728 | * I2C :: DATA_IN1 |
| 6729 | ***************************************************************************/ |
| 6730 | /* I2C :: DATA_IN1 :: reserved0 [31:08] */ |
| 6731 | #define I2C_DATA_IN1_reserved0_MASK 0xffffff00 |
| 6732 | #define I2C_DATA_IN1_reserved0_ALIGN 0 |
| 6733 | #define I2C_DATA_IN1_reserved0_BITS 24 |
| 6734 | #define I2C_DATA_IN1_reserved0_SHIFT 8 |
| 6735 | |
| 6736 | /* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ |
| 6737 | #define I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff |
| 6738 | #define I2C_DATA_IN1_DATA_IN1_ALIGN 0 |
| 6739 | #define I2C_DATA_IN1_DATA_IN1_BITS 8 |
| 6740 | #define I2C_DATA_IN1_DATA_IN1_SHIFT 0 |
| 6741 | |
| 6742 | |
| 6743 | /**************************************************************************** |
| 6744 | * I2C :: DATA_IN2 |
| 6745 | ***************************************************************************/ |
| 6746 | /* I2C :: DATA_IN2 :: reserved0 [31:08] */ |
| 6747 | #define I2C_DATA_IN2_reserved0_MASK 0xffffff00 |
| 6748 | #define I2C_DATA_IN2_reserved0_ALIGN 0 |
| 6749 | #define I2C_DATA_IN2_reserved0_BITS 24 |
| 6750 | #define I2C_DATA_IN2_reserved0_SHIFT 8 |
| 6751 | |
| 6752 | /* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ |
| 6753 | #define I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff |
| 6754 | #define I2C_DATA_IN2_DATA_IN2_ALIGN 0 |
| 6755 | #define I2C_DATA_IN2_DATA_IN2_BITS 8 |
| 6756 | #define I2C_DATA_IN2_DATA_IN2_SHIFT 0 |
| 6757 | |
| 6758 | |
| 6759 | /**************************************************************************** |
| 6760 | * I2C :: DATA_IN3 |
| 6761 | ***************************************************************************/ |
| 6762 | /* I2C :: DATA_IN3 :: reserved0 [31:08] */ |
| 6763 | #define I2C_DATA_IN3_reserved0_MASK 0xffffff00 |
| 6764 | #define I2C_DATA_IN3_reserved0_ALIGN 0 |
| 6765 | #define I2C_DATA_IN3_reserved0_BITS 24 |
| 6766 | #define I2C_DATA_IN3_reserved0_SHIFT 8 |
| 6767 | |
| 6768 | /* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ |
| 6769 | #define I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff |
| 6770 | #define I2C_DATA_IN3_DATA_IN3_ALIGN 0 |
| 6771 | #define I2C_DATA_IN3_DATA_IN3_BITS 8 |
| 6772 | #define I2C_DATA_IN3_DATA_IN3_SHIFT 0 |
| 6773 | |
| 6774 | |
| 6775 | /**************************************************************************** |
| 6776 | * I2C :: DATA_IN4 |
| 6777 | ***************************************************************************/ |
| 6778 | /* I2C :: DATA_IN4 :: reserved0 [31:08] */ |
| 6779 | #define I2C_DATA_IN4_reserved0_MASK 0xffffff00 |
| 6780 | #define I2C_DATA_IN4_reserved0_ALIGN 0 |
| 6781 | #define I2C_DATA_IN4_reserved0_BITS 24 |
| 6782 | #define I2C_DATA_IN4_reserved0_SHIFT 8 |
| 6783 | |
| 6784 | /* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ |
| 6785 | #define I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff |
| 6786 | #define I2C_DATA_IN4_DATA_IN4_ALIGN 0 |
| 6787 | #define I2C_DATA_IN4_DATA_IN4_BITS 8 |
| 6788 | #define I2C_DATA_IN4_DATA_IN4_SHIFT 0 |
| 6789 | |
| 6790 | |
| 6791 | /**************************************************************************** |
| 6792 | * I2C :: DATA_IN5 |
| 6793 | ***************************************************************************/ |
| 6794 | /* I2C :: DATA_IN5 :: reserved0 [31:08] */ |
| 6795 | #define I2C_DATA_IN5_reserved0_MASK 0xffffff00 |
| 6796 | #define I2C_DATA_IN5_reserved0_ALIGN 0 |
| 6797 | #define I2C_DATA_IN5_reserved0_BITS 24 |
| 6798 | #define I2C_DATA_IN5_reserved0_SHIFT 8 |
| 6799 | |
| 6800 | /* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ |
| 6801 | #define I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff |
| 6802 | #define I2C_DATA_IN5_DATA_IN5_ALIGN 0 |
| 6803 | #define I2C_DATA_IN5_DATA_IN5_BITS 8 |
| 6804 | #define I2C_DATA_IN5_DATA_IN5_SHIFT 0 |
| 6805 | |
| 6806 | |
| 6807 | /**************************************************************************** |
| 6808 | * I2C :: DATA_IN6 |
| 6809 | ***************************************************************************/ |
| 6810 | /* I2C :: DATA_IN6 :: reserved0 [31:08] */ |
| 6811 | #define I2C_DATA_IN6_reserved0_MASK 0xffffff00 |
| 6812 | #define I2C_DATA_IN6_reserved0_ALIGN 0 |
| 6813 | #define I2C_DATA_IN6_reserved0_BITS 24 |
| 6814 | #define I2C_DATA_IN6_reserved0_SHIFT 8 |
| 6815 | |
| 6816 | /* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ |
| 6817 | #define I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff |
| 6818 | #define I2C_DATA_IN6_DATA_IN6_ALIGN 0 |
| 6819 | #define I2C_DATA_IN6_DATA_IN6_BITS 8 |
| 6820 | #define I2C_DATA_IN6_DATA_IN6_SHIFT 0 |
| 6821 | |
| 6822 | |
| 6823 | /**************************************************************************** |
| 6824 | * I2C :: DATA_IN7 |
| 6825 | ***************************************************************************/ |
| 6826 | /* I2C :: DATA_IN7 :: reserved0 [31:08] */ |
| 6827 | #define I2C_DATA_IN7_reserved0_MASK 0xffffff00 |
| 6828 | #define I2C_DATA_IN7_reserved0_ALIGN 0 |
| 6829 | #define I2C_DATA_IN7_reserved0_BITS 24 |
| 6830 | #define I2C_DATA_IN7_reserved0_SHIFT 8 |
| 6831 | |
| 6832 | /* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ |
| 6833 | #define I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff |
| 6834 | #define I2C_DATA_IN7_DATA_IN7_ALIGN 0 |
| 6835 | #define I2C_DATA_IN7_DATA_IN7_BITS 8 |
| 6836 | #define I2C_DATA_IN7_DATA_IN7_SHIFT 0 |
| 6837 | |
| 6838 | |
| 6839 | /**************************************************************************** |
| 6840 | * I2C :: CNT_REG |
| 6841 | ***************************************************************************/ |
| 6842 | /* I2C :: CNT_REG :: reserved0 [31:08] */ |
| 6843 | #define I2C_CNT_REG_reserved0_MASK 0xffffff00 |
| 6844 | #define I2C_CNT_REG_reserved0_ALIGN 0 |
| 6845 | #define I2C_CNT_REG_reserved0_BITS 24 |
| 6846 | #define I2C_CNT_REG_reserved0_SHIFT 8 |
| 6847 | |
| 6848 | /* I2C :: CNT_REG :: CNT_REG2 [07:04] */ |
| 6849 | #define I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 |
| 6850 | #define I2C_CNT_REG_CNT_REG2_ALIGN 0 |
| 6851 | #define I2C_CNT_REG_CNT_REG2_BITS 4 |
| 6852 | #define I2C_CNT_REG_CNT_REG2_SHIFT 4 |
| 6853 | |
| 6854 | /* I2C :: CNT_REG :: CNT_REG1 [03:00] */ |
| 6855 | #define I2C_CNT_REG_CNT_REG1_MASK 0x0000000f |
| 6856 | #define I2C_CNT_REG_CNT_REG1_ALIGN 0 |
| 6857 | #define I2C_CNT_REG_CNT_REG1_BITS 4 |
| 6858 | #define I2C_CNT_REG_CNT_REG1_SHIFT 0 |
| 6859 | |
| 6860 | |
| 6861 | /**************************************************************************** |
| 6862 | * I2C :: CTL_REG |
| 6863 | ***************************************************************************/ |
| 6864 | /* I2C :: CTL_REG :: reserved0 [31:08] */ |
| 6865 | #define I2C_CTL_REG_reserved0_MASK 0xffffff00 |
| 6866 | #define I2C_CTL_REG_reserved0_ALIGN 0 |
| 6867 | #define I2C_CTL_REG_reserved0_BITS 24 |
| 6868 | #define I2C_CTL_REG_reserved0_SHIFT 8 |
| 6869 | |
| 6870 | /* I2C :: CTL_REG :: DIV_CLK [07:07] */ |
| 6871 | #define I2C_CTL_REG_DIV_CLK_MASK 0x00000080 |
| 6872 | #define I2C_CTL_REG_DIV_CLK_ALIGN 0 |
| 6873 | #define I2C_CTL_REG_DIV_CLK_BITS 1 |
| 6874 | #define I2C_CTL_REG_DIV_CLK_SHIFT 7 |
| 6875 | |
| 6876 | /* I2C :: CTL_REG :: INT_EN [06:06] */ |
| 6877 | #define I2C_CTL_REG_INT_EN_MASK 0x00000040 |
| 6878 | #define I2C_CTL_REG_INT_EN_ALIGN 0 |
| 6879 | #define I2C_CTL_REG_INT_EN_BITS 1 |
| 6880 | #define I2C_CTL_REG_INT_EN_SHIFT 6 |
| 6881 | |
| 6882 | /* I2C :: CTL_REG :: SCL_SEL [05:04] */ |
| 6883 | #define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 |
| 6884 | #define I2C_CTL_REG_SCL_SEL_ALIGN 0 |
| 6885 | #define I2C_CTL_REG_SCL_SEL_BITS 2 |
| 6886 | #define I2C_CTL_REG_SCL_SEL_SHIFT 4 |
| 6887 | |
| 6888 | /* I2C :: CTL_REG :: DELAY_DIS [03:03] */ |
| 6889 | #define I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 |
| 6890 | #define I2C_CTL_REG_DELAY_DIS_ALIGN 0 |
| 6891 | #define I2C_CTL_REG_DELAY_DIS_BITS 1 |
| 6892 | #define I2C_CTL_REG_DELAY_DIS_SHIFT 3 |
| 6893 | |
| 6894 | /* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ |
| 6895 | #define I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 |
| 6896 | #define I2C_CTL_REG_DEGLITCH_DIS_ALIGN 0 |
| 6897 | #define I2C_CTL_REG_DEGLITCH_DIS_BITS 1 |
| 6898 | #define I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 |
| 6899 | |
| 6900 | /* I2C :: CTL_REG :: DTF [01:00] */ |
| 6901 | #define I2C_CTL_REG_DTF_MASK 0x00000003 |
| 6902 | #define I2C_CTL_REG_DTF_ALIGN 0 |
| 6903 | #define I2C_CTL_REG_DTF_BITS 2 |
| 6904 | #define I2C_CTL_REG_DTF_SHIFT 0 |
| 6905 | |
| 6906 | |
| 6907 | /**************************************************************************** |
| 6908 | * I2C :: IIC_ENABLE |
| 6909 | ***************************************************************************/ |
| 6910 | /* I2C :: IIC_ENABLE :: reserved0 [31:07] */ |
| 6911 | #define I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 |
| 6912 | #define I2C_IIC_ENABLE_reserved0_ALIGN 0 |
| 6913 | #define I2C_IIC_ENABLE_reserved0_BITS 25 |
| 6914 | #define I2C_IIC_ENABLE_reserved0_SHIFT 7 |
| 6915 | |
| 6916 | /* I2C :: IIC_ENABLE :: RESTART [06:06] */ |
| 6917 | #define I2C_IIC_ENABLE_RESTART_MASK 0x00000040 |
| 6918 | #define I2C_IIC_ENABLE_RESTART_ALIGN 0 |
| 6919 | #define I2C_IIC_ENABLE_RESTART_BITS 1 |
| 6920 | #define I2C_IIC_ENABLE_RESTART_SHIFT 6 |
| 6921 | |
| 6922 | /* I2C :: IIC_ENABLE :: NO_START [05:05] */ |
| 6923 | #define I2C_IIC_ENABLE_NO_START_MASK 0x00000020 |
| 6924 | #define I2C_IIC_ENABLE_NO_START_ALIGN 0 |
| 6925 | #define I2C_IIC_ENABLE_NO_START_BITS 1 |
| 6926 | #define I2C_IIC_ENABLE_NO_START_SHIFT 5 |
| 6927 | |
| 6928 | /* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ |
| 6929 | #define I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 |
| 6930 | #define I2C_IIC_ENABLE_NO_STOP_ALIGN 0 |
| 6931 | #define I2C_IIC_ENABLE_NO_STOP_BITS 1 |
| 6932 | #define I2C_IIC_ENABLE_NO_STOP_SHIFT 4 |
| 6933 | |
| 6934 | /* I2C :: IIC_ENABLE :: reserved1 [03:03] */ |
| 6935 | #define I2C_IIC_ENABLE_reserved1_MASK 0x00000008 |
| 6936 | #define I2C_IIC_ENABLE_reserved1_ALIGN 0 |
| 6937 | #define I2C_IIC_ENABLE_reserved1_BITS 1 |
| 6938 | #define I2C_IIC_ENABLE_reserved1_SHIFT 3 |
| 6939 | |
| 6940 | /* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ |
| 6941 | #define I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 |
| 6942 | #define I2C_IIC_ENABLE_NO_ACK_ALIGN 0 |
| 6943 | #define I2C_IIC_ENABLE_NO_ACK_BITS 1 |
| 6944 | #define I2C_IIC_ENABLE_NO_ACK_SHIFT 2 |
| 6945 | |
| 6946 | /* I2C :: IIC_ENABLE :: INTRP [01:01] */ |
| 6947 | #define I2C_IIC_ENABLE_INTRP_MASK 0x00000002 |
| 6948 | #define I2C_IIC_ENABLE_INTRP_ALIGN 0 |
| 6949 | #define I2C_IIC_ENABLE_INTRP_BITS 1 |
| 6950 | #define I2C_IIC_ENABLE_INTRP_SHIFT 1 |
| 6951 | |
| 6952 | /* I2C :: IIC_ENABLE :: ENABLE [00:00] */ |
| 6953 | #define I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 |
| 6954 | #define I2C_IIC_ENABLE_ENABLE_ALIGN 0 |
| 6955 | #define I2C_IIC_ENABLE_ENABLE_BITS 1 |
| 6956 | #define I2C_IIC_ENABLE_ENABLE_SHIFT 0 |
| 6957 | |
| 6958 | |
| 6959 | /**************************************************************************** |
| 6960 | * I2C :: DATA_OUT0 |
| 6961 | ***************************************************************************/ |
| 6962 | /* I2C :: DATA_OUT0 :: reserved0 [31:08] */ |
| 6963 | #define I2C_DATA_OUT0_reserved0_MASK 0xffffff00 |
| 6964 | #define I2C_DATA_OUT0_reserved0_ALIGN 0 |
| 6965 | #define I2C_DATA_OUT0_reserved0_BITS 24 |
| 6966 | #define I2C_DATA_OUT0_reserved0_SHIFT 8 |
| 6967 | |
| 6968 | /* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ |
| 6969 | #define I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff |
| 6970 | #define I2C_DATA_OUT0_DATA_OUT0_ALIGN 0 |
| 6971 | #define I2C_DATA_OUT0_DATA_OUT0_BITS 8 |
| 6972 | #define I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 |
| 6973 | |
| 6974 | |
| 6975 | /**************************************************************************** |
| 6976 | * I2C :: DATA_OUT1 |
| 6977 | ***************************************************************************/ |
| 6978 | /* I2C :: DATA_OUT1 :: reserved0 [31:08] */ |
| 6979 | #define I2C_DATA_OUT1_reserved0_MASK 0xffffff00 |
| 6980 | #define I2C_DATA_OUT1_reserved0_ALIGN 0 |
| 6981 | #define I2C_DATA_OUT1_reserved0_BITS 24 |
| 6982 | #define I2C_DATA_OUT1_reserved0_SHIFT 8 |
| 6983 | |
| 6984 | /* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ |
| 6985 | #define I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff |
| 6986 | #define I2C_DATA_OUT1_DATA_OUT1_ALIGN 0 |
| 6987 | #define I2C_DATA_OUT1_DATA_OUT1_BITS 8 |
| 6988 | #define I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 |
| 6989 | |
| 6990 | |
| 6991 | /**************************************************************************** |
| 6992 | * I2C :: DATA_OUT2 |
| 6993 | ***************************************************************************/ |
| 6994 | /* I2C :: DATA_OUT2 :: reserved0 [31:08] */ |
| 6995 | #define I2C_DATA_OUT2_reserved0_MASK 0xffffff00 |
| 6996 | #define I2C_DATA_OUT2_reserved0_ALIGN 0 |
| 6997 | #define I2C_DATA_OUT2_reserved0_BITS 24 |
| 6998 | #define I2C_DATA_OUT2_reserved0_SHIFT 8 |
| 6999 | |
| 7000 | /* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ |
| 7001 | #define I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff |
| 7002 | #define I2C_DATA_OUT2_DATA_OUT2_ALIGN 0 |
| 7003 | #define I2C_DATA_OUT2_DATA_OUT2_BITS 8 |
| 7004 | #define I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 |
| 7005 | |
| 7006 | |
| 7007 | /**************************************************************************** |
| 7008 | * I2C :: DATA_OUT3 |
| 7009 | ***************************************************************************/ |
| 7010 | /* I2C :: DATA_OUT3 :: reserved0 [31:08] */ |
| 7011 | #define I2C_DATA_OUT3_reserved0_MASK 0xffffff00 |
| 7012 | #define I2C_DATA_OUT3_reserved0_ALIGN 0 |
| 7013 | #define I2C_DATA_OUT3_reserved0_BITS 24 |
| 7014 | #define I2C_DATA_OUT3_reserved0_SHIFT 8 |
| 7015 | |
| 7016 | /* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ |
| 7017 | #define I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff |
| 7018 | #define I2C_DATA_OUT3_DATA_OUT3_ALIGN 0 |
| 7019 | #define I2C_DATA_OUT3_DATA_OUT3_BITS 8 |
| 7020 | #define I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 |
| 7021 | |
| 7022 | |
| 7023 | /**************************************************************************** |
| 7024 | * I2C :: DATA_OUT4 |
| 7025 | ***************************************************************************/ |
| 7026 | /* I2C :: DATA_OUT4 :: reserved0 [31:08] */ |
| 7027 | #define I2C_DATA_OUT4_reserved0_MASK 0xffffff00 |
| 7028 | #define I2C_DATA_OUT4_reserved0_ALIGN 0 |
| 7029 | #define I2C_DATA_OUT4_reserved0_BITS 24 |
| 7030 | #define I2C_DATA_OUT4_reserved0_SHIFT 8 |
| 7031 | |
| 7032 | /* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ |
| 7033 | #define I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff |
| 7034 | #define I2C_DATA_OUT4_DATA_OUT4_ALIGN 0 |
| 7035 | #define I2C_DATA_OUT4_DATA_OUT4_BITS 8 |
| 7036 | #define I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 |
| 7037 | |
| 7038 | |
| 7039 | /**************************************************************************** |
| 7040 | * I2C :: DATA_OUT5 |
| 7041 | ***************************************************************************/ |
| 7042 | /* I2C :: DATA_OUT5 :: reserved0 [31:08] */ |
| 7043 | #define I2C_DATA_OUT5_reserved0_MASK 0xffffff00 |
| 7044 | #define I2C_DATA_OUT5_reserved0_ALIGN 0 |
| 7045 | #define I2C_DATA_OUT5_reserved0_BITS 24 |
| 7046 | #define I2C_DATA_OUT5_reserved0_SHIFT 8 |
| 7047 | |
| 7048 | /* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ |
| 7049 | #define I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff |
| 7050 | #define I2C_DATA_OUT5_DATA_OUT5_ALIGN 0 |
| 7051 | #define I2C_DATA_OUT5_DATA_OUT5_BITS 8 |
| 7052 | #define I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 |
| 7053 | |
| 7054 | |
| 7055 | /**************************************************************************** |
| 7056 | * I2C :: DATA_OUT6 |
| 7057 | ***************************************************************************/ |
| 7058 | /* I2C :: DATA_OUT6 :: reserved0 [31:08] */ |
| 7059 | #define I2C_DATA_OUT6_reserved0_MASK 0xffffff00 |
| 7060 | #define I2C_DATA_OUT6_reserved0_ALIGN 0 |
| 7061 | #define I2C_DATA_OUT6_reserved0_BITS 24 |
| 7062 | #define I2C_DATA_OUT6_reserved0_SHIFT 8 |
| 7063 | |
| 7064 | /* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ |
| 7065 | #define I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff |
| 7066 | #define I2C_DATA_OUT6_DATA_OUT6_ALIGN 0 |
| 7067 | #define I2C_DATA_OUT6_DATA_OUT6_BITS 8 |
| 7068 | #define I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 |
| 7069 | |
| 7070 | |
| 7071 | /**************************************************************************** |
| 7072 | * I2C :: DATA_OUT7 |
| 7073 | ***************************************************************************/ |
| 7074 | /* I2C :: DATA_OUT7 :: reserved0 [31:08] */ |
| 7075 | #define I2C_DATA_OUT7_reserved0_MASK 0xffffff00 |
| 7076 | #define I2C_DATA_OUT7_reserved0_ALIGN 0 |
| 7077 | #define I2C_DATA_OUT7_reserved0_BITS 24 |
| 7078 | #define I2C_DATA_OUT7_reserved0_SHIFT 8 |
| 7079 | |
| 7080 | /* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ |
| 7081 | #define I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff |
| 7082 | #define I2C_DATA_OUT7_DATA_OUT7_ALIGN 0 |
| 7083 | #define I2C_DATA_OUT7_DATA_OUT7_BITS 8 |
| 7084 | #define I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 |
| 7085 | |
| 7086 | |
| 7087 | /**************************************************************************** |
| 7088 | * I2C :: CTLHI_REG |
| 7089 | ***************************************************************************/ |
| 7090 | /* I2C :: CTLHI_REG :: reserved0 [31:02] */ |
| 7091 | #define I2C_CTLHI_REG_reserved0_MASK 0xfffffffc |
| 7092 | #define I2C_CTLHI_REG_reserved0_ALIGN 0 |
| 7093 | #define I2C_CTLHI_REG_reserved0_BITS 30 |
| 7094 | #define I2C_CTLHI_REG_reserved0_SHIFT 2 |
| 7095 | |
| 7096 | /* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ |
| 7097 | #define I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 |
| 7098 | #define I2C_CTLHI_REG_IGNORE_ACK_ALIGN 0 |
| 7099 | #define I2C_CTLHI_REG_IGNORE_ACK_BITS 1 |
| 7100 | #define I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 |
| 7101 | |
| 7102 | /* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ |
| 7103 | #define I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 |
| 7104 | #define I2C_CTLHI_REG_WAIT_DIS_ALIGN 0 |
| 7105 | #define I2C_CTLHI_REG_WAIT_DIS_BITS 1 |
| 7106 | #define I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 |
| 7107 | |
| 7108 | |
| 7109 | /**************************************************************************** |
| 7110 | * I2C :: SCL_PARAM |
| 7111 | ***************************************************************************/ |
| 7112 | /* I2C :: SCL_PARAM :: reserved0 [31:00] */ |
| 7113 | #define I2C_SCL_PARAM_reserved0_MASK 0xffffffff |
| 7114 | #define I2C_SCL_PARAM_reserved0_ALIGN 0 |
| 7115 | #define I2C_SCL_PARAM_reserved0_BITS 32 |
| 7116 | #define I2C_SCL_PARAM_reserved0_SHIFT 0 |
| 7117 | |
| 7118 | |
| 7119 | /**************************************************************************** |
| 7120 | * BCM70012_I2C_TOP_I2C_GR_BRIDGE |
| 7121 | ***************************************************************************/ |
| 7122 | /**************************************************************************** |
| 7123 | * I2C_GR_BRIDGE :: REVISION |
| 7124 | ***************************************************************************/ |
| 7125 | /* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 7126 | #define I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 7127 | #define I2C_GR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 7128 | #define I2C_GR_BRIDGE_REVISION_reserved0_BITS 16 |
| 7129 | #define I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 7130 | |
| 7131 | /* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 7132 | #define I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 7133 | #define I2C_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 7134 | #define I2C_GR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 7135 | #define I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 7136 | |
| 7137 | /* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 7138 | #define I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 7139 | #define I2C_GR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 7140 | #define I2C_GR_BRIDGE_REVISION_MINOR_BITS 8 |
| 7141 | #define I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 7142 | |
| 7143 | |
| 7144 | /**************************************************************************** |
| 7145 | * I2C_GR_BRIDGE :: CTRL |
| 7146 | ***************************************************************************/ |
| 7147 | /* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ |
| 7148 | #define I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe |
| 7149 | #define I2C_GR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 7150 | #define I2C_GR_BRIDGE_CTRL_reserved0_BITS 31 |
| 7151 | #define I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 |
| 7152 | |
| 7153 | /* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 7154 | #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 7155 | #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 7156 | #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 7157 | #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 7158 | #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 7159 | #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 7160 | |
| 7161 | |
| 7162 | /**************************************************************************** |
| 7163 | * I2C_GR_BRIDGE :: SPARE_SW_RESET_0 |
| 7164 | ***************************************************************************/ |
| 7165 | /* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 7166 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 7167 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 7168 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 7169 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 7170 | |
| 7171 | /* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 7172 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 7173 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 7174 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 7175 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 7176 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 7177 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 7178 | |
| 7179 | |
| 7180 | /**************************************************************************** |
| 7181 | * I2C_GR_BRIDGE :: SPARE_SW_RESET_1 |
| 7182 | ***************************************************************************/ |
| 7183 | /* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 7184 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 7185 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 7186 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 7187 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 7188 | |
| 7189 | /* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 7190 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 7191 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 7192 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 7193 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 7194 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 |
| 7195 | #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 |
| 7196 | |
| 7197 | |
| 7198 | /**************************************************************************** |
| 7199 | * BCM70012_MISC_TOP_MISC1 |
| 7200 | ***************************************************************************/ |
| 7201 | /**************************************************************************** |
| 7202 | * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 |
| 7203 | ***************************************************************************/ |
| 7204 | /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ |
| 7205 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 |
| 7206 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 |
| 7207 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 |
| 7208 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 |
| 7209 | |
| 7210 | /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ |
| 7211 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e |
| 7212 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 |
| 7213 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 |
| 7214 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 |
| 7215 | |
| 7216 | /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ |
| 7217 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 |
| 7218 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_ALIGN 0 |
| 7219 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_BITS 1 |
| 7220 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 |
| 7221 | |
| 7222 | |
| 7223 | /**************************************************************************** |
| 7224 | * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 |
| 7225 | ***************************************************************************/ |
| 7226 | /* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ |
| 7227 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff |
| 7228 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 |
| 7229 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 |
| 7230 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 |
| 7231 | |
| 7232 | |
| 7233 | /**************************************************************************** |
| 7234 | * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 |
| 7235 | ***************************************************************************/ |
| 7236 | /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ |
| 7237 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 |
| 7238 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 |
| 7239 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 |
| 7240 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 |
| 7241 | |
| 7242 | /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ |
| 7243 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e |
| 7244 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 |
| 7245 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 |
| 7246 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 |
| 7247 | |
| 7248 | /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ |
| 7249 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 |
| 7250 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_ALIGN 0 |
| 7251 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_BITS 1 |
| 7252 | #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 |
| 7253 | |
| 7254 | |
| 7255 | /**************************************************************************** |
| 7256 | * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 |
| 7257 | ***************************************************************************/ |
| 7258 | /* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ |
| 7259 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff |
| 7260 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 |
| 7261 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 |
| 7262 | #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 |
| 7263 | |
| 7264 | |
| 7265 | /**************************************************************************** |
| 7266 | * MISC1 :: TX_SW_DESC_LIST_CTRL_STS |
| 7267 | ***************************************************************************/ |
| 7268 | /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ |
| 7269 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 |
| 7270 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 |
| 7271 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 |
| 7272 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 |
| 7273 | |
| 7274 | /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ |
| 7275 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 |
| 7276 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 |
| 7277 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 |
| 7278 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 |
| 7279 | |
| 7280 | /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ |
| 7281 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 |
| 7282 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 |
| 7283 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 |
| 7284 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 |
| 7285 | |
| 7286 | /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ |
| 7287 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 |
| 7288 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 |
| 7289 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 |
| 7290 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 |
| 7291 | |
| 7292 | /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ |
| 7293 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 |
| 7294 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 |
| 7295 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 |
| 7296 | #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 |
| 7297 | |
| 7298 | |
| 7299 | /**************************************************************************** |
| 7300 | * MISC1 :: TX_DMA_ERROR_STATUS |
| 7301 | ***************************************************************************/ |
| 7302 | /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ |
| 7303 | #define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 |
| 7304 | #define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 |
| 7305 | #define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 |
| 7306 | #define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 |
| 7307 | |
| 7308 | /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ |
| 7309 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 |
| 7310 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 |
| 7311 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 |
| 7312 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 |
| 7313 | |
| 7314 | /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ |
| 7315 | #define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 |
| 7316 | #define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 |
| 7317 | #define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 |
| 7318 | #define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 |
| 7319 | |
| 7320 | /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ |
| 7321 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 |
| 7322 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 |
| 7323 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 |
| 7324 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 |
| 7325 | |
| 7326 | /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ |
| 7327 | #define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 |
| 7328 | #define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 |
| 7329 | #define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 |
| 7330 | #define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 |
| 7331 | |
| 7332 | /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ |
| 7333 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 |
| 7334 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 |
| 7335 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 |
| 7336 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 |
| 7337 | |
| 7338 | /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ |
| 7339 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 |
| 7340 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 |
| 7341 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 |
| 7342 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 |
| 7343 | |
| 7344 | /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ |
| 7345 | #define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 |
| 7346 | #define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 |
| 7347 | #define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 |
| 7348 | #define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 |
| 7349 | |
| 7350 | /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ |
| 7351 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 |
| 7352 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 |
| 7353 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 |
| 7354 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 |
| 7355 | |
| 7356 | /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ |
| 7357 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 |
| 7358 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 |
| 7359 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 |
| 7360 | #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 |
| 7361 | |
| 7362 | /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ |
| 7363 | #define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 |
| 7364 | #define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 |
| 7365 | #define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 |
| 7366 | #define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 |
| 7367 | |
| 7368 | |
| 7369 | /**************************************************************************** |
| 7370 | * MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR |
| 7371 | ***************************************************************************/ |
| 7372 | /* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ |
| 7373 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 |
| 7374 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_ALIGN 0 |
| 7375 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_BITS 27 |
| 7376 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 |
| 7377 | |
| 7378 | /* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ |
| 7379 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f |
| 7380 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 |
| 7381 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 |
| 7382 | #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 |
| 7383 | |
| 7384 | |
| 7385 | /**************************************************************************** |
| 7386 | * MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR |
| 7387 | ***************************************************************************/ |
| 7388 | /* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ |
| 7389 | #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff |
| 7390 | #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_ALIGN 0 |
| 7391 | #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_BITS 32 |
| 7392 | #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 |
| 7393 | |
| 7394 | |
| 7395 | /**************************************************************************** |
| 7396 | * MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM |
| 7397 | ***************************************************************************/ |
| 7398 | /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ |
| 7399 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 |
| 7400 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 |
| 7401 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_BITS 8 |
| 7402 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 |
| 7403 | |
| 7404 | /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ |
| 7405 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc |
| 7406 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_ALIGN 0 |
| 7407 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_BITS 22 |
| 7408 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 |
| 7409 | |
| 7410 | /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ |
| 7411 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 |
| 7412 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 |
| 7413 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_BITS 2 |
| 7414 | #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 |
| 7415 | |
| 7416 | |
| 7417 | /**************************************************************************** |
| 7418 | * MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR |
| 7419 | ***************************************************************************/ |
| 7420 | /* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ |
| 7421 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 |
| 7422 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_ALIGN 0 |
| 7423 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_BITS 27 |
| 7424 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 |
| 7425 | |
| 7426 | /* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ |
| 7427 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f |
| 7428 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 |
| 7429 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 |
| 7430 | #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 |
| 7431 | |
| 7432 | |
| 7433 | /**************************************************************************** |
| 7434 | * MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR |
| 7435 | ***************************************************************************/ |
| 7436 | /* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ |
| 7437 | #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff |
| 7438 | #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_ALIGN 0 |
| 7439 | #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_BITS 32 |
| 7440 | #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 |
| 7441 | |
| 7442 | |
| 7443 | /**************************************************************************** |
| 7444 | * MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM |
| 7445 | ***************************************************************************/ |
| 7446 | /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ |
| 7447 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 |
| 7448 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 |
| 7449 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_BITS 8 |
| 7450 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 |
| 7451 | |
| 7452 | /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ |
| 7453 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc |
| 7454 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_ALIGN 0 |
| 7455 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_BITS 22 |
| 7456 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 |
| 7457 | |
| 7458 | /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ |
| 7459 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 |
| 7460 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 |
| 7461 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_BITS 2 |
| 7462 | #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 |
| 7463 | |
| 7464 | |
| 7465 | /**************************************************************************** |
| 7466 | * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 |
| 7467 | ***************************************************************************/ |
| 7468 | /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ |
| 7469 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 |
| 7470 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 |
| 7471 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 |
| 7472 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 |
| 7473 | |
| 7474 | /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ |
| 7475 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e |
| 7476 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 |
| 7477 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 |
| 7478 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 |
| 7479 | |
| 7480 | /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ |
| 7481 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 |
| 7482 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 |
| 7483 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 |
| 7484 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 |
| 7485 | |
| 7486 | |
| 7487 | /**************************************************************************** |
| 7488 | * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 |
| 7489 | ***************************************************************************/ |
| 7490 | /* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ |
| 7491 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff |
| 7492 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 |
| 7493 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 |
| 7494 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 |
| 7495 | |
| 7496 | |
| 7497 | /**************************************************************************** |
| 7498 | * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 |
| 7499 | ***************************************************************************/ |
| 7500 | /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ |
| 7501 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 |
| 7502 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 |
| 7503 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 |
| 7504 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 |
| 7505 | |
| 7506 | /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ |
| 7507 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e |
| 7508 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 |
| 7509 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 |
| 7510 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 |
| 7511 | |
| 7512 | /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ |
| 7513 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 |
| 7514 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 |
| 7515 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 |
| 7516 | #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 |
| 7517 | |
| 7518 | |
| 7519 | /**************************************************************************** |
| 7520 | * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 |
| 7521 | ***************************************************************************/ |
| 7522 | /* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ |
| 7523 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff |
| 7524 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 |
| 7525 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 |
| 7526 | #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 |
| 7527 | |
| 7528 | |
| 7529 | /**************************************************************************** |
| 7530 | * MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS |
| 7531 | ***************************************************************************/ |
| 7532 | /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ |
| 7533 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 |
| 7534 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 |
| 7535 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 |
| 7536 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 |
| 7537 | |
| 7538 | /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ |
| 7539 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 |
| 7540 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 |
| 7541 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 |
| 7542 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 |
| 7543 | |
| 7544 | /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ |
| 7545 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 |
| 7546 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 |
| 7547 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 |
| 7548 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 |
| 7549 | |
| 7550 | /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ |
| 7551 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 |
| 7552 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 |
| 7553 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 |
| 7554 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 |
| 7555 | |
| 7556 | /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ |
| 7557 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 |
| 7558 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 |
| 7559 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 |
| 7560 | #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 |
| 7561 | |
| 7562 | |
| 7563 | /**************************************************************************** |
| 7564 | * MISC1 :: Y_RX_ERROR_STATUS |
| 7565 | ***************************************************************************/ |
| 7566 | /* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ |
| 7567 | #define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 |
| 7568 | #define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 |
| 7569 | #define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 |
| 7570 | #define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 |
| 7571 | |
| 7572 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ |
| 7573 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 |
| 7574 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 |
| 7575 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 |
| 7576 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 |
| 7577 | |
| 7578 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ |
| 7579 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 |
| 7580 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 |
| 7581 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 |
| 7582 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 |
| 7583 | |
| 7584 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ |
| 7585 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 |
| 7586 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 |
| 7587 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 |
| 7588 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 |
| 7589 | |
| 7590 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ |
| 7591 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 |
| 7592 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 |
| 7593 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 |
| 7594 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 |
| 7595 | |
| 7596 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ |
| 7597 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 |
| 7598 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 |
| 7599 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 |
| 7600 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 |
| 7601 | |
| 7602 | /* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ |
| 7603 | #define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 |
| 7604 | #define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 |
| 7605 | #define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 |
| 7606 | #define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 |
| 7607 | |
| 7608 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ |
| 7609 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 |
| 7610 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 |
| 7611 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 |
| 7612 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 |
| 7613 | |
| 7614 | /* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ |
| 7615 | #define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 |
| 7616 | #define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 |
| 7617 | #define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 |
| 7618 | #define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 |
| 7619 | |
| 7620 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ |
| 7621 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 |
| 7622 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 |
| 7623 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 |
| 7624 | #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 |
| 7625 | |
| 7626 | /* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ |
| 7627 | #define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c |
| 7628 | #define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 |
| 7629 | #define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 |
| 7630 | #define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 |
| 7631 | |
| 7632 | /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ |
| 7633 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 |
| 7634 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 |
| 7635 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 |
| 7636 | #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 |
| 7637 | |
| 7638 | /* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ |
| 7639 | #define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 |
| 7640 | #define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 |
| 7641 | #define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 |
| 7642 | #define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 |
| 7643 | |
| 7644 | |
| 7645 | /**************************************************************************** |
| 7646 | * MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR |
| 7647 | ***************************************************************************/ |
| 7648 | /* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ |
| 7649 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 |
| 7650 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 |
| 7651 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 |
| 7652 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 |
| 7653 | |
| 7654 | /* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ |
| 7655 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f |
| 7656 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 |
| 7657 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 |
| 7658 | #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 |
| 7659 | |
| 7660 | |
| 7661 | /**************************************************************************** |
| 7662 | * MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR |
| 7663 | ***************************************************************************/ |
| 7664 | /* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ |
| 7665 | #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff |
| 7666 | #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 |
| 7667 | #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 |
| 7668 | #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 |
| 7669 | |
| 7670 | |
| 7671 | /**************************************************************************** |
| 7672 | * MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT |
| 7673 | ***************************************************************************/ |
| 7674 | /* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ |
| 7675 | #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff |
| 7676 | #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 |
| 7677 | #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 |
| 7678 | #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 |
| 7679 | |
| 7680 | |
| 7681 | /**************************************************************************** |
| 7682 | * MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR |
| 7683 | ***************************************************************************/ |
| 7684 | /* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ |
| 7685 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 |
| 7686 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 |
| 7687 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 |
| 7688 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 |
| 7689 | |
| 7690 | /* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ |
| 7691 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f |
| 7692 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 |
| 7693 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 |
| 7694 | #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 |
| 7695 | |
| 7696 | |
| 7697 | /**************************************************************************** |
| 7698 | * MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR |
| 7699 | ***************************************************************************/ |
| 7700 | /* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ |
| 7701 | #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff |
| 7702 | #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 |
| 7703 | #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 |
| 7704 | #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 |
| 7705 | |
| 7706 | |
| 7707 | /**************************************************************************** |
| 7708 | * MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT |
| 7709 | ***************************************************************************/ |
| 7710 | /* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ |
| 7711 | #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff |
| 7712 | #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 |
| 7713 | #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 |
| 7714 | #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 |
| 7715 | |
| 7716 | |
| 7717 | /**************************************************************************** |
| 7718 | * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 |
| 7719 | ***************************************************************************/ |
| 7720 | /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ |
| 7721 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 |
| 7722 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 |
| 7723 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 |
| 7724 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 |
| 7725 | |
| 7726 | /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ |
| 7727 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e |
| 7728 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 |
| 7729 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 |
| 7730 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 |
| 7731 | |
| 7732 | /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ |
| 7733 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 |
| 7734 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 |
| 7735 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 |
| 7736 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 |
| 7737 | |
| 7738 | |
| 7739 | /**************************************************************************** |
| 7740 | * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 |
| 7741 | ***************************************************************************/ |
| 7742 | /* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ |
| 7743 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff |
| 7744 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 |
| 7745 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 |
| 7746 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 |
| 7747 | |
| 7748 | |
| 7749 | /**************************************************************************** |
| 7750 | * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 |
| 7751 | ***************************************************************************/ |
| 7752 | /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ |
| 7753 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 |
| 7754 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 |
| 7755 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 |
| 7756 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 |
| 7757 | |
| 7758 | /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ |
| 7759 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e |
| 7760 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 |
| 7761 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 |
| 7762 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 |
| 7763 | |
| 7764 | /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ |
| 7765 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 |
| 7766 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 |
| 7767 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 |
| 7768 | #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 |
| 7769 | |
| 7770 | |
| 7771 | /**************************************************************************** |
| 7772 | * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 |
| 7773 | ***************************************************************************/ |
| 7774 | /* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ |
| 7775 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff |
| 7776 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 |
| 7777 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 |
| 7778 | #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 |
| 7779 | |
| 7780 | |
| 7781 | /**************************************************************************** |
| 7782 | * MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS |
| 7783 | ***************************************************************************/ |
| 7784 | /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ |
| 7785 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 |
| 7786 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 |
| 7787 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 |
| 7788 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 |
| 7789 | |
| 7790 | /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ |
| 7791 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 |
| 7792 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 |
| 7793 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 |
| 7794 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 |
| 7795 | |
| 7796 | /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ |
| 7797 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 |
| 7798 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 |
| 7799 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 |
| 7800 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 |
| 7801 | |
| 7802 | /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ |
| 7803 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 |
| 7804 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 |
| 7805 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 |
| 7806 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 |
| 7807 | |
| 7808 | /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ |
| 7809 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 |
| 7810 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 |
| 7811 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 |
| 7812 | #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 |
| 7813 | |
| 7814 | |
| 7815 | /**************************************************************************** |
| 7816 | * MISC1 :: UV_RX_ERROR_STATUS |
| 7817 | ***************************************************************************/ |
| 7818 | /* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ |
| 7819 | #define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 |
| 7820 | #define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 |
| 7821 | #define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 |
| 7822 | #define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 |
| 7823 | |
| 7824 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ |
| 7825 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 |
| 7826 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 |
| 7827 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 |
| 7828 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 |
| 7829 | |
| 7830 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ |
| 7831 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 |
| 7832 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 |
| 7833 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 |
| 7834 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 |
| 7835 | |
| 7836 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ |
| 7837 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 |
| 7838 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 |
| 7839 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 |
| 7840 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 |
| 7841 | |
| 7842 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ |
| 7843 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 |
| 7844 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 |
| 7845 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 |
| 7846 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 |
| 7847 | |
| 7848 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ |
| 7849 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 |
| 7850 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 |
| 7851 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 |
| 7852 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 |
| 7853 | |
| 7854 | /* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ |
| 7855 | #define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 |
| 7856 | #define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 |
| 7857 | #define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 |
| 7858 | #define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 |
| 7859 | |
| 7860 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ |
| 7861 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 |
| 7862 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 |
| 7863 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 |
| 7864 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 |
| 7865 | |
| 7866 | /* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ |
| 7867 | #define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 |
| 7868 | #define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 |
| 7869 | #define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 |
| 7870 | #define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 |
| 7871 | |
| 7872 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ |
| 7873 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 |
| 7874 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 |
| 7875 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 |
| 7876 | #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 |
| 7877 | |
| 7878 | /* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ |
| 7879 | #define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c |
| 7880 | #define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 |
| 7881 | #define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 |
| 7882 | #define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 |
| 7883 | |
| 7884 | /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ |
| 7885 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 |
| 7886 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 |
| 7887 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 |
| 7888 | #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 |
| 7889 | |
| 7890 | /* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ |
| 7891 | #define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 |
| 7892 | #define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 |
| 7893 | #define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 |
| 7894 | #define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 |
| 7895 | |
| 7896 | |
| 7897 | /**************************************************************************** |
| 7898 | * MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR |
| 7899 | ***************************************************************************/ |
| 7900 | /* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ |
| 7901 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 |
| 7902 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 |
| 7903 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 |
| 7904 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 |
| 7905 | |
| 7906 | /* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ |
| 7907 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f |
| 7908 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 |
| 7909 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 |
| 7910 | #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 |
| 7911 | |
| 7912 | |
| 7913 | /**************************************************************************** |
| 7914 | * MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR |
| 7915 | ***************************************************************************/ |
| 7916 | /* MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ |
| 7917 | #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff |
| 7918 | #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 |
| 7919 | #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 |
| 7920 | #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 |
| 7921 | |
| 7922 | |
| 7923 | /**************************************************************************** |
| 7924 | * MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT |
| 7925 | ***************************************************************************/ |
| 7926 | /* MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ |
| 7927 | #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff |
| 7928 | #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 |
| 7929 | #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 |
| 7930 | #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 |
| 7931 | |
| 7932 | |
| 7933 | /**************************************************************************** |
| 7934 | * MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR |
| 7935 | ***************************************************************************/ |
| 7936 | /* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ |
| 7937 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 |
| 7938 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 |
| 7939 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 |
| 7940 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 |
| 7941 | |
| 7942 | /* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ |
| 7943 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f |
| 7944 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 |
| 7945 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 |
| 7946 | #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 |
| 7947 | |
| 7948 | |
| 7949 | /**************************************************************************** |
| 7950 | * MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR |
| 7951 | ***************************************************************************/ |
| 7952 | /* MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ |
| 7953 | #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff |
| 7954 | #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 |
| 7955 | #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 |
| 7956 | #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 |
| 7957 | |
| 7958 | |
| 7959 | /**************************************************************************** |
| 7960 | * MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT |
| 7961 | ***************************************************************************/ |
| 7962 | /* MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ |
| 7963 | #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff |
| 7964 | #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 |
| 7965 | #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 |
| 7966 | #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 |
| 7967 | |
| 7968 | |
| 7969 | /**************************************************************************** |
| 7970 | * MISC1 :: DMA_DEBUG_OPTIONS_REG |
| 7971 | ***************************************************************************/ |
| 7972 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ |
| 7973 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 |
| 7974 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_ALIGN 0 |
| 7975 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_BITS 1 |
| 7976 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 |
| 7977 | |
| 7978 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ |
| 7979 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 |
| 7980 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_ALIGN 0 |
| 7981 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_BITS 1 |
| 7982 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 |
| 7983 | |
| 7984 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ |
| 7985 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 |
| 7986 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_ALIGN 0 |
| 7987 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_BITS 1 |
| 7988 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 |
| 7989 | |
| 7990 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ |
| 7991 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 |
| 7992 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_ALIGN 0 |
| 7993 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_BITS 1 |
| 7994 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 |
| 7995 | |
| 7996 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ |
| 7997 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 |
| 7998 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_ALIGN 0 |
| 7999 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_BITS 23 |
| 8000 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 |
| 8001 | |
| 8002 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ |
| 8003 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 |
| 8004 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_ALIGN 0 |
| 8005 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_BITS 1 |
| 8006 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 |
| 8007 | |
| 8008 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ |
| 8009 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 |
| 8010 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_ALIGN 0 |
| 8011 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_BITS 1 |
| 8012 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 |
| 8013 | |
| 8014 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ |
| 8015 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 |
| 8016 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_ALIGN 0 |
| 8017 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_BITS 1 |
| 8018 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 |
| 8019 | |
| 8020 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ |
| 8021 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 |
| 8022 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_ALIGN 0 |
| 8023 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_BITS 1 |
| 8024 | #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 |
| 8025 | |
| 8026 | /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ |
| 8027 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 |
| 8028 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_ALIGN 0 |
| 8029 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_BITS 1 |
| 8030 | #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 |
| 8031 | |
| 8032 | |
| 8033 | /**************************************************************************** |
| 8034 | * MISC1 :: READ_CHANNEL_ERROR_STATUS |
| 8035 | ***************************************************************************/ |
| 8036 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ |
| 8037 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 |
| 8038 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_ALIGN 0 |
| 8039 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_BITS 4 |
| 8040 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 |
| 8041 | |
| 8042 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ |
| 8043 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 |
| 8044 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_ALIGN 0 |
| 8045 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_BITS 4 |
| 8046 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 |
| 8047 | |
| 8048 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ |
| 8049 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 |
| 8050 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_ALIGN 0 |
| 8051 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_BITS 4 |
| 8052 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 |
| 8053 | |
| 8054 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ |
| 8055 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 |
| 8056 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_ALIGN 0 |
| 8057 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_BITS 4 |
| 8058 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 |
| 8059 | |
| 8060 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ |
| 8061 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 |
| 8062 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_ALIGN 0 |
| 8063 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_BITS 4 |
| 8064 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 |
| 8065 | |
| 8066 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ |
| 8067 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 |
| 8068 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_ALIGN 0 |
| 8069 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_BITS 4 |
| 8070 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 |
| 8071 | |
| 8072 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ |
| 8073 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 |
| 8074 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_ALIGN 0 |
| 8075 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_BITS 4 |
| 8076 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 |
| 8077 | |
| 8078 | /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ |
| 8079 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f |
| 8080 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_ALIGN 0 |
| 8081 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_BITS 4 |
| 8082 | #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 |
| 8083 | |
| 8084 | |
| 8085 | /**************************************************************************** |
| 8086 | * MISC1 :: PCIE_DMA_CTRL |
| 8087 | ***************************************************************************/ |
| 8088 | /* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ |
| 8089 | #define MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 |
| 8090 | #define MISC1_PCIE_DMA_CTRL_reserved0_ALIGN 0 |
| 8091 | #define MISC1_PCIE_DMA_CTRL_reserved0_BITS 14 |
| 8092 | #define MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 |
| 8093 | |
| 8094 | /* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ |
| 8095 | #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 |
| 8096 | #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_ALIGN 0 |
| 8097 | #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_BITS 2 |
| 8098 | #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 |
| 8099 | |
| 8100 | /* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:10] */ |
| 8101 | #define MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fc00 |
| 8102 | #define MISC1_PCIE_DMA_CTRL_reserved1_ALIGN 0 |
| 8103 | #define MISC1_PCIE_DMA_CTRL_reserved1_BITS 6 |
| 8104 | #define MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 10 |
| 8105 | |
| 8106 | /* MISC1 :: PCIE_DMA_CTRL :: EN_WEIGHTED_RR [09:09] */ |
| 8107 | #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_MASK 0x00000200 |
| 8108 | #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_ALIGN 0 |
| 8109 | #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_BITS 1 |
| 8110 | #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_SHIFT 9 |
| 8111 | |
| 8112 | /* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ |
| 8113 | #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 |
| 8114 | #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_ALIGN 0 |
| 8115 | #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_BITS 1 |
| 8116 | #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 |
| 8117 | |
| 8118 | /* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ |
| 8119 | #define MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 |
| 8120 | #define MISC1_PCIE_DMA_CTRL_reserved2_ALIGN 0 |
| 8121 | #define MISC1_PCIE_DMA_CTRL_reserved2_BITS 3 |
| 8122 | #define MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 |
| 8123 | |
| 8124 | /* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ |
| 8125 | #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 |
| 8126 | #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_ALIGN 0 |
| 8127 | #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_BITS 1 |
| 8128 | #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 |
| 8129 | |
| 8130 | /* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ |
| 8131 | #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 |
| 8132 | #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_ALIGN 0 |
| 8133 | #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_BITS 1 |
| 8134 | #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 |
| 8135 | |
| 8136 | /* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ |
| 8137 | #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 |
| 8138 | #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_ALIGN 0 |
| 8139 | #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_BITS 3 |
| 8140 | #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 |
| 8141 | |
| 8142 | |
| 8143 | /**************************************************************************** |
| 8144 | * BCM70012_MISC_TOP_MISC2 |
| 8145 | ***************************************************************************/ |
| 8146 | /**************************************************************************** |
| 8147 | * MISC2 :: GLOBAL_CTRL |
| 8148 | ***************************************************************************/ |
| 8149 | /* MISC2 :: GLOBAL_CTRL :: reserved0 [31:21] */ |
| 8150 | #define MISC2_GLOBAL_CTRL_reserved0_MASK 0xffe00000 |
| 8151 | #define MISC2_GLOBAL_CTRL_reserved0_ALIGN 0 |
| 8152 | #define MISC2_GLOBAL_CTRL_reserved0_BITS 11 |
| 8153 | #define MISC2_GLOBAL_CTRL_reserved0_SHIFT 21 |
| 8154 | |
| 8155 | /* MISC2 :: GLOBAL_CTRL :: EN_WRITE_ALL [20:20] */ |
| 8156 | #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_MASK 0x00100000 |
| 8157 | #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_ALIGN 0 |
| 8158 | #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_BITS 1 |
| 8159 | #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_SHIFT 20 |
| 8160 | |
| 8161 | /* MISC2 :: GLOBAL_CTRL :: reserved1 [19:17] */ |
| 8162 | #define MISC2_GLOBAL_CTRL_reserved1_MASK 0x000e0000 |
| 8163 | #define MISC2_GLOBAL_CTRL_reserved1_ALIGN 0 |
| 8164 | #define MISC2_GLOBAL_CTRL_reserved1_BITS 3 |
| 8165 | #define MISC2_GLOBAL_CTRL_reserved1_SHIFT 17 |
| 8166 | |
| 8167 | /* MISC2 :: GLOBAL_CTRL :: EN_SINGLE_DMA [16:16] */ |
| 8168 | #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_MASK 0x00010000 |
| 8169 | #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_ALIGN 0 |
| 8170 | #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_BITS 1 |
| 8171 | #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_SHIFT 16 |
| 8172 | |
| 8173 | /* MISC2 :: GLOBAL_CTRL :: reserved2 [15:11] */ |
| 8174 | #define MISC2_GLOBAL_CTRL_reserved2_MASK 0x0000f800 |
| 8175 | #define MISC2_GLOBAL_CTRL_reserved2_ALIGN 0 |
| 8176 | #define MISC2_GLOBAL_CTRL_reserved2_BITS 5 |
| 8177 | #define MISC2_GLOBAL_CTRL_reserved2_SHIFT 11 |
| 8178 | |
| 8179 | /* MISC2 :: GLOBAL_CTRL :: Y_UV_FIFO_LEN_SEL [10:10] */ |
| 8180 | #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_MASK 0x00000400 |
| 8181 | #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_ALIGN 0 |
| 8182 | #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_BITS 1 |
| 8183 | #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_SHIFT 10 |
| 8184 | |
| 8185 | /* MISC2 :: GLOBAL_CTRL :: ODD_DE_EOFRST_DIS [09:09] */ |
| 8186 | #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_MASK 0x00000200 |
| 8187 | #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_ALIGN 0 |
| 8188 | #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_BITS 1 |
| 8189 | #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_SHIFT 9 |
| 8190 | |
| 8191 | /* MISC2 :: GLOBAL_CTRL :: DIS_BIT_STUFFING [08:08] */ |
| 8192 | #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_MASK 0x00000100 |
| 8193 | #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_ALIGN 0 |
| 8194 | #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_BITS 1 |
| 8195 | #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_SHIFT 8 |
| 8196 | |
| 8197 | /* MISC2 :: GLOBAL_CTRL :: reserved3 [07:05] */ |
| 8198 | #define MISC2_GLOBAL_CTRL_reserved3_MASK 0x000000e0 |
| 8199 | #define MISC2_GLOBAL_CTRL_reserved3_ALIGN 0 |
| 8200 | #define MISC2_GLOBAL_CTRL_reserved3_BITS 3 |
| 8201 | #define MISC2_GLOBAL_CTRL_reserved3_SHIFT 5 |
| 8202 | |
| 8203 | /* MISC2 :: GLOBAL_CTRL :: EN_PROG_MODE [04:04] */ |
| 8204 | #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_MASK 0x00000010 |
| 8205 | #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_ALIGN 0 |
| 8206 | #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_BITS 1 |
| 8207 | #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_SHIFT 4 |
| 8208 | |
| 8209 | /* MISC2 :: GLOBAL_CTRL :: reserved4 [03:01] */ |
| 8210 | #define MISC2_GLOBAL_CTRL_reserved4_MASK 0x0000000e |
| 8211 | #define MISC2_GLOBAL_CTRL_reserved4_ALIGN 0 |
| 8212 | #define MISC2_GLOBAL_CTRL_reserved4_BITS 3 |
| 8213 | #define MISC2_GLOBAL_CTRL_reserved4_SHIFT 1 |
| 8214 | |
| 8215 | /* MISC2 :: GLOBAL_CTRL :: EN_188B [00:00] */ |
| 8216 | #define MISC2_GLOBAL_CTRL_EN_188B_MASK 0x00000001 |
| 8217 | #define MISC2_GLOBAL_CTRL_EN_188B_ALIGN 0 |
| 8218 | #define MISC2_GLOBAL_CTRL_EN_188B_BITS 1 |
| 8219 | #define MISC2_GLOBAL_CTRL_EN_188B_SHIFT 0 |
| 8220 | |
| 8221 | |
| 8222 | /**************************************************************************** |
| 8223 | * MISC2 :: INTERNAL_STATUS |
| 8224 | ***************************************************************************/ |
| 8225 | /* MISC2 :: INTERNAL_STATUS :: reserved0 [31:12] */ |
| 8226 | #define MISC2_INTERNAL_STATUS_reserved0_MASK 0xfffff000 |
| 8227 | #define MISC2_INTERNAL_STATUS_reserved0_ALIGN 0 |
| 8228 | #define MISC2_INTERNAL_STATUS_reserved0_BITS 20 |
| 8229 | #define MISC2_INTERNAL_STATUS_reserved0_SHIFT 12 |
| 8230 | |
| 8231 | /* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_FULL [11:11] */ |
| 8232 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_MASK 0x00000800 |
| 8233 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_ALIGN 0 |
| 8234 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_BITS 1 |
| 8235 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_SHIFT 11 |
| 8236 | |
| 8237 | /* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_FULL [10:10] */ |
| 8238 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_MASK 0x00000400 |
| 8239 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_ALIGN 0 |
| 8240 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_BITS 1 |
| 8241 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_SHIFT 10 |
| 8242 | |
| 8243 | /* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_FULL [09:09] */ |
| 8244 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 |
| 8245 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_ALIGN 0 |
| 8246 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_BITS 1 |
| 8247 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_SHIFT 9 |
| 8248 | |
| 8249 | /* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_FULL [08:08] */ |
| 8250 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_MASK 0x00000100 |
| 8251 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_ALIGN 0 |
| 8252 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_BITS 1 |
| 8253 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_SHIFT 8 |
| 8254 | |
| 8255 | /* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_EMPTY [07:07] */ |
| 8256 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000080 |
| 8257 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 |
| 8258 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_BITS 1 |
| 8259 | #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_SHIFT 7 |
| 8260 | |
| 8261 | /* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_EMPTY [06:06] */ |
| 8262 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_MASK 0x00000040 |
| 8263 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_ALIGN 0 |
| 8264 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_BITS 1 |
| 8265 | #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_SHIFT 6 |
| 8266 | |
| 8267 | /* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_EMPTY [05:05] */ |
| 8268 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 |
| 8269 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 |
| 8270 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_BITS 1 |
| 8271 | #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 |
| 8272 | |
| 8273 | /* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_EMPTY [04:04] */ |
| 8274 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_MASK 0x00000010 |
| 8275 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_ALIGN 0 |
| 8276 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_BITS 1 |
| 8277 | #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_SHIFT 4 |
| 8278 | |
| 8279 | /* MISC2 :: INTERNAL_STATUS :: reserved1 [03:00] */ |
| 8280 | #define MISC2_INTERNAL_STATUS_reserved1_MASK 0x0000000f |
| 8281 | #define MISC2_INTERNAL_STATUS_reserved1_ALIGN 0 |
| 8282 | #define MISC2_INTERNAL_STATUS_reserved1_BITS 4 |
| 8283 | #define MISC2_INTERNAL_STATUS_reserved1_SHIFT 0 |
| 8284 | |
| 8285 | |
| 8286 | /**************************************************************************** |
| 8287 | * MISC2 :: INTERNAL_STATUS_MUX_CTRL |
| 8288 | ***************************************************************************/ |
| 8289 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ |
| 8290 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 |
| 8291 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_ALIGN 0 |
| 8292 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_BITS 16 |
| 8293 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 |
| 8294 | |
| 8295 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ |
| 8296 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 |
| 8297 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_ALIGN 0 |
| 8298 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_BITS 1 |
| 8299 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 |
| 8300 | |
| 8301 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ |
| 8302 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 |
| 8303 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_ALIGN 0 |
| 8304 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_BITS 3 |
| 8305 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 |
| 8306 | |
| 8307 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ |
| 8308 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 |
| 8309 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_ALIGN 0 |
| 8310 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_BITS 3 |
| 8311 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 |
| 8312 | |
| 8313 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ |
| 8314 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 |
| 8315 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_ALIGN 0 |
| 8316 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_BITS 1 |
| 8317 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 |
| 8318 | |
| 8319 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ |
| 8320 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 |
| 8321 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_ALIGN 0 |
| 8322 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_BITS 4 |
| 8323 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 |
| 8324 | |
| 8325 | /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ |
| 8326 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f |
| 8327 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_ALIGN 0 |
| 8328 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_BITS 4 |
| 8329 | #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 |
| 8330 | |
| 8331 | |
| 8332 | /**************************************************************************** |
| 8333 | * MISC2 :: DEBUG_FIFO_LENGTH |
| 8334 | ***************************************************************************/ |
| 8335 | /* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ |
| 8336 | #define MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 |
| 8337 | #define MISC2_DEBUG_FIFO_LENGTH_reserved0_ALIGN 0 |
| 8338 | #define MISC2_DEBUG_FIFO_LENGTH_reserved0_BITS 11 |
| 8339 | #define MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 |
| 8340 | |
| 8341 | /* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ |
| 8342 | #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff |
| 8343 | #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_ALIGN 0 |
| 8344 | #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_BITS 21 |
| 8345 | #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 |
| 8346 | |
| 8347 | |
| 8348 | /**************************************************************************** |
| 8349 | * BCM70012_MISC_TOP_MISC3 |
| 8350 | ***************************************************************************/ |
| 8351 | /**************************************************************************** |
| 8352 | * MISC3 :: RESET_CTRL |
| 8353 | ***************************************************************************/ |
| 8354 | /* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ |
| 8355 | #define MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 |
| 8356 | #define MISC3_RESET_CTRL_reserved0_ALIGN 0 |
| 8357 | #define MISC3_RESET_CTRL_reserved0_BITS 23 |
| 8358 | #define MISC3_RESET_CTRL_reserved0_SHIFT 9 |
| 8359 | |
| 8360 | /* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ |
| 8361 | #define MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 |
| 8362 | #define MISC3_RESET_CTRL_PLL_RESET_ALIGN 0 |
| 8363 | #define MISC3_RESET_CTRL_PLL_RESET_BITS 1 |
| 8364 | #define MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 |
| 8365 | |
| 8366 | /* MISC3 :: RESET_CTRL :: reserved1 [07:02] */ |
| 8367 | #define MISC3_RESET_CTRL_reserved1_MASK 0x000000fc |
| 8368 | #define MISC3_RESET_CTRL_reserved1_ALIGN 0 |
| 8369 | #define MISC3_RESET_CTRL_reserved1_BITS 6 |
| 8370 | #define MISC3_RESET_CTRL_reserved1_SHIFT 2 |
| 8371 | |
| 8372 | /* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ |
| 8373 | #define MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 |
| 8374 | #define MISC3_RESET_CTRL_POR_RESET_ALIGN 0 |
| 8375 | #define MISC3_RESET_CTRL_POR_RESET_BITS 1 |
| 8376 | #define MISC3_RESET_CTRL_POR_RESET_SHIFT 1 |
| 8377 | |
| 8378 | /* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ |
| 8379 | #define MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 |
| 8380 | #define MISC3_RESET_CTRL_CORE_RESET_ALIGN 0 |
| 8381 | #define MISC3_RESET_CTRL_CORE_RESET_BITS 1 |
| 8382 | #define MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 |
| 8383 | |
| 8384 | |
| 8385 | /**************************************************************************** |
| 8386 | * MISC3 :: BIST_CTRL |
| 8387 | ***************************************************************************/ |
| 8388 | /* MISC3 :: BIST_CTRL :: MBIST_OVERRIDE [31:31] */ |
| 8389 | #define MISC3_BIST_CTRL_MBIST_OVERRIDE_MASK 0x80000000 |
| 8390 | #define MISC3_BIST_CTRL_MBIST_OVERRIDE_ALIGN 0 |
| 8391 | #define MISC3_BIST_CTRL_MBIST_OVERRIDE_BITS 1 |
| 8392 | #define MISC3_BIST_CTRL_MBIST_OVERRIDE_SHIFT 31 |
| 8393 | |
| 8394 | /* MISC3 :: BIST_CTRL :: reserved0 [30:15] */ |
| 8395 | #define MISC3_BIST_CTRL_reserved0_MASK 0x7fff8000 |
| 8396 | #define MISC3_BIST_CTRL_reserved0_ALIGN 0 |
| 8397 | #define MISC3_BIST_CTRL_reserved0_BITS 16 |
| 8398 | #define MISC3_BIST_CTRL_reserved0_SHIFT 15 |
| 8399 | |
| 8400 | /* MISC3 :: BIST_CTRL :: MBIST_EN_2 [14:14] */ |
| 8401 | #define MISC3_BIST_CTRL_MBIST_EN_2_MASK 0x00004000 |
| 8402 | #define MISC3_BIST_CTRL_MBIST_EN_2_ALIGN 0 |
| 8403 | #define MISC3_BIST_CTRL_MBIST_EN_2_BITS 1 |
| 8404 | #define MISC3_BIST_CTRL_MBIST_EN_2_SHIFT 14 |
| 8405 | |
| 8406 | /* MISC3 :: BIST_CTRL :: MBIST_EN_1 [13:13] */ |
| 8407 | #define MISC3_BIST_CTRL_MBIST_EN_1_MASK 0x00002000 |
| 8408 | #define MISC3_BIST_CTRL_MBIST_EN_1_ALIGN 0 |
| 8409 | #define MISC3_BIST_CTRL_MBIST_EN_1_BITS 1 |
| 8410 | #define MISC3_BIST_CTRL_MBIST_EN_1_SHIFT 13 |
| 8411 | |
| 8412 | /* MISC3 :: BIST_CTRL :: MBIST_EN_0 [12:12] */ |
| 8413 | #define MISC3_BIST_CTRL_MBIST_EN_0_MASK 0x00001000 |
| 8414 | #define MISC3_BIST_CTRL_MBIST_EN_0_ALIGN 0 |
| 8415 | #define MISC3_BIST_CTRL_MBIST_EN_0_BITS 1 |
| 8416 | #define MISC3_BIST_CTRL_MBIST_EN_0_SHIFT 12 |
| 8417 | |
| 8418 | /* MISC3 :: BIST_CTRL :: reserved1 [11:06] */ |
| 8419 | #define MISC3_BIST_CTRL_reserved1_MASK 0x00000fc0 |
| 8420 | #define MISC3_BIST_CTRL_reserved1_ALIGN 0 |
| 8421 | #define MISC3_BIST_CTRL_reserved1_BITS 6 |
| 8422 | #define MISC3_BIST_CTRL_reserved1_SHIFT 6 |
| 8423 | |
| 8424 | /* MISC3 :: BIST_CTRL :: MBIST_SETUP [05:04] */ |
| 8425 | #define MISC3_BIST_CTRL_MBIST_SETUP_MASK 0x00000030 |
| 8426 | #define MISC3_BIST_CTRL_MBIST_SETUP_ALIGN 0 |
| 8427 | #define MISC3_BIST_CTRL_MBIST_SETUP_BITS 2 |
| 8428 | #define MISC3_BIST_CTRL_MBIST_SETUP_SHIFT 4 |
| 8429 | |
| 8430 | /* MISC3 :: BIST_CTRL :: reserved2 [03:01] */ |
| 8431 | #define MISC3_BIST_CTRL_reserved2_MASK 0x0000000e |
| 8432 | #define MISC3_BIST_CTRL_reserved2_ALIGN 0 |
| 8433 | #define MISC3_BIST_CTRL_reserved2_BITS 3 |
| 8434 | #define MISC3_BIST_CTRL_reserved2_SHIFT 1 |
| 8435 | |
| 8436 | /* MISC3 :: BIST_CTRL :: MBIST_ASYNC_RESET [00:00] */ |
| 8437 | #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_MASK 0x00000001 |
| 8438 | #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_ALIGN 0 |
| 8439 | #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_BITS 1 |
| 8440 | #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_SHIFT 0 |
| 8441 | |
| 8442 | |
| 8443 | /**************************************************************************** |
| 8444 | * MISC3 :: BIST_STATUS |
| 8445 | ***************************************************************************/ |
| 8446 | /* MISC3 :: BIST_STATUS :: reserved0 [31:31] */ |
| 8447 | #define MISC3_BIST_STATUS_reserved0_MASK 0x80000000 |
| 8448 | #define MISC3_BIST_STATUS_reserved0_ALIGN 0 |
| 8449 | #define MISC3_BIST_STATUS_reserved0_BITS 1 |
| 8450 | #define MISC3_BIST_STATUS_reserved0_SHIFT 31 |
| 8451 | |
| 8452 | /* MISC3 :: BIST_STATUS :: MBIST_GO_2 [30:30] */ |
| 8453 | #define MISC3_BIST_STATUS_MBIST_GO_2_MASK 0x40000000 |
| 8454 | #define MISC3_BIST_STATUS_MBIST_GO_2_ALIGN 0 |
| 8455 | #define MISC3_BIST_STATUS_MBIST_GO_2_BITS 1 |
| 8456 | #define MISC3_BIST_STATUS_MBIST_GO_2_SHIFT 30 |
| 8457 | |
| 8458 | /* MISC3 :: BIST_STATUS :: MBIST_GO_1 [29:29] */ |
| 8459 | #define MISC3_BIST_STATUS_MBIST_GO_1_MASK 0x20000000 |
| 8460 | #define MISC3_BIST_STATUS_MBIST_GO_1_ALIGN 0 |
| 8461 | #define MISC3_BIST_STATUS_MBIST_GO_1_BITS 1 |
| 8462 | #define MISC3_BIST_STATUS_MBIST_GO_1_SHIFT 29 |
| 8463 | |
| 8464 | /* MISC3 :: BIST_STATUS :: MBIST_GO_0 [28:28] */ |
| 8465 | #define MISC3_BIST_STATUS_MBIST_GO_0_MASK 0x10000000 |
| 8466 | #define MISC3_BIST_STATUS_MBIST_GO_0_ALIGN 0 |
| 8467 | #define MISC3_BIST_STATUS_MBIST_GO_0_BITS 1 |
| 8468 | #define MISC3_BIST_STATUS_MBIST_GO_0_SHIFT 28 |
| 8469 | |
| 8470 | /* MISC3 :: BIST_STATUS :: reserved1 [27:27] */ |
| 8471 | #define MISC3_BIST_STATUS_reserved1_MASK 0x08000000 |
| 8472 | #define MISC3_BIST_STATUS_reserved1_ALIGN 0 |
| 8473 | #define MISC3_BIST_STATUS_reserved1_BITS 1 |
| 8474 | #define MISC3_BIST_STATUS_reserved1_SHIFT 27 |
| 8475 | |
| 8476 | /* MISC3 :: BIST_STATUS :: MBIST_DONE_2 [26:26] */ |
| 8477 | #define MISC3_BIST_STATUS_MBIST_DONE_2_MASK 0x04000000 |
| 8478 | #define MISC3_BIST_STATUS_MBIST_DONE_2_ALIGN 0 |
| 8479 | #define MISC3_BIST_STATUS_MBIST_DONE_2_BITS 1 |
| 8480 | #define MISC3_BIST_STATUS_MBIST_DONE_2_SHIFT 26 |
| 8481 | |
| 8482 | /* MISC3 :: BIST_STATUS :: MBIST_DONE_1 [25:25] */ |
| 8483 | #define MISC3_BIST_STATUS_MBIST_DONE_1_MASK 0x02000000 |
| 8484 | #define MISC3_BIST_STATUS_MBIST_DONE_1_ALIGN 0 |
| 8485 | #define MISC3_BIST_STATUS_MBIST_DONE_1_BITS 1 |
| 8486 | #define MISC3_BIST_STATUS_MBIST_DONE_1_SHIFT 25 |
| 8487 | |
| 8488 | /* MISC3 :: BIST_STATUS :: MBIST_DONE_0 [24:24] */ |
| 8489 | #define MISC3_BIST_STATUS_MBIST_DONE_0_MASK 0x01000000 |
| 8490 | #define MISC3_BIST_STATUS_MBIST_DONE_0_ALIGN 0 |
| 8491 | #define MISC3_BIST_STATUS_MBIST_DONE_0_BITS 1 |
| 8492 | #define MISC3_BIST_STATUS_MBIST_DONE_0_SHIFT 24 |
| 8493 | |
| 8494 | /* MISC3 :: BIST_STATUS :: reserved2 [23:06] */ |
| 8495 | #define MISC3_BIST_STATUS_reserved2_MASK 0x00ffffc0 |
| 8496 | #define MISC3_BIST_STATUS_reserved2_ALIGN 0 |
| 8497 | #define MISC3_BIST_STATUS_reserved2_BITS 18 |
| 8498 | #define MISC3_BIST_STATUS_reserved2_SHIFT 6 |
| 8499 | |
| 8500 | /* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_2 [05:04] */ |
| 8501 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_MASK 0x00000030 |
| 8502 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_ALIGN 0 |
| 8503 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_BITS 2 |
| 8504 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_SHIFT 4 |
| 8505 | |
| 8506 | /* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_1 [03:02] */ |
| 8507 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_MASK 0x0000000c |
| 8508 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_ALIGN 0 |
| 8509 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_BITS 2 |
| 8510 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_SHIFT 2 |
| 8511 | |
| 8512 | /* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_0 [01:00] */ |
| 8513 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_MASK 0x00000003 |
| 8514 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_ALIGN 0 |
| 8515 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_BITS 2 |
| 8516 | #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_SHIFT 0 |
| 8517 | |
| 8518 | |
| 8519 | /**************************************************************************** |
| 8520 | * MISC3 :: RX_CHECKSUM |
| 8521 | ***************************************************************************/ |
| 8522 | /* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ |
| 8523 | #define MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff |
| 8524 | #define MISC3_RX_CHECKSUM_RX_CHECKSUM_ALIGN 0 |
| 8525 | #define MISC3_RX_CHECKSUM_RX_CHECKSUM_BITS 32 |
| 8526 | #define MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 |
| 8527 | |
| 8528 | |
| 8529 | /**************************************************************************** |
| 8530 | * MISC3 :: TX_CHECKSUM |
| 8531 | ***************************************************************************/ |
| 8532 | /* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ |
| 8533 | #define MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff |
| 8534 | #define MISC3_TX_CHECKSUM_TX_CHECKSUM_ALIGN 0 |
| 8535 | #define MISC3_TX_CHECKSUM_TX_CHECKSUM_BITS 32 |
| 8536 | #define MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 |
| 8537 | |
| 8538 | |
| 8539 | /**************************************************************************** |
| 8540 | * MISC3 :: ECO_CTRL_CORE |
| 8541 | ***************************************************************************/ |
| 8542 | /* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ |
| 8543 | #define MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 |
| 8544 | #define MISC3_ECO_CTRL_CORE_reserved0_ALIGN 0 |
| 8545 | #define MISC3_ECO_CTRL_CORE_reserved0_BITS 16 |
| 8546 | #define MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 |
| 8547 | |
| 8548 | /* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ |
| 8549 | #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff |
| 8550 | #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_ALIGN 0 |
| 8551 | #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_BITS 16 |
| 8552 | #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 |
| 8553 | |
| 8554 | |
| 8555 | /**************************************************************************** |
| 8556 | * MISC3 :: CSI_TEST_CTRL |
| 8557 | ***************************************************************************/ |
| 8558 | /* MISC3 :: CSI_TEST_CTRL :: ENABLE_CSI_TEST [31:31] */ |
| 8559 | #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_MASK 0x80000000 |
| 8560 | #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_ALIGN 0 |
| 8561 | #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_BITS 1 |
| 8562 | #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_SHIFT 31 |
| 8563 | |
| 8564 | /* MISC3 :: CSI_TEST_CTRL :: reserved0 [30:24] */ |
| 8565 | #define MISC3_CSI_TEST_CTRL_reserved0_MASK 0x7f000000 |
| 8566 | #define MISC3_CSI_TEST_CTRL_reserved0_ALIGN 0 |
| 8567 | #define MISC3_CSI_TEST_CTRL_reserved0_BITS 7 |
| 8568 | #define MISC3_CSI_TEST_CTRL_reserved0_SHIFT 24 |
| 8569 | |
| 8570 | /* MISC3 :: CSI_TEST_CTRL :: CSI_CLOCK_ENABLE [23:16] */ |
| 8571 | #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_MASK 0x00ff0000 |
| 8572 | #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_ALIGN 0 |
| 8573 | #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_BITS 8 |
| 8574 | #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_SHIFT 16 |
| 8575 | |
| 8576 | /* MISC3 :: CSI_TEST_CTRL :: CSI_SYNC [15:08] */ |
| 8577 | #define MISC3_CSI_TEST_CTRL_CSI_SYNC_MASK 0x0000ff00 |
| 8578 | #define MISC3_CSI_TEST_CTRL_CSI_SYNC_ALIGN 0 |
| 8579 | #define MISC3_CSI_TEST_CTRL_CSI_SYNC_BITS 8 |
| 8580 | #define MISC3_CSI_TEST_CTRL_CSI_SYNC_SHIFT 8 |
| 8581 | |
| 8582 | /* MISC3 :: CSI_TEST_CTRL :: CSI_DATA [07:00] */ |
| 8583 | #define MISC3_CSI_TEST_CTRL_CSI_DATA_MASK 0x000000ff |
| 8584 | #define MISC3_CSI_TEST_CTRL_CSI_DATA_ALIGN 0 |
| 8585 | #define MISC3_CSI_TEST_CTRL_CSI_DATA_BITS 8 |
| 8586 | #define MISC3_CSI_TEST_CTRL_CSI_DATA_SHIFT 0 |
| 8587 | |
| 8588 | |
| 8589 | /**************************************************************************** |
| 8590 | * MISC3 :: HD_DVI_TEST_CTRL |
| 8591 | ***************************************************************************/ |
| 8592 | /* MISC3 :: HD_DVI_TEST_CTRL :: reserved0 [31:25] */ |
| 8593 | #define MISC3_HD_DVI_TEST_CTRL_reserved0_MASK 0xfe000000 |
| 8594 | #define MISC3_HD_DVI_TEST_CTRL_reserved0_ALIGN 0 |
| 8595 | #define MISC3_HD_DVI_TEST_CTRL_reserved0_BITS 7 |
| 8596 | #define MISC3_HD_DVI_TEST_CTRL_reserved0_SHIFT 25 |
| 8597 | |
| 8598 | /* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_VBLANK_N [24:24] */ |
| 8599 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_MASK 0x01000000 |
| 8600 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_ALIGN 0 |
| 8601 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_BITS 1 |
| 8602 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_SHIFT 24 |
| 8603 | |
| 8604 | /* MISC3 :: HD_DVI_TEST_CTRL :: NEG_VIDO_DVI_DATA [23:12] */ |
| 8605 | #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_MASK 0x00fff000 |
| 8606 | #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_ALIGN 0 |
| 8607 | #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_BITS 12 |
| 8608 | #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_SHIFT 12 |
| 8609 | |
| 8610 | /* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_DVI_DATA [11:00] */ |
| 8611 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_MASK 0x00000fff |
| 8612 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_ALIGN 0 |
| 8613 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_BITS 12 |
| 8614 | #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_SHIFT 0 |
| 8615 | |
| 8616 | |
| 8617 | /**************************************************************************** |
| 8618 | * BCM70012_MISC_TOP_MISC_PERST |
| 8619 | ***************************************************************************/ |
| 8620 | /**************************************************************************** |
| 8621 | * MISC_PERST :: ECO_CTRL_PERST |
| 8622 | ***************************************************************************/ |
| 8623 | /* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ |
| 8624 | #define MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 |
| 8625 | #define MISC_PERST_ECO_CTRL_PERST_reserved0_ALIGN 0 |
| 8626 | #define MISC_PERST_ECO_CTRL_PERST_reserved0_BITS 16 |
| 8627 | #define MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 |
| 8628 | |
| 8629 | /* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ |
| 8630 | #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff |
| 8631 | #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_ALIGN 0 |
| 8632 | #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_BITS 16 |
| 8633 | #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 |
| 8634 | |
| 8635 | |
| 8636 | /**************************************************************************** |
| 8637 | * MISC_PERST :: DECODER_CTRL |
| 8638 | ***************************************************************************/ |
| 8639 | /* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ |
| 8640 | #define MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 |
| 8641 | #define MISC_PERST_DECODER_CTRL_reserved0_ALIGN 0 |
| 8642 | #define MISC_PERST_DECODER_CTRL_reserved0_BITS 27 |
| 8643 | #define MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 |
| 8644 | |
| 8645 | /* MISC_PERST :: DECODER_CTRL :: STOP_BCM7412_CLK [04:04] */ |
| 8646 | #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_MASK 0x00000010 |
| 8647 | #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_ALIGN 0 |
| 8648 | #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_BITS 1 |
| 8649 | #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_SHIFT 4 |
| 8650 | |
| 8651 | /* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ |
| 8652 | #define MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e |
| 8653 | #define MISC_PERST_DECODER_CTRL_reserved1_ALIGN 0 |
| 8654 | #define MISC_PERST_DECODER_CTRL_reserved1_BITS 3 |
| 8655 | #define MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 |
| 8656 | |
| 8657 | /* MISC_PERST :: DECODER_CTRL :: BCM7412_RESET [00:00] */ |
| 8658 | #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_MASK 0x00000001 |
| 8659 | #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_ALIGN 0 |
| 8660 | #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_BITS 1 |
| 8661 | #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_SHIFT 0 |
| 8662 | |
| 8663 | |
| 8664 | /**************************************************************************** |
| 8665 | * MISC_PERST :: CCE_STATUS |
| 8666 | ***************************************************************************/ |
| 8667 | /* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ |
| 8668 | #define MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 |
| 8669 | #define MISC_PERST_CCE_STATUS_CCE_DONE_ALIGN 0 |
| 8670 | #define MISC_PERST_CCE_STATUS_CCE_DONE_BITS 1 |
| 8671 | #define MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 |
| 8672 | |
| 8673 | /* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ |
| 8674 | #define MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 |
| 8675 | #define MISC_PERST_CCE_STATUS_reserved0_ALIGN 0 |
| 8676 | #define MISC_PERST_CCE_STATUS_reserved0_BITS 28 |
| 8677 | #define MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 |
| 8678 | |
| 8679 | /* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ |
| 8680 | #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 |
| 8681 | #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_ALIGN 0 |
| 8682 | #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_BITS 1 |
| 8683 | #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 |
| 8684 | |
| 8685 | /* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ |
| 8686 | #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 |
| 8687 | #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_ALIGN 0 |
| 8688 | #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_BITS 1 |
| 8689 | #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 |
| 8690 | |
| 8691 | /* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ |
| 8692 | #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 |
| 8693 | #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_ALIGN 0 |
| 8694 | #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_BITS 1 |
| 8695 | #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 |
| 8696 | |
| 8697 | |
| 8698 | /**************************************************************************** |
| 8699 | * MISC_PERST :: PCIE_DEBUG |
| 8700 | ***************************************************************************/ |
| 8701 | /* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ |
| 8702 | #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 |
| 8703 | #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_ALIGN 0 |
| 8704 | #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_BITS 16 |
| 8705 | #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 |
| 8706 | |
| 8707 | /* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:11] */ |
| 8708 | #define MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000f800 |
| 8709 | #define MISC_PERST_PCIE_DEBUG_reserved0_ALIGN 0 |
| 8710 | #define MISC_PERST_PCIE_DEBUG_reserved0_BITS 5 |
| 8711 | #define MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 11 |
| 8712 | |
| 8713 | /* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ |
| 8714 | #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 |
| 8715 | #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_ALIGN 0 |
| 8716 | #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_BITS 1 |
| 8717 | #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 |
| 8718 | |
| 8719 | /* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ |
| 8720 | #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 |
| 8721 | #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_ALIGN 0 |
| 8722 | #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_BITS 1 |
| 8723 | #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 |
| 8724 | |
| 8725 | /* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ |
| 8726 | #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 |
| 8727 | #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_ALIGN 0 |
| 8728 | #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_BITS 1 |
| 8729 | #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 |
| 8730 | |
| 8731 | /* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ |
| 8732 | #define MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 |
| 8733 | #define MISC_PERST_PCIE_DEBUG_reserved1_ALIGN 0 |
| 8734 | #define MISC_PERST_PCIE_DEBUG_reserved1_BITS 4 |
| 8735 | #define MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 |
| 8736 | |
| 8737 | /* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ |
| 8738 | #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f |
| 8739 | #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_ALIGN 0 |
| 8740 | #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_BITS 4 |
| 8741 | #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 |
| 8742 | |
| 8743 | |
| 8744 | /**************************************************************************** |
| 8745 | * MISC_PERST :: PCIE_DEBUG_STATUS |
| 8746 | ***************************************************************************/ |
| 8747 | /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:06] */ |
| 8748 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xffffffc0 |
| 8749 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_ALIGN 0 |
| 8750 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_BITS 26 |
| 8751 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 6 |
| 8752 | |
| 8753 | /* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ |
| 8754 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 |
| 8755 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_ALIGN 0 |
| 8756 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_BITS 1 |
| 8757 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 |
| 8758 | |
| 8759 | /* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ |
| 8760 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 |
| 8761 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_ALIGN 0 |
| 8762 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_BITS 1 |
| 8763 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 |
| 8764 | |
| 8765 | /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [03:02] */ |
| 8766 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000000c |
| 8767 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_ALIGN 0 |
| 8768 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_BITS 2 |
| 8769 | #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 2 |
| 8770 | |
| 8771 | /* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ |
| 8772 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 |
| 8773 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_ALIGN 0 |
| 8774 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_BITS 1 |
| 8775 | #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 |
| 8776 | |
| 8777 | /* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ |
| 8778 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 |
| 8779 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_ALIGN 0 |
| 8780 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_BITS 1 |
| 8781 | #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 |
| 8782 | |
| 8783 | |
| 8784 | /**************************************************************************** |
| 8785 | * MISC_PERST :: VREG_CTRL |
| 8786 | ***************************************************************************/ |
| 8787 | /* MISC_PERST :: VREG_CTRL :: reserved0 [31:08] */ |
| 8788 | #define MISC_PERST_VREG_CTRL_reserved0_MASK 0xffffff00 |
| 8789 | #define MISC_PERST_VREG_CTRL_reserved0_ALIGN 0 |
| 8790 | #define MISC_PERST_VREG_CTRL_reserved0_BITS 24 |
| 8791 | #define MISC_PERST_VREG_CTRL_reserved0_SHIFT 8 |
| 8792 | |
| 8793 | /* MISC_PERST :: VREG_CTRL :: VREG1P2_SEL [07:04] */ |
| 8794 | #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_MASK 0x000000f0 |
| 8795 | #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_ALIGN 0 |
| 8796 | #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_BITS 4 |
| 8797 | #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_SHIFT 4 |
| 8798 | |
| 8799 | /* MISC_PERST :: VREG_CTRL :: VREG2P5_SEL [03:00] */ |
| 8800 | #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_MASK 0x0000000f |
| 8801 | #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_ALIGN 0 |
| 8802 | #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_BITS 4 |
| 8803 | #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_SHIFT 0 |
| 8804 | |
| 8805 | |
| 8806 | /**************************************************************************** |
| 8807 | * MISC_PERST :: MEM_CTRL |
| 8808 | ***************************************************************************/ |
| 8809 | /* MISC_PERST :: MEM_CTRL :: reserved0 [31:04] */ |
| 8810 | #define MISC_PERST_MEM_CTRL_reserved0_MASK 0xfffffff0 |
| 8811 | #define MISC_PERST_MEM_CTRL_reserved0_ALIGN 0 |
| 8812 | #define MISC_PERST_MEM_CTRL_reserved0_BITS 28 |
| 8813 | #define MISC_PERST_MEM_CTRL_reserved0_SHIFT 4 |
| 8814 | |
| 8815 | /* MISC_PERST :: MEM_CTRL :: Y_RM [03:03] */ |
| 8816 | #define MISC_PERST_MEM_CTRL_Y_RM_MASK 0x00000008 |
| 8817 | #define MISC_PERST_MEM_CTRL_Y_RM_ALIGN 0 |
| 8818 | #define MISC_PERST_MEM_CTRL_Y_RM_BITS 1 |
| 8819 | #define MISC_PERST_MEM_CTRL_Y_RM_SHIFT 3 |
| 8820 | |
| 8821 | /* MISC_PERST :: MEM_CTRL :: Y_CCM [02:02] */ |
| 8822 | #define MISC_PERST_MEM_CTRL_Y_CCM_MASK 0x00000004 |
| 8823 | #define MISC_PERST_MEM_CTRL_Y_CCM_ALIGN 0 |
| 8824 | #define MISC_PERST_MEM_CTRL_Y_CCM_BITS 1 |
| 8825 | #define MISC_PERST_MEM_CTRL_Y_CCM_SHIFT 2 |
| 8826 | |
| 8827 | /* MISC_PERST :: MEM_CTRL :: UV_RM [01:01] */ |
| 8828 | #define MISC_PERST_MEM_CTRL_UV_RM_MASK 0x00000002 |
| 8829 | #define MISC_PERST_MEM_CTRL_UV_RM_ALIGN 0 |
| 8830 | #define MISC_PERST_MEM_CTRL_UV_RM_BITS 1 |
| 8831 | #define MISC_PERST_MEM_CTRL_UV_RM_SHIFT 1 |
| 8832 | |
| 8833 | /* MISC_PERST :: MEM_CTRL :: UV_CCM [00:00] */ |
| 8834 | #define MISC_PERST_MEM_CTRL_UV_CCM_MASK 0x00000001 |
| 8835 | #define MISC_PERST_MEM_CTRL_UV_CCM_ALIGN 0 |
| 8836 | #define MISC_PERST_MEM_CTRL_UV_CCM_BITS 1 |
| 8837 | #define MISC_PERST_MEM_CTRL_UV_CCM_SHIFT 0 |
| 8838 | |
| 8839 | |
| 8840 | /**************************************************************************** |
| 8841 | * MISC_PERST :: CLOCK_CTRL |
| 8842 | ***************************************************************************/ |
| 8843 | /* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:20] */ |
| 8844 | #define MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfff00000 |
| 8845 | #define MISC_PERST_CLOCK_CTRL_reserved0_ALIGN 0 |
| 8846 | #define MISC_PERST_CLOCK_CTRL_reserved0_BITS 12 |
| 8847 | #define MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 20 |
| 8848 | |
| 8849 | /* MISC_PERST :: CLOCK_CTRL :: PLL_DIV [19:16] */ |
| 8850 | #define MISC_PERST_CLOCK_CTRL_PLL_DIV_MASK 0x000f0000 |
| 8851 | #define MISC_PERST_CLOCK_CTRL_PLL_DIV_ALIGN 0 |
| 8852 | #define MISC_PERST_CLOCK_CTRL_PLL_DIV_BITS 4 |
| 8853 | #define MISC_PERST_CLOCK_CTRL_PLL_DIV_SHIFT 16 |
| 8854 | |
| 8855 | /* MISC_PERST :: CLOCK_CTRL :: PLL_MULT [15:08] */ |
| 8856 | #define MISC_PERST_CLOCK_CTRL_PLL_MULT_MASK 0x0000ff00 |
| 8857 | #define MISC_PERST_CLOCK_CTRL_PLL_MULT_ALIGN 0 |
| 8858 | #define MISC_PERST_CLOCK_CTRL_PLL_MULT_BITS 8 |
| 8859 | #define MISC_PERST_CLOCK_CTRL_PLL_MULT_SHIFT 8 |
| 8860 | |
| 8861 | /* MISC_PERST :: CLOCK_CTRL :: reserved1 [07:03] */ |
| 8862 | #define MISC_PERST_CLOCK_CTRL_reserved1_MASK 0x000000f8 |
| 8863 | #define MISC_PERST_CLOCK_CTRL_reserved1_ALIGN 0 |
| 8864 | #define MISC_PERST_CLOCK_CTRL_reserved1_BITS 5 |
| 8865 | #define MISC_PERST_CLOCK_CTRL_reserved1_SHIFT 3 |
| 8866 | |
| 8867 | /* MISC_PERST :: CLOCK_CTRL :: PLL_PWRDOWN [02:02] */ |
| 8868 | #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_MASK 0x00000004 |
| 8869 | #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_ALIGN 0 |
| 8870 | #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_BITS 1 |
| 8871 | #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_SHIFT 2 |
| 8872 | |
| 8873 | /* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ |
| 8874 | #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 |
| 8875 | #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_ALIGN 0 |
| 8876 | #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_BITS 1 |
| 8877 | #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 |
| 8878 | |
| 8879 | /* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ |
| 8880 | #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 |
| 8881 | #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_ALIGN 0 |
| 8882 | #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_BITS 1 |
| 8883 | #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 |
| 8884 | |
| 8885 | |
| 8886 | /**************************************************************************** |
| 8887 | * BCM70012_MISC_TOP_GISB_ARBITER |
| 8888 | ***************************************************************************/ |
| 8889 | /**************************************************************************** |
| 8890 | * GISB_ARBITER :: REVISION |
| 8891 | ***************************************************************************/ |
| 8892 | /* GISB_ARBITER :: REVISION :: reserved0 [31:16] */ |
| 8893 | #define GISB_ARBITER_REVISION_reserved0_MASK 0xffff0000 |
| 8894 | #define GISB_ARBITER_REVISION_reserved0_ALIGN 0 |
| 8895 | #define GISB_ARBITER_REVISION_reserved0_BITS 16 |
| 8896 | #define GISB_ARBITER_REVISION_reserved0_SHIFT 16 |
| 8897 | |
| 8898 | /* GISB_ARBITER :: REVISION :: MAJOR [15:08] */ |
| 8899 | #define GISB_ARBITER_REVISION_MAJOR_MASK 0x0000ff00 |
| 8900 | #define GISB_ARBITER_REVISION_MAJOR_ALIGN 0 |
| 8901 | #define GISB_ARBITER_REVISION_MAJOR_BITS 8 |
| 8902 | #define GISB_ARBITER_REVISION_MAJOR_SHIFT 8 |
| 8903 | |
| 8904 | /* GISB_ARBITER :: REVISION :: MINOR [07:00] */ |
| 8905 | #define GISB_ARBITER_REVISION_MINOR_MASK 0x000000ff |
| 8906 | #define GISB_ARBITER_REVISION_MINOR_ALIGN 0 |
| 8907 | #define GISB_ARBITER_REVISION_MINOR_BITS 8 |
| 8908 | #define GISB_ARBITER_REVISION_MINOR_SHIFT 0 |
| 8909 | |
| 8910 | |
| 8911 | /**************************************************************************** |
| 8912 | * GISB_ARBITER :: SCRATCH |
| 8913 | ***************************************************************************/ |
| 8914 | /* GISB_ARBITER :: SCRATCH :: scratch_bit [31:00] */ |
| 8915 | #define GISB_ARBITER_SCRATCH_scratch_bit_MASK 0xffffffff |
| 8916 | #define GISB_ARBITER_SCRATCH_scratch_bit_ALIGN 0 |
| 8917 | #define GISB_ARBITER_SCRATCH_scratch_bit_BITS 32 |
| 8918 | #define GISB_ARBITER_SCRATCH_scratch_bit_SHIFT 0 |
| 8919 | |
| 8920 | |
| 8921 | /**************************************************************************** |
| 8922 | * GISB_ARBITER :: REQ_MASK |
| 8923 | ***************************************************************************/ |
| 8924 | /* GISB_ARBITER :: REQ_MASK :: reserved0 [31:06] */ |
| 8925 | #define GISB_ARBITER_REQ_MASK_reserved0_MASK 0xffffffc0 |
| 8926 | #define GISB_ARBITER_REQ_MASK_reserved0_ALIGN 0 |
| 8927 | #define GISB_ARBITER_REQ_MASK_reserved0_BITS 26 |
| 8928 | #define GISB_ARBITER_REQ_MASK_reserved0_SHIFT 6 |
| 8929 | |
| 8930 | /* GISB_ARBITER :: REQ_MASK :: bsp [05:05] */ |
| 8931 | #define GISB_ARBITER_REQ_MASK_bsp_MASK 0x00000020 |
| 8932 | #define GISB_ARBITER_REQ_MASK_bsp_ALIGN 0 |
| 8933 | #define GISB_ARBITER_REQ_MASK_bsp_BITS 1 |
| 8934 | #define GISB_ARBITER_REQ_MASK_bsp_SHIFT 5 |
| 8935 | #define GISB_ARBITER_REQ_MASK_bsp_UNMASK 0 |
| 8936 | |
| 8937 | /* GISB_ARBITER :: REQ_MASK :: tgt [04:04] */ |
| 8938 | #define GISB_ARBITER_REQ_MASK_tgt_MASK 0x00000010 |
| 8939 | #define GISB_ARBITER_REQ_MASK_tgt_ALIGN 0 |
| 8940 | #define GISB_ARBITER_REQ_MASK_tgt_BITS 1 |
| 8941 | #define GISB_ARBITER_REQ_MASK_tgt_SHIFT 4 |
| 8942 | #define GISB_ARBITER_REQ_MASK_tgt_UNMASK 0 |
| 8943 | |
| 8944 | /* GISB_ARBITER :: REQ_MASK :: aes [03:03] */ |
| 8945 | #define GISB_ARBITER_REQ_MASK_aes_MASK 0x00000008 |
| 8946 | #define GISB_ARBITER_REQ_MASK_aes_ALIGN 0 |
| 8947 | #define GISB_ARBITER_REQ_MASK_aes_BITS 1 |
| 8948 | #define GISB_ARBITER_REQ_MASK_aes_SHIFT 3 |
| 8949 | #define GISB_ARBITER_REQ_MASK_aes_UNMASK 0 |
| 8950 | |
| 8951 | /* GISB_ARBITER :: REQ_MASK :: dci [02:02] */ |
| 8952 | #define GISB_ARBITER_REQ_MASK_dci_MASK 0x00000004 |
| 8953 | #define GISB_ARBITER_REQ_MASK_dci_ALIGN 0 |
| 8954 | #define GISB_ARBITER_REQ_MASK_dci_BITS 1 |
| 8955 | #define GISB_ARBITER_REQ_MASK_dci_SHIFT 2 |
| 8956 | #define GISB_ARBITER_REQ_MASK_dci_UNMASK 0 |
| 8957 | |
| 8958 | /* GISB_ARBITER :: REQ_MASK :: cce [01:01] */ |
| 8959 | #define GISB_ARBITER_REQ_MASK_cce_MASK 0x00000002 |
| 8960 | #define GISB_ARBITER_REQ_MASK_cce_ALIGN 0 |
| 8961 | #define GISB_ARBITER_REQ_MASK_cce_BITS 1 |
| 8962 | #define GISB_ARBITER_REQ_MASK_cce_SHIFT 1 |
| 8963 | #define GISB_ARBITER_REQ_MASK_cce_UNMASK 0 |
| 8964 | |
| 8965 | /* GISB_ARBITER :: REQ_MASK :: dbu [00:00] */ |
| 8966 | #define GISB_ARBITER_REQ_MASK_dbu_MASK 0x00000001 |
| 8967 | #define GISB_ARBITER_REQ_MASK_dbu_ALIGN 0 |
| 8968 | #define GISB_ARBITER_REQ_MASK_dbu_BITS 1 |
| 8969 | #define GISB_ARBITER_REQ_MASK_dbu_SHIFT 0 |
| 8970 | #define GISB_ARBITER_REQ_MASK_dbu_UNMASK 0 |
| 8971 | |
| 8972 | |
| 8973 | /**************************************************************************** |
| 8974 | * GISB_ARBITER :: TIMER |
| 8975 | ***************************************************************************/ |
| 8976 | /* GISB_ARBITER :: TIMER :: hi_count [31:16] */ |
| 8977 | #define GISB_ARBITER_TIMER_hi_count_MASK 0xffff0000 |
| 8978 | #define GISB_ARBITER_TIMER_hi_count_ALIGN 0 |
| 8979 | #define GISB_ARBITER_TIMER_hi_count_BITS 16 |
| 8980 | #define GISB_ARBITER_TIMER_hi_count_SHIFT 16 |
| 8981 | |
| 8982 | /* GISB_ARBITER :: TIMER :: lo_count [15:00] */ |
| 8983 | #define GISB_ARBITER_TIMER_lo_count_MASK 0x0000ffff |
| 8984 | #define GISB_ARBITER_TIMER_lo_count_ALIGN 0 |
| 8985 | #define GISB_ARBITER_TIMER_lo_count_BITS 16 |
| 8986 | #define GISB_ARBITER_TIMER_lo_count_SHIFT 0 |
| 8987 | |
| 8988 | |
| 8989 | /**************************************************************************** |
| 8990 | * GISB_ARBITER :: BP_CTRL |
| 8991 | ***************************************************************************/ |
| 8992 | /* GISB_ARBITER :: BP_CTRL :: reserved0 [31:02] */ |
| 8993 | #define GISB_ARBITER_BP_CTRL_reserved0_MASK 0xfffffffc |
| 8994 | #define GISB_ARBITER_BP_CTRL_reserved0_ALIGN 0 |
| 8995 | #define GISB_ARBITER_BP_CTRL_reserved0_BITS 30 |
| 8996 | #define GISB_ARBITER_BP_CTRL_reserved0_SHIFT 2 |
| 8997 | |
| 8998 | /* GISB_ARBITER :: BP_CTRL :: breakpoint_tea [01:01] */ |
| 8999 | #define GISB_ARBITER_BP_CTRL_breakpoint_tea_MASK 0x00000002 |
| 9000 | #define GISB_ARBITER_BP_CTRL_breakpoint_tea_ALIGN 0 |
| 9001 | #define GISB_ARBITER_BP_CTRL_breakpoint_tea_BITS 1 |
| 9002 | #define GISB_ARBITER_BP_CTRL_breakpoint_tea_SHIFT 1 |
| 9003 | #define GISB_ARBITER_BP_CTRL_breakpoint_tea_DISABLE 0 |
| 9004 | #define GISB_ARBITER_BP_CTRL_breakpoint_tea_ENABLE 1 |
| 9005 | |
| 9006 | /* GISB_ARBITER :: BP_CTRL :: repeat_capture [00:00] */ |
| 9007 | #define GISB_ARBITER_BP_CTRL_repeat_capture_MASK 0x00000001 |
| 9008 | #define GISB_ARBITER_BP_CTRL_repeat_capture_ALIGN 0 |
| 9009 | #define GISB_ARBITER_BP_CTRL_repeat_capture_BITS 1 |
| 9010 | #define GISB_ARBITER_BP_CTRL_repeat_capture_SHIFT 0 |
| 9011 | #define GISB_ARBITER_BP_CTRL_repeat_capture_DISABLE 0 |
| 9012 | #define GISB_ARBITER_BP_CTRL_repeat_capture_ENABLE 1 |
| 9013 | |
| 9014 | |
| 9015 | /**************************************************************************** |
| 9016 | * GISB_ARBITER :: BP_CAP_CLR |
| 9017 | ***************************************************************************/ |
| 9018 | /* GISB_ARBITER :: BP_CAP_CLR :: reserved0 [31:01] */ |
| 9019 | #define GISB_ARBITER_BP_CAP_CLR_reserved0_MASK 0xfffffffe |
| 9020 | #define GISB_ARBITER_BP_CAP_CLR_reserved0_ALIGN 0 |
| 9021 | #define GISB_ARBITER_BP_CAP_CLR_reserved0_BITS 31 |
| 9022 | #define GISB_ARBITER_BP_CAP_CLR_reserved0_SHIFT 1 |
| 9023 | |
| 9024 | /* GISB_ARBITER :: BP_CAP_CLR :: clear [00:00] */ |
| 9025 | #define GISB_ARBITER_BP_CAP_CLR_clear_MASK 0x00000001 |
| 9026 | #define GISB_ARBITER_BP_CAP_CLR_clear_ALIGN 0 |
| 9027 | #define GISB_ARBITER_BP_CAP_CLR_clear_BITS 1 |
| 9028 | #define GISB_ARBITER_BP_CAP_CLR_clear_SHIFT 0 |
| 9029 | |
| 9030 | |
| 9031 | /**************************************************************************** |
| 9032 | * GISB_ARBITER :: BP_START_ADDR_0 |
| 9033 | ***************************************************************************/ |
| 9034 | /* GISB_ARBITER :: BP_START_ADDR_0 :: start [31:00] */ |
| 9035 | #define GISB_ARBITER_BP_START_ADDR_0_start_MASK 0xffffffff |
| 9036 | #define GISB_ARBITER_BP_START_ADDR_0_start_ALIGN 0 |
| 9037 | #define GISB_ARBITER_BP_START_ADDR_0_start_BITS 32 |
| 9038 | #define GISB_ARBITER_BP_START_ADDR_0_start_SHIFT 0 |
| 9039 | |
| 9040 | |
| 9041 | /**************************************************************************** |
| 9042 | * GISB_ARBITER :: BP_END_ADDR_0 |
| 9043 | ***************************************************************************/ |
| 9044 | /* GISB_ARBITER :: BP_END_ADDR_0 :: end [31:00] */ |
| 9045 | #define GISB_ARBITER_BP_END_ADDR_0_end_MASK 0xffffffff |
| 9046 | #define GISB_ARBITER_BP_END_ADDR_0_end_ALIGN 0 |
| 9047 | #define GISB_ARBITER_BP_END_ADDR_0_end_BITS 32 |
| 9048 | #define GISB_ARBITER_BP_END_ADDR_0_end_SHIFT 0 |
| 9049 | |
| 9050 | |
| 9051 | /**************************************************************************** |
| 9052 | * GISB_ARBITER :: BP_READ_0 |
| 9053 | ***************************************************************************/ |
| 9054 | /* GISB_ARBITER :: BP_READ_0 :: reserved0 [31:06] */ |
| 9055 | #define GISB_ARBITER_BP_READ_0_reserved0_MASK 0xffffffc0 |
| 9056 | #define GISB_ARBITER_BP_READ_0_reserved0_ALIGN 0 |
| 9057 | #define GISB_ARBITER_BP_READ_0_reserved0_BITS 26 |
| 9058 | #define GISB_ARBITER_BP_READ_0_reserved0_SHIFT 6 |
| 9059 | |
| 9060 | /* GISB_ARBITER :: BP_READ_0 :: bsp [05:05] */ |
| 9061 | #define GISB_ARBITER_BP_READ_0_bsp_MASK 0x00000020 |
| 9062 | #define GISB_ARBITER_BP_READ_0_bsp_ALIGN 0 |
| 9063 | #define GISB_ARBITER_BP_READ_0_bsp_BITS 1 |
| 9064 | #define GISB_ARBITER_BP_READ_0_bsp_SHIFT 5 |
| 9065 | #define GISB_ARBITER_BP_READ_0_bsp_DISABLE 0 |
| 9066 | #define GISB_ARBITER_BP_READ_0_bsp_ENABLE 1 |
| 9067 | |
| 9068 | /* GISB_ARBITER :: BP_READ_0 :: aes [04:04] */ |
| 9069 | #define GISB_ARBITER_BP_READ_0_aes_MASK 0x00000010 |
| 9070 | #define GISB_ARBITER_BP_READ_0_aes_ALIGN 0 |
| 9071 | #define GISB_ARBITER_BP_READ_0_aes_BITS 1 |
| 9072 | #define GISB_ARBITER_BP_READ_0_aes_SHIFT 4 |
| 9073 | #define GISB_ARBITER_BP_READ_0_aes_DISABLE 0 |
| 9074 | #define GISB_ARBITER_BP_READ_0_aes_ENABLE 1 |
| 9075 | |
| 9076 | /* GISB_ARBITER :: BP_READ_0 :: fve [03:03] */ |
| 9077 | #define GISB_ARBITER_BP_READ_0_fve_MASK 0x00000008 |
| 9078 | #define GISB_ARBITER_BP_READ_0_fve_ALIGN 0 |
| 9079 | #define GISB_ARBITER_BP_READ_0_fve_BITS 1 |
| 9080 | #define GISB_ARBITER_BP_READ_0_fve_SHIFT 3 |
| 9081 | #define GISB_ARBITER_BP_READ_0_fve_DISABLE 0 |
| 9082 | #define GISB_ARBITER_BP_READ_0_fve_ENABLE 1 |
| 9083 | |
| 9084 | /* GISB_ARBITER :: BP_READ_0 :: tgt [02:02] */ |
| 9085 | #define GISB_ARBITER_BP_READ_0_tgt_MASK 0x00000004 |
| 9086 | #define GISB_ARBITER_BP_READ_0_tgt_ALIGN 0 |
| 9087 | #define GISB_ARBITER_BP_READ_0_tgt_BITS 1 |
| 9088 | #define GISB_ARBITER_BP_READ_0_tgt_SHIFT 2 |
| 9089 | #define GISB_ARBITER_BP_READ_0_tgt_DISABLE 0 |
| 9090 | #define GISB_ARBITER_BP_READ_0_tgt_ENABLE 1 |
| 9091 | |
| 9092 | /* GISB_ARBITER :: BP_READ_0 :: dbu [01:01] */ |
| 9093 | #define GISB_ARBITER_BP_READ_0_dbu_MASK 0x00000002 |
| 9094 | #define GISB_ARBITER_BP_READ_0_dbu_ALIGN 0 |
| 9095 | #define GISB_ARBITER_BP_READ_0_dbu_BITS 1 |
| 9096 | #define GISB_ARBITER_BP_READ_0_dbu_SHIFT 1 |
| 9097 | #define GISB_ARBITER_BP_READ_0_dbu_DISABLE 0 |
| 9098 | #define GISB_ARBITER_BP_READ_0_dbu_ENABLE 1 |
| 9099 | |
| 9100 | /* GISB_ARBITER :: BP_READ_0 :: cce [00:00] */ |
| 9101 | #define GISB_ARBITER_BP_READ_0_cce_MASK 0x00000001 |
| 9102 | #define GISB_ARBITER_BP_READ_0_cce_ALIGN 0 |
| 9103 | #define GISB_ARBITER_BP_READ_0_cce_BITS 1 |
| 9104 | #define GISB_ARBITER_BP_READ_0_cce_SHIFT 0 |
| 9105 | #define GISB_ARBITER_BP_READ_0_cce_DISABLE 0 |
| 9106 | #define GISB_ARBITER_BP_READ_0_cce_ENABLE 1 |
| 9107 | |
| 9108 | |
| 9109 | /**************************************************************************** |
| 9110 | * GISB_ARBITER :: BP_WRITE_0 |
| 9111 | ***************************************************************************/ |
| 9112 | /* GISB_ARBITER :: BP_WRITE_0 :: reserved0 [31:06] */ |
| 9113 | #define GISB_ARBITER_BP_WRITE_0_reserved0_MASK 0xffffffc0 |
| 9114 | #define GISB_ARBITER_BP_WRITE_0_reserved0_ALIGN 0 |
| 9115 | #define GISB_ARBITER_BP_WRITE_0_reserved0_BITS 26 |
| 9116 | #define GISB_ARBITER_BP_WRITE_0_reserved0_SHIFT 6 |
| 9117 | |
| 9118 | /* GISB_ARBITER :: BP_WRITE_0 :: bsp [05:05] */ |
| 9119 | #define GISB_ARBITER_BP_WRITE_0_bsp_MASK 0x00000020 |
| 9120 | #define GISB_ARBITER_BP_WRITE_0_bsp_ALIGN 0 |
| 9121 | #define GISB_ARBITER_BP_WRITE_0_bsp_BITS 1 |
| 9122 | #define GISB_ARBITER_BP_WRITE_0_bsp_SHIFT 5 |
| 9123 | #define GISB_ARBITER_BP_WRITE_0_bsp_DISABLE 0 |
| 9124 | #define GISB_ARBITER_BP_WRITE_0_bsp_ENABLE 1 |
| 9125 | |
| 9126 | /* GISB_ARBITER :: BP_WRITE_0 :: aes [04:04] */ |
| 9127 | #define GISB_ARBITER_BP_WRITE_0_aes_MASK 0x00000010 |
| 9128 | #define GISB_ARBITER_BP_WRITE_0_aes_ALIGN 0 |
| 9129 | #define GISB_ARBITER_BP_WRITE_0_aes_BITS 1 |
| 9130 | #define GISB_ARBITER_BP_WRITE_0_aes_SHIFT 4 |
| 9131 | #define GISB_ARBITER_BP_WRITE_0_aes_DISABLE 0 |
| 9132 | #define GISB_ARBITER_BP_WRITE_0_aes_ENABLE 1 |
| 9133 | |
| 9134 | /* GISB_ARBITER :: BP_WRITE_0 :: fve [03:03] */ |
| 9135 | #define GISB_ARBITER_BP_WRITE_0_fve_MASK 0x00000008 |
| 9136 | #define GISB_ARBITER_BP_WRITE_0_fve_ALIGN 0 |
| 9137 | #define GISB_ARBITER_BP_WRITE_0_fve_BITS 1 |
| 9138 | #define GISB_ARBITER_BP_WRITE_0_fve_SHIFT 3 |
| 9139 | #define GISB_ARBITER_BP_WRITE_0_fve_DISABLE 0 |
| 9140 | #define GISB_ARBITER_BP_WRITE_0_fve_ENABLE 1 |
| 9141 | |
| 9142 | /* GISB_ARBITER :: BP_WRITE_0 :: tgt [02:02] */ |
| 9143 | #define GISB_ARBITER_BP_WRITE_0_tgt_MASK 0x00000004 |
| 9144 | #define GISB_ARBITER_BP_WRITE_0_tgt_ALIGN 0 |
| 9145 | #define GISB_ARBITER_BP_WRITE_0_tgt_BITS 1 |
| 9146 | #define GISB_ARBITER_BP_WRITE_0_tgt_SHIFT 2 |
| 9147 | #define GISB_ARBITER_BP_WRITE_0_tgt_DISABLE 0 |
| 9148 | #define GISB_ARBITER_BP_WRITE_0_tgt_ENABLE 1 |
| 9149 | |
| 9150 | /* GISB_ARBITER :: BP_WRITE_0 :: dbu [01:01] */ |
| 9151 | #define GISB_ARBITER_BP_WRITE_0_dbu_MASK 0x00000002 |
| 9152 | #define GISB_ARBITER_BP_WRITE_0_dbu_ALIGN 0 |
| 9153 | #define GISB_ARBITER_BP_WRITE_0_dbu_BITS 1 |
| 9154 | #define GISB_ARBITER_BP_WRITE_0_dbu_SHIFT 1 |
| 9155 | #define GISB_ARBITER_BP_WRITE_0_dbu_DISABLE 0 |
| 9156 | #define GISB_ARBITER_BP_WRITE_0_dbu_ENABLE 1 |
| 9157 | |
| 9158 | /* GISB_ARBITER :: BP_WRITE_0 :: cce [00:00] */ |
| 9159 | #define GISB_ARBITER_BP_WRITE_0_cce_MASK 0x00000001 |
| 9160 | #define GISB_ARBITER_BP_WRITE_0_cce_ALIGN 0 |
| 9161 | #define GISB_ARBITER_BP_WRITE_0_cce_BITS 1 |
| 9162 | #define GISB_ARBITER_BP_WRITE_0_cce_SHIFT 0 |
| 9163 | #define GISB_ARBITER_BP_WRITE_0_cce_DISABLE 0 |
| 9164 | #define GISB_ARBITER_BP_WRITE_0_cce_ENABLE 1 |
| 9165 | |
| 9166 | |
| 9167 | /**************************************************************************** |
| 9168 | * GISB_ARBITER :: BP_ENABLE_0 |
| 9169 | ***************************************************************************/ |
| 9170 | /* GISB_ARBITER :: BP_ENABLE_0 :: reserved0 [31:03] */ |
| 9171 | #define GISB_ARBITER_BP_ENABLE_0_reserved0_MASK 0xfffffff8 |
| 9172 | #define GISB_ARBITER_BP_ENABLE_0_reserved0_ALIGN 0 |
| 9173 | #define GISB_ARBITER_BP_ENABLE_0_reserved0_BITS 29 |
| 9174 | #define GISB_ARBITER_BP_ENABLE_0_reserved0_SHIFT 3 |
| 9175 | |
| 9176 | /* GISB_ARBITER :: BP_ENABLE_0 :: block [02:02] */ |
| 9177 | #define GISB_ARBITER_BP_ENABLE_0_block_MASK 0x00000004 |
| 9178 | #define GISB_ARBITER_BP_ENABLE_0_block_ALIGN 0 |
| 9179 | #define GISB_ARBITER_BP_ENABLE_0_block_BITS 1 |
| 9180 | #define GISB_ARBITER_BP_ENABLE_0_block_SHIFT 2 |
| 9181 | #define GISB_ARBITER_BP_ENABLE_0_block_DISABLE 0 |
| 9182 | #define GISB_ARBITER_BP_ENABLE_0_block_ENABLE 1 |
| 9183 | |
| 9184 | /* GISB_ARBITER :: BP_ENABLE_0 :: address [01:01] */ |
| 9185 | #define GISB_ARBITER_BP_ENABLE_0_address_MASK 0x00000002 |
| 9186 | #define GISB_ARBITER_BP_ENABLE_0_address_ALIGN 0 |
| 9187 | #define GISB_ARBITER_BP_ENABLE_0_address_BITS 1 |
| 9188 | #define GISB_ARBITER_BP_ENABLE_0_address_SHIFT 1 |
| 9189 | #define GISB_ARBITER_BP_ENABLE_0_address_DISABLE 0 |
| 9190 | #define GISB_ARBITER_BP_ENABLE_0_address_ENABLE 1 |
| 9191 | |
| 9192 | /* GISB_ARBITER :: BP_ENABLE_0 :: access [00:00] */ |
| 9193 | #define GISB_ARBITER_BP_ENABLE_0_access_MASK 0x00000001 |
| 9194 | #define GISB_ARBITER_BP_ENABLE_0_access_ALIGN 0 |
| 9195 | #define GISB_ARBITER_BP_ENABLE_0_access_BITS 1 |
| 9196 | #define GISB_ARBITER_BP_ENABLE_0_access_SHIFT 0 |
| 9197 | #define GISB_ARBITER_BP_ENABLE_0_access_DISABLE 0 |
| 9198 | #define GISB_ARBITER_BP_ENABLE_0_access_ENABLE 1 |
| 9199 | |
| 9200 | |
| 9201 | /**************************************************************************** |
| 9202 | * GISB_ARBITER :: BP_START_ADDR_1 |
| 9203 | ***************************************************************************/ |
| 9204 | /* GISB_ARBITER :: BP_START_ADDR_1 :: start [31:00] */ |
| 9205 | #define GISB_ARBITER_BP_START_ADDR_1_start_MASK 0xffffffff |
| 9206 | #define GISB_ARBITER_BP_START_ADDR_1_start_ALIGN 0 |
| 9207 | #define GISB_ARBITER_BP_START_ADDR_1_start_BITS 32 |
| 9208 | #define GISB_ARBITER_BP_START_ADDR_1_start_SHIFT 0 |
| 9209 | |
| 9210 | |
| 9211 | /**************************************************************************** |
| 9212 | * GISB_ARBITER :: BP_END_ADDR_1 |
| 9213 | ***************************************************************************/ |
| 9214 | /* GISB_ARBITER :: BP_END_ADDR_1 :: end [31:00] */ |
| 9215 | #define GISB_ARBITER_BP_END_ADDR_1_end_MASK 0xffffffff |
| 9216 | #define GISB_ARBITER_BP_END_ADDR_1_end_ALIGN 0 |
| 9217 | #define GISB_ARBITER_BP_END_ADDR_1_end_BITS 32 |
| 9218 | #define GISB_ARBITER_BP_END_ADDR_1_end_SHIFT 0 |
| 9219 | |
| 9220 | |
| 9221 | /**************************************************************************** |
| 9222 | * GISB_ARBITER :: BP_READ_1 |
| 9223 | ***************************************************************************/ |
| 9224 | /* GISB_ARBITER :: BP_READ_1 :: reserved0 [31:06] */ |
| 9225 | #define GISB_ARBITER_BP_READ_1_reserved0_MASK 0xffffffc0 |
| 9226 | #define GISB_ARBITER_BP_READ_1_reserved0_ALIGN 0 |
| 9227 | #define GISB_ARBITER_BP_READ_1_reserved0_BITS 26 |
| 9228 | #define GISB_ARBITER_BP_READ_1_reserved0_SHIFT 6 |
| 9229 | |
| 9230 | /* GISB_ARBITER :: BP_READ_1 :: bsp [05:05] */ |
| 9231 | #define GISB_ARBITER_BP_READ_1_bsp_MASK 0x00000020 |
| 9232 | #define GISB_ARBITER_BP_READ_1_bsp_ALIGN 0 |
| 9233 | #define GISB_ARBITER_BP_READ_1_bsp_BITS 1 |
| 9234 | #define GISB_ARBITER_BP_READ_1_bsp_SHIFT 5 |
| 9235 | #define GISB_ARBITER_BP_READ_1_bsp_DISABLE 0 |
| 9236 | #define GISB_ARBITER_BP_READ_1_bsp_ENABLE 1 |
| 9237 | |
| 9238 | /* GISB_ARBITER :: BP_READ_1 :: aes [04:04] */ |
| 9239 | #define GISB_ARBITER_BP_READ_1_aes_MASK 0x00000010 |
| 9240 | #define GISB_ARBITER_BP_READ_1_aes_ALIGN 0 |
| 9241 | #define GISB_ARBITER_BP_READ_1_aes_BITS 1 |
| 9242 | #define GISB_ARBITER_BP_READ_1_aes_SHIFT 4 |
| 9243 | #define GISB_ARBITER_BP_READ_1_aes_DISABLE 0 |
| 9244 | #define GISB_ARBITER_BP_READ_1_aes_ENABLE 1 |
| 9245 | |
| 9246 | /* GISB_ARBITER :: BP_READ_1 :: fve [03:03] */ |
| 9247 | #define GISB_ARBITER_BP_READ_1_fve_MASK 0x00000008 |
| 9248 | #define GISB_ARBITER_BP_READ_1_fve_ALIGN 0 |
| 9249 | #define GISB_ARBITER_BP_READ_1_fve_BITS 1 |
| 9250 | #define GISB_ARBITER_BP_READ_1_fve_SHIFT 3 |
| 9251 | #define GISB_ARBITER_BP_READ_1_fve_DISABLE 0 |
| 9252 | #define GISB_ARBITER_BP_READ_1_fve_ENABLE 1 |
| 9253 | |
| 9254 | /* GISB_ARBITER :: BP_READ_1 :: tgt [02:02] */ |
| 9255 | #define GISB_ARBITER_BP_READ_1_tgt_MASK 0x00000004 |
| 9256 | #define GISB_ARBITER_BP_READ_1_tgt_ALIGN 0 |
| 9257 | #define GISB_ARBITER_BP_READ_1_tgt_BITS 1 |
| 9258 | #define GISB_ARBITER_BP_READ_1_tgt_SHIFT 2 |
| 9259 | #define GISB_ARBITER_BP_READ_1_tgt_DISABLE 0 |
| 9260 | #define GISB_ARBITER_BP_READ_1_tgt_ENABLE 1 |
| 9261 | |
| 9262 | /* GISB_ARBITER :: BP_READ_1 :: dbu [01:01] */ |
| 9263 | #define GISB_ARBITER_BP_READ_1_dbu_MASK 0x00000002 |
| 9264 | #define GISB_ARBITER_BP_READ_1_dbu_ALIGN 0 |
| 9265 | #define GISB_ARBITER_BP_READ_1_dbu_BITS 1 |
| 9266 | #define GISB_ARBITER_BP_READ_1_dbu_SHIFT 1 |
| 9267 | #define GISB_ARBITER_BP_READ_1_dbu_DISABLE 0 |
| 9268 | #define GISB_ARBITER_BP_READ_1_dbu_ENABLE 1 |
| 9269 | |
| 9270 | /* GISB_ARBITER :: BP_READ_1 :: cce [00:00] */ |
| 9271 | #define GISB_ARBITER_BP_READ_1_cce_MASK 0x00000001 |
| 9272 | #define GISB_ARBITER_BP_READ_1_cce_ALIGN 0 |
| 9273 | #define GISB_ARBITER_BP_READ_1_cce_BITS 1 |
| 9274 | #define GISB_ARBITER_BP_READ_1_cce_SHIFT 0 |
| 9275 | #define GISB_ARBITER_BP_READ_1_cce_DISABLE 0 |
| 9276 | #define GISB_ARBITER_BP_READ_1_cce_ENABLE 1 |
| 9277 | |
| 9278 | |
| 9279 | /**************************************************************************** |
| 9280 | * GISB_ARBITER :: BP_WRITE_1 |
| 9281 | ***************************************************************************/ |
| 9282 | /* GISB_ARBITER :: BP_WRITE_1 :: reserved0 [31:06] */ |
| 9283 | #define GISB_ARBITER_BP_WRITE_1_reserved0_MASK 0xffffffc0 |
| 9284 | #define GISB_ARBITER_BP_WRITE_1_reserved0_ALIGN 0 |
| 9285 | #define GISB_ARBITER_BP_WRITE_1_reserved0_BITS 26 |
| 9286 | #define GISB_ARBITER_BP_WRITE_1_reserved0_SHIFT 6 |
| 9287 | |
| 9288 | /* GISB_ARBITER :: BP_WRITE_1 :: bsp [05:05] */ |
| 9289 | #define GISB_ARBITER_BP_WRITE_1_bsp_MASK 0x00000020 |
| 9290 | #define GISB_ARBITER_BP_WRITE_1_bsp_ALIGN 0 |
| 9291 | #define GISB_ARBITER_BP_WRITE_1_bsp_BITS 1 |
| 9292 | #define GISB_ARBITER_BP_WRITE_1_bsp_SHIFT 5 |
| 9293 | #define GISB_ARBITER_BP_WRITE_1_bsp_DISABLE 0 |
| 9294 | #define GISB_ARBITER_BP_WRITE_1_bsp_ENABLE 1 |
| 9295 | |
| 9296 | /* GISB_ARBITER :: BP_WRITE_1 :: aes [04:04] */ |
| 9297 | #define GISB_ARBITER_BP_WRITE_1_aes_MASK 0x00000010 |
| 9298 | #define GISB_ARBITER_BP_WRITE_1_aes_ALIGN 0 |
| 9299 | #define GISB_ARBITER_BP_WRITE_1_aes_BITS 1 |
| 9300 | #define GISB_ARBITER_BP_WRITE_1_aes_SHIFT 4 |
| 9301 | #define GISB_ARBITER_BP_WRITE_1_aes_DISABLE 0 |
| 9302 | #define GISB_ARBITER_BP_WRITE_1_aes_ENABLE 1 |
| 9303 | |
| 9304 | /* GISB_ARBITER :: BP_WRITE_1 :: fve [03:03] */ |
| 9305 | #define GISB_ARBITER_BP_WRITE_1_fve_MASK 0x00000008 |
| 9306 | #define GISB_ARBITER_BP_WRITE_1_fve_ALIGN 0 |
| 9307 | #define GISB_ARBITER_BP_WRITE_1_fve_BITS 1 |
| 9308 | #define GISB_ARBITER_BP_WRITE_1_fve_SHIFT 3 |
| 9309 | #define GISB_ARBITER_BP_WRITE_1_fve_DISABLE 0 |
| 9310 | #define GISB_ARBITER_BP_WRITE_1_fve_ENABLE 1 |
| 9311 | |
| 9312 | /* GISB_ARBITER :: BP_WRITE_1 :: tgt [02:02] */ |
| 9313 | #define GISB_ARBITER_BP_WRITE_1_tgt_MASK 0x00000004 |
| 9314 | #define GISB_ARBITER_BP_WRITE_1_tgt_ALIGN 0 |
| 9315 | #define GISB_ARBITER_BP_WRITE_1_tgt_BITS 1 |
| 9316 | #define GISB_ARBITER_BP_WRITE_1_tgt_SHIFT 2 |
| 9317 | #define GISB_ARBITER_BP_WRITE_1_tgt_DISABLE 0 |
| 9318 | #define GISB_ARBITER_BP_WRITE_1_tgt_ENABLE 1 |
| 9319 | |
| 9320 | /* GISB_ARBITER :: BP_WRITE_1 :: dbu [01:01] */ |
| 9321 | #define GISB_ARBITER_BP_WRITE_1_dbu_MASK 0x00000002 |
| 9322 | #define GISB_ARBITER_BP_WRITE_1_dbu_ALIGN 0 |
| 9323 | #define GISB_ARBITER_BP_WRITE_1_dbu_BITS 1 |
| 9324 | #define GISB_ARBITER_BP_WRITE_1_dbu_SHIFT 1 |
| 9325 | #define GISB_ARBITER_BP_WRITE_1_dbu_DISABLE 0 |
| 9326 | #define GISB_ARBITER_BP_WRITE_1_dbu_ENABLE 1 |
| 9327 | |
| 9328 | /* GISB_ARBITER :: BP_WRITE_1 :: cce [00:00] */ |
| 9329 | #define GISB_ARBITER_BP_WRITE_1_cce_MASK 0x00000001 |
| 9330 | #define GISB_ARBITER_BP_WRITE_1_cce_ALIGN 0 |
| 9331 | #define GISB_ARBITER_BP_WRITE_1_cce_BITS 1 |
| 9332 | #define GISB_ARBITER_BP_WRITE_1_cce_SHIFT 0 |
| 9333 | #define GISB_ARBITER_BP_WRITE_1_cce_DISABLE 0 |
| 9334 | #define GISB_ARBITER_BP_WRITE_1_cce_ENABLE 1 |
| 9335 | |
| 9336 | |
| 9337 | /**************************************************************************** |
| 9338 | * GISB_ARBITER :: BP_ENABLE_1 |
| 9339 | ***************************************************************************/ |
| 9340 | /* GISB_ARBITER :: BP_ENABLE_1 :: reserved0 [31:03] */ |
| 9341 | #define GISB_ARBITER_BP_ENABLE_1_reserved0_MASK 0xfffffff8 |
| 9342 | #define GISB_ARBITER_BP_ENABLE_1_reserved0_ALIGN 0 |
| 9343 | #define GISB_ARBITER_BP_ENABLE_1_reserved0_BITS 29 |
| 9344 | #define GISB_ARBITER_BP_ENABLE_1_reserved0_SHIFT 3 |
| 9345 | |
| 9346 | /* GISB_ARBITER :: BP_ENABLE_1 :: block [02:02] */ |
| 9347 | #define GISB_ARBITER_BP_ENABLE_1_block_MASK 0x00000004 |
| 9348 | #define GISB_ARBITER_BP_ENABLE_1_block_ALIGN 0 |
| 9349 | #define GISB_ARBITER_BP_ENABLE_1_block_BITS 1 |
| 9350 | #define GISB_ARBITER_BP_ENABLE_1_block_SHIFT 2 |
| 9351 | #define GISB_ARBITER_BP_ENABLE_1_block_DISABLE 0 |
| 9352 | #define GISB_ARBITER_BP_ENABLE_1_block_ENABLE 1 |
| 9353 | |
| 9354 | /* GISB_ARBITER :: BP_ENABLE_1 :: address [01:01] */ |
| 9355 | #define GISB_ARBITER_BP_ENABLE_1_address_MASK 0x00000002 |
| 9356 | #define GISB_ARBITER_BP_ENABLE_1_address_ALIGN 0 |
| 9357 | #define GISB_ARBITER_BP_ENABLE_1_address_BITS 1 |
| 9358 | #define GISB_ARBITER_BP_ENABLE_1_address_SHIFT 1 |
| 9359 | #define GISB_ARBITER_BP_ENABLE_1_address_DISABLE 0 |
| 9360 | #define GISB_ARBITER_BP_ENABLE_1_address_ENABLE 1 |
| 9361 | |
| 9362 | /* GISB_ARBITER :: BP_ENABLE_1 :: access [00:00] */ |
| 9363 | #define GISB_ARBITER_BP_ENABLE_1_access_MASK 0x00000001 |
| 9364 | #define GISB_ARBITER_BP_ENABLE_1_access_ALIGN 0 |
| 9365 | #define GISB_ARBITER_BP_ENABLE_1_access_BITS 1 |
| 9366 | #define GISB_ARBITER_BP_ENABLE_1_access_SHIFT 0 |
| 9367 | #define GISB_ARBITER_BP_ENABLE_1_access_DISABLE 0 |
| 9368 | #define GISB_ARBITER_BP_ENABLE_1_access_ENABLE 1 |
| 9369 | |
| 9370 | |
| 9371 | /**************************************************************************** |
| 9372 | * GISB_ARBITER :: BP_START_ADDR_2 |
| 9373 | ***************************************************************************/ |
| 9374 | /* GISB_ARBITER :: BP_START_ADDR_2 :: start [31:00] */ |
| 9375 | #define GISB_ARBITER_BP_START_ADDR_2_start_MASK 0xffffffff |
| 9376 | #define GISB_ARBITER_BP_START_ADDR_2_start_ALIGN 0 |
| 9377 | #define GISB_ARBITER_BP_START_ADDR_2_start_BITS 32 |
| 9378 | #define GISB_ARBITER_BP_START_ADDR_2_start_SHIFT 0 |
| 9379 | |
| 9380 | |
| 9381 | /**************************************************************************** |
| 9382 | * GISB_ARBITER :: BP_END_ADDR_2 |
| 9383 | ***************************************************************************/ |
| 9384 | /* GISB_ARBITER :: BP_END_ADDR_2 :: end [31:00] */ |
| 9385 | #define GISB_ARBITER_BP_END_ADDR_2_end_MASK 0xffffffff |
| 9386 | #define GISB_ARBITER_BP_END_ADDR_2_end_ALIGN 0 |
| 9387 | #define GISB_ARBITER_BP_END_ADDR_2_end_BITS 32 |
| 9388 | #define GISB_ARBITER_BP_END_ADDR_2_end_SHIFT 0 |
| 9389 | |
| 9390 | |
| 9391 | /**************************************************************************** |
| 9392 | * GISB_ARBITER :: BP_READ_2 |
| 9393 | ***************************************************************************/ |
| 9394 | /* GISB_ARBITER :: BP_READ_2 :: reserved0 [31:06] */ |
| 9395 | #define GISB_ARBITER_BP_READ_2_reserved0_MASK 0xffffffc0 |
| 9396 | #define GISB_ARBITER_BP_READ_2_reserved0_ALIGN 0 |
| 9397 | #define GISB_ARBITER_BP_READ_2_reserved0_BITS 26 |
| 9398 | #define GISB_ARBITER_BP_READ_2_reserved0_SHIFT 6 |
| 9399 | |
| 9400 | /* GISB_ARBITER :: BP_READ_2 :: bsp [05:05] */ |
| 9401 | #define GISB_ARBITER_BP_READ_2_bsp_MASK 0x00000020 |
| 9402 | #define GISB_ARBITER_BP_READ_2_bsp_ALIGN 0 |
| 9403 | #define GISB_ARBITER_BP_READ_2_bsp_BITS 1 |
| 9404 | #define GISB_ARBITER_BP_READ_2_bsp_SHIFT 5 |
| 9405 | #define GISB_ARBITER_BP_READ_2_bsp_DISABLE 0 |
| 9406 | #define GISB_ARBITER_BP_READ_2_bsp_ENABLE 1 |
| 9407 | |
| 9408 | /* GISB_ARBITER :: BP_READ_2 :: aes [04:04] */ |
| 9409 | #define GISB_ARBITER_BP_READ_2_aes_MASK 0x00000010 |
| 9410 | #define GISB_ARBITER_BP_READ_2_aes_ALIGN 0 |
| 9411 | #define GISB_ARBITER_BP_READ_2_aes_BITS 1 |
| 9412 | #define GISB_ARBITER_BP_READ_2_aes_SHIFT 4 |
| 9413 | #define GISB_ARBITER_BP_READ_2_aes_DISABLE 0 |
| 9414 | #define GISB_ARBITER_BP_READ_2_aes_ENABLE 1 |
| 9415 | |
| 9416 | /* GISB_ARBITER :: BP_READ_2 :: fve [03:03] */ |
| 9417 | #define GISB_ARBITER_BP_READ_2_fve_MASK 0x00000008 |
| 9418 | #define GISB_ARBITER_BP_READ_2_fve_ALIGN 0 |
| 9419 | #define GISB_ARBITER_BP_READ_2_fve_BITS 1 |
| 9420 | #define GISB_ARBITER_BP_READ_2_fve_SHIFT 3 |
| 9421 | #define GISB_ARBITER_BP_READ_2_fve_DISABLE 0 |
| 9422 | #define GISB_ARBITER_BP_READ_2_fve_ENABLE 1 |
| 9423 | |
| 9424 | /* GISB_ARBITER :: BP_READ_2 :: tgt [02:02] */ |
| 9425 | #define GISB_ARBITER_BP_READ_2_tgt_MASK 0x00000004 |
| 9426 | #define GISB_ARBITER_BP_READ_2_tgt_ALIGN 0 |
| 9427 | #define GISB_ARBITER_BP_READ_2_tgt_BITS 1 |
| 9428 | #define GISB_ARBITER_BP_READ_2_tgt_SHIFT 2 |
| 9429 | #define GISB_ARBITER_BP_READ_2_tgt_DISABLE 0 |
| 9430 | #define GISB_ARBITER_BP_READ_2_tgt_ENABLE 1 |
| 9431 | |
| 9432 | /* GISB_ARBITER :: BP_READ_2 :: dbu [01:01] */ |
| 9433 | #define GISB_ARBITER_BP_READ_2_dbu_MASK 0x00000002 |
| 9434 | #define GISB_ARBITER_BP_READ_2_dbu_ALIGN 0 |
| 9435 | #define GISB_ARBITER_BP_READ_2_dbu_BITS 1 |
| 9436 | #define GISB_ARBITER_BP_READ_2_dbu_SHIFT 1 |
| 9437 | #define GISB_ARBITER_BP_READ_2_dbu_DISABLE 0 |
| 9438 | #define GISB_ARBITER_BP_READ_2_dbu_ENABLE 1 |
| 9439 | |
| 9440 | /* GISB_ARBITER :: BP_READ_2 :: cce [00:00] */ |
| 9441 | #define GISB_ARBITER_BP_READ_2_cce_MASK 0x00000001 |
| 9442 | #define GISB_ARBITER_BP_READ_2_cce_ALIGN 0 |
| 9443 | #define GISB_ARBITER_BP_READ_2_cce_BITS 1 |
| 9444 | #define GISB_ARBITER_BP_READ_2_cce_SHIFT 0 |
| 9445 | #define GISB_ARBITER_BP_READ_2_cce_DISABLE 0 |
| 9446 | #define GISB_ARBITER_BP_READ_2_cce_ENABLE 1 |
| 9447 | |
| 9448 | |
| 9449 | /**************************************************************************** |
| 9450 | * GISB_ARBITER :: BP_WRITE_2 |
| 9451 | ***************************************************************************/ |
| 9452 | /* GISB_ARBITER :: BP_WRITE_2 :: reserved0 [31:06] */ |
| 9453 | #define GISB_ARBITER_BP_WRITE_2_reserved0_MASK 0xffffffc0 |
| 9454 | #define GISB_ARBITER_BP_WRITE_2_reserved0_ALIGN 0 |
| 9455 | #define GISB_ARBITER_BP_WRITE_2_reserved0_BITS 26 |
| 9456 | #define GISB_ARBITER_BP_WRITE_2_reserved0_SHIFT 6 |
| 9457 | |
| 9458 | /* GISB_ARBITER :: BP_WRITE_2 :: bsp [05:05] */ |
| 9459 | #define GISB_ARBITER_BP_WRITE_2_bsp_MASK 0x00000020 |
| 9460 | #define GISB_ARBITER_BP_WRITE_2_bsp_ALIGN 0 |
| 9461 | #define GISB_ARBITER_BP_WRITE_2_bsp_BITS 1 |
| 9462 | #define GISB_ARBITER_BP_WRITE_2_bsp_SHIFT 5 |
| 9463 | #define GISB_ARBITER_BP_WRITE_2_bsp_DISABLE 0 |
| 9464 | #define GISB_ARBITER_BP_WRITE_2_bsp_ENABLE 1 |
| 9465 | |
| 9466 | /* GISB_ARBITER :: BP_WRITE_2 :: aes [04:04] */ |
| 9467 | #define GISB_ARBITER_BP_WRITE_2_aes_MASK 0x00000010 |
| 9468 | #define GISB_ARBITER_BP_WRITE_2_aes_ALIGN 0 |
| 9469 | #define GISB_ARBITER_BP_WRITE_2_aes_BITS 1 |
| 9470 | #define GISB_ARBITER_BP_WRITE_2_aes_SHIFT 4 |
| 9471 | #define GISB_ARBITER_BP_WRITE_2_aes_DISABLE 0 |
| 9472 | #define GISB_ARBITER_BP_WRITE_2_aes_ENABLE 1 |
| 9473 | |
| 9474 | /* GISB_ARBITER :: BP_WRITE_2 :: fve [03:03] */ |
| 9475 | #define GISB_ARBITER_BP_WRITE_2_fve_MASK 0x00000008 |
| 9476 | #define GISB_ARBITER_BP_WRITE_2_fve_ALIGN 0 |
| 9477 | #define GISB_ARBITER_BP_WRITE_2_fve_BITS 1 |
| 9478 | #define GISB_ARBITER_BP_WRITE_2_fve_SHIFT 3 |
| 9479 | #define GISB_ARBITER_BP_WRITE_2_fve_DISABLE 0 |
| 9480 | #define GISB_ARBITER_BP_WRITE_2_fve_ENABLE 1 |
| 9481 | |
| 9482 | /* GISB_ARBITER :: BP_WRITE_2 :: tgt [02:02] */ |
| 9483 | #define GISB_ARBITER_BP_WRITE_2_tgt_MASK 0x00000004 |
| 9484 | #define GISB_ARBITER_BP_WRITE_2_tgt_ALIGN 0 |
| 9485 | #define GISB_ARBITER_BP_WRITE_2_tgt_BITS 1 |
| 9486 | #define GISB_ARBITER_BP_WRITE_2_tgt_SHIFT 2 |
| 9487 | #define GISB_ARBITER_BP_WRITE_2_tgt_DISABLE 0 |
| 9488 | #define GISB_ARBITER_BP_WRITE_2_tgt_ENABLE 1 |
| 9489 | |
| 9490 | /* GISB_ARBITER :: BP_WRITE_2 :: dbu [01:01] */ |
| 9491 | #define GISB_ARBITER_BP_WRITE_2_dbu_MASK 0x00000002 |
| 9492 | #define GISB_ARBITER_BP_WRITE_2_dbu_ALIGN 0 |
| 9493 | #define GISB_ARBITER_BP_WRITE_2_dbu_BITS 1 |
| 9494 | #define GISB_ARBITER_BP_WRITE_2_dbu_SHIFT 1 |
| 9495 | #define GISB_ARBITER_BP_WRITE_2_dbu_DISABLE 0 |
| 9496 | #define GISB_ARBITER_BP_WRITE_2_dbu_ENABLE 1 |
| 9497 | |
| 9498 | /* GISB_ARBITER :: BP_WRITE_2 :: cce [00:00] */ |
| 9499 | #define GISB_ARBITER_BP_WRITE_2_cce_MASK 0x00000001 |
| 9500 | #define GISB_ARBITER_BP_WRITE_2_cce_ALIGN 0 |
| 9501 | #define GISB_ARBITER_BP_WRITE_2_cce_BITS 1 |
| 9502 | #define GISB_ARBITER_BP_WRITE_2_cce_SHIFT 0 |
| 9503 | #define GISB_ARBITER_BP_WRITE_2_cce_DISABLE 0 |
| 9504 | #define GISB_ARBITER_BP_WRITE_2_cce_ENABLE 1 |
| 9505 | |
| 9506 | |
| 9507 | /**************************************************************************** |
| 9508 | * GISB_ARBITER :: BP_ENABLE_2 |
| 9509 | ***************************************************************************/ |
| 9510 | /* GISB_ARBITER :: BP_ENABLE_2 :: reserved0 [31:03] */ |
| 9511 | #define GISB_ARBITER_BP_ENABLE_2_reserved0_MASK 0xfffffff8 |
| 9512 | #define GISB_ARBITER_BP_ENABLE_2_reserved0_ALIGN 0 |
| 9513 | #define GISB_ARBITER_BP_ENABLE_2_reserved0_BITS 29 |
| 9514 | #define GISB_ARBITER_BP_ENABLE_2_reserved0_SHIFT 3 |
| 9515 | |
| 9516 | /* GISB_ARBITER :: BP_ENABLE_2 :: block [02:02] */ |
| 9517 | #define GISB_ARBITER_BP_ENABLE_2_block_MASK 0x00000004 |
| 9518 | #define GISB_ARBITER_BP_ENABLE_2_block_ALIGN 0 |
| 9519 | #define GISB_ARBITER_BP_ENABLE_2_block_BITS 1 |
| 9520 | #define GISB_ARBITER_BP_ENABLE_2_block_SHIFT 2 |
| 9521 | #define GISB_ARBITER_BP_ENABLE_2_block_DISABLE 0 |
| 9522 | #define GISB_ARBITER_BP_ENABLE_2_block_ENABLE 1 |
| 9523 | |
| 9524 | /* GISB_ARBITER :: BP_ENABLE_2 :: address [01:01] */ |
| 9525 | #define GISB_ARBITER_BP_ENABLE_2_address_MASK 0x00000002 |
| 9526 | #define GISB_ARBITER_BP_ENABLE_2_address_ALIGN 0 |
| 9527 | #define GISB_ARBITER_BP_ENABLE_2_address_BITS 1 |
| 9528 | #define GISB_ARBITER_BP_ENABLE_2_address_SHIFT 1 |
| 9529 | #define GISB_ARBITER_BP_ENABLE_2_address_DISABLE 0 |
| 9530 | #define GISB_ARBITER_BP_ENABLE_2_address_ENABLE 1 |
| 9531 | |
| 9532 | /* GISB_ARBITER :: BP_ENABLE_2 :: access [00:00] */ |
| 9533 | #define GISB_ARBITER_BP_ENABLE_2_access_MASK 0x00000001 |
| 9534 | #define GISB_ARBITER_BP_ENABLE_2_access_ALIGN 0 |
| 9535 | #define GISB_ARBITER_BP_ENABLE_2_access_BITS 1 |
| 9536 | #define GISB_ARBITER_BP_ENABLE_2_access_SHIFT 0 |
| 9537 | #define GISB_ARBITER_BP_ENABLE_2_access_DISABLE 0 |
| 9538 | #define GISB_ARBITER_BP_ENABLE_2_access_ENABLE 1 |
| 9539 | |
| 9540 | |
| 9541 | /**************************************************************************** |
| 9542 | * GISB_ARBITER :: BP_START_ADDR_3 |
| 9543 | ***************************************************************************/ |
| 9544 | /* GISB_ARBITER :: BP_START_ADDR_3 :: start [31:00] */ |
| 9545 | #define GISB_ARBITER_BP_START_ADDR_3_start_MASK 0xffffffff |
| 9546 | #define GISB_ARBITER_BP_START_ADDR_3_start_ALIGN 0 |
| 9547 | #define GISB_ARBITER_BP_START_ADDR_3_start_BITS 32 |
| 9548 | #define GISB_ARBITER_BP_START_ADDR_3_start_SHIFT 0 |
| 9549 | |
| 9550 | |
| 9551 | /**************************************************************************** |
| 9552 | * GISB_ARBITER :: BP_END_ADDR_3 |
| 9553 | ***************************************************************************/ |
| 9554 | /* GISB_ARBITER :: BP_END_ADDR_3 :: end [31:00] */ |
| 9555 | #define GISB_ARBITER_BP_END_ADDR_3_end_MASK 0xffffffff |
| 9556 | #define GISB_ARBITER_BP_END_ADDR_3_end_ALIGN 0 |
| 9557 | #define GISB_ARBITER_BP_END_ADDR_3_end_BITS 32 |
| 9558 | #define GISB_ARBITER_BP_END_ADDR_3_end_SHIFT 0 |
| 9559 | |
| 9560 | |
| 9561 | /**************************************************************************** |
| 9562 | * GISB_ARBITER :: BP_READ_3 |
| 9563 | ***************************************************************************/ |
| 9564 | /* GISB_ARBITER :: BP_READ_3 :: reserved0 [31:06] */ |
| 9565 | #define GISB_ARBITER_BP_READ_3_reserved0_MASK 0xffffffc0 |
| 9566 | #define GISB_ARBITER_BP_READ_3_reserved0_ALIGN 0 |
| 9567 | #define GISB_ARBITER_BP_READ_3_reserved0_BITS 26 |
| 9568 | #define GISB_ARBITER_BP_READ_3_reserved0_SHIFT 6 |
| 9569 | |
| 9570 | /* GISB_ARBITER :: BP_READ_3 :: bsp [05:05] */ |
| 9571 | #define GISB_ARBITER_BP_READ_3_bsp_MASK 0x00000020 |
| 9572 | #define GISB_ARBITER_BP_READ_3_bsp_ALIGN 0 |
| 9573 | #define GISB_ARBITER_BP_READ_3_bsp_BITS 1 |
| 9574 | #define GISB_ARBITER_BP_READ_3_bsp_SHIFT 5 |
| 9575 | #define GISB_ARBITER_BP_READ_3_bsp_DISABLE 0 |
| 9576 | #define GISB_ARBITER_BP_READ_3_bsp_ENABLE 1 |
| 9577 | |
| 9578 | /* GISB_ARBITER :: BP_READ_3 :: aes [04:04] */ |
| 9579 | #define GISB_ARBITER_BP_READ_3_aes_MASK 0x00000010 |
| 9580 | #define GISB_ARBITER_BP_READ_3_aes_ALIGN 0 |
| 9581 | #define GISB_ARBITER_BP_READ_3_aes_BITS 1 |
| 9582 | #define GISB_ARBITER_BP_READ_3_aes_SHIFT 4 |
| 9583 | #define GISB_ARBITER_BP_READ_3_aes_DISABLE 0 |
| 9584 | #define GISB_ARBITER_BP_READ_3_aes_ENABLE 1 |
| 9585 | |
| 9586 | /* GISB_ARBITER :: BP_READ_3 :: fve [03:03] */ |
| 9587 | #define GISB_ARBITER_BP_READ_3_fve_MASK 0x00000008 |
| 9588 | #define GISB_ARBITER_BP_READ_3_fve_ALIGN 0 |
| 9589 | #define GISB_ARBITER_BP_READ_3_fve_BITS 1 |
| 9590 | #define GISB_ARBITER_BP_READ_3_fve_SHIFT 3 |
| 9591 | #define GISB_ARBITER_BP_READ_3_fve_DISABLE 0 |
| 9592 | #define GISB_ARBITER_BP_READ_3_fve_ENABLE 1 |
| 9593 | |
| 9594 | /* GISB_ARBITER :: BP_READ_3 :: tgt [02:02] */ |
| 9595 | #define GISB_ARBITER_BP_READ_3_tgt_MASK 0x00000004 |
| 9596 | #define GISB_ARBITER_BP_READ_3_tgt_ALIGN 0 |
| 9597 | #define GISB_ARBITER_BP_READ_3_tgt_BITS 1 |
| 9598 | #define GISB_ARBITER_BP_READ_3_tgt_SHIFT 2 |
| 9599 | #define GISB_ARBITER_BP_READ_3_tgt_DISABLE 0 |
| 9600 | #define GISB_ARBITER_BP_READ_3_tgt_ENABLE 1 |
| 9601 | |
| 9602 | /* GISB_ARBITER :: BP_READ_3 :: dbu [01:01] */ |
| 9603 | #define GISB_ARBITER_BP_READ_3_dbu_MASK 0x00000002 |
| 9604 | #define GISB_ARBITER_BP_READ_3_dbu_ALIGN 0 |
| 9605 | #define GISB_ARBITER_BP_READ_3_dbu_BITS 1 |
| 9606 | #define GISB_ARBITER_BP_READ_3_dbu_SHIFT 1 |
| 9607 | #define GISB_ARBITER_BP_READ_3_dbu_DISABLE 0 |
| 9608 | #define GISB_ARBITER_BP_READ_3_dbu_ENABLE 1 |
| 9609 | |
| 9610 | /* GISB_ARBITER :: BP_READ_3 :: cce [00:00] */ |
| 9611 | #define GISB_ARBITER_BP_READ_3_cce_MASK 0x00000001 |
| 9612 | #define GISB_ARBITER_BP_READ_3_cce_ALIGN 0 |
| 9613 | #define GISB_ARBITER_BP_READ_3_cce_BITS 1 |
| 9614 | #define GISB_ARBITER_BP_READ_3_cce_SHIFT 0 |
| 9615 | #define GISB_ARBITER_BP_READ_3_cce_DISABLE 0 |
| 9616 | #define GISB_ARBITER_BP_READ_3_cce_ENABLE 1 |
| 9617 | |
| 9618 | |
| 9619 | /**************************************************************************** |
| 9620 | * GISB_ARBITER :: BP_WRITE_3 |
| 9621 | ***************************************************************************/ |
| 9622 | /* GISB_ARBITER :: BP_WRITE_3 :: reserved0 [31:06] */ |
| 9623 | #define GISB_ARBITER_BP_WRITE_3_reserved0_MASK 0xffffffc0 |
| 9624 | #define GISB_ARBITER_BP_WRITE_3_reserved0_ALIGN 0 |
| 9625 | #define GISB_ARBITER_BP_WRITE_3_reserved0_BITS 26 |
| 9626 | #define GISB_ARBITER_BP_WRITE_3_reserved0_SHIFT 6 |
| 9627 | |
| 9628 | /* GISB_ARBITER :: BP_WRITE_3 :: bsp [05:05] */ |
| 9629 | #define GISB_ARBITER_BP_WRITE_3_bsp_MASK 0x00000020 |
| 9630 | #define GISB_ARBITER_BP_WRITE_3_bsp_ALIGN 0 |
| 9631 | #define GISB_ARBITER_BP_WRITE_3_bsp_BITS 1 |
| 9632 | #define GISB_ARBITER_BP_WRITE_3_bsp_SHIFT 5 |
| 9633 | #define GISB_ARBITER_BP_WRITE_3_bsp_DISABLE 0 |
| 9634 | #define GISB_ARBITER_BP_WRITE_3_bsp_ENABLE 1 |
| 9635 | |
| 9636 | /* GISB_ARBITER :: BP_WRITE_3 :: aes [04:04] */ |
| 9637 | #define GISB_ARBITER_BP_WRITE_3_aes_MASK 0x00000010 |
| 9638 | #define GISB_ARBITER_BP_WRITE_3_aes_ALIGN 0 |
| 9639 | #define GISB_ARBITER_BP_WRITE_3_aes_BITS 1 |
| 9640 | #define GISB_ARBITER_BP_WRITE_3_aes_SHIFT 4 |
| 9641 | #define GISB_ARBITER_BP_WRITE_3_aes_DISABLE 0 |
| 9642 | #define GISB_ARBITER_BP_WRITE_3_aes_ENABLE 1 |
| 9643 | |
| 9644 | /* GISB_ARBITER :: BP_WRITE_3 :: fve [03:03] */ |
| 9645 | #define GISB_ARBITER_BP_WRITE_3_fve_MASK 0x00000008 |
| 9646 | #define GISB_ARBITER_BP_WRITE_3_fve_ALIGN 0 |
| 9647 | #define GISB_ARBITER_BP_WRITE_3_fve_BITS 1 |
| 9648 | #define GISB_ARBITER_BP_WRITE_3_fve_SHIFT 3 |
| 9649 | #define GISB_ARBITER_BP_WRITE_3_fve_DISABLE 0 |
| 9650 | #define GISB_ARBITER_BP_WRITE_3_fve_ENABLE 1 |
| 9651 | |
| 9652 | /* GISB_ARBITER :: BP_WRITE_3 :: tgt [02:02] */ |
| 9653 | #define GISB_ARBITER_BP_WRITE_3_tgt_MASK 0x00000004 |
| 9654 | #define GISB_ARBITER_BP_WRITE_3_tgt_ALIGN 0 |
| 9655 | #define GISB_ARBITER_BP_WRITE_3_tgt_BITS 1 |
| 9656 | #define GISB_ARBITER_BP_WRITE_3_tgt_SHIFT 2 |
| 9657 | #define GISB_ARBITER_BP_WRITE_3_tgt_DISABLE 0 |
| 9658 | #define GISB_ARBITER_BP_WRITE_3_tgt_ENABLE 1 |
| 9659 | |
| 9660 | /* GISB_ARBITER :: BP_WRITE_3 :: dbu [01:01] */ |
| 9661 | #define GISB_ARBITER_BP_WRITE_3_dbu_MASK 0x00000002 |
| 9662 | #define GISB_ARBITER_BP_WRITE_3_dbu_ALIGN 0 |
| 9663 | #define GISB_ARBITER_BP_WRITE_3_dbu_BITS 1 |
| 9664 | #define GISB_ARBITER_BP_WRITE_3_dbu_SHIFT 1 |
| 9665 | #define GISB_ARBITER_BP_WRITE_3_dbu_DISABLE 0 |
| 9666 | #define GISB_ARBITER_BP_WRITE_3_dbu_ENABLE 1 |
| 9667 | |
| 9668 | /* GISB_ARBITER :: BP_WRITE_3 :: cce [00:00] */ |
| 9669 | #define GISB_ARBITER_BP_WRITE_3_cce_MASK 0x00000001 |
| 9670 | #define GISB_ARBITER_BP_WRITE_3_cce_ALIGN 0 |
| 9671 | #define GISB_ARBITER_BP_WRITE_3_cce_BITS 1 |
| 9672 | #define GISB_ARBITER_BP_WRITE_3_cce_SHIFT 0 |
| 9673 | #define GISB_ARBITER_BP_WRITE_3_cce_DISABLE 0 |
| 9674 | #define GISB_ARBITER_BP_WRITE_3_cce_ENABLE 1 |
| 9675 | |
| 9676 | |
| 9677 | /**************************************************************************** |
| 9678 | * GISB_ARBITER :: BP_ENABLE_3 |
| 9679 | ***************************************************************************/ |
| 9680 | /* GISB_ARBITER :: BP_ENABLE_3 :: reserved0 [31:03] */ |
| 9681 | #define GISB_ARBITER_BP_ENABLE_3_reserved0_MASK 0xfffffff8 |
| 9682 | #define GISB_ARBITER_BP_ENABLE_3_reserved0_ALIGN 0 |
| 9683 | #define GISB_ARBITER_BP_ENABLE_3_reserved0_BITS 29 |
| 9684 | #define GISB_ARBITER_BP_ENABLE_3_reserved0_SHIFT 3 |
| 9685 | |
| 9686 | /* GISB_ARBITER :: BP_ENABLE_3 :: block [02:02] */ |
| 9687 | #define GISB_ARBITER_BP_ENABLE_3_block_MASK 0x00000004 |
| 9688 | #define GISB_ARBITER_BP_ENABLE_3_block_ALIGN 0 |
| 9689 | #define GISB_ARBITER_BP_ENABLE_3_block_BITS 1 |
| 9690 | #define GISB_ARBITER_BP_ENABLE_3_block_SHIFT 2 |
| 9691 | #define GISB_ARBITER_BP_ENABLE_3_block_DISABLE 0 |
| 9692 | #define GISB_ARBITER_BP_ENABLE_3_block_ENABLE 1 |
| 9693 | |
| 9694 | /* GISB_ARBITER :: BP_ENABLE_3 :: address [01:01] */ |
| 9695 | #define GISB_ARBITER_BP_ENABLE_3_address_MASK 0x00000002 |
| 9696 | #define GISB_ARBITER_BP_ENABLE_3_address_ALIGN 0 |
| 9697 | #define GISB_ARBITER_BP_ENABLE_3_address_BITS 1 |
| 9698 | #define GISB_ARBITER_BP_ENABLE_3_address_SHIFT 1 |
| 9699 | #define GISB_ARBITER_BP_ENABLE_3_address_DISABLE 0 |
| 9700 | #define GISB_ARBITER_BP_ENABLE_3_address_ENABLE 1 |
| 9701 | |
| 9702 | /* GISB_ARBITER :: BP_ENABLE_3 :: access [00:00] */ |
| 9703 | #define GISB_ARBITER_BP_ENABLE_3_access_MASK 0x00000001 |
| 9704 | #define GISB_ARBITER_BP_ENABLE_3_access_ALIGN 0 |
| 9705 | #define GISB_ARBITER_BP_ENABLE_3_access_BITS 1 |
| 9706 | #define GISB_ARBITER_BP_ENABLE_3_access_SHIFT 0 |
| 9707 | #define GISB_ARBITER_BP_ENABLE_3_access_DISABLE 0 |
| 9708 | #define GISB_ARBITER_BP_ENABLE_3_access_ENABLE 1 |
| 9709 | |
| 9710 | |
| 9711 | /**************************************************************************** |
| 9712 | * GISB_ARBITER :: BP_START_ADDR_4 |
| 9713 | ***************************************************************************/ |
| 9714 | /* GISB_ARBITER :: BP_START_ADDR_4 :: start [31:00] */ |
| 9715 | #define GISB_ARBITER_BP_START_ADDR_4_start_MASK 0xffffffff |
| 9716 | #define GISB_ARBITER_BP_START_ADDR_4_start_ALIGN 0 |
| 9717 | #define GISB_ARBITER_BP_START_ADDR_4_start_BITS 32 |
| 9718 | #define GISB_ARBITER_BP_START_ADDR_4_start_SHIFT 0 |
| 9719 | |
| 9720 | |
| 9721 | /**************************************************************************** |
| 9722 | * GISB_ARBITER :: BP_END_ADDR_4 |
| 9723 | ***************************************************************************/ |
| 9724 | /* GISB_ARBITER :: BP_END_ADDR_4 :: end [31:00] */ |
| 9725 | #define GISB_ARBITER_BP_END_ADDR_4_end_MASK 0xffffffff |
| 9726 | #define GISB_ARBITER_BP_END_ADDR_4_end_ALIGN 0 |
| 9727 | #define GISB_ARBITER_BP_END_ADDR_4_end_BITS 32 |
| 9728 | #define GISB_ARBITER_BP_END_ADDR_4_end_SHIFT 0 |
| 9729 | |
| 9730 | |
| 9731 | /**************************************************************************** |
| 9732 | * GISB_ARBITER :: BP_READ_4 |
| 9733 | ***************************************************************************/ |
| 9734 | /* GISB_ARBITER :: BP_READ_4 :: reserved0 [31:06] */ |
| 9735 | #define GISB_ARBITER_BP_READ_4_reserved0_MASK 0xffffffc0 |
| 9736 | #define GISB_ARBITER_BP_READ_4_reserved0_ALIGN 0 |
| 9737 | #define GISB_ARBITER_BP_READ_4_reserved0_BITS 26 |
| 9738 | #define GISB_ARBITER_BP_READ_4_reserved0_SHIFT 6 |
| 9739 | |
| 9740 | /* GISB_ARBITER :: BP_READ_4 :: bsp [05:05] */ |
| 9741 | #define GISB_ARBITER_BP_READ_4_bsp_MASK 0x00000020 |
| 9742 | #define GISB_ARBITER_BP_READ_4_bsp_ALIGN 0 |
| 9743 | #define GISB_ARBITER_BP_READ_4_bsp_BITS 1 |
| 9744 | #define GISB_ARBITER_BP_READ_4_bsp_SHIFT 5 |
| 9745 | #define GISB_ARBITER_BP_READ_4_bsp_DISABLE 0 |
| 9746 | #define GISB_ARBITER_BP_READ_4_bsp_ENABLE 1 |
| 9747 | |
| 9748 | /* GISB_ARBITER :: BP_READ_4 :: aes [04:04] */ |
| 9749 | #define GISB_ARBITER_BP_READ_4_aes_MASK 0x00000010 |
| 9750 | #define GISB_ARBITER_BP_READ_4_aes_ALIGN 0 |
| 9751 | #define GISB_ARBITER_BP_READ_4_aes_BITS 1 |
| 9752 | #define GISB_ARBITER_BP_READ_4_aes_SHIFT 4 |
| 9753 | #define GISB_ARBITER_BP_READ_4_aes_DISABLE 0 |
| 9754 | #define GISB_ARBITER_BP_READ_4_aes_ENABLE 1 |
| 9755 | |
| 9756 | /* GISB_ARBITER :: BP_READ_4 :: fve [03:03] */ |
| 9757 | #define GISB_ARBITER_BP_READ_4_fve_MASK 0x00000008 |
| 9758 | #define GISB_ARBITER_BP_READ_4_fve_ALIGN 0 |
| 9759 | #define GISB_ARBITER_BP_READ_4_fve_BITS 1 |
| 9760 | #define GISB_ARBITER_BP_READ_4_fve_SHIFT 3 |
| 9761 | #define GISB_ARBITER_BP_READ_4_fve_DISABLE 0 |
| 9762 | #define GISB_ARBITER_BP_READ_4_fve_ENABLE 1 |
| 9763 | |
| 9764 | /* GISB_ARBITER :: BP_READ_4 :: tgt [02:02] */ |
| 9765 | #define GISB_ARBITER_BP_READ_4_tgt_MASK 0x00000004 |
| 9766 | #define GISB_ARBITER_BP_READ_4_tgt_ALIGN 0 |
| 9767 | #define GISB_ARBITER_BP_READ_4_tgt_BITS 1 |
| 9768 | #define GISB_ARBITER_BP_READ_4_tgt_SHIFT 2 |
| 9769 | #define GISB_ARBITER_BP_READ_4_tgt_DISABLE 0 |
| 9770 | #define GISB_ARBITER_BP_READ_4_tgt_ENABLE 1 |
| 9771 | |
| 9772 | /* GISB_ARBITER :: BP_READ_4 :: dbu [01:01] */ |
| 9773 | #define GISB_ARBITER_BP_READ_4_dbu_MASK 0x00000002 |
| 9774 | #define GISB_ARBITER_BP_READ_4_dbu_ALIGN 0 |
| 9775 | #define GISB_ARBITER_BP_READ_4_dbu_BITS 1 |
| 9776 | #define GISB_ARBITER_BP_READ_4_dbu_SHIFT 1 |
| 9777 | #define GISB_ARBITER_BP_READ_4_dbu_DISABLE 0 |
| 9778 | #define GISB_ARBITER_BP_READ_4_dbu_ENABLE 1 |
| 9779 | |
| 9780 | /* GISB_ARBITER :: BP_READ_4 :: cce [00:00] */ |
| 9781 | #define GISB_ARBITER_BP_READ_4_cce_MASK 0x00000001 |
| 9782 | #define GISB_ARBITER_BP_READ_4_cce_ALIGN 0 |
| 9783 | #define GISB_ARBITER_BP_READ_4_cce_BITS 1 |
| 9784 | #define GISB_ARBITER_BP_READ_4_cce_SHIFT 0 |
| 9785 | #define GISB_ARBITER_BP_READ_4_cce_DISABLE 0 |
| 9786 | #define GISB_ARBITER_BP_READ_4_cce_ENABLE 1 |
| 9787 | |
| 9788 | |
| 9789 | /**************************************************************************** |
| 9790 | * GISB_ARBITER :: BP_WRITE_4 |
| 9791 | ***************************************************************************/ |
| 9792 | /* GISB_ARBITER :: BP_WRITE_4 :: reserved0 [31:06] */ |
| 9793 | #define GISB_ARBITER_BP_WRITE_4_reserved0_MASK 0xffffffc0 |
| 9794 | #define GISB_ARBITER_BP_WRITE_4_reserved0_ALIGN 0 |
| 9795 | #define GISB_ARBITER_BP_WRITE_4_reserved0_BITS 26 |
| 9796 | #define GISB_ARBITER_BP_WRITE_4_reserved0_SHIFT 6 |
| 9797 | |
| 9798 | /* GISB_ARBITER :: BP_WRITE_4 :: bsp [05:05] */ |
| 9799 | #define GISB_ARBITER_BP_WRITE_4_bsp_MASK 0x00000020 |
| 9800 | #define GISB_ARBITER_BP_WRITE_4_bsp_ALIGN 0 |
| 9801 | #define GISB_ARBITER_BP_WRITE_4_bsp_BITS 1 |
| 9802 | #define GISB_ARBITER_BP_WRITE_4_bsp_SHIFT 5 |
| 9803 | #define GISB_ARBITER_BP_WRITE_4_bsp_DISABLE 0 |
| 9804 | #define GISB_ARBITER_BP_WRITE_4_bsp_ENABLE 1 |
| 9805 | |
| 9806 | /* GISB_ARBITER :: BP_WRITE_4 :: aes [04:04] */ |
| 9807 | #define GISB_ARBITER_BP_WRITE_4_aes_MASK 0x00000010 |
| 9808 | #define GISB_ARBITER_BP_WRITE_4_aes_ALIGN 0 |
| 9809 | #define GISB_ARBITER_BP_WRITE_4_aes_BITS 1 |
| 9810 | #define GISB_ARBITER_BP_WRITE_4_aes_SHIFT 4 |
| 9811 | #define GISB_ARBITER_BP_WRITE_4_aes_DISABLE 0 |
| 9812 | #define GISB_ARBITER_BP_WRITE_4_aes_ENABLE 1 |
| 9813 | |
| 9814 | /* GISB_ARBITER :: BP_WRITE_4 :: fve [03:03] */ |
| 9815 | #define GISB_ARBITER_BP_WRITE_4_fve_MASK 0x00000008 |
| 9816 | #define GISB_ARBITER_BP_WRITE_4_fve_ALIGN 0 |
| 9817 | #define GISB_ARBITER_BP_WRITE_4_fve_BITS 1 |
| 9818 | #define GISB_ARBITER_BP_WRITE_4_fve_SHIFT 3 |
| 9819 | #define GISB_ARBITER_BP_WRITE_4_fve_DISABLE 0 |
| 9820 | #define GISB_ARBITER_BP_WRITE_4_fve_ENABLE 1 |
| 9821 | |
| 9822 | /* GISB_ARBITER :: BP_WRITE_4 :: tgt [02:02] */ |
| 9823 | #define GISB_ARBITER_BP_WRITE_4_tgt_MASK 0x00000004 |
| 9824 | #define GISB_ARBITER_BP_WRITE_4_tgt_ALIGN 0 |
| 9825 | #define GISB_ARBITER_BP_WRITE_4_tgt_BITS 1 |
| 9826 | #define GISB_ARBITER_BP_WRITE_4_tgt_SHIFT 2 |
| 9827 | #define GISB_ARBITER_BP_WRITE_4_tgt_DISABLE 0 |
| 9828 | #define GISB_ARBITER_BP_WRITE_4_tgt_ENABLE 1 |
| 9829 | |
| 9830 | /* GISB_ARBITER :: BP_WRITE_4 :: dbu [01:01] */ |
| 9831 | #define GISB_ARBITER_BP_WRITE_4_dbu_MASK 0x00000002 |
| 9832 | #define GISB_ARBITER_BP_WRITE_4_dbu_ALIGN 0 |
| 9833 | #define GISB_ARBITER_BP_WRITE_4_dbu_BITS 1 |
| 9834 | #define GISB_ARBITER_BP_WRITE_4_dbu_SHIFT 1 |
| 9835 | #define GISB_ARBITER_BP_WRITE_4_dbu_DISABLE 0 |
| 9836 | #define GISB_ARBITER_BP_WRITE_4_dbu_ENABLE 1 |
| 9837 | |
| 9838 | /* GISB_ARBITER :: BP_WRITE_4 :: cce [00:00] */ |
| 9839 | #define GISB_ARBITER_BP_WRITE_4_cce_MASK 0x00000001 |
| 9840 | #define GISB_ARBITER_BP_WRITE_4_cce_ALIGN 0 |
| 9841 | #define GISB_ARBITER_BP_WRITE_4_cce_BITS 1 |
| 9842 | #define GISB_ARBITER_BP_WRITE_4_cce_SHIFT 0 |
| 9843 | #define GISB_ARBITER_BP_WRITE_4_cce_DISABLE 0 |
| 9844 | #define GISB_ARBITER_BP_WRITE_4_cce_ENABLE 1 |
| 9845 | |
| 9846 | |
| 9847 | /**************************************************************************** |
| 9848 | * GISB_ARBITER :: BP_ENABLE_4 |
| 9849 | ***************************************************************************/ |
| 9850 | /* GISB_ARBITER :: BP_ENABLE_4 :: reserved0 [31:03] */ |
| 9851 | #define GISB_ARBITER_BP_ENABLE_4_reserved0_MASK 0xfffffff8 |
| 9852 | #define GISB_ARBITER_BP_ENABLE_4_reserved0_ALIGN 0 |
| 9853 | #define GISB_ARBITER_BP_ENABLE_4_reserved0_BITS 29 |
| 9854 | #define GISB_ARBITER_BP_ENABLE_4_reserved0_SHIFT 3 |
| 9855 | |
| 9856 | /* GISB_ARBITER :: BP_ENABLE_4 :: block [02:02] */ |
| 9857 | #define GISB_ARBITER_BP_ENABLE_4_block_MASK 0x00000004 |
| 9858 | #define GISB_ARBITER_BP_ENABLE_4_block_ALIGN 0 |
| 9859 | #define GISB_ARBITER_BP_ENABLE_4_block_BITS 1 |
| 9860 | #define GISB_ARBITER_BP_ENABLE_4_block_SHIFT 2 |
| 9861 | #define GISB_ARBITER_BP_ENABLE_4_block_DISABLE 0 |
| 9862 | #define GISB_ARBITER_BP_ENABLE_4_block_ENABLE 1 |
| 9863 | |
| 9864 | /* GISB_ARBITER :: BP_ENABLE_4 :: address [01:01] */ |
| 9865 | #define GISB_ARBITER_BP_ENABLE_4_address_MASK 0x00000002 |
| 9866 | #define GISB_ARBITER_BP_ENABLE_4_address_ALIGN 0 |
| 9867 | #define GISB_ARBITER_BP_ENABLE_4_address_BITS 1 |
| 9868 | #define GISB_ARBITER_BP_ENABLE_4_address_SHIFT 1 |
| 9869 | #define GISB_ARBITER_BP_ENABLE_4_address_DISABLE 0 |
| 9870 | #define GISB_ARBITER_BP_ENABLE_4_address_ENABLE 1 |
| 9871 | |
| 9872 | /* GISB_ARBITER :: BP_ENABLE_4 :: access [00:00] */ |
| 9873 | #define GISB_ARBITER_BP_ENABLE_4_access_MASK 0x00000001 |
| 9874 | #define GISB_ARBITER_BP_ENABLE_4_access_ALIGN 0 |
| 9875 | #define GISB_ARBITER_BP_ENABLE_4_access_BITS 1 |
| 9876 | #define GISB_ARBITER_BP_ENABLE_4_access_SHIFT 0 |
| 9877 | #define GISB_ARBITER_BP_ENABLE_4_access_DISABLE 0 |
| 9878 | #define GISB_ARBITER_BP_ENABLE_4_access_ENABLE 1 |
| 9879 | |
| 9880 | |
| 9881 | /**************************************************************************** |
| 9882 | * GISB_ARBITER :: BP_START_ADDR_5 |
| 9883 | ***************************************************************************/ |
| 9884 | /* GISB_ARBITER :: BP_START_ADDR_5 :: start [31:00] */ |
| 9885 | #define GISB_ARBITER_BP_START_ADDR_5_start_MASK 0xffffffff |
| 9886 | #define GISB_ARBITER_BP_START_ADDR_5_start_ALIGN 0 |
| 9887 | #define GISB_ARBITER_BP_START_ADDR_5_start_BITS 32 |
| 9888 | #define GISB_ARBITER_BP_START_ADDR_5_start_SHIFT 0 |
| 9889 | |
| 9890 | |
| 9891 | /**************************************************************************** |
| 9892 | * GISB_ARBITER :: BP_END_ADDR_5 |
| 9893 | ***************************************************************************/ |
| 9894 | /* GISB_ARBITER :: BP_END_ADDR_5 :: end [31:00] */ |
| 9895 | #define GISB_ARBITER_BP_END_ADDR_5_end_MASK 0xffffffff |
| 9896 | #define GISB_ARBITER_BP_END_ADDR_5_end_ALIGN 0 |
| 9897 | #define GISB_ARBITER_BP_END_ADDR_5_end_BITS 32 |
| 9898 | #define GISB_ARBITER_BP_END_ADDR_5_end_SHIFT 0 |
| 9899 | |
| 9900 | |
| 9901 | /**************************************************************************** |
| 9902 | * GISB_ARBITER :: BP_READ_5 |
| 9903 | ***************************************************************************/ |
| 9904 | /* GISB_ARBITER :: BP_READ_5 :: reserved0 [31:06] */ |
| 9905 | #define GISB_ARBITER_BP_READ_5_reserved0_MASK 0xffffffc0 |
| 9906 | #define GISB_ARBITER_BP_READ_5_reserved0_ALIGN 0 |
| 9907 | #define GISB_ARBITER_BP_READ_5_reserved0_BITS 26 |
| 9908 | #define GISB_ARBITER_BP_READ_5_reserved0_SHIFT 6 |
| 9909 | |
| 9910 | /* GISB_ARBITER :: BP_READ_5 :: bsp [05:05] */ |
| 9911 | #define GISB_ARBITER_BP_READ_5_bsp_MASK 0x00000020 |
| 9912 | #define GISB_ARBITER_BP_READ_5_bsp_ALIGN 0 |
| 9913 | #define GISB_ARBITER_BP_READ_5_bsp_BITS 1 |
| 9914 | #define GISB_ARBITER_BP_READ_5_bsp_SHIFT 5 |
| 9915 | #define GISB_ARBITER_BP_READ_5_bsp_DISABLE 0 |
| 9916 | #define GISB_ARBITER_BP_READ_5_bsp_ENABLE 1 |
| 9917 | |
| 9918 | /* GISB_ARBITER :: BP_READ_5 :: aes [04:04] */ |
| 9919 | #define GISB_ARBITER_BP_READ_5_aes_MASK 0x00000010 |
| 9920 | #define GISB_ARBITER_BP_READ_5_aes_ALIGN 0 |
| 9921 | #define GISB_ARBITER_BP_READ_5_aes_BITS 1 |
| 9922 | #define GISB_ARBITER_BP_READ_5_aes_SHIFT 4 |
| 9923 | #define GISB_ARBITER_BP_READ_5_aes_DISABLE 0 |
| 9924 | #define GISB_ARBITER_BP_READ_5_aes_ENABLE 1 |
| 9925 | |
| 9926 | /* GISB_ARBITER :: BP_READ_5 :: fve [03:03] */ |
| 9927 | #define GISB_ARBITER_BP_READ_5_fve_MASK 0x00000008 |
| 9928 | #define GISB_ARBITER_BP_READ_5_fve_ALIGN 0 |
| 9929 | #define GISB_ARBITER_BP_READ_5_fve_BITS 1 |
| 9930 | #define GISB_ARBITER_BP_READ_5_fve_SHIFT 3 |
| 9931 | #define GISB_ARBITER_BP_READ_5_fve_DISABLE 0 |
| 9932 | #define GISB_ARBITER_BP_READ_5_fve_ENABLE 1 |
| 9933 | |
| 9934 | /* GISB_ARBITER :: BP_READ_5 :: tgt [02:02] */ |
| 9935 | #define GISB_ARBITER_BP_READ_5_tgt_MASK 0x00000004 |
| 9936 | #define GISB_ARBITER_BP_READ_5_tgt_ALIGN 0 |
| 9937 | #define GISB_ARBITER_BP_READ_5_tgt_BITS 1 |
| 9938 | #define GISB_ARBITER_BP_READ_5_tgt_SHIFT 2 |
| 9939 | #define GISB_ARBITER_BP_READ_5_tgt_DISABLE 0 |
| 9940 | #define GISB_ARBITER_BP_READ_5_tgt_ENABLE 1 |
| 9941 | |
| 9942 | /* GISB_ARBITER :: BP_READ_5 :: dbu [01:01] */ |
| 9943 | #define GISB_ARBITER_BP_READ_5_dbu_MASK 0x00000002 |
| 9944 | #define GISB_ARBITER_BP_READ_5_dbu_ALIGN 0 |
| 9945 | #define GISB_ARBITER_BP_READ_5_dbu_BITS 1 |
| 9946 | #define GISB_ARBITER_BP_READ_5_dbu_SHIFT 1 |
| 9947 | #define GISB_ARBITER_BP_READ_5_dbu_DISABLE 0 |
| 9948 | #define GISB_ARBITER_BP_READ_5_dbu_ENABLE 1 |
| 9949 | |
| 9950 | /* GISB_ARBITER :: BP_READ_5 :: cce [00:00] */ |
| 9951 | #define GISB_ARBITER_BP_READ_5_cce_MASK 0x00000001 |
| 9952 | #define GISB_ARBITER_BP_READ_5_cce_ALIGN 0 |
| 9953 | #define GISB_ARBITER_BP_READ_5_cce_BITS 1 |
| 9954 | #define GISB_ARBITER_BP_READ_5_cce_SHIFT 0 |
| 9955 | #define GISB_ARBITER_BP_READ_5_cce_DISABLE 0 |
| 9956 | #define GISB_ARBITER_BP_READ_5_cce_ENABLE 1 |
| 9957 | |
| 9958 | |
| 9959 | /**************************************************************************** |
| 9960 | * GISB_ARBITER :: BP_WRITE_5 |
| 9961 | ***************************************************************************/ |
| 9962 | /* GISB_ARBITER :: BP_WRITE_5 :: reserved0 [31:06] */ |
| 9963 | #define GISB_ARBITER_BP_WRITE_5_reserved0_MASK 0xffffffc0 |
| 9964 | #define GISB_ARBITER_BP_WRITE_5_reserved0_ALIGN 0 |
| 9965 | #define GISB_ARBITER_BP_WRITE_5_reserved0_BITS 26 |
| 9966 | #define GISB_ARBITER_BP_WRITE_5_reserved0_SHIFT 6 |
| 9967 | |
| 9968 | /* GISB_ARBITER :: BP_WRITE_5 :: bsp [05:05] */ |
| 9969 | #define GISB_ARBITER_BP_WRITE_5_bsp_MASK 0x00000020 |
| 9970 | #define GISB_ARBITER_BP_WRITE_5_bsp_ALIGN 0 |
| 9971 | #define GISB_ARBITER_BP_WRITE_5_bsp_BITS 1 |
| 9972 | #define GISB_ARBITER_BP_WRITE_5_bsp_SHIFT 5 |
| 9973 | #define GISB_ARBITER_BP_WRITE_5_bsp_DISABLE 0 |
| 9974 | #define GISB_ARBITER_BP_WRITE_5_bsp_ENABLE 1 |
| 9975 | |
| 9976 | /* GISB_ARBITER :: BP_WRITE_5 :: aes [04:04] */ |
| 9977 | #define GISB_ARBITER_BP_WRITE_5_aes_MASK 0x00000010 |
| 9978 | #define GISB_ARBITER_BP_WRITE_5_aes_ALIGN 0 |
| 9979 | #define GISB_ARBITER_BP_WRITE_5_aes_BITS 1 |
| 9980 | #define GISB_ARBITER_BP_WRITE_5_aes_SHIFT 4 |
| 9981 | #define GISB_ARBITER_BP_WRITE_5_aes_DISABLE 0 |
| 9982 | #define GISB_ARBITER_BP_WRITE_5_aes_ENABLE 1 |
| 9983 | |
| 9984 | /* GISB_ARBITER :: BP_WRITE_5 :: fve [03:03] */ |
| 9985 | #define GISB_ARBITER_BP_WRITE_5_fve_MASK 0x00000008 |
| 9986 | #define GISB_ARBITER_BP_WRITE_5_fve_ALIGN 0 |
| 9987 | #define GISB_ARBITER_BP_WRITE_5_fve_BITS 1 |
| 9988 | #define GISB_ARBITER_BP_WRITE_5_fve_SHIFT 3 |
| 9989 | #define GISB_ARBITER_BP_WRITE_5_fve_DISABLE 0 |
| 9990 | #define GISB_ARBITER_BP_WRITE_5_fve_ENABLE 1 |
| 9991 | |
| 9992 | /* GISB_ARBITER :: BP_WRITE_5 :: tgt [02:02] */ |
| 9993 | #define GISB_ARBITER_BP_WRITE_5_tgt_MASK 0x00000004 |
| 9994 | #define GISB_ARBITER_BP_WRITE_5_tgt_ALIGN 0 |
| 9995 | #define GISB_ARBITER_BP_WRITE_5_tgt_BITS 1 |
| 9996 | #define GISB_ARBITER_BP_WRITE_5_tgt_SHIFT 2 |
| 9997 | #define GISB_ARBITER_BP_WRITE_5_tgt_DISABLE 0 |
| 9998 | #define GISB_ARBITER_BP_WRITE_5_tgt_ENABLE 1 |
| 9999 | |
| 10000 | /* GISB_ARBITER :: BP_WRITE_5 :: dbu [01:01] */ |
| 10001 | #define GISB_ARBITER_BP_WRITE_5_dbu_MASK 0x00000002 |
| 10002 | #define GISB_ARBITER_BP_WRITE_5_dbu_ALIGN 0 |
| 10003 | #define GISB_ARBITER_BP_WRITE_5_dbu_BITS 1 |
| 10004 | #define GISB_ARBITER_BP_WRITE_5_dbu_SHIFT 1 |
| 10005 | #define GISB_ARBITER_BP_WRITE_5_dbu_DISABLE 0 |
| 10006 | #define GISB_ARBITER_BP_WRITE_5_dbu_ENABLE 1 |
| 10007 | |
| 10008 | /* GISB_ARBITER :: BP_WRITE_5 :: cce [00:00] */ |
| 10009 | #define GISB_ARBITER_BP_WRITE_5_cce_MASK 0x00000001 |
| 10010 | #define GISB_ARBITER_BP_WRITE_5_cce_ALIGN 0 |
| 10011 | #define GISB_ARBITER_BP_WRITE_5_cce_BITS 1 |
| 10012 | #define GISB_ARBITER_BP_WRITE_5_cce_SHIFT 0 |
| 10013 | #define GISB_ARBITER_BP_WRITE_5_cce_DISABLE 0 |
| 10014 | #define GISB_ARBITER_BP_WRITE_5_cce_ENABLE 1 |
| 10015 | |
| 10016 | |
| 10017 | /**************************************************************************** |
| 10018 | * GISB_ARBITER :: BP_ENABLE_5 |
| 10019 | ***************************************************************************/ |
| 10020 | /* GISB_ARBITER :: BP_ENABLE_5 :: reserved0 [31:03] */ |
| 10021 | #define GISB_ARBITER_BP_ENABLE_5_reserved0_MASK 0xfffffff8 |
| 10022 | #define GISB_ARBITER_BP_ENABLE_5_reserved0_ALIGN 0 |
| 10023 | #define GISB_ARBITER_BP_ENABLE_5_reserved0_BITS 29 |
| 10024 | #define GISB_ARBITER_BP_ENABLE_5_reserved0_SHIFT 3 |
| 10025 | |
| 10026 | /* GISB_ARBITER :: BP_ENABLE_5 :: block [02:02] */ |
| 10027 | #define GISB_ARBITER_BP_ENABLE_5_block_MASK 0x00000004 |
| 10028 | #define GISB_ARBITER_BP_ENABLE_5_block_ALIGN 0 |
| 10029 | #define GISB_ARBITER_BP_ENABLE_5_block_BITS 1 |
| 10030 | #define GISB_ARBITER_BP_ENABLE_5_block_SHIFT 2 |
| 10031 | #define GISB_ARBITER_BP_ENABLE_5_block_DISABLE 0 |
| 10032 | #define GISB_ARBITER_BP_ENABLE_5_block_ENABLE 1 |
| 10033 | |
| 10034 | /* GISB_ARBITER :: BP_ENABLE_5 :: address [01:01] */ |
| 10035 | #define GISB_ARBITER_BP_ENABLE_5_address_MASK 0x00000002 |
| 10036 | #define GISB_ARBITER_BP_ENABLE_5_address_ALIGN 0 |
| 10037 | #define GISB_ARBITER_BP_ENABLE_5_address_BITS 1 |
| 10038 | #define GISB_ARBITER_BP_ENABLE_5_address_SHIFT 1 |
| 10039 | #define GISB_ARBITER_BP_ENABLE_5_address_DISABLE 0 |
| 10040 | #define GISB_ARBITER_BP_ENABLE_5_address_ENABLE 1 |
| 10041 | |
| 10042 | /* GISB_ARBITER :: BP_ENABLE_5 :: access [00:00] */ |
| 10043 | #define GISB_ARBITER_BP_ENABLE_5_access_MASK 0x00000001 |
| 10044 | #define GISB_ARBITER_BP_ENABLE_5_access_ALIGN 0 |
| 10045 | #define GISB_ARBITER_BP_ENABLE_5_access_BITS 1 |
| 10046 | #define GISB_ARBITER_BP_ENABLE_5_access_SHIFT 0 |
| 10047 | #define GISB_ARBITER_BP_ENABLE_5_access_DISABLE 0 |
| 10048 | #define GISB_ARBITER_BP_ENABLE_5_access_ENABLE 1 |
| 10049 | |
| 10050 | |
| 10051 | /**************************************************************************** |
| 10052 | * GISB_ARBITER :: BP_START_ADDR_6 |
| 10053 | ***************************************************************************/ |
| 10054 | /* GISB_ARBITER :: BP_START_ADDR_6 :: start [31:00] */ |
| 10055 | #define GISB_ARBITER_BP_START_ADDR_6_start_MASK 0xffffffff |
| 10056 | #define GISB_ARBITER_BP_START_ADDR_6_start_ALIGN 0 |
| 10057 | #define GISB_ARBITER_BP_START_ADDR_6_start_BITS 32 |
| 10058 | #define GISB_ARBITER_BP_START_ADDR_6_start_SHIFT 0 |
| 10059 | |
| 10060 | |
| 10061 | /**************************************************************************** |
| 10062 | * GISB_ARBITER :: BP_END_ADDR_6 |
| 10063 | ***************************************************************************/ |
| 10064 | /* GISB_ARBITER :: BP_END_ADDR_6 :: end [31:00] */ |
| 10065 | #define GISB_ARBITER_BP_END_ADDR_6_end_MASK 0xffffffff |
| 10066 | #define GISB_ARBITER_BP_END_ADDR_6_end_ALIGN 0 |
| 10067 | #define GISB_ARBITER_BP_END_ADDR_6_end_BITS 32 |
| 10068 | #define GISB_ARBITER_BP_END_ADDR_6_end_SHIFT 0 |
| 10069 | |
| 10070 | |
| 10071 | /**************************************************************************** |
| 10072 | * GISB_ARBITER :: BP_READ_6 |
| 10073 | ***************************************************************************/ |
| 10074 | /* GISB_ARBITER :: BP_READ_6 :: reserved0 [31:06] */ |
| 10075 | #define GISB_ARBITER_BP_READ_6_reserved0_MASK 0xffffffc0 |
| 10076 | #define GISB_ARBITER_BP_READ_6_reserved0_ALIGN 0 |
| 10077 | #define GISB_ARBITER_BP_READ_6_reserved0_BITS 26 |
| 10078 | #define GISB_ARBITER_BP_READ_6_reserved0_SHIFT 6 |
| 10079 | |
| 10080 | /* GISB_ARBITER :: BP_READ_6 :: bsp [05:05] */ |
| 10081 | #define GISB_ARBITER_BP_READ_6_bsp_MASK 0x00000020 |
| 10082 | #define GISB_ARBITER_BP_READ_6_bsp_ALIGN 0 |
| 10083 | #define GISB_ARBITER_BP_READ_6_bsp_BITS 1 |
| 10084 | #define GISB_ARBITER_BP_READ_6_bsp_SHIFT 5 |
| 10085 | #define GISB_ARBITER_BP_READ_6_bsp_DISABLE 0 |
| 10086 | #define GISB_ARBITER_BP_READ_6_bsp_ENABLE 1 |
| 10087 | |
| 10088 | /* GISB_ARBITER :: BP_READ_6 :: aes [04:04] */ |
| 10089 | #define GISB_ARBITER_BP_READ_6_aes_MASK 0x00000010 |
| 10090 | #define GISB_ARBITER_BP_READ_6_aes_ALIGN 0 |
| 10091 | #define GISB_ARBITER_BP_READ_6_aes_BITS 1 |
| 10092 | #define GISB_ARBITER_BP_READ_6_aes_SHIFT 4 |
| 10093 | #define GISB_ARBITER_BP_READ_6_aes_DISABLE 0 |
| 10094 | #define GISB_ARBITER_BP_READ_6_aes_ENABLE 1 |
| 10095 | |
| 10096 | /* GISB_ARBITER :: BP_READ_6 :: fve [03:03] */ |
| 10097 | #define GISB_ARBITER_BP_READ_6_fve_MASK 0x00000008 |
| 10098 | #define GISB_ARBITER_BP_READ_6_fve_ALIGN 0 |
| 10099 | #define GISB_ARBITER_BP_READ_6_fve_BITS 1 |
| 10100 | #define GISB_ARBITER_BP_READ_6_fve_SHIFT 3 |
| 10101 | #define GISB_ARBITER_BP_READ_6_fve_DISABLE 0 |
| 10102 | #define GISB_ARBITER_BP_READ_6_fve_ENABLE 1 |
| 10103 | |
| 10104 | /* GISB_ARBITER :: BP_READ_6 :: tgt [02:02] */ |
| 10105 | #define GISB_ARBITER_BP_READ_6_tgt_MASK 0x00000004 |
| 10106 | #define GISB_ARBITER_BP_READ_6_tgt_ALIGN 0 |
| 10107 | #define GISB_ARBITER_BP_READ_6_tgt_BITS 1 |
| 10108 | #define GISB_ARBITER_BP_READ_6_tgt_SHIFT 2 |
| 10109 | #define GISB_ARBITER_BP_READ_6_tgt_DISABLE 0 |
| 10110 | #define GISB_ARBITER_BP_READ_6_tgt_ENABLE 1 |
| 10111 | |
| 10112 | /* GISB_ARBITER :: BP_READ_6 :: dbu [01:01] */ |
| 10113 | #define GISB_ARBITER_BP_READ_6_dbu_MASK 0x00000002 |
| 10114 | #define GISB_ARBITER_BP_READ_6_dbu_ALIGN 0 |
| 10115 | #define GISB_ARBITER_BP_READ_6_dbu_BITS 1 |
| 10116 | #define GISB_ARBITER_BP_READ_6_dbu_SHIFT 1 |
| 10117 | #define GISB_ARBITER_BP_READ_6_dbu_DISABLE 0 |
| 10118 | #define GISB_ARBITER_BP_READ_6_dbu_ENABLE 1 |
| 10119 | |
| 10120 | /* GISB_ARBITER :: BP_READ_6 :: cce [00:00] */ |
| 10121 | #define GISB_ARBITER_BP_READ_6_cce_MASK 0x00000001 |
| 10122 | #define GISB_ARBITER_BP_READ_6_cce_ALIGN 0 |
| 10123 | #define GISB_ARBITER_BP_READ_6_cce_BITS 1 |
| 10124 | #define GISB_ARBITER_BP_READ_6_cce_SHIFT 0 |
| 10125 | #define GISB_ARBITER_BP_READ_6_cce_DISABLE 0 |
| 10126 | #define GISB_ARBITER_BP_READ_6_cce_ENABLE 1 |
| 10127 | |
| 10128 | |
| 10129 | /**************************************************************************** |
| 10130 | * GISB_ARBITER :: BP_WRITE_6 |
| 10131 | ***************************************************************************/ |
| 10132 | /* GISB_ARBITER :: BP_WRITE_6 :: reserved0 [31:06] */ |
| 10133 | #define GISB_ARBITER_BP_WRITE_6_reserved0_MASK 0xffffffc0 |
| 10134 | #define GISB_ARBITER_BP_WRITE_6_reserved0_ALIGN 0 |
| 10135 | #define GISB_ARBITER_BP_WRITE_6_reserved0_BITS 26 |
| 10136 | #define GISB_ARBITER_BP_WRITE_6_reserved0_SHIFT 6 |
| 10137 | |
| 10138 | /* GISB_ARBITER :: BP_WRITE_6 :: bsp [05:05] */ |
| 10139 | #define GISB_ARBITER_BP_WRITE_6_bsp_MASK 0x00000020 |
| 10140 | #define GISB_ARBITER_BP_WRITE_6_bsp_ALIGN 0 |
| 10141 | #define GISB_ARBITER_BP_WRITE_6_bsp_BITS 1 |
| 10142 | #define GISB_ARBITER_BP_WRITE_6_bsp_SHIFT 5 |
| 10143 | #define GISB_ARBITER_BP_WRITE_6_bsp_DISABLE 0 |
| 10144 | #define GISB_ARBITER_BP_WRITE_6_bsp_ENABLE 1 |
| 10145 | |
| 10146 | /* GISB_ARBITER :: BP_WRITE_6 :: aes [04:04] */ |
| 10147 | #define GISB_ARBITER_BP_WRITE_6_aes_MASK 0x00000010 |
| 10148 | #define GISB_ARBITER_BP_WRITE_6_aes_ALIGN 0 |
| 10149 | #define GISB_ARBITER_BP_WRITE_6_aes_BITS 1 |
| 10150 | #define GISB_ARBITER_BP_WRITE_6_aes_SHIFT 4 |
| 10151 | #define GISB_ARBITER_BP_WRITE_6_aes_DISABLE 0 |
| 10152 | #define GISB_ARBITER_BP_WRITE_6_aes_ENABLE 1 |
| 10153 | |
| 10154 | /* GISB_ARBITER :: BP_WRITE_6 :: fve [03:03] */ |
| 10155 | #define GISB_ARBITER_BP_WRITE_6_fve_MASK 0x00000008 |
| 10156 | #define GISB_ARBITER_BP_WRITE_6_fve_ALIGN 0 |
| 10157 | #define GISB_ARBITER_BP_WRITE_6_fve_BITS 1 |
| 10158 | #define GISB_ARBITER_BP_WRITE_6_fve_SHIFT 3 |
| 10159 | #define GISB_ARBITER_BP_WRITE_6_fve_DISABLE 0 |
| 10160 | #define GISB_ARBITER_BP_WRITE_6_fve_ENABLE 1 |
| 10161 | |
| 10162 | /* GISB_ARBITER :: BP_WRITE_6 :: tgt [02:02] */ |
| 10163 | #define GISB_ARBITER_BP_WRITE_6_tgt_MASK 0x00000004 |
| 10164 | #define GISB_ARBITER_BP_WRITE_6_tgt_ALIGN 0 |
| 10165 | #define GISB_ARBITER_BP_WRITE_6_tgt_BITS 1 |
| 10166 | #define GISB_ARBITER_BP_WRITE_6_tgt_SHIFT 2 |
| 10167 | #define GISB_ARBITER_BP_WRITE_6_tgt_DISABLE 0 |
| 10168 | #define GISB_ARBITER_BP_WRITE_6_tgt_ENABLE 1 |
| 10169 | |
| 10170 | /* GISB_ARBITER :: BP_WRITE_6 :: dbu [01:01] */ |
| 10171 | #define GISB_ARBITER_BP_WRITE_6_dbu_MASK 0x00000002 |
| 10172 | #define GISB_ARBITER_BP_WRITE_6_dbu_ALIGN 0 |
| 10173 | #define GISB_ARBITER_BP_WRITE_6_dbu_BITS 1 |
| 10174 | #define GISB_ARBITER_BP_WRITE_6_dbu_SHIFT 1 |
| 10175 | #define GISB_ARBITER_BP_WRITE_6_dbu_DISABLE 0 |
| 10176 | #define GISB_ARBITER_BP_WRITE_6_dbu_ENABLE 1 |
| 10177 | |
| 10178 | /* GISB_ARBITER :: BP_WRITE_6 :: cce [00:00] */ |
| 10179 | #define GISB_ARBITER_BP_WRITE_6_cce_MASK 0x00000001 |
| 10180 | #define GISB_ARBITER_BP_WRITE_6_cce_ALIGN 0 |
| 10181 | #define GISB_ARBITER_BP_WRITE_6_cce_BITS 1 |
| 10182 | #define GISB_ARBITER_BP_WRITE_6_cce_SHIFT 0 |
| 10183 | #define GISB_ARBITER_BP_WRITE_6_cce_DISABLE 0 |
| 10184 | #define GISB_ARBITER_BP_WRITE_6_cce_ENABLE 1 |
| 10185 | |
| 10186 | |
| 10187 | /**************************************************************************** |
| 10188 | * GISB_ARBITER :: BP_ENABLE_6 |
| 10189 | ***************************************************************************/ |
| 10190 | /* GISB_ARBITER :: BP_ENABLE_6 :: reserved0 [31:03] */ |
| 10191 | #define GISB_ARBITER_BP_ENABLE_6_reserved0_MASK 0xfffffff8 |
| 10192 | #define GISB_ARBITER_BP_ENABLE_6_reserved0_ALIGN 0 |
| 10193 | #define GISB_ARBITER_BP_ENABLE_6_reserved0_BITS 29 |
| 10194 | #define GISB_ARBITER_BP_ENABLE_6_reserved0_SHIFT 3 |
| 10195 | |
| 10196 | /* GISB_ARBITER :: BP_ENABLE_6 :: block [02:02] */ |
| 10197 | #define GISB_ARBITER_BP_ENABLE_6_block_MASK 0x00000004 |
| 10198 | #define GISB_ARBITER_BP_ENABLE_6_block_ALIGN 0 |
| 10199 | #define GISB_ARBITER_BP_ENABLE_6_block_BITS 1 |
| 10200 | #define GISB_ARBITER_BP_ENABLE_6_block_SHIFT 2 |
| 10201 | #define GISB_ARBITER_BP_ENABLE_6_block_DISABLE 0 |
| 10202 | #define GISB_ARBITER_BP_ENABLE_6_block_ENABLE 1 |
| 10203 | |
| 10204 | /* GISB_ARBITER :: BP_ENABLE_6 :: address [01:01] */ |
| 10205 | #define GISB_ARBITER_BP_ENABLE_6_address_MASK 0x00000002 |
| 10206 | #define GISB_ARBITER_BP_ENABLE_6_address_ALIGN 0 |
| 10207 | #define GISB_ARBITER_BP_ENABLE_6_address_BITS 1 |
| 10208 | #define GISB_ARBITER_BP_ENABLE_6_address_SHIFT 1 |
| 10209 | #define GISB_ARBITER_BP_ENABLE_6_address_DISABLE 0 |
| 10210 | #define GISB_ARBITER_BP_ENABLE_6_address_ENABLE 1 |
| 10211 | |
| 10212 | /* GISB_ARBITER :: BP_ENABLE_6 :: access [00:00] */ |
| 10213 | #define GISB_ARBITER_BP_ENABLE_6_access_MASK 0x00000001 |
| 10214 | #define GISB_ARBITER_BP_ENABLE_6_access_ALIGN 0 |
| 10215 | #define GISB_ARBITER_BP_ENABLE_6_access_BITS 1 |
| 10216 | #define GISB_ARBITER_BP_ENABLE_6_access_SHIFT 0 |
| 10217 | #define GISB_ARBITER_BP_ENABLE_6_access_DISABLE 0 |
| 10218 | #define GISB_ARBITER_BP_ENABLE_6_access_ENABLE 1 |
| 10219 | |
| 10220 | |
| 10221 | /**************************************************************************** |
| 10222 | * GISB_ARBITER :: BP_START_ADDR_7 |
| 10223 | ***************************************************************************/ |
| 10224 | /* GISB_ARBITER :: BP_START_ADDR_7 :: start [31:00] */ |
| 10225 | #define GISB_ARBITER_BP_START_ADDR_7_start_MASK 0xffffffff |
| 10226 | #define GISB_ARBITER_BP_START_ADDR_7_start_ALIGN 0 |
| 10227 | #define GISB_ARBITER_BP_START_ADDR_7_start_BITS 32 |
| 10228 | #define GISB_ARBITER_BP_START_ADDR_7_start_SHIFT 0 |
| 10229 | |
| 10230 | |
| 10231 | /**************************************************************************** |
| 10232 | * GISB_ARBITER :: BP_END_ADDR_7 |
| 10233 | ***************************************************************************/ |
| 10234 | /* GISB_ARBITER :: BP_END_ADDR_7 :: end [31:00] */ |
| 10235 | #define GISB_ARBITER_BP_END_ADDR_7_end_MASK 0xffffffff |
| 10236 | #define GISB_ARBITER_BP_END_ADDR_7_end_ALIGN 0 |
| 10237 | #define GISB_ARBITER_BP_END_ADDR_7_end_BITS 32 |
| 10238 | #define GISB_ARBITER_BP_END_ADDR_7_end_SHIFT 0 |
| 10239 | |
| 10240 | |
| 10241 | /**************************************************************************** |
| 10242 | * GISB_ARBITER :: BP_READ_7 |
| 10243 | ***************************************************************************/ |
| 10244 | /* GISB_ARBITER :: BP_READ_7 :: reserved0 [31:06] */ |
| 10245 | #define GISB_ARBITER_BP_READ_7_reserved0_MASK 0xffffffc0 |
| 10246 | #define GISB_ARBITER_BP_READ_7_reserved0_ALIGN 0 |
| 10247 | #define GISB_ARBITER_BP_READ_7_reserved0_BITS 26 |
| 10248 | #define GISB_ARBITER_BP_READ_7_reserved0_SHIFT 6 |
| 10249 | |
| 10250 | /* GISB_ARBITER :: BP_READ_7 :: bsp [05:05] */ |
| 10251 | #define GISB_ARBITER_BP_READ_7_bsp_MASK 0x00000020 |
| 10252 | #define GISB_ARBITER_BP_READ_7_bsp_ALIGN 0 |
| 10253 | #define GISB_ARBITER_BP_READ_7_bsp_BITS 1 |
| 10254 | #define GISB_ARBITER_BP_READ_7_bsp_SHIFT 5 |
| 10255 | #define GISB_ARBITER_BP_READ_7_bsp_DISABLE 0 |
| 10256 | #define GISB_ARBITER_BP_READ_7_bsp_ENABLE 1 |
| 10257 | |
| 10258 | /* GISB_ARBITER :: BP_READ_7 :: aes [04:04] */ |
| 10259 | #define GISB_ARBITER_BP_READ_7_aes_MASK 0x00000010 |
| 10260 | #define GISB_ARBITER_BP_READ_7_aes_ALIGN 0 |
| 10261 | #define GISB_ARBITER_BP_READ_7_aes_BITS 1 |
| 10262 | #define GISB_ARBITER_BP_READ_7_aes_SHIFT 4 |
| 10263 | #define GISB_ARBITER_BP_READ_7_aes_DISABLE 0 |
| 10264 | #define GISB_ARBITER_BP_READ_7_aes_ENABLE 1 |
| 10265 | |
| 10266 | /* GISB_ARBITER :: BP_READ_7 :: fve [03:03] */ |
| 10267 | #define GISB_ARBITER_BP_READ_7_fve_MASK 0x00000008 |
| 10268 | #define GISB_ARBITER_BP_READ_7_fve_ALIGN 0 |
| 10269 | #define GISB_ARBITER_BP_READ_7_fve_BITS 1 |
| 10270 | #define GISB_ARBITER_BP_READ_7_fve_SHIFT 3 |
| 10271 | #define GISB_ARBITER_BP_READ_7_fve_DISABLE 0 |
| 10272 | #define GISB_ARBITER_BP_READ_7_fve_ENABLE 1 |
| 10273 | |
| 10274 | /* GISB_ARBITER :: BP_READ_7 :: tgt [02:02] */ |
| 10275 | #define GISB_ARBITER_BP_READ_7_tgt_MASK 0x00000004 |
| 10276 | #define GISB_ARBITER_BP_READ_7_tgt_ALIGN 0 |
| 10277 | #define GISB_ARBITER_BP_READ_7_tgt_BITS 1 |
| 10278 | #define GISB_ARBITER_BP_READ_7_tgt_SHIFT 2 |
| 10279 | #define GISB_ARBITER_BP_READ_7_tgt_DISABLE 0 |
| 10280 | #define GISB_ARBITER_BP_READ_7_tgt_ENABLE 1 |
| 10281 | |
| 10282 | /* GISB_ARBITER :: BP_READ_7 :: dbu [01:01] */ |
| 10283 | #define GISB_ARBITER_BP_READ_7_dbu_MASK 0x00000002 |
| 10284 | #define GISB_ARBITER_BP_READ_7_dbu_ALIGN 0 |
| 10285 | #define GISB_ARBITER_BP_READ_7_dbu_BITS 1 |
| 10286 | #define GISB_ARBITER_BP_READ_7_dbu_SHIFT 1 |
| 10287 | #define GISB_ARBITER_BP_READ_7_dbu_DISABLE 0 |
| 10288 | #define GISB_ARBITER_BP_READ_7_dbu_ENABLE 1 |
| 10289 | |
| 10290 | /* GISB_ARBITER :: BP_READ_7 :: cce [00:00] */ |
| 10291 | #define GISB_ARBITER_BP_READ_7_cce_MASK 0x00000001 |
| 10292 | #define GISB_ARBITER_BP_READ_7_cce_ALIGN 0 |
| 10293 | #define GISB_ARBITER_BP_READ_7_cce_BITS 1 |
| 10294 | #define GISB_ARBITER_BP_READ_7_cce_SHIFT 0 |
| 10295 | #define GISB_ARBITER_BP_READ_7_cce_DISABLE 0 |
| 10296 | #define GISB_ARBITER_BP_READ_7_cce_ENABLE 1 |
| 10297 | |
| 10298 | |
| 10299 | /**************************************************************************** |
| 10300 | * GISB_ARBITER :: BP_WRITE_7 |
| 10301 | ***************************************************************************/ |
| 10302 | /* GISB_ARBITER :: BP_WRITE_7 :: reserved0 [31:06] */ |
| 10303 | #define GISB_ARBITER_BP_WRITE_7_reserved0_MASK 0xffffffc0 |
| 10304 | #define GISB_ARBITER_BP_WRITE_7_reserved0_ALIGN 0 |
| 10305 | #define GISB_ARBITER_BP_WRITE_7_reserved0_BITS 26 |
| 10306 | #define GISB_ARBITER_BP_WRITE_7_reserved0_SHIFT 6 |
| 10307 | |
| 10308 | /* GISB_ARBITER :: BP_WRITE_7 :: bsp [05:05] */ |
| 10309 | #define GISB_ARBITER_BP_WRITE_7_bsp_MASK 0x00000020 |
| 10310 | #define GISB_ARBITER_BP_WRITE_7_bsp_ALIGN 0 |
| 10311 | #define GISB_ARBITER_BP_WRITE_7_bsp_BITS 1 |
| 10312 | #define GISB_ARBITER_BP_WRITE_7_bsp_SHIFT 5 |
| 10313 | #define GISB_ARBITER_BP_WRITE_7_bsp_DISABLE 0 |
| 10314 | #define GISB_ARBITER_BP_WRITE_7_bsp_ENABLE 1 |
| 10315 | |
| 10316 | /* GISB_ARBITER :: BP_WRITE_7 :: aes [04:04] */ |
| 10317 | #define GISB_ARBITER_BP_WRITE_7_aes_MASK 0x00000010 |
| 10318 | #define GISB_ARBITER_BP_WRITE_7_aes_ALIGN 0 |
| 10319 | #define GISB_ARBITER_BP_WRITE_7_aes_BITS 1 |
| 10320 | #define GISB_ARBITER_BP_WRITE_7_aes_SHIFT 4 |
| 10321 | #define GISB_ARBITER_BP_WRITE_7_aes_DISABLE 0 |
| 10322 | #define GISB_ARBITER_BP_WRITE_7_aes_ENABLE 1 |
| 10323 | |
| 10324 | /* GISB_ARBITER :: BP_WRITE_7 :: fve [03:03] */ |
| 10325 | #define GISB_ARBITER_BP_WRITE_7_fve_MASK 0x00000008 |
| 10326 | #define GISB_ARBITER_BP_WRITE_7_fve_ALIGN 0 |
| 10327 | #define GISB_ARBITER_BP_WRITE_7_fve_BITS 1 |
| 10328 | #define GISB_ARBITER_BP_WRITE_7_fve_SHIFT 3 |
| 10329 | #define GISB_ARBITER_BP_WRITE_7_fve_DISABLE 0 |
| 10330 | #define GISB_ARBITER_BP_WRITE_7_fve_ENABLE 1 |
| 10331 | |
| 10332 | /* GISB_ARBITER :: BP_WRITE_7 :: tgt [02:02] */ |
| 10333 | #define GISB_ARBITER_BP_WRITE_7_tgt_MASK 0x00000004 |
| 10334 | #define GISB_ARBITER_BP_WRITE_7_tgt_ALIGN 0 |
| 10335 | #define GISB_ARBITER_BP_WRITE_7_tgt_BITS 1 |
| 10336 | #define GISB_ARBITER_BP_WRITE_7_tgt_SHIFT 2 |
| 10337 | #define GISB_ARBITER_BP_WRITE_7_tgt_DISABLE 0 |
| 10338 | #define GISB_ARBITER_BP_WRITE_7_tgt_ENABLE 1 |
| 10339 | |
| 10340 | /* GISB_ARBITER :: BP_WRITE_7 :: dbu [01:01] */ |
| 10341 | #define GISB_ARBITER_BP_WRITE_7_dbu_MASK 0x00000002 |
| 10342 | #define GISB_ARBITER_BP_WRITE_7_dbu_ALIGN 0 |
| 10343 | #define GISB_ARBITER_BP_WRITE_7_dbu_BITS 1 |
| 10344 | #define GISB_ARBITER_BP_WRITE_7_dbu_SHIFT 1 |
| 10345 | #define GISB_ARBITER_BP_WRITE_7_dbu_DISABLE 0 |
| 10346 | #define GISB_ARBITER_BP_WRITE_7_dbu_ENABLE 1 |
| 10347 | |
| 10348 | /* GISB_ARBITER :: BP_WRITE_7 :: cce [00:00] */ |
| 10349 | #define GISB_ARBITER_BP_WRITE_7_cce_MASK 0x00000001 |
| 10350 | #define GISB_ARBITER_BP_WRITE_7_cce_ALIGN 0 |
| 10351 | #define GISB_ARBITER_BP_WRITE_7_cce_BITS 1 |
| 10352 | #define GISB_ARBITER_BP_WRITE_7_cce_SHIFT 0 |
| 10353 | #define GISB_ARBITER_BP_WRITE_7_cce_DISABLE 0 |
| 10354 | #define GISB_ARBITER_BP_WRITE_7_cce_ENABLE 1 |
| 10355 | |
| 10356 | |
| 10357 | /**************************************************************************** |
| 10358 | * GISB_ARBITER :: BP_ENABLE_7 |
| 10359 | ***************************************************************************/ |
| 10360 | /* GISB_ARBITER :: BP_ENABLE_7 :: reserved0 [31:03] */ |
| 10361 | #define GISB_ARBITER_BP_ENABLE_7_reserved0_MASK 0xfffffff8 |
| 10362 | #define GISB_ARBITER_BP_ENABLE_7_reserved0_ALIGN 0 |
| 10363 | #define GISB_ARBITER_BP_ENABLE_7_reserved0_BITS 29 |
| 10364 | #define GISB_ARBITER_BP_ENABLE_7_reserved0_SHIFT 3 |
| 10365 | |
| 10366 | /* GISB_ARBITER :: BP_ENABLE_7 :: block [02:02] */ |
| 10367 | #define GISB_ARBITER_BP_ENABLE_7_block_MASK 0x00000004 |
| 10368 | #define GISB_ARBITER_BP_ENABLE_7_block_ALIGN 0 |
| 10369 | #define GISB_ARBITER_BP_ENABLE_7_block_BITS 1 |
| 10370 | #define GISB_ARBITER_BP_ENABLE_7_block_SHIFT 2 |
| 10371 | #define GISB_ARBITER_BP_ENABLE_7_block_DISABLE 0 |
| 10372 | #define GISB_ARBITER_BP_ENABLE_7_block_ENABLE 1 |
| 10373 | |
| 10374 | /* GISB_ARBITER :: BP_ENABLE_7 :: address [01:01] */ |
| 10375 | #define GISB_ARBITER_BP_ENABLE_7_address_MASK 0x00000002 |
| 10376 | #define GISB_ARBITER_BP_ENABLE_7_address_ALIGN 0 |
| 10377 | #define GISB_ARBITER_BP_ENABLE_7_address_BITS 1 |
| 10378 | #define GISB_ARBITER_BP_ENABLE_7_address_SHIFT 1 |
| 10379 | #define GISB_ARBITER_BP_ENABLE_7_address_DISABLE 0 |
| 10380 | #define GISB_ARBITER_BP_ENABLE_7_address_ENABLE 1 |
| 10381 | |
| 10382 | /* GISB_ARBITER :: BP_ENABLE_7 :: access [00:00] */ |
| 10383 | #define GISB_ARBITER_BP_ENABLE_7_access_MASK 0x00000001 |
| 10384 | #define GISB_ARBITER_BP_ENABLE_7_access_ALIGN 0 |
| 10385 | #define GISB_ARBITER_BP_ENABLE_7_access_BITS 1 |
| 10386 | #define GISB_ARBITER_BP_ENABLE_7_access_SHIFT 0 |
| 10387 | #define GISB_ARBITER_BP_ENABLE_7_access_DISABLE 0 |
| 10388 | #define GISB_ARBITER_BP_ENABLE_7_access_ENABLE 1 |
| 10389 | |
| 10390 | |
| 10391 | /**************************************************************************** |
| 10392 | * GISB_ARBITER :: BP_CAP_ADDR |
| 10393 | ***************************************************************************/ |
| 10394 | /* GISB_ARBITER :: BP_CAP_ADDR :: address [31:00] */ |
| 10395 | #define GISB_ARBITER_BP_CAP_ADDR_address_MASK 0xffffffff |
| 10396 | #define GISB_ARBITER_BP_CAP_ADDR_address_ALIGN 0 |
| 10397 | #define GISB_ARBITER_BP_CAP_ADDR_address_BITS 32 |
| 10398 | #define GISB_ARBITER_BP_CAP_ADDR_address_SHIFT 0 |
| 10399 | |
| 10400 | |
| 10401 | /**************************************************************************** |
| 10402 | * GISB_ARBITER :: BP_CAP_DATA |
| 10403 | ***************************************************************************/ |
| 10404 | /* GISB_ARBITER :: BP_CAP_DATA :: data [31:00] */ |
| 10405 | #define GISB_ARBITER_BP_CAP_DATA_data_MASK 0xffffffff |
| 10406 | #define GISB_ARBITER_BP_CAP_DATA_data_ALIGN 0 |
| 10407 | #define GISB_ARBITER_BP_CAP_DATA_data_BITS 32 |
| 10408 | #define GISB_ARBITER_BP_CAP_DATA_data_SHIFT 0 |
| 10409 | |
| 10410 | |
| 10411 | /**************************************************************************** |
| 10412 | * GISB_ARBITER :: BP_CAP_STATUS |
| 10413 | ***************************************************************************/ |
| 10414 | /* GISB_ARBITER :: BP_CAP_STATUS :: reserved0 [31:06] */ |
| 10415 | #define GISB_ARBITER_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 |
| 10416 | #define GISB_ARBITER_BP_CAP_STATUS_reserved0_ALIGN 0 |
| 10417 | #define GISB_ARBITER_BP_CAP_STATUS_reserved0_BITS 26 |
| 10418 | #define GISB_ARBITER_BP_CAP_STATUS_reserved0_SHIFT 6 |
| 10419 | |
| 10420 | /* GISB_ARBITER :: BP_CAP_STATUS :: bs_b [05:02] */ |
| 10421 | #define GISB_ARBITER_BP_CAP_STATUS_bs_b_MASK 0x0000003c |
| 10422 | #define GISB_ARBITER_BP_CAP_STATUS_bs_b_ALIGN 0 |
| 10423 | #define GISB_ARBITER_BP_CAP_STATUS_bs_b_BITS 4 |
| 10424 | #define GISB_ARBITER_BP_CAP_STATUS_bs_b_SHIFT 2 |
| 10425 | |
| 10426 | /* GISB_ARBITER :: BP_CAP_STATUS :: write [01:01] */ |
| 10427 | #define GISB_ARBITER_BP_CAP_STATUS_write_MASK 0x00000002 |
| 10428 | #define GISB_ARBITER_BP_CAP_STATUS_write_ALIGN 0 |
| 10429 | #define GISB_ARBITER_BP_CAP_STATUS_write_BITS 1 |
| 10430 | #define GISB_ARBITER_BP_CAP_STATUS_write_SHIFT 1 |
| 10431 | |
| 10432 | /* GISB_ARBITER :: BP_CAP_STATUS :: valid [00:00] */ |
| 10433 | #define GISB_ARBITER_BP_CAP_STATUS_valid_MASK 0x00000001 |
| 10434 | #define GISB_ARBITER_BP_CAP_STATUS_valid_ALIGN 0 |
| 10435 | #define GISB_ARBITER_BP_CAP_STATUS_valid_BITS 1 |
| 10436 | #define GISB_ARBITER_BP_CAP_STATUS_valid_SHIFT 0 |
| 10437 | |
| 10438 | |
| 10439 | /**************************************************************************** |
| 10440 | * GISB_ARBITER :: BP_CAP_MASTER |
| 10441 | ***************************************************************************/ |
| 10442 | /* GISB_ARBITER :: BP_CAP_MASTER :: reserved0 [31:06] */ |
| 10443 | #define GISB_ARBITER_BP_CAP_MASTER_reserved0_MASK 0xffffffc0 |
| 10444 | #define GISB_ARBITER_BP_CAP_MASTER_reserved0_ALIGN 0 |
| 10445 | #define GISB_ARBITER_BP_CAP_MASTER_reserved0_BITS 26 |
| 10446 | #define GISB_ARBITER_BP_CAP_MASTER_reserved0_SHIFT 6 |
| 10447 | |
| 10448 | /* GISB_ARBITER :: BP_CAP_MASTER :: bsp [05:05] */ |
| 10449 | #define GISB_ARBITER_BP_CAP_MASTER_bsp_MASK 0x00000020 |
| 10450 | #define GISB_ARBITER_BP_CAP_MASTER_bsp_ALIGN 0 |
| 10451 | #define GISB_ARBITER_BP_CAP_MASTER_bsp_BITS 1 |
| 10452 | #define GISB_ARBITER_BP_CAP_MASTER_bsp_SHIFT 5 |
| 10453 | |
| 10454 | /* GISB_ARBITER :: BP_CAP_MASTER :: aes [04:04] */ |
| 10455 | #define GISB_ARBITER_BP_CAP_MASTER_aes_MASK 0x00000010 |
| 10456 | #define GISB_ARBITER_BP_CAP_MASTER_aes_ALIGN 0 |
| 10457 | #define GISB_ARBITER_BP_CAP_MASTER_aes_BITS 1 |
| 10458 | #define GISB_ARBITER_BP_CAP_MASTER_aes_SHIFT 4 |
| 10459 | |
| 10460 | /* GISB_ARBITER :: BP_CAP_MASTER :: fve [03:03] */ |
| 10461 | #define GISB_ARBITER_BP_CAP_MASTER_fve_MASK 0x00000008 |
| 10462 | #define GISB_ARBITER_BP_CAP_MASTER_fve_ALIGN 0 |
| 10463 | #define GISB_ARBITER_BP_CAP_MASTER_fve_BITS 1 |
| 10464 | #define GISB_ARBITER_BP_CAP_MASTER_fve_SHIFT 3 |
| 10465 | |
| 10466 | /* GISB_ARBITER :: BP_CAP_MASTER :: tgt [02:02] */ |
| 10467 | #define GISB_ARBITER_BP_CAP_MASTER_tgt_MASK 0x00000004 |
| 10468 | #define GISB_ARBITER_BP_CAP_MASTER_tgt_ALIGN 0 |
| 10469 | #define GISB_ARBITER_BP_CAP_MASTER_tgt_BITS 1 |
| 10470 | #define GISB_ARBITER_BP_CAP_MASTER_tgt_SHIFT 2 |
| 10471 | |
| 10472 | /* GISB_ARBITER :: BP_CAP_MASTER :: dbu [01:01] */ |
| 10473 | #define GISB_ARBITER_BP_CAP_MASTER_dbu_MASK 0x00000002 |
| 10474 | #define GISB_ARBITER_BP_CAP_MASTER_dbu_ALIGN 0 |
| 10475 | #define GISB_ARBITER_BP_CAP_MASTER_dbu_BITS 1 |
| 10476 | #define GISB_ARBITER_BP_CAP_MASTER_dbu_SHIFT 1 |
| 10477 | |
| 10478 | /* GISB_ARBITER :: BP_CAP_MASTER :: cce [00:00] */ |
| 10479 | #define GISB_ARBITER_BP_CAP_MASTER_cce_MASK 0x00000001 |
| 10480 | #define GISB_ARBITER_BP_CAP_MASTER_cce_ALIGN 0 |
| 10481 | #define GISB_ARBITER_BP_CAP_MASTER_cce_BITS 1 |
| 10482 | #define GISB_ARBITER_BP_CAP_MASTER_cce_SHIFT 0 |
| 10483 | |
| 10484 | |
| 10485 | /**************************************************************************** |
| 10486 | * GISB_ARBITER :: ERR_CAP_CLR |
| 10487 | ***************************************************************************/ |
| 10488 | /* GISB_ARBITER :: ERR_CAP_CLR :: reserved0 [31:01] */ |
| 10489 | #define GISB_ARBITER_ERR_CAP_CLR_reserved0_MASK 0xfffffffe |
| 10490 | #define GISB_ARBITER_ERR_CAP_CLR_reserved0_ALIGN 0 |
| 10491 | #define GISB_ARBITER_ERR_CAP_CLR_reserved0_BITS 31 |
| 10492 | #define GISB_ARBITER_ERR_CAP_CLR_reserved0_SHIFT 1 |
| 10493 | |
| 10494 | /* GISB_ARBITER :: ERR_CAP_CLR :: clear [00:00] */ |
| 10495 | #define GISB_ARBITER_ERR_CAP_CLR_clear_MASK 0x00000001 |
| 10496 | #define GISB_ARBITER_ERR_CAP_CLR_clear_ALIGN 0 |
| 10497 | #define GISB_ARBITER_ERR_CAP_CLR_clear_BITS 1 |
| 10498 | #define GISB_ARBITER_ERR_CAP_CLR_clear_SHIFT 0 |
| 10499 | |
| 10500 | |
| 10501 | /**************************************************************************** |
| 10502 | * GISB_ARBITER :: ERR_CAP_ADDR |
| 10503 | ***************************************************************************/ |
| 10504 | /* GISB_ARBITER :: ERR_CAP_ADDR :: address [31:00] */ |
| 10505 | #define GISB_ARBITER_ERR_CAP_ADDR_address_MASK 0xffffffff |
| 10506 | #define GISB_ARBITER_ERR_CAP_ADDR_address_ALIGN 0 |
| 10507 | #define GISB_ARBITER_ERR_CAP_ADDR_address_BITS 32 |
| 10508 | #define GISB_ARBITER_ERR_CAP_ADDR_address_SHIFT 0 |
| 10509 | |
| 10510 | |
| 10511 | /**************************************************************************** |
| 10512 | * GISB_ARBITER :: ERR_CAP_DATA |
| 10513 | ***************************************************************************/ |
| 10514 | /* GISB_ARBITER :: ERR_CAP_DATA :: data [31:00] */ |
| 10515 | #define GISB_ARBITER_ERR_CAP_DATA_data_MASK 0xffffffff |
| 10516 | #define GISB_ARBITER_ERR_CAP_DATA_data_ALIGN 0 |
| 10517 | #define GISB_ARBITER_ERR_CAP_DATA_data_BITS 32 |
| 10518 | #define GISB_ARBITER_ERR_CAP_DATA_data_SHIFT 0 |
| 10519 | |
| 10520 | |
| 10521 | /**************************************************************************** |
| 10522 | * GISB_ARBITER :: ERR_CAP_STATUS |
| 10523 | ***************************************************************************/ |
| 10524 | /* GISB_ARBITER :: ERR_CAP_STATUS :: reserved0 [31:13] */ |
| 10525 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 |
| 10526 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_ALIGN 0 |
| 10527 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_BITS 19 |
| 10528 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_SHIFT 13 |
| 10529 | |
| 10530 | /* GISB_ARBITER :: ERR_CAP_STATUS :: timeout [12:12] */ |
| 10531 | #define GISB_ARBITER_ERR_CAP_STATUS_timeout_MASK 0x00001000 |
| 10532 | #define GISB_ARBITER_ERR_CAP_STATUS_timeout_ALIGN 0 |
| 10533 | #define GISB_ARBITER_ERR_CAP_STATUS_timeout_BITS 1 |
| 10534 | #define GISB_ARBITER_ERR_CAP_STATUS_timeout_SHIFT 12 |
| 10535 | |
| 10536 | /* GISB_ARBITER :: ERR_CAP_STATUS :: tea [11:11] */ |
| 10537 | #define GISB_ARBITER_ERR_CAP_STATUS_tea_MASK 0x00000800 |
| 10538 | #define GISB_ARBITER_ERR_CAP_STATUS_tea_ALIGN 0 |
| 10539 | #define GISB_ARBITER_ERR_CAP_STATUS_tea_BITS 1 |
| 10540 | #define GISB_ARBITER_ERR_CAP_STATUS_tea_SHIFT 11 |
| 10541 | |
| 10542 | /* GISB_ARBITER :: ERR_CAP_STATUS :: reserved1 [10:06] */ |
| 10543 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 |
| 10544 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_ALIGN 0 |
| 10545 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_BITS 5 |
| 10546 | #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_SHIFT 6 |
| 10547 | |
| 10548 | /* GISB_ARBITER :: ERR_CAP_STATUS :: bs_b [05:02] */ |
| 10549 | #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_MASK 0x0000003c |
| 10550 | #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_ALIGN 0 |
| 10551 | #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_BITS 4 |
| 10552 | #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_SHIFT 2 |
| 10553 | |
| 10554 | /* GISB_ARBITER :: ERR_CAP_STATUS :: write [01:01] */ |
| 10555 | #define GISB_ARBITER_ERR_CAP_STATUS_write_MASK 0x00000002 |
| 10556 | #define GISB_ARBITER_ERR_CAP_STATUS_write_ALIGN 0 |
| 10557 | #define GISB_ARBITER_ERR_CAP_STATUS_write_BITS 1 |
| 10558 | #define GISB_ARBITER_ERR_CAP_STATUS_write_SHIFT 1 |
| 10559 | |
| 10560 | /* GISB_ARBITER :: ERR_CAP_STATUS :: valid [00:00] */ |
| 10561 | #define GISB_ARBITER_ERR_CAP_STATUS_valid_MASK 0x00000001 |
| 10562 | #define GISB_ARBITER_ERR_CAP_STATUS_valid_ALIGN 0 |
| 10563 | #define GISB_ARBITER_ERR_CAP_STATUS_valid_BITS 1 |
| 10564 | #define GISB_ARBITER_ERR_CAP_STATUS_valid_SHIFT 0 |
| 10565 | |
| 10566 | |
| 10567 | /**************************************************************************** |
| 10568 | * GISB_ARBITER :: ERR_CAP_MASTER |
| 10569 | ***************************************************************************/ |
| 10570 | /* GISB_ARBITER :: ERR_CAP_MASTER :: reserved0 [31:06] */ |
| 10571 | #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_MASK 0xffffffc0 |
| 10572 | #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_ALIGN 0 |
| 10573 | #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_BITS 26 |
| 10574 | #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_SHIFT 6 |
| 10575 | |
| 10576 | /* GISB_ARBITER :: ERR_CAP_MASTER :: bsp [05:05] */ |
| 10577 | #define GISB_ARBITER_ERR_CAP_MASTER_bsp_MASK 0x00000020 |
| 10578 | #define GISB_ARBITER_ERR_CAP_MASTER_bsp_ALIGN 0 |
| 10579 | #define GISB_ARBITER_ERR_CAP_MASTER_bsp_BITS 1 |
| 10580 | #define GISB_ARBITER_ERR_CAP_MASTER_bsp_SHIFT 5 |
| 10581 | |
| 10582 | /* GISB_ARBITER :: ERR_CAP_MASTER :: aes [04:04] */ |
| 10583 | #define GISB_ARBITER_ERR_CAP_MASTER_aes_MASK 0x00000010 |
| 10584 | #define GISB_ARBITER_ERR_CAP_MASTER_aes_ALIGN 0 |
| 10585 | #define GISB_ARBITER_ERR_CAP_MASTER_aes_BITS 1 |
| 10586 | #define GISB_ARBITER_ERR_CAP_MASTER_aes_SHIFT 4 |
| 10587 | |
| 10588 | /* GISB_ARBITER :: ERR_CAP_MASTER :: fve [03:03] */ |
| 10589 | #define GISB_ARBITER_ERR_CAP_MASTER_fve_MASK 0x00000008 |
| 10590 | #define GISB_ARBITER_ERR_CAP_MASTER_fve_ALIGN 0 |
| 10591 | #define GISB_ARBITER_ERR_CAP_MASTER_fve_BITS 1 |
| 10592 | #define GISB_ARBITER_ERR_CAP_MASTER_fve_SHIFT 3 |
| 10593 | |
| 10594 | /* GISB_ARBITER :: ERR_CAP_MASTER :: tgt [02:02] */ |
| 10595 | #define GISB_ARBITER_ERR_CAP_MASTER_tgt_MASK 0x00000004 |
| 10596 | #define GISB_ARBITER_ERR_CAP_MASTER_tgt_ALIGN 0 |
| 10597 | #define GISB_ARBITER_ERR_CAP_MASTER_tgt_BITS 1 |
| 10598 | #define GISB_ARBITER_ERR_CAP_MASTER_tgt_SHIFT 2 |
| 10599 | |
| 10600 | /* GISB_ARBITER :: ERR_CAP_MASTER :: dbu [01:01] */ |
| 10601 | #define GISB_ARBITER_ERR_CAP_MASTER_dbu_MASK 0x00000002 |
| 10602 | #define GISB_ARBITER_ERR_CAP_MASTER_dbu_ALIGN 0 |
| 10603 | #define GISB_ARBITER_ERR_CAP_MASTER_dbu_BITS 1 |
| 10604 | #define GISB_ARBITER_ERR_CAP_MASTER_dbu_SHIFT 1 |
| 10605 | |
| 10606 | /* GISB_ARBITER :: ERR_CAP_MASTER :: cce [00:00] */ |
| 10607 | #define GISB_ARBITER_ERR_CAP_MASTER_cce_MASK 0x00000001 |
| 10608 | #define GISB_ARBITER_ERR_CAP_MASTER_cce_ALIGN 0 |
| 10609 | #define GISB_ARBITER_ERR_CAP_MASTER_cce_BITS 1 |
| 10610 | #define GISB_ARBITER_ERR_CAP_MASTER_cce_SHIFT 0 |
| 10611 | |
| 10612 | |
| 10613 | /**************************************************************************** |
| 10614 | * BCM70012_MISC_TOP_MISC_GR_BRIDGE |
| 10615 | ***************************************************************************/ |
| 10616 | /**************************************************************************** |
| 10617 | * MISC_GR_BRIDGE :: REVISION |
| 10618 | ***************************************************************************/ |
| 10619 | /* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 10620 | #define MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 10621 | #define MISC_GR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 10622 | #define MISC_GR_BRIDGE_REVISION_reserved0_BITS 16 |
| 10623 | #define MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 10624 | |
| 10625 | /* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 10626 | #define MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 10627 | #define MISC_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 10628 | #define MISC_GR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 10629 | #define MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 10630 | |
| 10631 | /* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 10632 | #define MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 10633 | #define MISC_GR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 10634 | #define MISC_GR_BRIDGE_REVISION_MINOR_BITS 8 |
| 10635 | #define MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 10636 | |
| 10637 | |
| 10638 | /**************************************************************************** |
| 10639 | * MISC_GR_BRIDGE :: CTRL |
| 10640 | ***************************************************************************/ |
| 10641 | /* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ |
| 10642 | #define MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe |
| 10643 | #define MISC_GR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 10644 | #define MISC_GR_BRIDGE_CTRL_reserved0_BITS 31 |
| 10645 | #define MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 |
| 10646 | |
| 10647 | /* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 10648 | #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 10649 | #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 10650 | #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 10651 | #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 10652 | #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 10653 | #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 10654 | |
| 10655 | |
| 10656 | /**************************************************************************** |
| 10657 | * MISC_GR_BRIDGE :: SPARE_SW_RESET_0 |
| 10658 | ***************************************************************************/ |
| 10659 | /* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 10660 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 10661 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 10662 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 10663 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 10664 | |
| 10665 | /* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 10666 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 10667 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 10668 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 10669 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 10670 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 10671 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 10672 | |
| 10673 | |
| 10674 | /**************************************************************************** |
| 10675 | * MISC_GR_BRIDGE :: SPARE_SW_RESET_1 |
| 10676 | ***************************************************************************/ |
| 10677 | /* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 10678 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 10679 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 10680 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 10681 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 10682 | |
| 10683 | /* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 10684 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 10685 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 10686 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 10687 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 10688 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 |
| 10689 | #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 |
| 10690 | |
| 10691 | |
| 10692 | /**************************************************************************** |
| 10693 | * BCM70012_DBU_TOP_DBU |
| 10694 | ***************************************************************************/ |
| 10695 | /**************************************************************************** |
| 10696 | * DBU :: DBU_CMD |
| 10697 | ***************************************************************************/ |
| 10698 | /* DBU :: DBU_CMD :: reserved0 [31:03] */ |
| 10699 | #define DBU_DBU_CMD_reserved0_MASK 0xfffffff8 |
| 10700 | #define DBU_DBU_CMD_reserved0_ALIGN 0 |
| 10701 | #define DBU_DBU_CMD_reserved0_BITS 29 |
| 10702 | #define DBU_DBU_CMD_reserved0_SHIFT 3 |
| 10703 | |
| 10704 | /* DBU :: DBU_CMD :: RX_OVERFLOW [02:02] */ |
| 10705 | #define DBU_DBU_CMD_RX_OVERFLOW_MASK 0x00000004 |
| 10706 | #define DBU_DBU_CMD_RX_OVERFLOW_ALIGN 0 |
| 10707 | #define DBU_DBU_CMD_RX_OVERFLOW_BITS 1 |
| 10708 | #define DBU_DBU_CMD_RX_OVERFLOW_SHIFT 2 |
| 10709 | |
| 10710 | /* DBU :: DBU_CMD :: RX_ERROR [01:01] */ |
| 10711 | #define DBU_DBU_CMD_RX_ERROR_MASK 0x00000002 |
| 10712 | #define DBU_DBU_CMD_RX_ERROR_ALIGN 0 |
| 10713 | #define DBU_DBU_CMD_RX_ERROR_BITS 1 |
| 10714 | #define DBU_DBU_CMD_RX_ERROR_SHIFT 1 |
| 10715 | |
| 10716 | /* DBU :: DBU_CMD :: ENABLE [00:00] */ |
| 10717 | #define DBU_DBU_CMD_ENABLE_MASK 0x00000001 |
| 10718 | #define DBU_DBU_CMD_ENABLE_ALIGN 0 |
| 10719 | #define DBU_DBU_CMD_ENABLE_BITS 1 |
| 10720 | #define DBU_DBU_CMD_ENABLE_SHIFT 0 |
| 10721 | |
| 10722 | |
| 10723 | /**************************************************************************** |
| 10724 | * DBU :: DBU_STATUS |
| 10725 | ***************************************************************************/ |
| 10726 | /* DBU :: DBU_STATUS :: reserved0 [31:02] */ |
| 10727 | #define DBU_DBU_STATUS_reserved0_MASK 0xfffffffc |
| 10728 | #define DBU_DBU_STATUS_reserved0_ALIGN 0 |
| 10729 | #define DBU_DBU_STATUS_reserved0_BITS 30 |
| 10730 | #define DBU_DBU_STATUS_reserved0_SHIFT 2 |
| 10731 | |
| 10732 | /* DBU :: DBU_STATUS :: TXDATA_OCCUPIED [01:01] */ |
| 10733 | #define DBU_DBU_STATUS_TXDATA_OCCUPIED_MASK 0x00000002 |
| 10734 | #define DBU_DBU_STATUS_TXDATA_OCCUPIED_ALIGN 0 |
| 10735 | #define DBU_DBU_STATUS_TXDATA_OCCUPIED_BITS 1 |
| 10736 | #define DBU_DBU_STATUS_TXDATA_OCCUPIED_SHIFT 1 |
| 10737 | |
| 10738 | /* DBU :: DBU_STATUS :: RXDATA_VALID [00:00] */ |
| 10739 | #define DBU_DBU_STATUS_RXDATA_VALID_MASK 0x00000001 |
| 10740 | #define DBU_DBU_STATUS_RXDATA_VALID_ALIGN 0 |
| 10741 | #define DBU_DBU_STATUS_RXDATA_VALID_BITS 1 |
| 10742 | #define DBU_DBU_STATUS_RXDATA_VALID_SHIFT 0 |
| 10743 | |
| 10744 | |
| 10745 | /**************************************************************************** |
| 10746 | * DBU :: DBU_CONFIG |
| 10747 | ***************************************************************************/ |
| 10748 | /* DBU :: DBU_CONFIG :: reserved0 [31:03] */ |
| 10749 | #define DBU_DBU_CONFIG_reserved0_MASK 0xfffffff8 |
| 10750 | #define DBU_DBU_CONFIG_reserved0_ALIGN 0 |
| 10751 | #define DBU_DBU_CONFIG_reserved0_BITS 29 |
| 10752 | #define DBU_DBU_CONFIG_reserved0_SHIFT 3 |
| 10753 | |
| 10754 | /* DBU :: DBU_CONFIG :: CRLF_ENABLE [02:02] */ |
| 10755 | #define DBU_DBU_CONFIG_CRLF_ENABLE_MASK 0x00000004 |
| 10756 | #define DBU_DBU_CONFIG_CRLF_ENABLE_ALIGN 0 |
| 10757 | #define DBU_DBU_CONFIG_CRLF_ENABLE_BITS 1 |
| 10758 | #define DBU_DBU_CONFIG_CRLF_ENABLE_SHIFT 2 |
| 10759 | |
| 10760 | /* DBU :: DBU_CONFIG :: DEBUGSM_ENABLE [01:01] */ |
| 10761 | #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_MASK 0x00000002 |
| 10762 | #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_ALIGN 0 |
| 10763 | #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_BITS 1 |
| 10764 | #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_SHIFT 1 |
| 10765 | |
| 10766 | /* DBU :: DBU_CONFIG :: TIMING_OVERRIDE [00:00] */ |
| 10767 | #define DBU_DBU_CONFIG_TIMING_OVERRIDE_MASK 0x00000001 |
| 10768 | #define DBU_DBU_CONFIG_TIMING_OVERRIDE_ALIGN 0 |
| 10769 | #define DBU_DBU_CONFIG_TIMING_OVERRIDE_BITS 1 |
| 10770 | #define DBU_DBU_CONFIG_TIMING_OVERRIDE_SHIFT 0 |
| 10771 | |
| 10772 | |
| 10773 | /**************************************************************************** |
| 10774 | * DBU :: DBU_TIMING |
| 10775 | ***************************************************************************/ |
| 10776 | /* DBU :: DBU_TIMING :: BIT_INTERVAL [31:16] */ |
| 10777 | #define DBU_DBU_TIMING_BIT_INTERVAL_MASK 0xffff0000 |
| 10778 | #define DBU_DBU_TIMING_BIT_INTERVAL_ALIGN 0 |
| 10779 | #define DBU_DBU_TIMING_BIT_INTERVAL_BITS 16 |
| 10780 | #define DBU_DBU_TIMING_BIT_INTERVAL_SHIFT 16 |
| 10781 | |
| 10782 | /* DBU :: DBU_TIMING :: FB_SMPL_OFFSET [15:00] */ |
| 10783 | #define DBU_DBU_TIMING_FB_SMPL_OFFSET_MASK 0x0000ffff |
| 10784 | #define DBU_DBU_TIMING_FB_SMPL_OFFSET_ALIGN 0 |
| 10785 | #define DBU_DBU_TIMING_FB_SMPL_OFFSET_BITS 16 |
| 10786 | #define DBU_DBU_TIMING_FB_SMPL_OFFSET_SHIFT 0 |
| 10787 | |
| 10788 | |
| 10789 | /**************************************************************************** |
| 10790 | * DBU :: DBU_RXDATA |
| 10791 | ***************************************************************************/ |
| 10792 | /* DBU :: DBU_RXDATA :: reserved0 [31:09] */ |
| 10793 | #define DBU_DBU_RXDATA_reserved0_MASK 0xfffffe00 |
| 10794 | #define DBU_DBU_RXDATA_reserved0_ALIGN 0 |
| 10795 | #define DBU_DBU_RXDATA_reserved0_BITS 23 |
| 10796 | #define DBU_DBU_RXDATA_reserved0_SHIFT 9 |
| 10797 | |
| 10798 | /* DBU :: DBU_RXDATA :: ERROR [08:08] */ |
| 10799 | #define DBU_DBU_RXDATA_ERROR_MASK 0x00000100 |
| 10800 | #define DBU_DBU_RXDATA_ERROR_ALIGN 0 |
| 10801 | #define DBU_DBU_RXDATA_ERROR_BITS 1 |
| 10802 | #define DBU_DBU_RXDATA_ERROR_SHIFT 8 |
| 10803 | |
| 10804 | /* DBU :: DBU_RXDATA :: VALUE [07:00] */ |
| 10805 | #define DBU_DBU_RXDATA_VALUE_MASK 0x000000ff |
| 10806 | #define DBU_DBU_RXDATA_VALUE_ALIGN 0 |
| 10807 | #define DBU_DBU_RXDATA_VALUE_BITS 8 |
| 10808 | #define DBU_DBU_RXDATA_VALUE_SHIFT 0 |
| 10809 | |
| 10810 | |
| 10811 | /**************************************************************************** |
| 10812 | * DBU :: DBU_TXDATA |
| 10813 | ***************************************************************************/ |
| 10814 | /* DBU :: DBU_TXDATA :: reserved0 [31:08] */ |
| 10815 | #define DBU_DBU_TXDATA_reserved0_MASK 0xffffff00 |
| 10816 | #define DBU_DBU_TXDATA_reserved0_ALIGN 0 |
| 10817 | #define DBU_DBU_TXDATA_reserved0_BITS 24 |
| 10818 | #define DBU_DBU_TXDATA_reserved0_SHIFT 8 |
| 10819 | |
| 10820 | /* DBU :: DBU_TXDATA :: VALUE [07:00] */ |
| 10821 | #define DBU_DBU_TXDATA_VALUE_MASK 0x000000ff |
| 10822 | #define DBU_DBU_TXDATA_VALUE_ALIGN 0 |
| 10823 | #define DBU_DBU_TXDATA_VALUE_BITS 8 |
| 10824 | #define DBU_DBU_TXDATA_VALUE_SHIFT 0 |
| 10825 | |
| 10826 | |
| 10827 | /**************************************************************************** |
| 10828 | * BCM70012_DBU_TOP_DBU_RGR_BRIDGE |
| 10829 | ***************************************************************************/ |
| 10830 | /**************************************************************************** |
| 10831 | * DBU_RGR_BRIDGE :: REVISION |
| 10832 | ***************************************************************************/ |
| 10833 | /* DBU_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 10834 | #define DBU_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 10835 | #define DBU_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 10836 | #define DBU_RGR_BRIDGE_REVISION_reserved0_BITS 16 |
| 10837 | #define DBU_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 10838 | |
| 10839 | /* DBU_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 10840 | #define DBU_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 10841 | #define DBU_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 10842 | #define DBU_RGR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 10843 | #define DBU_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 10844 | |
| 10845 | /* DBU_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 10846 | #define DBU_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 10847 | #define DBU_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 10848 | #define DBU_RGR_BRIDGE_REVISION_MINOR_BITS 8 |
| 10849 | #define DBU_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 10850 | |
| 10851 | |
| 10852 | /**************************************************************************** |
| 10853 | * DBU_RGR_BRIDGE :: CTRL |
| 10854 | ***************************************************************************/ |
| 10855 | /* DBU_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ |
| 10856 | #define DBU_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc |
| 10857 | #define DBU_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 10858 | #define DBU_RGR_BRIDGE_CTRL_reserved0_BITS 30 |
| 10859 | #define DBU_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 |
| 10860 | |
| 10861 | /* DBU_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ |
| 10862 | #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 |
| 10863 | #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 |
| 10864 | #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 |
| 10865 | #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 |
| 10866 | #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 |
| 10867 | #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 |
| 10868 | |
| 10869 | /* DBU_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 10870 | #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 10871 | #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 10872 | #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 10873 | #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 10874 | #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 10875 | #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 10876 | |
| 10877 | |
| 10878 | /**************************************************************************** |
| 10879 | * DBU_RGR_BRIDGE :: RBUS_TIMER |
| 10880 | ***************************************************************************/ |
| 10881 | /* DBU_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ |
| 10882 | #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 |
| 10883 | #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 |
| 10884 | #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 |
| 10885 | #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 |
| 10886 | |
| 10887 | /* DBU_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ |
| 10888 | #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff |
| 10889 | #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 |
| 10890 | #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 |
| 10891 | #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 |
| 10892 | |
| 10893 | |
| 10894 | /**************************************************************************** |
| 10895 | * DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 |
| 10896 | ***************************************************************************/ |
| 10897 | /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 10898 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 10899 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 10900 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 10901 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 10902 | |
| 10903 | /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 10904 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 10905 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 10906 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 10907 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 10908 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 10909 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 10910 | |
| 10911 | |
| 10912 | /**************************************************************************** |
| 10913 | * DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 |
| 10914 | ***************************************************************************/ |
| 10915 | /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 10916 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 10917 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 10918 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 10919 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 10920 | |
| 10921 | /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 10922 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 10923 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 10924 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 10925 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 10926 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 |
| 10927 | #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 |
| 10928 | |
| 10929 | |
| 10930 | /**************************************************************************** |
| 10931 | * BCM70012_OTP_TOP_OTP |
| 10932 | ***************************************************************************/ |
| 10933 | /**************************************************************************** |
| 10934 | * OTP :: CONFIG_INFO |
| 10935 | ***************************************************************************/ |
| 10936 | /* OTP :: CONFIG_INFO :: reserved0 [31:22] */ |
| 10937 | #define OTP_CONFIG_INFO_reserved0_MASK 0xffc00000 |
| 10938 | #define OTP_CONFIG_INFO_reserved0_ALIGN 0 |
| 10939 | #define OTP_CONFIG_INFO_reserved0_BITS 10 |
| 10940 | #define OTP_CONFIG_INFO_reserved0_SHIFT 22 |
| 10941 | |
| 10942 | /* OTP :: CONFIG_INFO :: SELVL [21:20] */ |
| 10943 | #define OTP_CONFIG_INFO_SELVL_MASK 0x00300000 |
| 10944 | #define OTP_CONFIG_INFO_SELVL_ALIGN 0 |
| 10945 | #define OTP_CONFIG_INFO_SELVL_BITS 2 |
| 10946 | #define OTP_CONFIG_INFO_SELVL_SHIFT 20 |
| 10947 | |
| 10948 | /* OTP :: CONFIG_INFO :: reserved1 [19:17] */ |
| 10949 | #define OTP_CONFIG_INFO_reserved1_MASK 0x000e0000 |
| 10950 | #define OTP_CONFIG_INFO_reserved1_ALIGN 0 |
| 10951 | #define OTP_CONFIG_INFO_reserved1_BITS 3 |
| 10952 | #define OTP_CONFIG_INFO_reserved1_SHIFT 17 |
| 10953 | |
| 10954 | /* OTP :: CONFIG_INFO :: PTEST [16:16] */ |
| 10955 | #define OTP_CONFIG_INFO_PTEST_MASK 0x00010000 |
| 10956 | #define OTP_CONFIG_INFO_PTEST_ALIGN 0 |
| 10957 | #define OTP_CONFIG_INFO_PTEST_BITS 1 |
| 10958 | #define OTP_CONFIG_INFO_PTEST_SHIFT 16 |
| 10959 | |
| 10960 | /* OTP :: CONFIG_INFO :: reserved2 [15:13] */ |
| 10961 | #define OTP_CONFIG_INFO_reserved2_MASK 0x0000e000 |
| 10962 | #define OTP_CONFIG_INFO_reserved2_ALIGN 0 |
| 10963 | #define OTP_CONFIG_INFO_reserved2_BITS 3 |
| 10964 | #define OTP_CONFIG_INFO_reserved2_SHIFT 13 |
| 10965 | |
| 10966 | /* OTP :: CONFIG_INFO :: MAX_REDUNDANT_ROWS [12:08] */ |
| 10967 | #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_MASK 0x00001f00 |
| 10968 | #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_ALIGN 0 |
| 10969 | #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_BITS 5 |
| 10970 | #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_SHIFT 8 |
| 10971 | |
| 10972 | /* OTP :: CONFIG_INFO :: MAX_RETRY [07:04] */ |
| 10973 | #define OTP_CONFIG_INFO_MAX_RETRY_MASK 0x000000f0 |
| 10974 | #define OTP_CONFIG_INFO_MAX_RETRY_ALIGN 0 |
| 10975 | #define OTP_CONFIG_INFO_MAX_RETRY_BITS 4 |
| 10976 | #define OTP_CONFIG_INFO_MAX_RETRY_SHIFT 4 |
| 10977 | |
| 10978 | /* OTP :: CONFIG_INFO :: reserved3 [03:01] */ |
| 10979 | #define OTP_CONFIG_INFO_reserved3_MASK 0x0000000e |
| 10980 | #define OTP_CONFIG_INFO_reserved3_ALIGN 0 |
| 10981 | #define OTP_CONFIG_INFO_reserved3_BITS 3 |
| 10982 | #define OTP_CONFIG_INFO_reserved3_SHIFT 1 |
| 10983 | |
| 10984 | /* OTP :: CONFIG_INFO :: PROG_MODE [00:00] */ |
| 10985 | #define OTP_CONFIG_INFO_PROG_MODE_MASK 0x00000001 |
| 10986 | #define OTP_CONFIG_INFO_PROG_MODE_ALIGN 0 |
| 10987 | #define OTP_CONFIG_INFO_PROG_MODE_BITS 1 |
| 10988 | #define OTP_CONFIG_INFO_PROG_MODE_SHIFT 0 |
| 10989 | |
| 10990 | |
| 10991 | /**************************************************************************** |
| 10992 | * OTP :: CMD |
| 10993 | ***************************************************************************/ |
| 10994 | /* OTP :: CMD :: reserved0 [31:02] */ |
| 10995 | #define OTP_CMD_reserved0_MASK 0xfffffffc |
| 10996 | #define OTP_CMD_reserved0_ALIGN 0 |
| 10997 | #define OTP_CMD_reserved0_BITS 30 |
| 10998 | #define OTP_CMD_reserved0_SHIFT 2 |
| 10999 | |
| 11000 | /* OTP :: CMD :: KEYS_AVAIL [01:01] */ |
| 11001 | #define OTP_CMD_KEYS_AVAIL_MASK 0x00000002 |
| 11002 | #define OTP_CMD_KEYS_AVAIL_ALIGN 0 |
| 11003 | #define OTP_CMD_KEYS_AVAIL_BITS 1 |
| 11004 | #define OTP_CMD_KEYS_AVAIL_SHIFT 1 |
| 11005 | |
| 11006 | /* OTP :: CMD :: PROGRAM_OTP [00:00] */ |
| 11007 | #define OTP_CMD_PROGRAM_OTP_MASK 0x00000001 |
| 11008 | #define OTP_CMD_PROGRAM_OTP_ALIGN 0 |
| 11009 | #define OTP_CMD_PROGRAM_OTP_BITS 1 |
| 11010 | #define OTP_CMD_PROGRAM_OTP_SHIFT 0 |
| 11011 | |
| 11012 | |
| 11013 | /**************************************************************************** |
| 11014 | * OTP :: STATUS |
| 11015 | ***************************************************************************/ |
| 11016 | /* OTP :: STATUS :: reserved0 [31:30] */ |
| 11017 | #define OTP_STATUS_reserved0_MASK 0xc0000000 |
| 11018 | #define OTP_STATUS_reserved0_ALIGN 0 |
| 11019 | #define OTP_STATUS_reserved0_BITS 2 |
| 11020 | #define OTP_STATUS_reserved0_SHIFT 30 |
| 11021 | |
| 11022 | /* OTP :: STATUS :: TOTAL_RETRIES [29:17] */ |
| 11023 | #define OTP_STATUS_TOTAL_RETRIES_MASK 0x3ffe0000 |
| 11024 | #define OTP_STATUS_TOTAL_RETRIES_ALIGN 0 |
| 11025 | #define OTP_STATUS_TOTAL_RETRIES_BITS 13 |
| 11026 | #define OTP_STATUS_TOTAL_RETRIES_SHIFT 17 |
| 11027 | |
| 11028 | /* OTP :: STATUS :: ROWS_USED [16:12] */ |
| 11029 | #define OTP_STATUS_ROWS_USED_MASK 0x0001f000 |
| 11030 | #define OTP_STATUS_ROWS_USED_ALIGN 0 |
| 11031 | #define OTP_STATUS_ROWS_USED_BITS 5 |
| 11032 | #define OTP_STATUS_ROWS_USED_SHIFT 12 |
| 11033 | |
| 11034 | /* OTP :: STATUS :: MAX_RETRIES [11:08] */ |
| 11035 | #define OTP_STATUS_MAX_RETRIES_MASK 0x00000f00 |
| 11036 | #define OTP_STATUS_MAX_RETRIES_ALIGN 0 |
| 11037 | #define OTP_STATUS_MAX_RETRIES_BITS 4 |
| 11038 | #define OTP_STATUS_MAX_RETRIES_SHIFT 8 |
| 11039 | |
| 11040 | /* OTP :: STATUS :: PROG_STATUS [07:04] */ |
| 11041 | #define OTP_STATUS_PROG_STATUS_MASK 0x000000f0 |
| 11042 | #define OTP_STATUS_PROG_STATUS_ALIGN 0 |
| 11043 | #define OTP_STATUS_PROG_STATUS_BITS 4 |
| 11044 | #define OTP_STATUS_PROG_STATUS_SHIFT 4 |
| 11045 | |
| 11046 | /* OTP :: STATUS :: reserved1 [03:03] */ |
| 11047 | #define OTP_STATUS_reserved1_MASK 0x00000008 |
| 11048 | #define OTP_STATUS_reserved1_ALIGN 0 |
| 11049 | #define OTP_STATUS_reserved1_BITS 1 |
| 11050 | #define OTP_STATUS_reserved1_SHIFT 3 |
| 11051 | |
| 11052 | /* OTP :: STATUS :: CHECKSUM_MISMATCH [02:02] */ |
| 11053 | #define OTP_STATUS_CHECKSUM_MISMATCH_MASK 0x00000004 |
| 11054 | #define OTP_STATUS_CHECKSUM_MISMATCH_ALIGN 0 |
| 11055 | #define OTP_STATUS_CHECKSUM_MISMATCH_BITS 1 |
| 11056 | #define OTP_STATUS_CHECKSUM_MISMATCH_SHIFT 2 |
| 11057 | |
| 11058 | /* OTP :: STATUS :: INSUFFICIENT_ROWS [01:01] */ |
| 11059 | #define OTP_STATUS_INSUFFICIENT_ROWS_MASK 0x00000002 |
| 11060 | #define OTP_STATUS_INSUFFICIENT_ROWS_ALIGN 0 |
| 11061 | #define OTP_STATUS_INSUFFICIENT_ROWS_BITS 1 |
| 11062 | #define OTP_STATUS_INSUFFICIENT_ROWS_SHIFT 1 |
| 11063 | |
| 11064 | /* OTP :: STATUS :: PROGRAMMED [00:00] */ |
| 11065 | #define OTP_STATUS_PROGRAMMED_MASK 0x00000001 |
| 11066 | #define OTP_STATUS_PROGRAMMED_ALIGN 0 |
| 11067 | #define OTP_STATUS_PROGRAMMED_BITS 1 |
| 11068 | #define OTP_STATUS_PROGRAMMED_SHIFT 0 |
| 11069 | |
| 11070 | |
| 11071 | /**************************************************************************** |
| 11072 | * OTP :: CONTENT_MISC |
| 11073 | ***************************************************************************/ |
| 11074 | /* OTP :: CONTENT_MISC :: reserved0 [31:06] */ |
| 11075 | #define OTP_CONTENT_MISC_reserved0_MASK 0xffffffc0 |
| 11076 | #define OTP_CONTENT_MISC_reserved0_ALIGN 0 |
| 11077 | #define OTP_CONTENT_MISC_reserved0_BITS 26 |
| 11078 | #define OTP_CONTENT_MISC_reserved0_SHIFT 6 |
| 11079 | |
| 11080 | /* OTP :: CONTENT_MISC :: DCI_SECURITY_ENABLE [05:05] */ |
| 11081 | #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_MASK 0x00000020 |
| 11082 | #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_ALIGN 0 |
| 11083 | #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_BITS 1 |
| 11084 | #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_SHIFT 5 |
| 11085 | |
| 11086 | /* OTP :: CONTENT_MISC :: AES_SECURITY_ENABLE [04:04] */ |
| 11087 | #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_MASK 0x00000010 |
| 11088 | #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_ALIGN 0 |
| 11089 | #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_BITS 1 |
| 11090 | #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_SHIFT 4 |
| 11091 | |
| 11092 | /* OTP :: CONTENT_MISC :: DISABLE_JTAG [03:03] */ |
| 11093 | #define OTP_CONTENT_MISC_DISABLE_JTAG_MASK 0x00000008 |
| 11094 | #define OTP_CONTENT_MISC_DISABLE_JTAG_ALIGN 0 |
| 11095 | #define OTP_CONTENT_MISC_DISABLE_JTAG_BITS 1 |
| 11096 | #define OTP_CONTENT_MISC_DISABLE_JTAG_SHIFT 3 |
| 11097 | |
| 11098 | /* OTP :: CONTENT_MISC :: DISABLE_UART [02:02] */ |
| 11099 | #define OTP_CONTENT_MISC_DISABLE_UART_MASK 0x00000004 |
| 11100 | #define OTP_CONTENT_MISC_DISABLE_UART_ALIGN 0 |
| 11101 | #define OTP_CONTENT_MISC_DISABLE_UART_BITS 1 |
| 11102 | #define OTP_CONTENT_MISC_DISABLE_UART_SHIFT 2 |
| 11103 | |
| 11104 | /* OTP :: CONTENT_MISC :: ENABLE_RANDOMIZATION [01:01] */ |
| 11105 | #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_MASK 0x00000002 |
| 11106 | #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_ALIGN 0 |
| 11107 | #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_BITS 1 |
| 11108 | #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_SHIFT 1 |
| 11109 | |
| 11110 | /* OTP :: CONTENT_MISC :: OTP_SECURITY_ENABLE [00:00] */ |
| 11111 | #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_MASK 0x00000001 |
| 11112 | #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_ALIGN 0 |
| 11113 | #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_BITS 1 |
| 11114 | #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_SHIFT 0 |
| 11115 | |
| 11116 | |
| 11117 | /**************************************************************************** |
| 11118 | * OTP :: CONTENT_AES_0 |
| 11119 | ***************************************************************************/ |
| 11120 | /* OTP :: CONTENT_AES_0 :: AES_KEY_0 [31:00] */ |
| 11121 | #define OTP_CONTENT_AES_0_AES_KEY_0_MASK 0xffffffff |
| 11122 | #define OTP_CONTENT_AES_0_AES_KEY_0_ALIGN 0 |
| 11123 | #define OTP_CONTENT_AES_0_AES_KEY_0_BITS 32 |
| 11124 | #define OTP_CONTENT_AES_0_AES_KEY_0_SHIFT 0 |
| 11125 | |
| 11126 | |
| 11127 | /**************************************************************************** |
| 11128 | * OTP :: CONTENT_AES_1 |
| 11129 | ***************************************************************************/ |
| 11130 | /* OTP :: CONTENT_AES_1 :: AES_KEY_1 [31:00] */ |
| 11131 | #define OTP_CONTENT_AES_1_AES_KEY_1_MASK 0xffffffff |
| 11132 | #define OTP_CONTENT_AES_1_AES_KEY_1_ALIGN 0 |
| 11133 | #define OTP_CONTENT_AES_1_AES_KEY_1_BITS 32 |
| 11134 | #define OTP_CONTENT_AES_1_AES_KEY_1_SHIFT 0 |
| 11135 | |
| 11136 | |
| 11137 | /**************************************************************************** |
| 11138 | * OTP :: CONTENT_AES_2 |
| 11139 | ***************************************************************************/ |
| 11140 | /* OTP :: CONTENT_AES_2 :: AES_KEY_2 [31:00] */ |
| 11141 | #define OTP_CONTENT_AES_2_AES_KEY_2_MASK 0xffffffff |
| 11142 | #define OTP_CONTENT_AES_2_AES_KEY_2_ALIGN 0 |
| 11143 | #define OTP_CONTENT_AES_2_AES_KEY_2_BITS 32 |
| 11144 | #define OTP_CONTENT_AES_2_AES_KEY_2_SHIFT 0 |
| 11145 | |
| 11146 | |
| 11147 | /**************************************************************************** |
| 11148 | * OTP :: CONTENT_AES_3 |
| 11149 | ***************************************************************************/ |
| 11150 | /* OTP :: CONTENT_AES_3 :: AES_KEY_3 [31:00] */ |
| 11151 | #define OTP_CONTENT_AES_3_AES_KEY_3_MASK 0xffffffff |
| 11152 | #define OTP_CONTENT_AES_3_AES_KEY_3_ALIGN 0 |
| 11153 | #define OTP_CONTENT_AES_3_AES_KEY_3_BITS 32 |
| 11154 | #define OTP_CONTENT_AES_3_AES_KEY_3_SHIFT 0 |
| 11155 | |
| 11156 | |
| 11157 | /**************************************************************************** |
| 11158 | * OTP :: CONTENT_SHA_0 |
| 11159 | ***************************************************************************/ |
| 11160 | /* OTP :: CONTENT_SHA_0 :: SHA_KEY_0 [31:00] */ |
| 11161 | #define OTP_CONTENT_SHA_0_SHA_KEY_0_MASK 0xffffffff |
| 11162 | #define OTP_CONTENT_SHA_0_SHA_KEY_0_ALIGN 0 |
| 11163 | #define OTP_CONTENT_SHA_0_SHA_KEY_0_BITS 32 |
| 11164 | #define OTP_CONTENT_SHA_0_SHA_KEY_0_SHIFT 0 |
| 11165 | |
| 11166 | |
| 11167 | /**************************************************************************** |
| 11168 | * OTP :: CONTENT_SHA_1 |
| 11169 | ***************************************************************************/ |
| 11170 | /* OTP :: CONTENT_SHA_1 :: SHA_KEY_1 [31:00] */ |
| 11171 | #define OTP_CONTENT_SHA_1_SHA_KEY_1_MASK 0xffffffff |
| 11172 | #define OTP_CONTENT_SHA_1_SHA_KEY_1_ALIGN 0 |
| 11173 | #define OTP_CONTENT_SHA_1_SHA_KEY_1_BITS 32 |
| 11174 | #define OTP_CONTENT_SHA_1_SHA_KEY_1_SHIFT 0 |
| 11175 | |
| 11176 | |
| 11177 | /**************************************************************************** |
| 11178 | * OTP :: CONTENT_SHA_2 |
| 11179 | ***************************************************************************/ |
| 11180 | /* OTP :: CONTENT_SHA_2 :: SHA_KEY_2 [31:00] */ |
| 11181 | #define OTP_CONTENT_SHA_2_SHA_KEY_2_MASK 0xffffffff |
| 11182 | #define OTP_CONTENT_SHA_2_SHA_KEY_2_ALIGN 0 |
| 11183 | #define OTP_CONTENT_SHA_2_SHA_KEY_2_BITS 32 |
| 11184 | #define OTP_CONTENT_SHA_2_SHA_KEY_2_SHIFT 0 |
| 11185 | |
| 11186 | |
| 11187 | /**************************************************************************** |
| 11188 | * OTP :: CONTENT_SHA_3 |
| 11189 | ***************************************************************************/ |
| 11190 | /* OTP :: CONTENT_SHA_3 :: SHA_KEY_3 [31:00] */ |
| 11191 | #define OTP_CONTENT_SHA_3_SHA_KEY_3_MASK 0xffffffff |
| 11192 | #define OTP_CONTENT_SHA_3_SHA_KEY_3_ALIGN 0 |
| 11193 | #define OTP_CONTENT_SHA_3_SHA_KEY_3_BITS 32 |
| 11194 | #define OTP_CONTENT_SHA_3_SHA_KEY_3_SHIFT 0 |
| 11195 | |
| 11196 | |
| 11197 | /**************************************************************************** |
| 11198 | * OTP :: CONTENT_SHA_4 |
| 11199 | ***************************************************************************/ |
| 11200 | /* OTP :: CONTENT_SHA_4 :: SHA_KEY_4 [31:00] */ |
| 11201 | #define OTP_CONTENT_SHA_4_SHA_KEY_4_MASK 0xffffffff |
| 11202 | #define OTP_CONTENT_SHA_4_SHA_KEY_4_ALIGN 0 |
| 11203 | #define OTP_CONTENT_SHA_4_SHA_KEY_4_BITS 32 |
| 11204 | #define OTP_CONTENT_SHA_4_SHA_KEY_4_SHIFT 0 |
| 11205 | |
| 11206 | |
| 11207 | /**************************************************************************** |
| 11208 | * OTP :: CONTENT_SHA_5 |
| 11209 | ***************************************************************************/ |
| 11210 | /* OTP :: CONTENT_SHA_5 :: SHA_KEY_5 [31:00] */ |
| 11211 | #define OTP_CONTENT_SHA_5_SHA_KEY_5_MASK 0xffffffff |
| 11212 | #define OTP_CONTENT_SHA_5_SHA_KEY_5_ALIGN 0 |
| 11213 | #define OTP_CONTENT_SHA_5_SHA_KEY_5_BITS 32 |
| 11214 | #define OTP_CONTENT_SHA_5_SHA_KEY_5_SHIFT 0 |
| 11215 | |
| 11216 | |
| 11217 | /**************************************************************************** |
| 11218 | * OTP :: CONTENT_SHA_6 |
| 11219 | ***************************************************************************/ |
| 11220 | /* OTP :: CONTENT_SHA_6 :: SHA_KEY_6 [31:00] */ |
| 11221 | #define OTP_CONTENT_SHA_6_SHA_KEY_6_MASK 0xffffffff |
| 11222 | #define OTP_CONTENT_SHA_6_SHA_KEY_6_ALIGN 0 |
| 11223 | #define OTP_CONTENT_SHA_6_SHA_KEY_6_BITS 32 |
| 11224 | #define OTP_CONTENT_SHA_6_SHA_KEY_6_SHIFT 0 |
| 11225 | |
| 11226 | |
| 11227 | /**************************************************************************** |
| 11228 | * OTP :: CONTENT_SHA_7 |
| 11229 | ***************************************************************************/ |
| 11230 | /* OTP :: CONTENT_SHA_7 :: SHA_KEY_7 [31:00] */ |
| 11231 | #define OTP_CONTENT_SHA_7_SHA_KEY_7_MASK 0xffffffff |
| 11232 | #define OTP_CONTENT_SHA_7_SHA_KEY_7_ALIGN 0 |
| 11233 | #define OTP_CONTENT_SHA_7_SHA_KEY_7_BITS 32 |
| 11234 | #define OTP_CONTENT_SHA_7_SHA_KEY_7_SHIFT 0 |
| 11235 | |
| 11236 | |
| 11237 | /**************************************************************************** |
| 11238 | * OTP :: CONTENT_CHECKSUM |
| 11239 | ***************************************************************************/ |
| 11240 | /* OTP :: CONTENT_CHECKSUM :: reserved0 [31:16] */ |
| 11241 | #define OTP_CONTENT_CHECKSUM_reserved0_MASK 0xffff0000 |
| 11242 | #define OTP_CONTENT_CHECKSUM_reserved0_ALIGN 0 |
| 11243 | #define OTP_CONTENT_CHECKSUM_reserved0_BITS 16 |
| 11244 | #define OTP_CONTENT_CHECKSUM_reserved0_SHIFT 16 |
| 11245 | |
| 11246 | /* OTP :: CONTENT_CHECKSUM :: CHECKSUM [15:00] */ |
| 11247 | #define OTP_CONTENT_CHECKSUM_CHECKSUM_MASK 0x0000ffff |
| 11248 | #define OTP_CONTENT_CHECKSUM_CHECKSUM_ALIGN 0 |
| 11249 | #define OTP_CONTENT_CHECKSUM_CHECKSUM_BITS 16 |
| 11250 | #define OTP_CONTENT_CHECKSUM_CHECKSUM_SHIFT 0 |
| 11251 | |
| 11252 | |
| 11253 | /**************************************************************************** |
| 11254 | * OTP :: PROG_CTRL |
| 11255 | ***************************************************************************/ |
| 11256 | /* OTP :: PROG_CTRL :: reserved0 [31:02] */ |
| 11257 | #define OTP_PROG_CTRL_reserved0_MASK 0xfffffffc |
| 11258 | #define OTP_PROG_CTRL_reserved0_ALIGN 0 |
| 11259 | #define OTP_PROG_CTRL_reserved0_BITS 30 |
| 11260 | #define OTP_PROG_CTRL_reserved0_SHIFT 2 |
| 11261 | |
| 11262 | /* OTP :: PROG_CTRL :: ENABLE [01:01] */ |
| 11263 | #define OTP_PROG_CTRL_ENABLE_MASK 0x00000002 |
| 11264 | #define OTP_PROG_CTRL_ENABLE_ALIGN 0 |
| 11265 | #define OTP_PROG_CTRL_ENABLE_BITS 1 |
| 11266 | #define OTP_PROG_CTRL_ENABLE_SHIFT 1 |
| 11267 | |
| 11268 | /* OTP :: PROG_CTRL :: RST [00:00] */ |
| 11269 | #define OTP_PROG_CTRL_RST_MASK 0x00000001 |
| 11270 | #define OTP_PROG_CTRL_RST_ALIGN 0 |
| 11271 | #define OTP_PROG_CTRL_RST_BITS 1 |
| 11272 | #define OTP_PROG_CTRL_RST_SHIFT 0 |
| 11273 | |
| 11274 | |
| 11275 | /**************************************************************************** |
| 11276 | * OTP :: PROG_STATUS |
| 11277 | ***************************************************************************/ |
| 11278 | /* OTP :: PROG_STATUS :: reserved0 [31:02] */ |
| 11279 | #define OTP_PROG_STATUS_reserved0_MASK 0xfffffffc |
| 11280 | #define OTP_PROG_STATUS_reserved0_ALIGN 0 |
| 11281 | #define OTP_PROG_STATUS_reserved0_BITS 30 |
| 11282 | #define OTP_PROG_STATUS_reserved0_SHIFT 2 |
| 11283 | |
| 11284 | /* OTP :: PROG_STATUS :: ORDY [01:01] */ |
| 11285 | #define OTP_PROG_STATUS_ORDY_MASK 0x00000002 |
| 11286 | #define OTP_PROG_STATUS_ORDY_ALIGN 0 |
| 11287 | #define OTP_PROG_STATUS_ORDY_BITS 1 |
| 11288 | #define OTP_PROG_STATUS_ORDY_SHIFT 1 |
| 11289 | |
| 11290 | /* OTP :: PROG_STATUS :: IRDY [00:00] */ |
| 11291 | #define OTP_PROG_STATUS_IRDY_MASK 0x00000001 |
| 11292 | #define OTP_PROG_STATUS_IRDY_ALIGN 0 |
| 11293 | #define OTP_PROG_STATUS_IRDY_BITS 1 |
| 11294 | #define OTP_PROG_STATUS_IRDY_SHIFT 0 |
| 11295 | |
| 11296 | |
| 11297 | /**************************************************************************** |
| 11298 | * OTP :: PROG_PULSE |
| 11299 | ***************************************************************************/ |
| 11300 | /* OTP :: PROG_PULSE :: PROG_HI [31:00] */ |
| 11301 | #define OTP_PROG_PULSE_PROG_HI_MASK 0xffffffff |
| 11302 | #define OTP_PROG_PULSE_PROG_HI_ALIGN 0 |
| 11303 | #define OTP_PROG_PULSE_PROG_HI_BITS 32 |
| 11304 | #define OTP_PROG_PULSE_PROG_HI_SHIFT 0 |
| 11305 | |
| 11306 | |
| 11307 | /**************************************************************************** |
| 11308 | * OTP :: VERIFY_PULSE |
| 11309 | ***************************************************************************/ |
| 11310 | /* OTP :: VERIFY_PULSE :: PROG_LOW [31:16] */ |
| 11311 | #define OTP_VERIFY_PULSE_PROG_LOW_MASK 0xffff0000 |
| 11312 | #define OTP_VERIFY_PULSE_PROG_LOW_ALIGN 0 |
| 11313 | #define OTP_VERIFY_PULSE_PROG_LOW_BITS 16 |
| 11314 | #define OTP_VERIFY_PULSE_PROG_LOW_SHIFT 16 |
| 11315 | |
| 11316 | /* OTP :: VERIFY_PULSE :: VERIFY [15:00] */ |
| 11317 | #define OTP_VERIFY_PULSE_VERIFY_MASK 0x0000ffff |
| 11318 | #define OTP_VERIFY_PULSE_VERIFY_ALIGN 0 |
| 11319 | #define OTP_VERIFY_PULSE_VERIFY_BITS 16 |
| 11320 | #define OTP_VERIFY_PULSE_VERIFY_SHIFT 0 |
| 11321 | |
| 11322 | |
| 11323 | /**************************************************************************** |
| 11324 | * OTP :: PROG_MASK |
| 11325 | ***************************************************************************/ |
| 11326 | /* OTP :: PROG_MASK :: reserved0 [31:17] */ |
| 11327 | #define OTP_PROG_MASK_reserved0_MASK 0xfffe0000 |
| 11328 | #define OTP_PROG_MASK_reserved0_ALIGN 0 |
| 11329 | #define OTP_PROG_MASK_reserved0_BITS 15 |
| 11330 | #define OTP_PROG_MASK_reserved0_SHIFT 17 |
| 11331 | |
| 11332 | /* OTP :: PROG_MASK :: PROG_MASK [16:00] */ |
| 11333 | #define OTP_PROG_MASK_PROG_MASK_MASK 0x0001ffff |
| 11334 | #define OTP_PROG_MASK_PROG_MASK_ALIGN 0 |
| 11335 | #define OTP_PROG_MASK_PROG_MASK_BITS 17 |
| 11336 | #define OTP_PROG_MASK_PROG_MASK_SHIFT 0 |
| 11337 | |
| 11338 | |
| 11339 | /**************************************************************************** |
| 11340 | * OTP :: DATA_INPUT |
| 11341 | ***************************************************************************/ |
| 11342 | /* OTP :: DATA_INPUT :: reserved0 [31:31] */ |
| 11343 | #define OTP_DATA_INPUT_reserved0_MASK 0x80000000 |
| 11344 | #define OTP_DATA_INPUT_reserved0_ALIGN 0 |
| 11345 | #define OTP_DATA_INPUT_reserved0_BITS 1 |
| 11346 | #define OTP_DATA_INPUT_reserved0_SHIFT 31 |
| 11347 | |
| 11348 | /* OTP :: DATA_INPUT :: CMD [30:28] */ |
| 11349 | #define OTP_DATA_INPUT_CMD_MASK 0x70000000 |
| 11350 | #define OTP_DATA_INPUT_CMD_ALIGN 0 |
| 11351 | #define OTP_DATA_INPUT_CMD_BITS 3 |
| 11352 | #define OTP_DATA_INPUT_CMD_SHIFT 28 |
| 11353 | |
| 11354 | /* OTP :: DATA_INPUT :: reserved1 [27:26] */ |
| 11355 | #define OTP_DATA_INPUT_reserved1_MASK 0x0c000000 |
| 11356 | #define OTP_DATA_INPUT_reserved1_ALIGN 0 |
| 11357 | #define OTP_DATA_INPUT_reserved1_BITS 2 |
| 11358 | #define OTP_DATA_INPUT_reserved1_SHIFT 26 |
| 11359 | |
| 11360 | /* OTP :: DATA_INPUT :: ADDR [25:20] */ |
| 11361 | #define OTP_DATA_INPUT_ADDR_MASK 0x03f00000 |
| 11362 | #define OTP_DATA_INPUT_ADDR_ALIGN 0 |
| 11363 | #define OTP_DATA_INPUT_ADDR_BITS 6 |
| 11364 | #define OTP_DATA_INPUT_ADDR_SHIFT 20 |
| 11365 | |
| 11366 | /* OTP :: DATA_INPUT :: reserved2 [19:18] */ |
| 11367 | #define OTP_DATA_INPUT_reserved2_MASK 0x000c0000 |
| 11368 | #define OTP_DATA_INPUT_reserved2_ALIGN 0 |
| 11369 | #define OTP_DATA_INPUT_reserved2_BITS 2 |
| 11370 | #define OTP_DATA_INPUT_reserved2_SHIFT 18 |
| 11371 | |
| 11372 | /* OTP :: DATA_INPUT :: WRCOL [17:17] */ |
| 11373 | #define OTP_DATA_INPUT_WRCOL_MASK 0x00020000 |
| 11374 | #define OTP_DATA_INPUT_WRCOL_ALIGN 0 |
| 11375 | #define OTP_DATA_INPUT_WRCOL_BITS 1 |
| 11376 | #define OTP_DATA_INPUT_WRCOL_SHIFT 17 |
| 11377 | |
| 11378 | /* OTP :: DATA_INPUT :: DIN [16:00] */ |
| 11379 | #define OTP_DATA_INPUT_DIN_MASK 0x0001ffff |
| 11380 | #define OTP_DATA_INPUT_DIN_ALIGN 0 |
| 11381 | #define OTP_DATA_INPUT_DIN_BITS 17 |
| 11382 | #define OTP_DATA_INPUT_DIN_SHIFT 0 |
| 11383 | |
| 11384 | |
| 11385 | /**************************************************************************** |
| 11386 | * OTP :: DATA_OUTPUT |
| 11387 | ***************************************************************************/ |
| 11388 | /* OTP :: DATA_OUTPUT :: reserved0 [31:17] */ |
| 11389 | #define OTP_DATA_OUTPUT_reserved0_MASK 0xfffe0000 |
| 11390 | #define OTP_DATA_OUTPUT_reserved0_ALIGN 0 |
| 11391 | #define OTP_DATA_OUTPUT_reserved0_BITS 15 |
| 11392 | #define OTP_DATA_OUTPUT_reserved0_SHIFT 17 |
| 11393 | |
| 11394 | /* OTP :: DATA_OUTPUT :: DOUT [16:00] */ |
| 11395 | #define OTP_DATA_OUTPUT_DOUT_MASK 0x0001ffff |
| 11396 | #define OTP_DATA_OUTPUT_DOUT_ALIGN 0 |
| 11397 | #define OTP_DATA_OUTPUT_DOUT_BITS 17 |
| 11398 | #define OTP_DATA_OUTPUT_DOUT_SHIFT 0 |
| 11399 | |
| 11400 | |
| 11401 | /**************************************************************************** |
| 11402 | * BCM70012_OTP_TOP_OTP_GR_BRIDGE |
| 11403 | ***************************************************************************/ |
| 11404 | /**************************************************************************** |
| 11405 | * OTP_GR_BRIDGE :: REVISION |
| 11406 | ***************************************************************************/ |
| 11407 | /* OTP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 11408 | #define OTP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 11409 | #define OTP_GR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 11410 | #define OTP_GR_BRIDGE_REVISION_reserved0_BITS 16 |
| 11411 | #define OTP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 11412 | |
| 11413 | /* OTP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 11414 | #define OTP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 11415 | #define OTP_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 11416 | #define OTP_GR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 11417 | #define OTP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 11418 | |
| 11419 | /* OTP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 11420 | #define OTP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 11421 | #define OTP_GR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 11422 | #define OTP_GR_BRIDGE_REVISION_MINOR_BITS 8 |
| 11423 | #define OTP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 11424 | |
| 11425 | |
| 11426 | /**************************************************************************** |
| 11427 | * OTP_GR_BRIDGE :: CTRL |
| 11428 | ***************************************************************************/ |
| 11429 | /* OTP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ |
| 11430 | #define OTP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe |
| 11431 | #define OTP_GR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 11432 | #define OTP_GR_BRIDGE_CTRL_reserved0_BITS 31 |
| 11433 | #define OTP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 |
| 11434 | |
| 11435 | /* OTP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 11436 | #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 11437 | #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 11438 | #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 11439 | #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 11440 | #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 11441 | #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 11442 | |
| 11443 | |
| 11444 | /**************************************************************************** |
| 11445 | * OTP_GR_BRIDGE :: SPARE_SW_RESET_0 |
| 11446 | ***************************************************************************/ |
| 11447 | /* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 11448 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 11449 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 11450 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 11451 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 11452 | |
| 11453 | /* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 11454 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 11455 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 11456 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 11457 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 11458 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 11459 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 11460 | |
| 11461 | |
| 11462 | /**************************************************************************** |
| 11463 | * OTP_GR_BRIDGE :: SPARE_SW_RESET_1 |
| 11464 | ***************************************************************************/ |
| 11465 | /* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 11466 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 11467 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 11468 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 11469 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 11470 | |
| 11471 | /* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: OTP_00_SW_RESET [00:00] */ |
| 11472 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_MASK 0x00000001 |
| 11473 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ALIGN 0 |
| 11474 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_BITS 1 |
| 11475 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_SHIFT 0 |
| 11476 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_DEASSERT 0 |
| 11477 | #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ASSERT 1 |
| 11478 | |
| 11479 | |
| 11480 | /**************************************************************************** |
| 11481 | * BCM70012_AES_TOP_AES |
| 11482 | ***************************************************************************/ |
| 11483 | /**************************************************************************** |
| 11484 | * AES :: CONFIG_INFO |
| 11485 | ***************************************************************************/ |
| 11486 | /* AES :: CONFIG_INFO :: SWAP [31:31] */ |
| 11487 | #define AES_CONFIG_INFO_SWAP_MASK 0x80000000 |
| 11488 | #define AES_CONFIG_INFO_SWAP_ALIGN 0 |
| 11489 | #define AES_CONFIG_INFO_SWAP_BITS 1 |
| 11490 | #define AES_CONFIG_INFO_SWAP_SHIFT 31 |
| 11491 | |
| 11492 | /* AES :: CONFIG_INFO :: reserved0 [30:19] */ |
| 11493 | #define AES_CONFIG_INFO_reserved0_MASK 0x7ff80000 |
| 11494 | #define AES_CONFIG_INFO_reserved0_ALIGN 0 |
| 11495 | #define AES_CONFIG_INFO_reserved0_BITS 12 |
| 11496 | #define AES_CONFIG_INFO_reserved0_SHIFT 19 |
| 11497 | |
| 11498 | /* AES :: CONFIG_INFO :: OFFSET [18:02] */ |
| 11499 | #define AES_CONFIG_INFO_OFFSET_MASK 0x0007fffc |
| 11500 | #define AES_CONFIG_INFO_OFFSET_ALIGN 0 |
| 11501 | #define AES_CONFIG_INFO_OFFSET_BITS 17 |
| 11502 | #define AES_CONFIG_INFO_OFFSET_SHIFT 2 |
| 11503 | |
| 11504 | /* AES :: CONFIG_INFO :: reserved1 [01:00] */ |
| 11505 | #define AES_CONFIG_INFO_reserved1_MASK 0x00000003 |
| 11506 | #define AES_CONFIG_INFO_reserved1_ALIGN 0 |
| 11507 | #define AES_CONFIG_INFO_reserved1_BITS 2 |
| 11508 | #define AES_CONFIG_INFO_reserved1_SHIFT 0 |
| 11509 | |
| 11510 | |
| 11511 | /**************************************************************************** |
| 11512 | * AES :: CMD |
| 11513 | ***************************************************************************/ |
| 11514 | /* AES :: CMD :: reserved0 [31:13] */ |
| 11515 | #define AES_CMD_reserved0_MASK 0xffffe000 |
| 11516 | #define AES_CMD_reserved0_ALIGN 0 |
| 11517 | #define AES_CMD_reserved0_BITS 19 |
| 11518 | #define AES_CMD_reserved0_SHIFT 13 |
| 11519 | |
| 11520 | /* AES :: CMD :: WRITE_EEPROM [12:12] */ |
| 11521 | #define AES_CMD_WRITE_EEPROM_MASK 0x00001000 |
| 11522 | #define AES_CMD_WRITE_EEPROM_ALIGN 0 |
| 11523 | #define AES_CMD_WRITE_EEPROM_BITS 1 |
| 11524 | #define AES_CMD_WRITE_EEPROM_SHIFT 12 |
| 11525 | |
| 11526 | /* AES :: CMD :: reserved1 [11:09] */ |
| 11527 | #define AES_CMD_reserved1_MASK 0x00000e00 |
| 11528 | #define AES_CMD_reserved1_ALIGN 0 |
| 11529 | #define AES_CMD_reserved1_BITS 3 |
| 11530 | #define AES_CMD_reserved1_SHIFT 9 |
| 11531 | |
| 11532 | /* AES :: CMD :: START_EEPROM_COPY [08:08] */ |
| 11533 | #define AES_CMD_START_EEPROM_COPY_MASK 0x00000100 |
| 11534 | #define AES_CMD_START_EEPROM_COPY_ALIGN 0 |
| 11535 | #define AES_CMD_START_EEPROM_COPY_BITS 1 |
| 11536 | #define AES_CMD_START_EEPROM_COPY_SHIFT 8 |
| 11537 | |
| 11538 | /* AES :: CMD :: reserved2 [07:05] */ |
| 11539 | #define AES_CMD_reserved2_MASK 0x000000e0 |
| 11540 | #define AES_CMD_reserved2_ALIGN 0 |
| 11541 | #define AES_CMD_reserved2_BITS 3 |
| 11542 | #define AES_CMD_reserved2_SHIFT 5 |
| 11543 | |
| 11544 | /* AES :: CMD :: PREPARE_ENCRYPTION [04:04] */ |
| 11545 | #define AES_CMD_PREPARE_ENCRYPTION_MASK 0x00000010 |
| 11546 | #define AES_CMD_PREPARE_ENCRYPTION_ALIGN 0 |
| 11547 | #define AES_CMD_PREPARE_ENCRYPTION_BITS 1 |
| 11548 | #define AES_CMD_PREPARE_ENCRYPTION_SHIFT 4 |
| 11549 | |
| 11550 | /* AES :: CMD :: reserved3 [03:01] */ |
| 11551 | #define AES_CMD_reserved3_MASK 0x0000000e |
| 11552 | #define AES_CMD_reserved3_ALIGN 0 |
| 11553 | #define AES_CMD_reserved3_BITS 3 |
| 11554 | #define AES_CMD_reserved3_SHIFT 1 |
| 11555 | |
| 11556 | /* AES :: CMD :: START_KEY_LOAD [00:00] */ |
| 11557 | #define AES_CMD_START_KEY_LOAD_MASK 0x00000001 |
| 11558 | #define AES_CMD_START_KEY_LOAD_ALIGN 0 |
| 11559 | #define AES_CMD_START_KEY_LOAD_BITS 1 |
| 11560 | #define AES_CMD_START_KEY_LOAD_SHIFT 0 |
| 11561 | |
| 11562 | |
| 11563 | /**************************************************************************** |
| 11564 | * AES :: STATUS |
| 11565 | ***************************************************************************/ |
| 11566 | /* AES :: STATUS :: reserved0 [31:23] */ |
| 11567 | #define AES_STATUS_reserved0_MASK 0xff800000 |
| 11568 | #define AES_STATUS_reserved0_ALIGN 0 |
| 11569 | #define AES_STATUS_reserved0_BITS 9 |
| 11570 | #define AES_STATUS_reserved0_SHIFT 23 |
| 11571 | |
| 11572 | /* AES :: STATUS :: STUCK_AT_ZERO [22:22] */ |
| 11573 | #define AES_STATUS_STUCK_AT_ZERO_MASK 0x00400000 |
| 11574 | #define AES_STATUS_STUCK_AT_ZERO_ALIGN 0 |
| 11575 | #define AES_STATUS_STUCK_AT_ZERO_BITS 1 |
| 11576 | #define AES_STATUS_STUCK_AT_ZERO_SHIFT 22 |
| 11577 | |
| 11578 | /* AES :: STATUS :: STUCK_AT_ONE [21:21] */ |
| 11579 | #define AES_STATUS_STUCK_AT_ONE_MASK 0x00200000 |
| 11580 | #define AES_STATUS_STUCK_AT_ONE_ALIGN 0 |
| 11581 | #define AES_STATUS_STUCK_AT_ONE_BITS 1 |
| 11582 | #define AES_STATUS_STUCK_AT_ONE_SHIFT 21 |
| 11583 | |
| 11584 | /* AES :: STATUS :: RANDOM_READY [20:20] */ |
| 11585 | #define AES_STATUS_RANDOM_READY_MASK 0x00100000 |
| 11586 | #define AES_STATUS_RANDOM_READY_ALIGN 0 |
| 11587 | #define AES_STATUS_RANDOM_READY_BITS 1 |
| 11588 | #define AES_STATUS_RANDOM_READY_SHIFT 20 |
| 11589 | |
| 11590 | /* AES :: STATUS :: reserved1 [19:16] */ |
| 11591 | #define AES_STATUS_reserved1_MASK 0x000f0000 |
| 11592 | #define AES_STATUS_reserved1_ALIGN 0 |
| 11593 | #define AES_STATUS_reserved1_BITS 4 |
| 11594 | #define AES_STATUS_reserved1_SHIFT 16 |
| 11595 | |
| 11596 | /* AES :: STATUS :: WRITE_EEPROM_TIMEOUT [15:15] */ |
| 11597 | #define AES_STATUS_WRITE_EEPROM_TIMEOUT_MASK 0x00008000 |
| 11598 | #define AES_STATUS_WRITE_EEPROM_TIMEOUT_ALIGN 0 |
| 11599 | #define AES_STATUS_WRITE_EEPROM_TIMEOUT_BITS 1 |
| 11600 | #define AES_STATUS_WRITE_EEPROM_TIMEOUT_SHIFT 15 |
| 11601 | |
| 11602 | /* AES :: STATUS :: WRITE_DATA_MISMATCH [14:14] */ |
| 11603 | #define AES_STATUS_WRITE_DATA_MISMATCH_MASK 0x00004000 |
| 11604 | #define AES_STATUS_WRITE_DATA_MISMATCH_ALIGN 0 |
| 11605 | #define AES_STATUS_WRITE_DATA_MISMATCH_BITS 1 |
| 11606 | #define AES_STATUS_WRITE_DATA_MISMATCH_SHIFT 14 |
| 11607 | |
| 11608 | /* AES :: STATUS :: WRITE_GISB_ERROR [13:13] */ |
| 11609 | #define AES_STATUS_WRITE_GISB_ERROR_MASK 0x00002000 |
| 11610 | #define AES_STATUS_WRITE_GISB_ERROR_ALIGN 0 |
| 11611 | #define AES_STATUS_WRITE_GISB_ERROR_BITS 1 |
| 11612 | #define AES_STATUS_WRITE_GISB_ERROR_SHIFT 13 |
| 11613 | |
| 11614 | /* AES :: STATUS :: WRITE_DONE [12:12] */ |
| 11615 | #define AES_STATUS_WRITE_DONE_MASK 0x00001000 |
| 11616 | #define AES_STATUS_WRITE_DONE_ALIGN 0 |
| 11617 | #define AES_STATUS_WRITE_DONE_BITS 1 |
| 11618 | #define AES_STATUS_WRITE_DONE_SHIFT 12 |
| 11619 | |
| 11620 | /* AES :: STATUS :: reserved2 [11:11] */ |
| 11621 | #define AES_STATUS_reserved2_MASK 0x00000800 |
| 11622 | #define AES_STATUS_reserved2_ALIGN 0 |
| 11623 | #define AES_STATUS_reserved2_BITS 1 |
| 11624 | #define AES_STATUS_reserved2_SHIFT 11 |
| 11625 | |
| 11626 | /* AES :: STATUS :: COPY_EEPROM_ERROR [10:10] */ |
| 11627 | #define AES_STATUS_COPY_EEPROM_ERROR_MASK 0x00000400 |
| 11628 | #define AES_STATUS_COPY_EEPROM_ERROR_ALIGN 0 |
| 11629 | #define AES_STATUS_COPY_EEPROM_ERROR_BITS 1 |
| 11630 | #define AES_STATUS_COPY_EEPROM_ERROR_SHIFT 10 |
| 11631 | |
| 11632 | /* AES :: STATUS :: COPY_GISB_ERROR [09:09] */ |
| 11633 | #define AES_STATUS_COPY_GISB_ERROR_MASK 0x00000200 |
| 11634 | #define AES_STATUS_COPY_GISB_ERROR_ALIGN 0 |
| 11635 | #define AES_STATUS_COPY_GISB_ERROR_BITS 1 |
| 11636 | #define AES_STATUS_COPY_GISB_ERROR_SHIFT 9 |
| 11637 | |
| 11638 | /* AES :: STATUS :: COPY_DONE [08:08] */ |
| 11639 | #define AES_STATUS_COPY_DONE_MASK 0x00000100 |
| 11640 | #define AES_STATUS_COPY_DONE_ALIGN 0 |
| 11641 | #define AES_STATUS_COPY_DONE_BITS 1 |
| 11642 | #define AES_STATUS_COPY_DONE_SHIFT 8 |
| 11643 | |
| 11644 | /* AES :: STATUS :: PREPARE_EEPROM_TIMEOUT [07:07] */ |
| 11645 | #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_MASK 0x00000080 |
| 11646 | #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_ALIGN 0 |
| 11647 | #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_BITS 1 |
| 11648 | #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_SHIFT 7 |
| 11649 | |
| 11650 | /* AES :: STATUS :: PREPARE_DATA_MISMATCH [06:06] */ |
| 11651 | #define AES_STATUS_PREPARE_DATA_MISMATCH_MASK 0x00000040 |
| 11652 | #define AES_STATUS_PREPARE_DATA_MISMATCH_ALIGN 0 |
| 11653 | #define AES_STATUS_PREPARE_DATA_MISMATCH_BITS 1 |
| 11654 | #define AES_STATUS_PREPARE_DATA_MISMATCH_SHIFT 6 |
| 11655 | |
| 11656 | /* AES :: STATUS :: PREPARE_GISB_ERROR [05:05] */ |
| 11657 | #define AES_STATUS_PREPARE_GISB_ERROR_MASK 0x00000020 |
| 11658 | #define AES_STATUS_PREPARE_GISB_ERROR_ALIGN 0 |
| 11659 | #define AES_STATUS_PREPARE_GISB_ERROR_BITS 1 |
| 11660 | #define AES_STATUS_PREPARE_GISB_ERROR_SHIFT 5 |
| 11661 | |
| 11662 | /* AES :: STATUS :: PREPARE_DONE [04:04] */ |
| 11663 | #define AES_STATUS_PREPARE_DONE_MASK 0x00000010 |
| 11664 | #define AES_STATUS_PREPARE_DONE_ALIGN 0 |
| 11665 | #define AES_STATUS_PREPARE_DONE_BITS 1 |
| 11666 | #define AES_STATUS_PREPARE_DONE_SHIFT 4 |
| 11667 | |
| 11668 | /* AES :: STATUS :: reserved3 [03:02] */ |
| 11669 | #define AES_STATUS_reserved3_MASK 0x0000000c |
| 11670 | #define AES_STATUS_reserved3_ALIGN 0 |
| 11671 | #define AES_STATUS_reserved3_BITS 2 |
| 11672 | #define AES_STATUS_reserved3_SHIFT 2 |
| 11673 | |
| 11674 | /* AES :: STATUS :: KEY_LOAD_GISB_ERROR [01:01] */ |
| 11675 | #define AES_STATUS_KEY_LOAD_GISB_ERROR_MASK 0x00000002 |
| 11676 | #define AES_STATUS_KEY_LOAD_GISB_ERROR_ALIGN 0 |
| 11677 | #define AES_STATUS_KEY_LOAD_GISB_ERROR_BITS 1 |
| 11678 | #define AES_STATUS_KEY_LOAD_GISB_ERROR_SHIFT 1 |
| 11679 | |
| 11680 | /* AES :: STATUS :: KEY_LOAD_DONE [00:00] */ |
| 11681 | #define AES_STATUS_KEY_LOAD_DONE_MASK 0x00000001 |
| 11682 | #define AES_STATUS_KEY_LOAD_DONE_ALIGN 0 |
| 11683 | #define AES_STATUS_KEY_LOAD_DONE_BITS 1 |
| 11684 | #define AES_STATUS_KEY_LOAD_DONE_SHIFT 0 |
| 11685 | |
| 11686 | |
| 11687 | /**************************************************************************** |
| 11688 | * AES :: EEPROM_CONFIG |
| 11689 | ***************************************************************************/ |
| 11690 | /* AES :: EEPROM_CONFIG :: LENGTH [31:20] */ |
| 11691 | #define AES_EEPROM_CONFIG_LENGTH_MASK 0xfff00000 |
| 11692 | #define AES_EEPROM_CONFIG_LENGTH_ALIGN 0 |
| 11693 | #define AES_EEPROM_CONFIG_LENGTH_BITS 12 |
| 11694 | #define AES_EEPROM_CONFIG_LENGTH_SHIFT 20 |
| 11695 | |
| 11696 | /* AES :: EEPROM_CONFIG :: reserved0 [19:16] */ |
| 11697 | #define AES_EEPROM_CONFIG_reserved0_MASK 0x000f0000 |
| 11698 | #define AES_EEPROM_CONFIG_reserved0_ALIGN 0 |
| 11699 | #define AES_EEPROM_CONFIG_reserved0_BITS 4 |
| 11700 | #define AES_EEPROM_CONFIG_reserved0_SHIFT 16 |
| 11701 | |
| 11702 | /* AES :: EEPROM_CONFIG :: START_ADDR [15:02] */ |
| 11703 | #define AES_EEPROM_CONFIG_START_ADDR_MASK 0x0000fffc |
| 11704 | #define AES_EEPROM_CONFIG_START_ADDR_ALIGN 0 |
| 11705 | #define AES_EEPROM_CONFIG_START_ADDR_BITS 14 |
| 11706 | #define AES_EEPROM_CONFIG_START_ADDR_SHIFT 2 |
| 11707 | |
| 11708 | /* AES :: EEPROM_CONFIG :: reserved1 [01:00] */ |
| 11709 | #define AES_EEPROM_CONFIG_reserved1_MASK 0x00000003 |
| 11710 | #define AES_EEPROM_CONFIG_reserved1_ALIGN 0 |
| 11711 | #define AES_EEPROM_CONFIG_reserved1_BITS 2 |
| 11712 | #define AES_EEPROM_CONFIG_reserved1_SHIFT 0 |
| 11713 | |
| 11714 | |
| 11715 | /**************************************************************************** |
| 11716 | * AES :: EEPROM_DATA_0 |
| 11717 | ***************************************************************************/ |
| 11718 | /* AES :: EEPROM_DATA_0 :: DATA [31:00] */ |
| 11719 | #define AES_EEPROM_DATA_0_DATA_MASK 0xffffffff |
| 11720 | #define AES_EEPROM_DATA_0_DATA_ALIGN 0 |
| 11721 | #define AES_EEPROM_DATA_0_DATA_BITS 32 |
| 11722 | #define AES_EEPROM_DATA_0_DATA_SHIFT 0 |
| 11723 | |
| 11724 | |
| 11725 | /**************************************************************************** |
| 11726 | * AES :: EEPROM_DATA_1 |
| 11727 | ***************************************************************************/ |
| 11728 | /* AES :: EEPROM_DATA_1 :: DATA [31:00] */ |
| 11729 | #define AES_EEPROM_DATA_1_DATA_MASK 0xffffffff |
| 11730 | #define AES_EEPROM_DATA_1_DATA_ALIGN 0 |
| 11731 | #define AES_EEPROM_DATA_1_DATA_BITS 32 |
| 11732 | #define AES_EEPROM_DATA_1_DATA_SHIFT 0 |
| 11733 | |
| 11734 | |
| 11735 | /**************************************************************************** |
| 11736 | * AES :: EEPROM_DATA_2 |
| 11737 | ***************************************************************************/ |
| 11738 | /* AES :: EEPROM_DATA_2 :: DATA [31:00] */ |
| 11739 | #define AES_EEPROM_DATA_2_DATA_MASK 0xffffffff |
| 11740 | #define AES_EEPROM_DATA_2_DATA_ALIGN 0 |
| 11741 | #define AES_EEPROM_DATA_2_DATA_BITS 32 |
| 11742 | #define AES_EEPROM_DATA_2_DATA_SHIFT 0 |
| 11743 | |
| 11744 | |
| 11745 | /**************************************************************************** |
| 11746 | * AES :: EEPROM_DATA_3 |
| 11747 | ***************************************************************************/ |
| 11748 | /* AES :: EEPROM_DATA_3 :: DATA [31:00] */ |
| 11749 | #define AES_EEPROM_DATA_3_DATA_MASK 0xffffffff |
| 11750 | #define AES_EEPROM_DATA_3_DATA_ALIGN 0 |
| 11751 | #define AES_EEPROM_DATA_3_DATA_BITS 32 |
| 11752 | #define AES_EEPROM_DATA_3_DATA_SHIFT 0 |
| 11753 | |
| 11754 | |
| 11755 | /**************************************************************************** |
| 11756 | * BCM70012_AES_TOP_AES_RGR_BRIDGE |
| 11757 | ***************************************************************************/ |
| 11758 | /**************************************************************************** |
| 11759 | * AES_RGR_BRIDGE :: REVISION |
| 11760 | ***************************************************************************/ |
| 11761 | /* AES_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 11762 | #define AES_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 11763 | #define AES_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 11764 | #define AES_RGR_BRIDGE_REVISION_reserved0_BITS 16 |
| 11765 | #define AES_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 11766 | |
| 11767 | /* AES_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 11768 | #define AES_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 11769 | #define AES_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 11770 | #define AES_RGR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 11771 | #define AES_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 11772 | |
| 11773 | /* AES_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 11774 | #define AES_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 11775 | #define AES_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 11776 | #define AES_RGR_BRIDGE_REVISION_MINOR_BITS 8 |
| 11777 | #define AES_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 11778 | |
| 11779 | |
| 11780 | /**************************************************************************** |
| 11781 | * AES_RGR_BRIDGE :: CTRL |
| 11782 | ***************************************************************************/ |
| 11783 | /* AES_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ |
| 11784 | #define AES_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc |
| 11785 | #define AES_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 11786 | #define AES_RGR_BRIDGE_CTRL_reserved0_BITS 30 |
| 11787 | #define AES_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 |
| 11788 | |
| 11789 | /* AES_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ |
| 11790 | #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 |
| 11791 | #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 |
| 11792 | #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 |
| 11793 | #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 |
| 11794 | #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 |
| 11795 | #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 |
| 11796 | |
| 11797 | /* AES_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 11798 | #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 11799 | #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 11800 | #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 11801 | #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 11802 | #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 11803 | #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 11804 | |
| 11805 | |
| 11806 | /**************************************************************************** |
| 11807 | * AES_RGR_BRIDGE :: RBUS_TIMER |
| 11808 | ***************************************************************************/ |
| 11809 | /* AES_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ |
| 11810 | #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 |
| 11811 | #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 |
| 11812 | #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 |
| 11813 | #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 |
| 11814 | |
| 11815 | /* AES_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ |
| 11816 | #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff |
| 11817 | #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 |
| 11818 | #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 |
| 11819 | #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 |
| 11820 | |
| 11821 | |
| 11822 | /**************************************************************************** |
| 11823 | * AES_RGR_BRIDGE :: SPARE_SW_RESET_0 |
| 11824 | ***************************************************************************/ |
| 11825 | /* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 11826 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 11827 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 11828 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 11829 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 11830 | |
| 11831 | /* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 11832 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 11833 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 11834 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 11835 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 11836 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 11837 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 11838 | |
| 11839 | |
| 11840 | /**************************************************************************** |
| 11841 | * AES_RGR_BRIDGE :: SPARE_SW_RESET_1 |
| 11842 | ***************************************************************************/ |
| 11843 | /* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 11844 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 11845 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 11846 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 11847 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 11848 | |
| 11849 | /* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 11850 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 11851 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 11852 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 11853 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 11854 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 |
| 11855 | #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 |
| 11856 | |
| 11857 | |
| 11858 | /**************************************************************************** |
| 11859 | * BCM70012_DCI_TOP_DCI |
| 11860 | ***************************************************************************/ |
| 11861 | /**************************************************************************** |
| 11862 | * DCI :: CMD |
| 11863 | ***************************************************************************/ |
| 11864 | /* DCI :: CMD :: reserved0 [31:09] */ |
| 11865 | #define DCI_CMD_reserved0_MASK 0xfffffe00 |
| 11866 | #define DCI_CMD_reserved0_ALIGN 0 |
| 11867 | #define DCI_CMD_reserved0_BITS 23 |
| 11868 | #define DCI_CMD_reserved0_SHIFT 9 |
| 11869 | |
| 11870 | /* DCI :: CMD :: FORCE_FW_VALIDATED [08:08] */ |
| 11871 | #define DCI_CMD_FORCE_FW_VALIDATED_MASK 0x00000100 |
| 11872 | #define DCI_CMD_FORCE_FW_VALIDATED_ALIGN 0 |
| 11873 | #define DCI_CMD_FORCE_FW_VALIDATED_BITS 1 |
| 11874 | #define DCI_CMD_FORCE_FW_VALIDATED_SHIFT 8 |
| 11875 | |
| 11876 | /* DCI :: CMD :: reserved1 [07:05] */ |
| 11877 | #define DCI_CMD_reserved1_MASK 0x000000e0 |
| 11878 | #define DCI_CMD_reserved1_ALIGN 0 |
| 11879 | #define DCI_CMD_reserved1_BITS 3 |
| 11880 | #define DCI_CMD_reserved1_SHIFT 5 |
| 11881 | |
| 11882 | /* DCI :: CMD :: START_PROCESSOR [04:04] */ |
| 11883 | #define DCI_CMD_START_PROCESSOR_MASK 0x00000010 |
| 11884 | #define DCI_CMD_START_PROCESSOR_ALIGN 0 |
| 11885 | #define DCI_CMD_START_PROCESSOR_BITS 1 |
| 11886 | #define DCI_CMD_START_PROCESSOR_SHIFT 4 |
| 11887 | |
| 11888 | /* DCI :: CMD :: reserved2 [03:02] */ |
| 11889 | #define DCI_CMD_reserved2_MASK 0x0000000c |
| 11890 | #define DCI_CMD_reserved2_ALIGN 0 |
| 11891 | #define DCI_CMD_reserved2_BITS 2 |
| 11892 | #define DCI_CMD_reserved2_SHIFT 2 |
| 11893 | |
| 11894 | /* DCI :: CMD :: DOWNLOAD_COMPLETE [01:01] */ |
| 11895 | #define DCI_CMD_DOWNLOAD_COMPLETE_MASK 0x00000002 |
| 11896 | #define DCI_CMD_DOWNLOAD_COMPLETE_ALIGN 0 |
| 11897 | #define DCI_CMD_DOWNLOAD_COMPLETE_BITS 1 |
| 11898 | #define DCI_CMD_DOWNLOAD_COMPLETE_SHIFT 1 |
| 11899 | |
| 11900 | /* DCI :: CMD :: INITIATE_FW_DOWNLOAD [00:00] */ |
| 11901 | #define DCI_CMD_INITIATE_FW_DOWNLOAD_MASK 0x00000001 |
| 11902 | #define DCI_CMD_INITIATE_FW_DOWNLOAD_ALIGN 0 |
| 11903 | #define DCI_CMD_INITIATE_FW_DOWNLOAD_BITS 1 |
| 11904 | #define DCI_CMD_INITIATE_FW_DOWNLOAD_SHIFT 0 |
| 11905 | |
| 11906 | |
| 11907 | /**************************************************************************** |
| 11908 | * DCI :: STATUS |
| 11909 | ***************************************************************************/ |
| 11910 | /* DCI :: STATUS :: reserved0 [31:10] */ |
| 11911 | #define DCI_STATUS_reserved0_MASK 0xfffffc00 |
| 11912 | #define DCI_STATUS_reserved0_ALIGN 0 |
| 11913 | #define DCI_STATUS_reserved0_BITS 22 |
| 11914 | #define DCI_STATUS_reserved0_SHIFT 10 |
| 11915 | |
| 11916 | /* DCI :: STATUS :: SIGNATURE_MATCHED [09:09] */ |
| 11917 | #define DCI_STATUS_SIGNATURE_MATCHED_MASK 0x00000200 |
| 11918 | #define DCI_STATUS_SIGNATURE_MATCHED_ALIGN 0 |
| 11919 | #define DCI_STATUS_SIGNATURE_MATCHED_BITS 1 |
| 11920 | #define DCI_STATUS_SIGNATURE_MATCHED_SHIFT 9 |
| 11921 | |
| 11922 | /* DCI :: STATUS :: SIGNATURE_MISMATCH [08:08] */ |
| 11923 | #define DCI_STATUS_SIGNATURE_MISMATCH_MASK 0x00000100 |
| 11924 | #define DCI_STATUS_SIGNATURE_MISMATCH_ALIGN 0 |
| 11925 | #define DCI_STATUS_SIGNATURE_MISMATCH_BITS 1 |
| 11926 | #define DCI_STATUS_SIGNATURE_MISMATCH_SHIFT 8 |
| 11927 | |
| 11928 | /* DCI :: STATUS :: reserved1 [07:06] */ |
| 11929 | #define DCI_STATUS_reserved1_MASK 0x000000c0 |
| 11930 | #define DCI_STATUS_reserved1_ALIGN 0 |
| 11931 | #define DCI_STATUS_reserved1_BITS 2 |
| 11932 | #define DCI_STATUS_reserved1_SHIFT 6 |
| 11933 | |
| 11934 | /* DCI :: STATUS :: GISB_ERROR [05:05] */ |
| 11935 | #define DCI_STATUS_GISB_ERROR_MASK 0x00000020 |
| 11936 | #define DCI_STATUS_GISB_ERROR_ALIGN 0 |
| 11937 | #define DCI_STATUS_GISB_ERROR_BITS 1 |
| 11938 | #define DCI_STATUS_GISB_ERROR_SHIFT 5 |
| 11939 | |
| 11940 | /* DCI :: STATUS :: DOWNLOAD_READY [04:04] */ |
| 11941 | #define DCI_STATUS_DOWNLOAD_READY_MASK 0x00000010 |
| 11942 | #define DCI_STATUS_DOWNLOAD_READY_ALIGN 0 |
| 11943 | #define DCI_STATUS_DOWNLOAD_READY_BITS 1 |
| 11944 | #define DCI_STATUS_DOWNLOAD_READY_SHIFT 4 |
| 11945 | |
| 11946 | /* DCI :: STATUS :: reserved2 [03:01] */ |
| 11947 | #define DCI_STATUS_reserved2_MASK 0x0000000e |
| 11948 | #define DCI_STATUS_reserved2_ALIGN 0 |
| 11949 | #define DCI_STATUS_reserved2_BITS 3 |
| 11950 | #define DCI_STATUS_reserved2_SHIFT 1 |
| 11951 | |
| 11952 | /* DCI :: STATUS :: FIRMWARE_VALIDATED [00:00] */ |
| 11953 | #define DCI_STATUS_FIRMWARE_VALIDATED_MASK 0x00000001 |
| 11954 | #define DCI_STATUS_FIRMWARE_VALIDATED_ALIGN 0 |
| 11955 | #define DCI_STATUS_FIRMWARE_VALIDATED_BITS 1 |
| 11956 | #define DCI_STATUS_FIRMWARE_VALIDATED_SHIFT 0 |
| 11957 | |
| 11958 | |
| 11959 | /**************************************************************************** |
| 11960 | * DCI :: DRAM_BASE_ADDR |
| 11961 | ***************************************************************************/ |
| 11962 | /* DCI :: DRAM_BASE_ADDR :: reserved0 [31:13] */ |
| 11963 | #define DCI_DRAM_BASE_ADDR_reserved0_MASK 0xffffe000 |
| 11964 | #define DCI_DRAM_BASE_ADDR_reserved0_ALIGN 0 |
| 11965 | #define DCI_DRAM_BASE_ADDR_reserved0_BITS 19 |
| 11966 | #define DCI_DRAM_BASE_ADDR_reserved0_SHIFT 13 |
| 11967 | |
| 11968 | /* DCI :: DRAM_BASE_ADDR :: BASE_ADDR [12:00] */ |
| 11969 | #define DCI_DRAM_BASE_ADDR_BASE_ADDR_MASK 0x00001fff |
| 11970 | #define DCI_DRAM_BASE_ADDR_BASE_ADDR_ALIGN 0 |
| 11971 | #define DCI_DRAM_BASE_ADDR_BASE_ADDR_BITS 13 |
| 11972 | #define DCI_DRAM_BASE_ADDR_BASE_ADDR_SHIFT 0 |
| 11973 | |
| 11974 | |
| 11975 | /**************************************************************************** |
| 11976 | * DCI :: FIRMWARE_ADDR |
| 11977 | ***************************************************************************/ |
| 11978 | /* DCI :: FIRMWARE_ADDR :: reserved0 [31:19] */ |
| 11979 | #define DCI_FIRMWARE_ADDR_reserved0_MASK 0xfff80000 |
| 11980 | #define DCI_FIRMWARE_ADDR_reserved0_ALIGN 0 |
| 11981 | #define DCI_FIRMWARE_ADDR_reserved0_BITS 13 |
| 11982 | #define DCI_FIRMWARE_ADDR_reserved0_SHIFT 19 |
| 11983 | |
| 11984 | /* DCI :: FIRMWARE_ADDR :: FW_ADDR [18:02] */ |
| 11985 | #define DCI_FIRMWARE_ADDR_FW_ADDR_MASK 0x0007fffc |
| 11986 | #define DCI_FIRMWARE_ADDR_FW_ADDR_ALIGN 0 |
| 11987 | #define DCI_FIRMWARE_ADDR_FW_ADDR_BITS 17 |
| 11988 | #define DCI_FIRMWARE_ADDR_FW_ADDR_SHIFT 2 |
| 11989 | |
| 11990 | /* DCI :: FIRMWARE_ADDR :: reserved1 [01:00] */ |
| 11991 | #define DCI_FIRMWARE_ADDR_reserved1_MASK 0x00000003 |
| 11992 | #define DCI_FIRMWARE_ADDR_reserved1_ALIGN 0 |
| 11993 | #define DCI_FIRMWARE_ADDR_reserved1_BITS 2 |
| 11994 | #define DCI_FIRMWARE_ADDR_reserved1_SHIFT 0 |
| 11995 | |
| 11996 | |
| 11997 | /**************************************************************************** |
| 11998 | * DCI :: FIRMWARE_DATA |
| 11999 | ***************************************************************************/ |
| 12000 | /* DCI :: FIRMWARE_DATA :: FW_DATA [31:00] */ |
| 12001 | #define DCI_FIRMWARE_DATA_FW_DATA_MASK 0xffffffff |
| 12002 | #define DCI_FIRMWARE_DATA_FW_DATA_ALIGN 0 |
| 12003 | #define DCI_FIRMWARE_DATA_FW_DATA_BITS 32 |
| 12004 | #define DCI_FIRMWARE_DATA_FW_DATA_SHIFT 0 |
| 12005 | |
| 12006 | |
| 12007 | /**************************************************************************** |
| 12008 | * DCI :: SIGNATURE_DATA_0 |
| 12009 | ***************************************************************************/ |
| 12010 | /* DCI :: SIGNATURE_DATA_0 :: SIG_DATA_0 [31:00] */ |
| 12011 | #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_MASK 0xffffffff |
| 12012 | #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_ALIGN 0 |
| 12013 | #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_BITS 32 |
| 12014 | #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_SHIFT 0 |
| 12015 | |
| 12016 | |
| 12017 | /**************************************************************************** |
| 12018 | * DCI :: SIGNATURE_DATA_1 |
| 12019 | ***************************************************************************/ |
| 12020 | /* DCI :: SIGNATURE_DATA_1 :: SIG_DATA_1 [31:00] */ |
| 12021 | #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_MASK 0xffffffff |
| 12022 | #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_ALIGN 0 |
| 12023 | #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_BITS 32 |
| 12024 | #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_SHIFT 0 |
| 12025 | |
| 12026 | |
| 12027 | /**************************************************************************** |
| 12028 | * DCI :: SIGNATURE_DATA_2 |
| 12029 | ***************************************************************************/ |
| 12030 | /* DCI :: SIGNATURE_DATA_2 :: SIG_DATA_2 [31:00] */ |
| 12031 | #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_MASK 0xffffffff |
| 12032 | #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_ALIGN 0 |
| 12033 | #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_BITS 32 |
| 12034 | #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_SHIFT 0 |
| 12035 | |
| 12036 | |
| 12037 | /**************************************************************************** |
| 12038 | * DCI :: SIGNATURE_DATA_3 |
| 12039 | ***************************************************************************/ |
| 12040 | /* DCI :: SIGNATURE_DATA_3 :: SIG_DATA_3 [31:00] */ |
| 12041 | #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_MASK 0xffffffff |
| 12042 | #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_ALIGN 0 |
| 12043 | #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_BITS 32 |
| 12044 | #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_SHIFT 0 |
| 12045 | |
| 12046 | |
| 12047 | /**************************************************************************** |
| 12048 | * DCI :: SIGNATURE_DATA_4 |
| 12049 | ***************************************************************************/ |
| 12050 | /* DCI :: SIGNATURE_DATA_4 :: SIG_DATA_4 [31:00] */ |
| 12051 | #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_MASK 0xffffffff |
| 12052 | #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_ALIGN 0 |
| 12053 | #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_BITS 32 |
| 12054 | #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_SHIFT 0 |
| 12055 | |
| 12056 | |
| 12057 | /**************************************************************************** |
| 12058 | * DCI :: SIGNATURE_DATA_5 |
| 12059 | ***************************************************************************/ |
| 12060 | /* DCI :: SIGNATURE_DATA_5 :: SIG_DATA_5 [31:00] */ |
| 12061 | #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_MASK 0xffffffff |
| 12062 | #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_ALIGN 0 |
| 12063 | #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_BITS 32 |
| 12064 | #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_SHIFT 0 |
| 12065 | |
| 12066 | |
| 12067 | /**************************************************************************** |
| 12068 | * DCI :: SIGNATURE_DATA_6 |
| 12069 | ***************************************************************************/ |
| 12070 | /* DCI :: SIGNATURE_DATA_6 :: SIG_DATA_6 [31:00] */ |
| 12071 | #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_MASK 0xffffffff |
| 12072 | #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_ALIGN 0 |
| 12073 | #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_BITS 32 |
| 12074 | #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_SHIFT 0 |
| 12075 | |
| 12076 | |
| 12077 | /**************************************************************************** |
| 12078 | * DCI :: SIGNATURE_DATA_7 |
| 12079 | ***************************************************************************/ |
| 12080 | /* DCI :: SIGNATURE_DATA_7 :: SIG_DATA_7 [31:00] */ |
| 12081 | #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_MASK 0xffffffff |
| 12082 | #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_ALIGN 0 |
| 12083 | #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_BITS 32 |
| 12084 | #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_SHIFT 0 |
| 12085 | |
| 12086 | |
| 12087 | /**************************************************************************** |
| 12088 | * BCM70012_DCI_TOP_DCI_RGR_BRIDGE |
| 12089 | ***************************************************************************/ |
| 12090 | /**************************************************************************** |
| 12091 | * DCI_RGR_BRIDGE :: REVISION |
| 12092 | ***************************************************************************/ |
| 12093 | /* DCI_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 12094 | #define DCI_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 12095 | #define DCI_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 12096 | #define DCI_RGR_BRIDGE_REVISION_reserved0_BITS 16 |
| 12097 | #define DCI_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 12098 | |
| 12099 | /* DCI_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 12100 | #define DCI_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 12101 | #define DCI_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 12102 | #define DCI_RGR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 12103 | #define DCI_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 12104 | |
| 12105 | /* DCI_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 12106 | #define DCI_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 12107 | #define DCI_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 12108 | #define DCI_RGR_BRIDGE_REVISION_MINOR_BITS 8 |
| 12109 | #define DCI_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 12110 | |
| 12111 | |
| 12112 | /**************************************************************************** |
| 12113 | * DCI_RGR_BRIDGE :: CTRL |
| 12114 | ***************************************************************************/ |
| 12115 | /* DCI_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ |
| 12116 | #define DCI_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc |
| 12117 | #define DCI_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 12118 | #define DCI_RGR_BRIDGE_CTRL_reserved0_BITS 30 |
| 12119 | #define DCI_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 |
| 12120 | |
| 12121 | /* DCI_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ |
| 12122 | #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 |
| 12123 | #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 |
| 12124 | #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 |
| 12125 | #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 |
| 12126 | #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 |
| 12127 | #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 |
| 12128 | |
| 12129 | /* DCI_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 12130 | #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 12131 | #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 12132 | #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 12133 | #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 12134 | #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 12135 | #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 12136 | |
| 12137 | |
| 12138 | /**************************************************************************** |
| 12139 | * DCI_RGR_BRIDGE :: RBUS_TIMER |
| 12140 | ***************************************************************************/ |
| 12141 | /* DCI_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ |
| 12142 | #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 |
| 12143 | #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 |
| 12144 | #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 |
| 12145 | #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 |
| 12146 | |
| 12147 | /* DCI_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ |
| 12148 | #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff |
| 12149 | #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 |
| 12150 | #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 |
| 12151 | #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 |
| 12152 | |
| 12153 | |
| 12154 | /**************************************************************************** |
| 12155 | * DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 |
| 12156 | ***************************************************************************/ |
| 12157 | /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 12158 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 12159 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 12160 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 12161 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 12162 | |
| 12163 | /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 12164 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 12165 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 12166 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 12167 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 12168 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 12169 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 12170 | |
| 12171 | |
| 12172 | /**************************************************************************** |
| 12173 | * DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 |
| 12174 | ***************************************************************************/ |
| 12175 | /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 12176 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 12177 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 12178 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 12179 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 12180 | |
| 12181 | /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 12182 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 12183 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 12184 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 12185 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 12186 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 |
| 12187 | #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 |
| 12188 | |
| 12189 | |
| 12190 | /**************************************************************************** |
| 12191 | * BCM70012_CCE_TOP_CCE_RGR_BRIDGE |
| 12192 | ***************************************************************************/ |
| 12193 | /**************************************************************************** |
| 12194 | * CCE_RGR_BRIDGE :: REVISION |
| 12195 | ***************************************************************************/ |
| 12196 | /* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ |
| 12197 | #define CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 |
| 12198 | #define CCE_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 |
| 12199 | #define CCE_RGR_BRIDGE_REVISION_reserved0_BITS 16 |
| 12200 | #define CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 |
| 12201 | |
| 12202 | /* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ |
| 12203 | #define CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 |
| 12204 | #define CCE_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 |
| 12205 | #define CCE_RGR_BRIDGE_REVISION_MAJOR_BITS 8 |
| 12206 | #define CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 |
| 12207 | |
| 12208 | /* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ |
| 12209 | #define CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff |
| 12210 | #define CCE_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 |
| 12211 | #define CCE_RGR_BRIDGE_REVISION_MINOR_BITS 8 |
| 12212 | #define CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 |
| 12213 | |
| 12214 | |
| 12215 | /**************************************************************************** |
| 12216 | * CCE_RGR_BRIDGE :: CTRL |
| 12217 | ***************************************************************************/ |
| 12218 | /* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ |
| 12219 | #define CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc |
| 12220 | #define CCE_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 |
| 12221 | #define CCE_RGR_BRIDGE_CTRL_reserved0_BITS 30 |
| 12222 | #define CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 |
| 12223 | |
| 12224 | /* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ |
| 12225 | #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 |
| 12226 | #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 |
| 12227 | #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 |
| 12228 | #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 |
| 12229 | #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 |
| 12230 | #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 |
| 12231 | |
| 12232 | /* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ |
| 12233 | #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 |
| 12234 | #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 |
| 12235 | #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 |
| 12236 | #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 |
| 12237 | #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 |
| 12238 | #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 |
| 12239 | |
| 12240 | |
| 12241 | /**************************************************************************** |
| 12242 | * CCE_RGR_BRIDGE :: RBUS_TIMER |
| 12243 | ***************************************************************************/ |
| 12244 | /* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ |
| 12245 | #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 |
| 12246 | #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 |
| 12247 | #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 |
| 12248 | #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 |
| 12249 | |
| 12250 | /* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ |
| 12251 | #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff |
| 12252 | #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 |
| 12253 | #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 |
| 12254 | #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 |
| 12255 | |
| 12256 | |
| 12257 | /**************************************************************************** |
| 12258 | * CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 |
| 12259 | ***************************************************************************/ |
| 12260 | /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ |
| 12261 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe |
| 12262 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 |
| 12263 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 |
| 12264 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 |
| 12265 | |
| 12266 | /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ |
| 12267 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 |
| 12268 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 |
| 12269 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 |
| 12270 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 |
| 12271 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 |
| 12272 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 |
| 12273 | |
| 12274 | |
| 12275 | /**************************************************************************** |
| 12276 | * CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 |
| 12277 | ***************************************************************************/ |
| 12278 | /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ |
| 12279 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe |
| 12280 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 |
| 12281 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 |
| 12282 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 |
| 12283 | |
| 12284 | /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ |
| 12285 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 |
| 12286 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 |
| 12287 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 |
| 12288 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 |
| 12289 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 |
| 12290 | #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 |
| 12291 | |
| 12292 | |
| 12293 | /**************************************************************************** |
| 12294 | * Datatype Definitions. |
| 12295 | ***************************************************************************/ |
| 12296 | #endif /* #ifndef MACFILE_H__ */ |
| 12297 | |
| 12298 | /* End of File */ |
| 12299 | |