blob: e0256deb91fbfd7acc478e29609831fcfdf39c12 [file] [log] [blame]
Nicolas Ferre13455622010-10-14 17:19:11 +02001/*
2 * reset AT91SAM9G20 as per errata
3 *
4 * (C) BitBox Ltd 2010
5 *
6 * unless the SDRAM is cleanly shutdown before we hit the
7 * reset register it can be left driving the data bus and
8 * killing the chance of a subsequent boot from NAND
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/linkage.h>
17#include <asm/system.h>
18#include <mach/hardware.h>
19#include <mach/at91sam9_sdramc.h>
20#include <mach/at91_rstc.h>
21
22 .arm
23
24 .globl at91sam9_alt_reset
25
26at91sam9_alt_reset: mrc p15, 0, r0, c1, c0, 0
27 orr r0, r0, #CR_I
28 mcr p15, 0, r0, c1, c0, 0 @ enable I-cache
29
30 ldr r0, .at91_va_base_sdramc @ preload constants
31 ldr r1, .at91_va_base_rstc_cr
32
33 mov r2, #1
34 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
35 ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
36
37 .balign 32 @ align to cache line
38
39 str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
40 str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
41 str r4, [r1] @ reset processor
42
43 b .
44
45.at91_va_base_sdramc:
46 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
47.at91_va_base_rstc_cr:
48 .word AT91_VA_BASE_SYS + AT91_RSTC_CR