| Kukjin Kim | 7d30e8b | 2011-02-14 16:33:10 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 2 | * |
| Kukjin Kim | 7d30e8b | 2011-02-14 16:33:10 +0900 | [diff] [blame] | 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 4 | * http://www.samsung.com |
| 5 | * |
| Kukjin Kim | 7d30e8b | 2011-02-14 16:33:10 +0900 | [diff] [blame] | 6 | * EXYNOS4 - Power management unit definition |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ASM_ARCH_REGS_PMU_H |
| 14 | #define __ASM_ARCH_REGS_PMU_H __FILE__ |
| 15 | |
| 16 | #include <mach/map.h> |
| 17 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 18 | #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 19 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 20 | #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) |
| Sylwester Nawrocki | 1d45ac4 | 2011-03-10 21:53:40 +0900 | [diff] [blame] | 21 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 22 | #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 23 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 24 | #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) |
| 25 | |
| 26 | #define S5P_USE_STANDBY_WFI0 (1 << 16) |
| 27 | #define S5P_USE_STANDBY_WFI1 (1 << 17) |
| 28 | #define S5P_USE_STANDBY_WFE0 (1 << 24) |
| 29 | #define S5P_USE_STANDBY_WFE1 (1 << 25) |
| 30 | #define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24)) |
| 31 | |
| Kyungmin Park | d2edddf | 2011-08-19 20:25:05 +0900 | [diff] [blame] | 32 | #define S5P_SWRESET S5P_PMUREG(0x0400) |
| 33 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 34 | #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) |
| 35 | #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) |
| 36 | #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) |
| 37 | |
| Joonyoung Shim | 8f1d169 | 2011-04-08 13:22:10 +0900 | [diff] [blame] | 38 | #define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) |
| 39 | #define S5P_USBHOST_PHY_ENABLE (1 << 0) |
| 40 | |
| Kukjin Kim | be7004f | 2011-03-12 10:20:07 +0900 | [diff] [blame] | 41 | #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) |
| 42 | #define S5P_MIPI_DPHY_ENABLE (1 << 0) |
| 43 | #define S5P_MIPI_DPHY_SRESETN (1 << 1) |
| 44 | #define S5P_MIPI_DPHY_MRESETN (1 << 2) |
| 45 | |
| Abhilash Kesavan | 4036021 | 2011-03-15 18:35:24 +0900 | [diff] [blame] | 46 | #define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 47 | #define S5P_INFORM0 S5P_PMUREG(0x0800) |
| 48 | #define S5P_INFORM1 S5P_PMUREG(0x0804) |
| 49 | #define S5P_INFORM2 S5P_PMUREG(0x0808) |
| 50 | #define S5P_INFORM3 S5P_PMUREG(0x080C) |
| 51 | #define S5P_INFORM4 S5P_PMUREG(0x0810) |
| 52 | #define S5P_INFORM5 S5P_PMUREG(0x0814) |
| 53 | #define S5P_INFORM6 S5P_PMUREG(0x0818) |
| 54 | #define S5P_INFORM7 S5P_PMUREG(0x081C) |
| 55 | |
| 56 | #define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) |
| 57 | #define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) |
| 58 | #define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) |
| 59 | #define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) |
| 60 | #define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) |
| 61 | #define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) |
| 62 | #define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) |
| 63 | #define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) |
| 64 | #define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) |
| 65 | #define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) |
| 66 | #define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) |
| 67 | #define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) |
| 68 | #define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) |
| 69 | #define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) |
| 70 | #define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) |
| 71 | #define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) |
| 72 | #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) |
| 73 | #define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) |
| 74 | #define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) |
| 75 | #define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) |
| 76 | #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) |
| 77 | #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) |
| 78 | #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) |
| 79 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) |
| 80 | #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) |
| 81 | #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) |
| 82 | #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) |
| 83 | #define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) |
| 84 | #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) |
| 85 | #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) |
| 86 | #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) |
| 87 | #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) |
| 88 | #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) |
| 89 | #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) |
| 90 | #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) |
| 91 | #define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) |
| 92 | #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) |
| 93 | #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) |
| 94 | #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) |
| 95 | #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) |
| 96 | #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) |
| 97 | #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) |
| 98 | #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) |
| 99 | #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) |
| 100 | #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) |
| 101 | #define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) |
| 102 | #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) |
| 103 | #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) |
| 104 | #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) |
| 105 | #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) |
| 106 | #define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) |
| 107 | #define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) |
| 108 | #define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) |
| 109 | #define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) |
| 110 | #define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) |
| 111 | #define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) |
| 112 | #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) |
| 113 | #define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) |
| 114 | #define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) |
| 115 | #define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) |
| 116 | #define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) |
| 117 | #define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) |
| 118 | #define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) |
| 119 | #define S5P_TV_LOWPWR S5P_PMUREG(0x1384) |
| 120 | #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) |
| 121 | #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) |
| 122 | #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) |
| 123 | #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) |
| 124 | #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) |
| 125 | #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) |
| 126 | #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) |
| 127 | |
| 128 | #define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) |
| 129 | #define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) |
| 130 | #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) |
| 131 | #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) |
| 132 | #define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) |
| 133 | |
| 134 | #define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) |
| 135 | #define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) |
| 136 | #define S5P_CAM_OPTION S5P_PMUREG(0x3C08) |
| 137 | #define S5P_TV_OPTION S5P_PMUREG(0x3C28) |
| 138 | #define S5P_MFC_OPTION S5P_PMUREG(0x3C48) |
| 139 | #define S5P_G3D_OPTION S5P_PMUREG(0x3C68) |
| 140 | #define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) |
| 141 | #define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) |
| 142 | #define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) |
| 143 | #define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) |
| 144 | #define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) |
| 145 | |
| 146 | #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) |
| 147 | #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) |
| 148 | #define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) |
| 149 | #define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) |
| 150 | #define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) |
| 151 | #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) |
| 152 | #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) |
| 153 | |
| 154 | #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) |
| 155 | #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) |
| 156 | #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) |
| 157 | #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) |
| 158 | #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) |
| 159 | #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) |
| 160 | #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) |
| 161 | |
| Abhilash Kesavan | 4036021 | 2011-03-15 18:35:24 +0900 | [diff] [blame] | 162 | #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 |
| JungHi Min | 911c29b | 2011-07-16 13:39:09 +0900 | [diff] [blame] | 163 | #define S5P_CORE_LOCAL_PWR_EN 0x3 |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 164 | #define S5P_INT_LOCAL_PWR_EN 0x7 |
| 165 | |
| 166 | #define S5P_CHECK_SLEEP 0x00000BAD |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 167 | |
| 168 | #endif /* __ASM_ARCH_REGS_PMU_H */ |