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Stephen Warren971dac72012-02-01 14:04:47 -07001/*
2 * Driver for the NVIDIA Tegra pinmux
3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __PINMUX_TEGRA_H__
17#define __PINMUX_TEGRA_H__
18
Stephen Warren3b2f9412012-08-28 14:38:18 -070019enum tegra_pinconf_param {
20 /* argument: tegra_pinconf_pull */
21 TEGRA_PINCONF_PARAM_PULL,
22 /* argument: tegra_pinconf_tristate */
23 TEGRA_PINCONF_PARAM_TRISTATE,
24 /* argument: Boolean */
25 TEGRA_PINCONF_PARAM_ENABLE_INPUT,
26 /* argument: Boolean */
27 TEGRA_PINCONF_PARAM_OPEN_DRAIN,
28 /* argument: Boolean */
29 TEGRA_PINCONF_PARAM_LOCK,
30 /* argument: Boolean */
31 TEGRA_PINCONF_PARAM_IORESET,
32 /* argument: Boolean */
33 TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
34 /* argument: Boolean */
35 TEGRA_PINCONF_PARAM_SCHMITT,
36 /* argument: Boolean */
37 TEGRA_PINCONF_PARAM_LOW_POWER_MODE,
38 /* argument: Integer, range is HW-dependant */
39 TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH,
40 /* argument: Integer, range is HW-dependant */
41 TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH,
42 /* argument: Integer, range is HW-dependant */
43 TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
44 /* argument: Integer, range is HW-dependant */
45 TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
46};
47
48enum tegra_pinconf_pull {
49 TEGRA_PINCONFIG_PULL_NONE,
50 TEGRA_PINCONFIG_PULL_DOWN,
51 TEGRA_PINCONFIG_PULL_UP,
52};
53
54enum tegra_pinconf_tristate {
55 TEGRA_PINCONFIG_DRIVEN,
56 TEGRA_PINCONFIG_TRISTATE,
57};
58
59#define TEGRA_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
60#define TEGRA_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
61#define TEGRA_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
62
Stephen Warren971dac72012-02-01 14:04:47 -070063/**
64 * struct tegra_function - Tegra pinctrl mux function
65 * @name: The name of the function, exported to pinctrl core.
66 * @groups: An array of pin groups that may select this function.
67 * @ngroups: The number of entries in @groups.
68 */
69struct tegra_function {
70 const char *name;
71 const char * const *groups;
72 unsigned ngroups;
73};
74
75/**
76 * struct tegra_pingroup - Tegra pin group
77 * @mux_reg: Mux register offset. -1 if unsupported.
78 * @mux_bank: Mux register bank. 0 if unsupported.
79 * @mux_bit: Mux register bit. 0 if unsupported.
80 * @pupd_reg: Pull-up/down register offset. -1 if unsupported.
81 * @pupd_bank: Pull-up/down register bank. 0 if unsupported.
82 * @pupd_bit: Pull-up/down register bit. 0 if unsupported.
83 * @tri_reg: Tri-state register offset. -1 if unsupported.
84 * @tri_bank: Tri-state register bank. 0 if unsupported.
85 * @tri_bit: Tri-state register bit. 0 if unsupported.
86 * @einput_reg: Enable-input register offset. -1 if unsupported.
87 * @einput_bank: Enable-input register bank. 0 if unsupported.
88 * @einput_bit: Enable-input register bit. 0 if unsupported.
89 * @odrain_reg: Open-drain register offset. -1 if unsupported.
90 * @odrain_bank: Open-drain register bank. 0 if unsupported.
91 * @odrain_bit: Open-drain register bit. 0 if unsupported.
92 * @lock_reg: Lock register offset. -1 if unsupported.
93 * @lock_bank: Lock register bank. 0 if unsupported.
94 * @lock_bit: Lock register bit. 0 if unsupported.
95 * @ioreset_reg: IO reset register offset. -1 if unsupported.
96 * @ioreset_bank: IO reset register bank. 0 if unsupported.
97 * @ioreset_bit: IO reset register bit. 0 if unsupported.
98 * @drv_reg: Drive fields register offset. -1 if unsupported.
99 * This register contains the hsm, schmitt, lpmd, drvdn,
100 * drvup, slwr, and slwf parameters.
101 * @drv_bank: Drive fields register bank. 0 if unsupported.
102 * @hsm_bit: High Speed Mode register bit. 0 if unsupported.
103 * @schmitt_bit: Scmitt register bit. 0 if unsupported.
104 * @lpmd_bit: Low Power Mode register bit. 0 if unsupported.
105 * @drvdn_bit: Drive Down register bit. 0 if unsupported.
106 * @drvdn_width: Drive Down field width. 0 if unsupported.
107 * @drvup_bit: Drive Up register bit. 0 if unsupported.
108 * @drvup_width: Drive Up field width. 0 if unsupported.
109 * @slwr_bit: Slew Rising register bit. 0 if unsupported.
110 * @slwr_width: Slew Rising field width. 0 if unsupported.
111 * @slwf_bit: Slew Falling register bit. 0 if unsupported.
112 * @slwf_width: Slew Falling field width. 0 if unsupported.
113 *
114 * A representation of a group of pins (possibly just one pin) in the Tegra
115 * pin controller. Each group allows some parameter or parameters to be
116 * configured. The most common is mux function selection. Many others exist
117 * such as pull-up/down, tri-state, etc. Tegra's pin controller is complex;
118 * certain groups may only support configuring certain parameters, hence
119 * each parameter is optional, represented by a -1 "reg" value.
120 */
121struct tegra_pingroup {
122 const char *name;
123 const unsigned *pins;
124 unsigned npins;
125 unsigned funcs[4];
126 unsigned func_safe;
127 s16 mux_reg;
128 s16 pupd_reg;
129 s16 tri_reg;
130 s16 einput_reg;
131 s16 odrain_reg;
132 s16 lock_reg;
133 s16 ioreset_reg;
134 s16 drv_reg;
135 u32 mux_bank:2;
136 u32 pupd_bank:2;
137 u32 tri_bank:2;
138 u32 einput_bank:2;
139 u32 odrain_bank:2;
140 u32 ioreset_bank:2;
141 u32 lock_bank:2;
142 u32 drv_bank:2;
143 u32 mux_bit:5;
144 u32 pupd_bit:5;
145 u32 tri_bit:5;
146 u32 einput_bit:5;
147 u32 odrain_bit:5;
148 u32 lock_bit:5;
149 u32 ioreset_bit:5;
150 u32 hsm_bit:5;
151 u32 schmitt_bit:5;
152 u32 lpmd_bit:5;
153 u32 drvdn_bit:5;
154 u32 drvup_bit:5;
155 u32 slwr_bit:5;
156 u32 slwf_bit:5;
157 u32 drvdn_width:6;
158 u32 drvup_width:6;
159 u32 slwr_width:6;
160 u32 slwf_width:6;
161};
162
163/**
164 * struct tegra_pinctrl_soc_data - Tegra pin controller driver configuration
165 * @ngpios: The number of GPIO pins the pin controller HW affects.
166 * @pins: An array describing all pins the pin controller affects.
167 * All pins which are also GPIOs must be listed first within the
168 * array, and be numbered identically to the GPIO controller's
169 * numbering.
170 * @npins: The numbmer of entries in @pins.
171 * @functions: An array describing all mux functions the SoC supports.
172 * @nfunctions: The numbmer of entries in @functions.
173 * @groups: An array describing all pin groups the pin SoC supports.
174 * @ngroups: The numbmer of entries in @groups.
175 */
176struct tegra_pinctrl_soc_data {
177 unsigned ngpios;
178 const struct pinctrl_pin_desc *pins;
179 unsigned npins;
180 const struct tegra_function *functions;
181 unsigned nfunctions;
182 const struct tegra_pingroup *groups;
183 unsigned ngroups;
184};
185
Stephen Warren52f48fe2012-04-11 12:53:09 -0600186int tegra_pinctrl_probe(struct platform_device *pdev,
187 const struct tegra_pinctrl_soc_data *soc_data);
188int tegra_pinctrl_remove(struct platform_device *pdev);
Stephen Warren971dac72012-02-01 14:04:47 -0700189
190#endif