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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
2 * pbm.h: UltraSparc PCI controller software state.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 */
6
7#ifndef __SPARC64_PBM_H
8#define __SPARC64_PBM_H
9
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/ioport.h>
13#include <linux/spinlock.h>
14
15#include <asm/io.h>
16#include <asm/page.h>
17#include <asm/oplib.h>
David S. Miller7c963ad2005-05-31 16:57:59 -070018#include <asm/iommu.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
20/* The abstraction used here is that there are PCI controllers,
21 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
22 * underneath. Each PCI bus module uses an IOMMU (shared by both
23 * PBMs of a controller, or per-PBM), and if a streaming buffer
24 * is present, each PCI bus module has it's own. (ie. the IOMMU
25 * might be shared between PBMs, the STC is never shared)
26 * Furthermore, each PCI bus module controls it's own autonomous
27 * PCI bus.
28 */
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030struct pci_controller_info;
31
32/* This contains the software state necessary to drive a PCI
33 * controller's IOMMU.
34 */
David S. Miller688cb302005-10-13 22:15:24 -070035struct pci_iommu_arena {
36 unsigned long *map;
37 unsigned int hint;
38 unsigned int limit;
39};
40
Linus Torvalds1da177e2005-04-16 15:20:36 -070041struct pci_iommu {
42 /* This protects the controller's IOMMU and all
43 * streaming buffers underneath.
44 */
45 spinlock_t lock;
46
David S. Miller688cb302005-10-13 22:15:24 -070047 struct pci_iommu_arena arena;
48
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 /* IOMMU page table, a linear array of ioptes. */
50 iopte_t *page_table; /* The page table itself. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
52 /* Base PCI memory space address where IOMMU mappings
53 * begin.
54 */
55 u32 page_table_map_base;
56
57 /* IOMMU Controller Registers */
58 unsigned long iommu_control; /* IOMMU control register */
59 unsigned long iommu_tsbbase; /* IOMMU page table base register */
60 unsigned long iommu_flush; /* IOMMU page flush register */
61 unsigned long iommu_ctxflush; /* IOMMU context flush register */
62
63 /* This is a register in the PCI controller, which if
64 * read will have no side-effects but will guarantee
65 * completion of all previous writes into IOMMU/STC.
66 */
67 unsigned long write_complete_reg;
68
Linus Torvalds1da177e2005-04-16 15:20:36 -070069 /* In order to deal with some buggy third-party PCI bridges that
70 * do wrong prefetching, we never mark valid mappings as invalid.
71 * Instead we point them at this dummy page.
72 */
73 unsigned long dummy_page;
74 unsigned long dummy_page_pa;
75
David S. Miller7c963ad2005-05-31 16:57:59 -070076 /* CTX allocation. */
77 unsigned long ctx_lowest_free;
78 unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
79
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 /* Here a PCI controller driver describes the areas of
81 * PCI memory space where DMA to/from physical memory
82 * are addressed. Drivers interrogate the PCI layer
83 * if their device has addressing limitations. They
84 * do so via pci_dma_supported, and pass in a mask of
85 * DMA address bits their device can actually drive.
86 *
87 * The test for being usable is:
88 * (device_mask & dma_addr_mask) == dma_addr_mask
89 */
90 u32 dma_addr_mask;
91};
92
David S. Miller51e85132005-10-13 21:10:08 -070093extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
95/* This describes a PCI bus module's streaming buffer. */
96struct pci_strbuf {
97 int strbuf_enabled; /* Present and using it? */
98
99 /* Streaming Buffer Control Registers */
100 unsigned long strbuf_control; /* STC control register */
101 unsigned long strbuf_pflush; /* STC page flush register */
102 unsigned long strbuf_fsync; /* STC flush synchronization reg */
103 unsigned long strbuf_ctxflush; /* STC context flush register */
104 unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */
105 unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */
106 volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
107
108 /* And this is the actual flush flag area.
109 * We allocate extra because the chips require
110 * a 64-byte aligned area.
111 */
112 volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
113};
114
115#define PCI_STC_FLUSHFLAG_INIT(STC) \
116 (*((STC)->strbuf_flushflag) = 0UL)
117#define PCI_STC_FLUSHFLAG_SET(STC) \
118 (*((STC)->strbuf_flushflag) != 0UL)
119
120/* There can be quite a few ranges and interrupt maps on a PCI
121 * segment. Thus...
122 */
123#define PROM_PCIRNG_MAX 64
124#define PROM_PCIIMAP_MAX 64
125
126struct pci_pbm_info {
127 /* PCI controller we sit under. */
128 struct pci_controller_info *parent;
129
130 /* Physical address base of controller registers. */
131 unsigned long controller_regs;
132
133 /* Physical address base of PBM registers. */
134 unsigned long pbm_regs;
135
David S. Millerbb6743f42005-07-04 13:26:04 -0700136 /* Physical address of DMA sync register, if any. */
137 unsigned long sync_reg;
138
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 /* Opaque 32-bit system bus Port ID. */
140 u32 portid;
141
142 /* Chipset version information. */
143 int chip_type;
144#define PBM_CHIP_TYPE_SABRE 1
145#define PBM_CHIP_TYPE_PSYCHO 2
146#define PBM_CHIP_TYPE_SCHIZO 3
147#define PBM_CHIP_TYPE_SCHIZO_PLUS 4
148#define PBM_CHIP_TYPE_TOMATILLO 5
149 int chip_version;
150 int chip_revision;
151
152 /* Name used for top-level resources. */
153 char name[64];
154
155 /* OBP specific information. */
156 int prom_node;
157 char prom_name[64];
158 struct linux_prom_pci_ranges pbm_ranges[PROM_PCIRNG_MAX];
159 int num_pbm_ranges;
160 struct linux_prom_pci_intmap pbm_intmap[PROM_PCIIMAP_MAX];
161 int num_pbm_intmap;
162 struct linux_prom_pci_intmask pbm_intmask;
163 u64 ino_bitmap;
164
165 /* PBM I/O and Memory space resources. */
166 struct resource io_space;
167 struct resource mem_space;
168
169 /* Base of PCI Config space, can be per-PBM or shared. */
170 unsigned long config_space;
171
172 /* State of 66MHz capabilities on this PBM. */
173 int is_66mhz_capable;
174 int all_devs_66mhz;
175
176 /* This PBM's streaming buffer. */
177 struct pci_strbuf stc;
178
179 /* IOMMU state, potentially shared by both PBM segments. */
180 struct pci_iommu *iommu;
181
182 /* PCI slot mapping. */
183 unsigned int pci_first_slot;
184
185 /* Now things for the actual PCI bus probes. */
186 unsigned int pci_first_busno;
187 unsigned int pci_last_busno;
188 struct pci_bus *pci_bus;
189};
190
191struct pci_controller_info {
192 /* List of all PCI controllers. */
193 struct pci_controller_info *next;
194
195 /* Each controller gets a unique index, used mostly for
196 * error logging purposes.
197 */
198 int index;
199
200 /* Do the PBMs both exist in the same PCI domain? */
201 int pbms_same_domain;
202
203 /* The PCI bus modules controlled by us. */
204 struct pci_pbm_info pbm_A;
205 struct pci_pbm_info pbm_B;
206
207 /* Operations which are controller specific. */
208 void (*scan_bus)(struct pci_controller_info *);
209 unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
210 void (*base_address_update)(struct pci_dev *, int);
211 void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
212
213 /* Now things for the actual PCI bus probes. */
214 struct pci_ops *pci_ops;
215 unsigned int pci_first_busno;
216 unsigned int pci_last_busno;
217
218 void *starfire_cookie;
219};
220
221/* PCI devices which are not bridges have this placed in their pci_dev
222 * sysdata member. This makes OBP aware PCI device drivers easier to
223 * code.
224 */
225struct pcidev_cookie {
226 struct pci_pbm_info *pbm;
227 char prom_name[64];
228 int prom_node;
229 struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
230 int num_prom_regs;
231 struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
232 int num_prom_assignments;
233};
234
235/* Currently these are the same across all PCI controllers
236 * we support. Someday they may not be...
237 */
238#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */
239#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */
240
241#endif /* !(__SPARC64_PBM_H) */