Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Driver for high-speed SCC boards (those with DMA support) |
| 3 | * Copyright (C) 1997-2000 Klaus Kudielka |
| 4 | * |
| 5 | * S5SCC/DMA support by Janko Koleznik S52HI |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 20 | */ |
| 21 | |
| 22 | |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <linux/if_arp.h> |
| 27 | #include <linux/in.h> |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/ioport.h> |
| 31 | #include <linux/kernel.h> |
| 32 | #include <linux/mm.h> |
| 33 | #include <linux/netdevice.h> |
| 34 | #include <linux/rtnetlink.h> |
| 35 | #include <linux/sockios.h> |
| 36 | #include <linux/workqueue.h> |
| 37 | #include <asm/atomic.h> |
| 38 | #include <asm/bitops.h> |
| 39 | #include <asm/dma.h> |
| 40 | #include <asm/io.h> |
| 41 | #include <asm/irq.h> |
| 42 | #include <asm/uaccess.h> |
| 43 | #include <net/ax25.h> |
| 44 | #include "z8530.h" |
| 45 | |
| 46 | |
| 47 | /* Number of buffers per channel */ |
| 48 | |
| 49 | #define NUM_TX_BUF 2 /* NUM_TX_BUF >= 1 (min. 2 recommended) */ |
| 50 | #define NUM_RX_BUF 6 /* NUM_RX_BUF >= 1 (min. 2 recommended) */ |
| 51 | #define BUF_SIZE 1576 /* BUF_SIZE >= mtu + hard_header_len */ |
| 52 | |
| 53 | |
| 54 | /* Cards supported */ |
| 55 | |
| 56 | #define HW_PI { "Ottawa PI", 0x300, 0x20, 0x10, 8, \ |
| 57 | 0, 8, 1843200, 3686400 } |
| 58 | #define HW_PI2 { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \ |
| 59 | 0, 8, 3686400, 7372800 } |
| 60 | #define HW_TWIN { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \ |
| 61 | 0, 4, 6144000, 6144000 } |
| 62 | #define HW_S5 { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \ |
| 63 | 0, 8, 4915200, 9830400 } |
| 64 | |
| 65 | #define HARDWARE { HW_PI, HW_PI2, HW_TWIN, HW_S5 } |
| 66 | |
| 67 | #define TMR_0_HZ 25600 /* Frequency of timer 0 */ |
| 68 | |
| 69 | #define TYPE_PI 0 |
| 70 | #define TYPE_PI2 1 |
| 71 | #define TYPE_TWIN 2 |
| 72 | #define TYPE_S5 3 |
| 73 | #define NUM_TYPES 4 |
| 74 | |
| 75 | #define MAX_NUM_DEVS 32 |
| 76 | |
| 77 | |
| 78 | /* SCC chips supported */ |
| 79 | |
| 80 | #define Z8530 0 |
| 81 | #define Z85C30 1 |
| 82 | #define Z85230 2 |
| 83 | |
| 84 | #define CHIPNAMES { "Z8530", "Z85C30", "Z85230" } |
| 85 | |
| 86 | |
| 87 | /* I/O registers */ |
| 88 | |
| 89 | /* 8530 registers relative to card base */ |
| 90 | #define SCCB_CMD 0x00 |
| 91 | #define SCCB_DATA 0x01 |
| 92 | #define SCCA_CMD 0x02 |
| 93 | #define SCCA_DATA 0x03 |
| 94 | |
| 95 | /* 8253/8254 registers relative to card base */ |
| 96 | #define TMR_CNT0 0x00 |
| 97 | #define TMR_CNT1 0x01 |
| 98 | #define TMR_CNT2 0x02 |
| 99 | #define TMR_CTRL 0x03 |
| 100 | |
| 101 | /* Additional PI/PI2 registers relative to card base */ |
| 102 | #define PI_DREQ_MASK 0x04 |
| 103 | |
| 104 | /* Additional PackeTwin registers relative to card base */ |
| 105 | #define TWIN_INT_REG 0x08 |
| 106 | #define TWIN_CLR_TMR1 0x09 |
| 107 | #define TWIN_CLR_TMR2 0x0a |
| 108 | #define TWIN_SPARE_1 0x0b |
| 109 | #define TWIN_DMA_CFG 0x08 |
| 110 | #define TWIN_SERIAL_CFG 0x09 |
| 111 | #define TWIN_DMA_CLR_FF 0x0a |
| 112 | #define TWIN_SPARE_2 0x0b |
| 113 | |
| 114 | |
| 115 | /* PackeTwin I/O register values */ |
| 116 | |
| 117 | /* INT_REG */ |
| 118 | #define TWIN_SCC_MSK 0x01 |
| 119 | #define TWIN_TMR1_MSK 0x02 |
| 120 | #define TWIN_TMR2_MSK 0x04 |
| 121 | #define TWIN_INT_MSK 0x07 |
| 122 | |
| 123 | /* SERIAL_CFG */ |
| 124 | #define TWIN_DTRA_ON 0x01 |
| 125 | #define TWIN_DTRB_ON 0x02 |
| 126 | #define TWIN_EXTCLKA 0x04 |
| 127 | #define TWIN_EXTCLKB 0x08 |
| 128 | #define TWIN_LOOPA_ON 0x10 |
| 129 | #define TWIN_LOOPB_ON 0x20 |
| 130 | #define TWIN_EI 0x80 |
| 131 | |
| 132 | /* DMA_CFG */ |
| 133 | #define TWIN_DMA_HDX_T1 0x08 |
| 134 | #define TWIN_DMA_HDX_R1 0x0a |
| 135 | #define TWIN_DMA_HDX_T3 0x14 |
| 136 | #define TWIN_DMA_HDX_R3 0x16 |
| 137 | #define TWIN_DMA_FDX_T3R1 0x1b |
| 138 | #define TWIN_DMA_FDX_T1R3 0x1d |
| 139 | |
| 140 | |
| 141 | /* Status values */ |
| 142 | |
| 143 | #define IDLE 0 |
| 144 | #define TX_HEAD 1 |
| 145 | #define TX_DATA 2 |
| 146 | #define TX_PAUSE 3 |
| 147 | #define TX_TAIL 4 |
| 148 | #define RTS_OFF 5 |
| 149 | #define WAIT 6 |
| 150 | #define DCD_ON 7 |
| 151 | #define RX_ON 8 |
| 152 | #define DCD_OFF 9 |
| 153 | |
| 154 | |
| 155 | /* Ioctls */ |
| 156 | |
| 157 | #define SIOCGSCCPARAM SIOCDEVPRIVATE |
| 158 | #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1) |
| 159 | |
| 160 | |
| 161 | /* Data types */ |
| 162 | |
| 163 | struct scc_param { |
| 164 | int pclk_hz; /* frequency of BRG input (don't change) */ |
| 165 | int brg_tc; /* BRG terminal count; BRG disabled if < 0 */ |
| 166 | int nrzi; /* 0 (nrz), 1 (nrzi) */ |
| 167 | int clocks; /* see dmascc_cfg documentation */ |
| 168 | int txdelay; /* [1/TMR_0_HZ] */ |
| 169 | int txtimeout; /* [1/HZ] */ |
| 170 | int txtail; /* [1/TMR_0_HZ] */ |
| 171 | int waittime; /* [1/TMR_0_HZ] */ |
| 172 | int slottime; /* [1/TMR_0_HZ] */ |
| 173 | int persist; /* 1 ... 256 */ |
| 174 | int dma; /* -1 (disable), 0, 1, 3 */ |
| 175 | int txpause; /* [1/TMR_0_HZ] */ |
| 176 | int rtsoff; /* [1/TMR_0_HZ] */ |
| 177 | int dcdon; /* [1/TMR_0_HZ] */ |
| 178 | int dcdoff; /* [1/TMR_0_HZ] */ |
| 179 | }; |
| 180 | |
| 181 | struct scc_hardware { |
| 182 | char *name; |
| 183 | int io_region; |
| 184 | int io_delta; |
| 185 | int io_size; |
| 186 | int num_devs; |
| 187 | int scc_offset; |
| 188 | int tmr_offset; |
| 189 | int tmr_hz; |
| 190 | int pclk_hz; |
| 191 | }; |
| 192 | |
| 193 | struct scc_priv { |
| 194 | int type; |
| 195 | int chip; |
| 196 | struct net_device *dev; |
| 197 | struct scc_info *info; |
| 198 | struct net_device_stats stats; |
| 199 | int channel; |
| 200 | int card_base, scc_cmd, scc_data; |
| 201 | int tmr_cnt, tmr_ctrl, tmr_mode; |
| 202 | struct scc_param param; |
| 203 | char rx_buf[NUM_RX_BUF][BUF_SIZE]; |
| 204 | int rx_len[NUM_RX_BUF]; |
| 205 | int rx_ptr; |
| 206 | struct work_struct rx_work; |
| 207 | int rx_head, rx_tail, rx_count; |
| 208 | int rx_over; |
| 209 | char tx_buf[NUM_TX_BUF][BUF_SIZE]; |
| 210 | int tx_len[NUM_TX_BUF]; |
| 211 | int tx_ptr; |
| 212 | int tx_head, tx_tail, tx_count; |
| 213 | int state; |
| 214 | unsigned long tx_start; |
| 215 | int rr0; |
| 216 | spinlock_t *register_lock; /* Per scc_info */ |
| 217 | spinlock_t ring_lock; |
| 218 | }; |
| 219 | |
| 220 | struct scc_info { |
| 221 | int irq_used; |
| 222 | int twin_serial_cfg; |
| 223 | struct net_device *dev[2]; |
| 224 | struct scc_priv priv[2]; |
| 225 | struct scc_info *next; |
| 226 | spinlock_t register_lock; /* Per device register lock */ |
| 227 | }; |
| 228 | |
| 229 | |
| 230 | /* Function declarations */ |
| 231 | static int setup_adapter(int card_base, int type, int n) __init; |
| 232 | |
| 233 | static void write_scc(struct scc_priv *priv, int reg, int val); |
| 234 | static void write_scc_data(struct scc_priv *priv, int val, int fast); |
| 235 | static int read_scc(struct scc_priv *priv, int reg); |
| 236 | static int read_scc_data(struct scc_priv *priv); |
| 237 | |
| 238 | static int scc_open(struct net_device *dev); |
| 239 | static int scc_close(struct net_device *dev); |
| 240 | static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); |
| 241 | static int scc_send_packet(struct sk_buff *skb, struct net_device *dev); |
| 242 | static struct net_device_stats *scc_get_stats(struct net_device *dev); |
| 243 | static int scc_set_mac_address(struct net_device *dev, void *sa); |
| 244 | |
| 245 | static inline void tx_on(struct scc_priv *priv); |
| 246 | static inline void rx_on(struct scc_priv *priv); |
| 247 | static inline void rx_off(struct scc_priv *priv); |
| 248 | static void start_timer(struct scc_priv *priv, int t, int r15); |
| 249 | static inline unsigned char random(void); |
| 250 | |
| 251 | static inline void z8530_isr(struct scc_info *info); |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 252 | static irqreturn_t scc_isr(int irq, void *dev_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | static void rx_isr(struct scc_priv *priv); |
| 254 | static void special_condition(struct scc_priv *priv, int rc); |
Al Viro | 7a87b6c | 2006-12-06 18:51:40 +0000 | [diff] [blame^] | 255 | static void rx_bh(struct work_struct *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | static void tx_isr(struct scc_priv *priv); |
| 257 | static void es_isr(struct scc_priv *priv); |
| 258 | static void tm_isr(struct scc_priv *priv); |
| 259 | |
| 260 | |
| 261 | /* Initialization variables */ |
| 262 | |
| 263 | static int io[MAX_NUM_DEVS] __initdata = { 0, }; |
| 264 | |
| 265 | /* Beware! hw[] is also used in cleanup_module(). */ |
| 266 | static struct scc_hardware hw[NUM_TYPES] __initdata_or_module = HARDWARE; |
| 267 | static char ax25_broadcast[7] __initdata = |
| 268 | { 'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, |
| 269 | '0' << 1 }; |
| 270 | static char ax25_test[7] __initdata = |
| 271 | { 'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, |
| 272 | '1' << 1 }; |
| 273 | |
| 274 | |
| 275 | /* Global variables */ |
| 276 | |
| 277 | static struct scc_info *first; |
| 278 | static unsigned long rand; |
| 279 | |
| 280 | |
| 281 | MODULE_AUTHOR("Klaus Kudielka"); |
| 282 | MODULE_DESCRIPTION("Driver for high-speed SCC boards"); |
Rusty Russell | 8d3b33f | 2006-03-25 03:07:05 -0800 | [diff] [blame] | 283 | module_param_array(io, int, NULL, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | MODULE_LICENSE("GPL"); |
| 285 | |
| 286 | static void __exit dmascc_exit(void) |
| 287 | { |
| 288 | int i; |
| 289 | struct scc_info *info; |
| 290 | |
| 291 | while (first) { |
| 292 | info = first; |
| 293 | |
| 294 | /* Unregister devices */ |
| 295 | for (i = 0; i < 2; i++) |
| 296 | unregister_netdev(info->dev[i]); |
| 297 | |
| 298 | /* Reset board */ |
| 299 | if (info->priv[0].type == TYPE_TWIN) |
| 300 | outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG); |
| 301 | write_scc(&info->priv[0], R9, FHWRES); |
| 302 | release_region(info->dev[0]->base_addr, |
| 303 | hw[info->priv[0].type].io_size); |
| 304 | |
| 305 | for (i = 0; i < 2; i++) |
| 306 | free_netdev(info->dev[i]); |
| 307 | |
| 308 | /* Free memory */ |
| 309 | first = info->next; |
| 310 | kfree(info); |
| 311 | } |
| 312 | } |
| 313 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 314 | static int __init dmascc_init(void) |
| 315 | { |
| 316 | int h, i, j, n; |
| 317 | int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS], |
| 318 | t1[MAX_NUM_DEVS]; |
| 319 | unsigned t_val; |
| 320 | unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS], |
| 321 | counting[MAX_NUM_DEVS]; |
| 322 | |
| 323 | /* Initialize random number generator */ |
| 324 | rand = jiffies; |
| 325 | /* Cards found = 0 */ |
| 326 | n = 0; |
| 327 | /* Warning message */ |
| 328 | if (!io[0]) |
| 329 | printk(KERN_INFO "dmascc: autoprobing (dangerous)\n"); |
| 330 | |
| 331 | /* Run autodetection for each card type */ |
| 332 | for (h = 0; h < NUM_TYPES; h++) { |
| 333 | |
| 334 | if (io[0]) { |
| 335 | /* User-specified I/O address regions */ |
| 336 | for (i = 0; i < hw[h].num_devs; i++) |
| 337 | base[i] = 0; |
| 338 | for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) { |
| 339 | j = (io[i] - |
| 340 | hw[h].io_region) / hw[h].io_delta; |
| 341 | if (j >= 0 && j < hw[h].num_devs |
| 342 | && hw[h].io_region + |
| 343 | j * hw[h].io_delta == io[i]) { |
| 344 | base[j] = io[i]; |
| 345 | } |
| 346 | } |
| 347 | } else { |
| 348 | /* Default I/O address regions */ |
| 349 | for (i = 0; i < hw[h].num_devs; i++) { |
| 350 | base[i] = |
| 351 | hw[h].io_region + i * hw[h].io_delta; |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | /* Check valid I/O address regions */ |
| 356 | for (i = 0; i < hw[h].num_devs; i++) |
| 357 | if (base[i]) { |
| 358 | if (!request_region |
| 359 | (base[i], hw[h].io_size, "dmascc")) |
| 360 | base[i] = 0; |
| 361 | else { |
| 362 | tcmd[i] = |
| 363 | base[i] + hw[h].tmr_offset + |
| 364 | TMR_CTRL; |
| 365 | t0[i] = |
| 366 | base[i] + hw[h].tmr_offset + |
| 367 | TMR_CNT0; |
| 368 | t1[i] = |
| 369 | base[i] + hw[h].tmr_offset + |
| 370 | TMR_CNT1; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | /* Start timers */ |
| 375 | for (i = 0; i < hw[h].num_devs; i++) |
| 376 | if (base[i]) { |
| 377 | /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */ |
| 378 | outb(0x36, tcmd[i]); |
| 379 | outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF, |
| 380 | t0[i]); |
| 381 | outb((hw[h].tmr_hz / TMR_0_HZ) >> 8, |
| 382 | t0[i]); |
| 383 | /* Timer 1: LSB+MSB, Mode 0, HZ/10 */ |
| 384 | outb(0x70, tcmd[i]); |
| 385 | outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]); |
| 386 | outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]); |
| 387 | start[i] = jiffies; |
| 388 | delay[i] = 0; |
| 389 | counting[i] = 1; |
| 390 | /* Timer 2: LSB+MSB, Mode 0 */ |
| 391 | outb(0xb0, tcmd[i]); |
| 392 | } |
| 393 | time = jiffies; |
| 394 | /* Wait until counter registers are loaded */ |
| 395 | udelay(2000000 / TMR_0_HZ); |
| 396 | |
| 397 | /* Timing loop */ |
| 398 | while (jiffies - time < 13) { |
| 399 | for (i = 0; i < hw[h].num_devs; i++) |
| 400 | if (base[i] && counting[i]) { |
| 401 | /* Read back Timer 1: latch; read LSB; read MSB */ |
| 402 | outb(0x40, tcmd[i]); |
| 403 | t_val = |
| 404 | inb(t1[i]) + (inb(t1[i]) << 8); |
| 405 | /* Also check whether counter did wrap */ |
| 406 | if (t_val == 0 |
| 407 | || t_val > TMR_0_HZ / HZ * 10) |
| 408 | counting[i] = 0; |
| 409 | delay[i] = jiffies - start[i]; |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /* Evaluate measurements */ |
| 414 | for (i = 0; i < hw[h].num_devs; i++) |
| 415 | if (base[i]) { |
| 416 | if ((delay[i] >= 9 && delay[i] <= 11) && |
| 417 | /* Ok, we have found an adapter */ |
| 418 | (setup_adapter(base[i], h, n) == 0)) |
| 419 | n++; |
| 420 | else |
| 421 | release_region(base[i], |
| 422 | hw[h].io_size); |
| 423 | } |
| 424 | |
| 425 | } /* NUM_TYPES */ |
| 426 | |
| 427 | /* If any adapter was successfully initialized, return ok */ |
| 428 | if (n) |
| 429 | return 0; |
| 430 | |
| 431 | /* If no adapter found, return error */ |
| 432 | printk(KERN_INFO "dmascc: no adapters found\n"); |
| 433 | return -EIO; |
| 434 | } |
| 435 | |
| 436 | module_init(dmascc_init); |
| 437 | module_exit(dmascc_exit); |
| 438 | |
Adrian Bunk | e2fdbc0 | 2006-06-26 12:31:46 +0200 | [diff] [blame] | 439 | static void __init dev_setup(struct net_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 440 | { |
| 441 | dev->type = ARPHRD_AX25; |
Ralf Baechle | c4bc7ee | 2005-09-12 14:19:26 -0700 | [diff] [blame] | 442 | dev->hard_header_len = AX25_MAX_HEADER_LEN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | dev->mtu = 1500; |
Ralf Baechle | c4bc7ee | 2005-09-12 14:19:26 -0700 | [diff] [blame] | 444 | dev->addr_len = AX25_ADDR_LEN; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | dev->tx_queue_len = 64; |
Ralf Baechle | c4bc7ee | 2005-09-12 14:19:26 -0700 | [diff] [blame] | 446 | memcpy(dev->broadcast, ax25_broadcast, AX25_ADDR_LEN); |
| 447 | memcpy(dev->dev_addr, ax25_test, AX25_ADDR_LEN); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | static int __init setup_adapter(int card_base, int type, int n) |
| 451 | { |
| 452 | int i, irq, chip; |
| 453 | struct scc_info *info; |
| 454 | struct net_device *dev; |
| 455 | struct scc_priv *priv; |
| 456 | unsigned long time; |
| 457 | unsigned int irqs; |
| 458 | int tmr_base = card_base + hw[type].tmr_offset; |
| 459 | int scc_base = card_base + hw[type].scc_offset; |
| 460 | char *chipnames[] = CHIPNAMES; |
| 461 | |
| 462 | /* Allocate memory */ |
| 463 | info = kmalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA); |
| 464 | if (!info) { |
| 465 | printk(KERN_ERR "dmascc: " |
| 466 | "could not allocate memory for %s at %#3x\n", |
| 467 | hw[type].name, card_base); |
| 468 | goto out; |
| 469 | } |
| 470 | |
| 471 | /* Initialize what is necessary for write_scc and write_scc_data */ |
| 472 | memset(info, 0, sizeof(struct scc_info)); |
| 473 | |
| 474 | info->dev[0] = alloc_netdev(0, "", dev_setup); |
| 475 | if (!info->dev[0]) { |
| 476 | printk(KERN_ERR "dmascc: " |
| 477 | "could not allocate memory for %s at %#3x\n", |
| 478 | hw[type].name, card_base); |
| 479 | goto out1; |
| 480 | } |
| 481 | |
| 482 | info->dev[1] = alloc_netdev(0, "", dev_setup); |
| 483 | if (!info->dev[1]) { |
| 484 | printk(KERN_ERR "dmascc: " |
| 485 | "could not allocate memory for %s at %#3x\n", |
| 486 | hw[type].name, card_base); |
| 487 | goto out2; |
| 488 | } |
| 489 | spin_lock_init(&info->register_lock); |
| 490 | |
| 491 | priv = &info->priv[0]; |
| 492 | priv->type = type; |
| 493 | priv->card_base = card_base; |
| 494 | priv->scc_cmd = scc_base + SCCA_CMD; |
| 495 | priv->scc_data = scc_base + SCCA_DATA; |
| 496 | priv->register_lock = &info->register_lock; |
| 497 | |
| 498 | /* Reset SCC */ |
| 499 | write_scc(priv, R9, FHWRES | MIE | NV); |
| 500 | |
| 501 | /* Determine type of chip by enabling SDLC/HDLC enhancements */ |
| 502 | write_scc(priv, R15, SHDLCE); |
| 503 | if (!read_scc(priv, R15)) { |
| 504 | /* WR7' not present. This is an ordinary Z8530 SCC. */ |
| 505 | chip = Z8530; |
| 506 | } else { |
| 507 | /* Put one character in TX FIFO */ |
| 508 | write_scc_data(priv, 0, 0); |
| 509 | if (read_scc(priv, R0) & Tx_BUF_EMP) { |
| 510 | /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */ |
| 511 | chip = Z85230; |
| 512 | } else { |
| 513 | /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */ |
| 514 | chip = Z85C30; |
| 515 | } |
| 516 | } |
| 517 | write_scc(priv, R15, 0); |
| 518 | |
| 519 | /* Start IRQ auto-detection */ |
| 520 | irqs = probe_irq_on(); |
| 521 | |
| 522 | /* Enable interrupts */ |
| 523 | if (type == TYPE_TWIN) { |
| 524 | outb(0, card_base + TWIN_DMA_CFG); |
| 525 | inb(card_base + TWIN_CLR_TMR1); |
| 526 | inb(card_base + TWIN_CLR_TMR2); |
| 527 | info->twin_serial_cfg = TWIN_EI; |
| 528 | outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG); |
| 529 | } else { |
| 530 | write_scc(priv, R15, CTSIE); |
| 531 | write_scc(priv, R0, RES_EXT_INT); |
| 532 | write_scc(priv, R1, EXT_INT_ENAB); |
| 533 | } |
| 534 | |
| 535 | /* Start timer */ |
| 536 | outb(1, tmr_base + TMR_CNT1); |
| 537 | outb(0, tmr_base + TMR_CNT1); |
| 538 | |
| 539 | /* Wait and detect IRQ */ |
| 540 | time = jiffies; |
| 541 | while (jiffies - time < 2 + HZ / TMR_0_HZ); |
| 542 | irq = probe_irq_off(irqs); |
| 543 | |
| 544 | /* Clear pending interrupt, disable interrupts */ |
| 545 | if (type == TYPE_TWIN) { |
| 546 | inb(card_base + TWIN_CLR_TMR1); |
| 547 | } else { |
| 548 | write_scc(priv, R1, 0); |
| 549 | write_scc(priv, R15, 0); |
| 550 | write_scc(priv, R0, RES_EXT_INT); |
| 551 | } |
| 552 | |
| 553 | if (irq <= 0) { |
| 554 | printk(KERN_ERR |
| 555 | "dmascc: could not find irq of %s at %#3x (irq=%d)\n", |
| 556 | hw[type].name, card_base, irq); |
| 557 | goto out3; |
| 558 | } |
| 559 | |
| 560 | /* Set up data structures */ |
| 561 | for (i = 0; i < 2; i++) { |
| 562 | dev = info->dev[i]; |
| 563 | priv = &info->priv[i]; |
| 564 | priv->type = type; |
| 565 | priv->chip = chip; |
| 566 | priv->dev = dev; |
| 567 | priv->info = info; |
| 568 | priv->channel = i; |
| 569 | spin_lock_init(&priv->ring_lock); |
| 570 | priv->register_lock = &info->register_lock; |
| 571 | priv->card_base = card_base; |
| 572 | priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD); |
| 573 | priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA); |
| 574 | priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1); |
| 575 | priv->tmr_ctrl = tmr_base + TMR_CTRL; |
| 576 | priv->tmr_mode = i ? 0xb0 : 0x70; |
| 577 | priv->param.pclk_hz = hw[type].pclk_hz; |
| 578 | priv->param.brg_tc = -1; |
| 579 | priv->param.clocks = TCTRxCP | RCRTxCP; |
| 580 | priv->param.persist = 256; |
| 581 | priv->param.dma = -1; |
Al Viro | 7a87b6c | 2006-12-06 18:51:40 +0000 | [diff] [blame^] | 582 | INIT_WORK(&priv->rx_work, rx_bh); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | dev->priv = priv; |
| 584 | sprintf(dev->name, "dmascc%i", 2 * n + i); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | dev->base_addr = card_base; |
| 586 | dev->irq = irq; |
| 587 | dev->open = scc_open; |
| 588 | dev->stop = scc_close; |
| 589 | dev->do_ioctl = scc_ioctl; |
| 590 | dev->hard_start_xmit = scc_send_packet; |
| 591 | dev->get_stats = scc_get_stats; |
Ralf Baechle | 6f74998 | 2005-09-12 14:21:01 -0700 | [diff] [blame] | 592 | dev->hard_header = ax25_hard_header; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 593 | dev->rebuild_header = ax25_rebuild_header; |
| 594 | dev->set_mac_address = scc_set_mac_address; |
| 595 | } |
| 596 | if (register_netdev(info->dev[0])) { |
| 597 | printk(KERN_ERR "dmascc: could not register %s\n", |
| 598 | info->dev[0]->name); |
| 599 | goto out3; |
| 600 | } |
| 601 | if (register_netdev(info->dev[1])) { |
| 602 | printk(KERN_ERR "dmascc: could not register %s\n", |
| 603 | info->dev[1]->name); |
| 604 | goto out4; |
| 605 | } |
| 606 | |
| 607 | |
| 608 | info->next = first; |
| 609 | first = info; |
| 610 | printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n", |
| 611 | hw[type].name, chipnames[chip], card_base, irq); |
| 612 | return 0; |
| 613 | |
| 614 | out4: |
| 615 | unregister_netdev(info->dev[0]); |
| 616 | out3: |
| 617 | if (info->priv[0].type == TYPE_TWIN) |
| 618 | outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG); |
| 619 | write_scc(&info->priv[0], R9, FHWRES); |
| 620 | free_netdev(info->dev[1]); |
| 621 | out2: |
| 622 | free_netdev(info->dev[0]); |
| 623 | out1: |
| 624 | kfree(info); |
| 625 | out: |
| 626 | return -1; |
| 627 | } |
| 628 | |
| 629 | |
| 630 | /* Driver functions */ |
| 631 | |
| 632 | static void write_scc(struct scc_priv *priv, int reg, int val) |
| 633 | { |
| 634 | unsigned long flags; |
| 635 | switch (priv->type) { |
| 636 | case TYPE_S5: |
| 637 | if (reg) |
| 638 | outb(reg, priv->scc_cmd); |
| 639 | outb(val, priv->scc_cmd); |
| 640 | return; |
| 641 | case TYPE_TWIN: |
| 642 | if (reg) |
| 643 | outb_p(reg, priv->scc_cmd); |
| 644 | outb_p(val, priv->scc_cmd); |
| 645 | return; |
| 646 | default: |
| 647 | spin_lock_irqsave(priv->register_lock, flags); |
| 648 | outb_p(0, priv->card_base + PI_DREQ_MASK); |
| 649 | if (reg) |
| 650 | outb_p(reg, priv->scc_cmd); |
| 651 | outb_p(val, priv->scc_cmd); |
| 652 | outb(1, priv->card_base + PI_DREQ_MASK); |
| 653 | spin_unlock_irqrestore(priv->register_lock, flags); |
| 654 | return; |
| 655 | } |
| 656 | } |
| 657 | |
| 658 | |
| 659 | static void write_scc_data(struct scc_priv *priv, int val, int fast) |
| 660 | { |
| 661 | unsigned long flags; |
| 662 | switch (priv->type) { |
| 663 | case TYPE_S5: |
| 664 | outb(val, priv->scc_data); |
| 665 | return; |
| 666 | case TYPE_TWIN: |
| 667 | outb_p(val, priv->scc_data); |
| 668 | return; |
| 669 | default: |
| 670 | if (fast) |
| 671 | outb_p(val, priv->scc_data); |
| 672 | else { |
| 673 | spin_lock_irqsave(priv->register_lock, flags); |
| 674 | outb_p(0, priv->card_base + PI_DREQ_MASK); |
| 675 | outb_p(val, priv->scc_data); |
| 676 | outb(1, priv->card_base + PI_DREQ_MASK); |
| 677 | spin_unlock_irqrestore(priv->register_lock, flags); |
| 678 | } |
| 679 | return; |
| 680 | } |
| 681 | } |
| 682 | |
| 683 | |
| 684 | static int read_scc(struct scc_priv *priv, int reg) |
| 685 | { |
| 686 | int rc; |
| 687 | unsigned long flags; |
| 688 | switch (priv->type) { |
| 689 | case TYPE_S5: |
| 690 | if (reg) |
| 691 | outb(reg, priv->scc_cmd); |
| 692 | return inb(priv->scc_cmd); |
| 693 | case TYPE_TWIN: |
| 694 | if (reg) |
| 695 | outb_p(reg, priv->scc_cmd); |
| 696 | return inb_p(priv->scc_cmd); |
| 697 | default: |
| 698 | spin_lock_irqsave(priv->register_lock, flags); |
| 699 | outb_p(0, priv->card_base + PI_DREQ_MASK); |
| 700 | if (reg) |
| 701 | outb_p(reg, priv->scc_cmd); |
| 702 | rc = inb_p(priv->scc_cmd); |
| 703 | outb(1, priv->card_base + PI_DREQ_MASK); |
| 704 | spin_unlock_irqrestore(priv->register_lock, flags); |
| 705 | return rc; |
| 706 | } |
| 707 | } |
| 708 | |
| 709 | |
| 710 | static int read_scc_data(struct scc_priv *priv) |
| 711 | { |
| 712 | int rc; |
| 713 | unsigned long flags; |
| 714 | switch (priv->type) { |
| 715 | case TYPE_S5: |
| 716 | return inb(priv->scc_data); |
| 717 | case TYPE_TWIN: |
| 718 | return inb_p(priv->scc_data); |
| 719 | default: |
| 720 | spin_lock_irqsave(priv->register_lock, flags); |
| 721 | outb_p(0, priv->card_base + PI_DREQ_MASK); |
| 722 | rc = inb_p(priv->scc_data); |
| 723 | outb(1, priv->card_base + PI_DREQ_MASK); |
| 724 | spin_unlock_irqrestore(priv->register_lock, flags); |
| 725 | return rc; |
| 726 | } |
| 727 | } |
| 728 | |
| 729 | |
| 730 | static int scc_open(struct net_device *dev) |
| 731 | { |
| 732 | struct scc_priv *priv = dev->priv; |
| 733 | struct scc_info *info = priv->info; |
| 734 | int card_base = priv->card_base; |
| 735 | |
| 736 | /* Request IRQ if not already used by other channel */ |
| 737 | if (!info->irq_used) { |
| 738 | if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) { |
| 739 | return -EAGAIN; |
| 740 | } |
| 741 | } |
| 742 | info->irq_used++; |
| 743 | |
| 744 | /* Request DMA if required */ |
| 745 | if (priv->param.dma >= 0) { |
| 746 | if (request_dma(priv->param.dma, "dmascc")) { |
| 747 | if (--info->irq_used == 0) |
| 748 | free_irq(dev->irq, info); |
| 749 | return -EAGAIN; |
| 750 | } else { |
| 751 | unsigned long flags = claim_dma_lock(); |
| 752 | clear_dma_ff(priv->param.dma); |
| 753 | release_dma_lock(flags); |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | /* Initialize local variables */ |
| 758 | priv->rx_ptr = 0; |
| 759 | priv->rx_over = 0; |
| 760 | priv->rx_head = priv->rx_tail = priv->rx_count = 0; |
| 761 | priv->state = IDLE; |
| 762 | priv->tx_head = priv->tx_tail = priv->tx_count = 0; |
| 763 | priv->tx_ptr = 0; |
| 764 | |
| 765 | /* Reset channel */ |
| 766 | write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); |
| 767 | /* X1 clock, SDLC mode */ |
| 768 | write_scc(priv, R4, SDLC | X1CLK); |
| 769 | /* DMA */ |
| 770 | write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); |
| 771 | /* 8 bit RX char, RX disable */ |
| 772 | write_scc(priv, R3, Rx8); |
| 773 | /* 8 bit TX char, TX disable */ |
| 774 | write_scc(priv, R5, Tx8); |
| 775 | /* SDLC address field */ |
| 776 | write_scc(priv, R6, 0); |
| 777 | /* SDLC flag */ |
| 778 | write_scc(priv, R7, FLAG); |
| 779 | switch (priv->chip) { |
| 780 | case Z85C30: |
| 781 | /* Select WR7' */ |
| 782 | write_scc(priv, R15, SHDLCE); |
| 783 | /* Auto EOM reset */ |
| 784 | write_scc(priv, R7, AUTOEOM); |
| 785 | write_scc(priv, R15, 0); |
| 786 | break; |
| 787 | case Z85230: |
| 788 | /* Select WR7' */ |
| 789 | write_scc(priv, R15, SHDLCE); |
| 790 | /* The following bits are set (see 2.5.2.1): |
| 791 | - Automatic EOM reset |
| 792 | - Interrupt request if RX FIFO is half full |
| 793 | This bit should be ignored in DMA mode (according to the |
| 794 | documentation), but actually isn't. The receiver doesn't work if |
| 795 | it is set. Thus, we have to clear it in DMA mode. |
| 796 | - Interrupt/DMA request if TX FIFO is completely empty |
| 797 | a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30 |
| 798 | compatibility). |
| 799 | b) If cleared, DMA requests may follow each other very quickly, |
| 800 | filling up the TX FIFO. |
| 801 | Advantage: TX works even in case of high bus latency. |
| 802 | Disadvantage: Edge-triggered DMA request circuitry may miss |
| 803 | a request. No more data is delivered, resulting |
| 804 | in a TX FIFO underrun. |
| 805 | Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared. |
| 806 | The PackeTwin doesn't. I don't know about the PI, but let's |
| 807 | assume it behaves like the PI2. |
| 808 | */ |
| 809 | if (priv->param.dma >= 0) { |
| 810 | if (priv->type == TYPE_TWIN) |
| 811 | write_scc(priv, R7, AUTOEOM | TXFIFOE); |
| 812 | else |
| 813 | write_scc(priv, R7, AUTOEOM); |
| 814 | } else { |
| 815 | write_scc(priv, R7, AUTOEOM | RXFIFOH); |
| 816 | } |
| 817 | write_scc(priv, R15, 0); |
| 818 | break; |
| 819 | } |
| 820 | /* Preset CRC, NRZ(I) encoding */ |
| 821 | write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); |
| 822 | |
| 823 | /* Configure baud rate generator */ |
| 824 | if (priv->param.brg_tc >= 0) { |
| 825 | /* Program BR generator */ |
| 826 | write_scc(priv, R12, priv->param.brg_tc & 0xFF); |
| 827 | write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF); |
| 828 | /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by |
| 829 | PackeTwin, not connected on the PI2); set DPLL source to BRG */ |
| 830 | write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); |
| 831 | /* Enable DPLL */ |
| 832 | write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); |
| 833 | } else { |
| 834 | /* Disable BR generator */ |
| 835 | write_scc(priv, R14, DTRREQ | BRSRC); |
| 836 | } |
| 837 | |
| 838 | /* Configure clocks */ |
| 839 | if (priv->type == TYPE_TWIN) { |
| 840 | /* Disable external TX clock receiver */ |
| 841 | outb((info->twin_serial_cfg &= |
| 842 | ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), |
| 843 | card_base + TWIN_SERIAL_CFG); |
| 844 | } |
| 845 | write_scc(priv, R11, priv->param.clocks); |
| 846 | if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) { |
| 847 | /* Enable external TX clock receiver */ |
| 848 | outb((info->twin_serial_cfg |= |
| 849 | (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)), |
| 850 | card_base + TWIN_SERIAL_CFG); |
| 851 | } |
| 852 | |
| 853 | /* Configure PackeTwin */ |
| 854 | if (priv->type == TYPE_TWIN) { |
| 855 | /* Assert DTR, enable interrupts */ |
| 856 | outb((info->twin_serial_cfg |= TWIN_EI | |
| 857 | (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)), |
| 858 | card_base + TWIN_SERIAL_CFG); |
| 859 | } |
| 860 | |
| 861 | /* Read current status */ |
| 862 | priv->rr0 = read_scc(priv, R0); |
| 863 | /* Enable DCD interrupt */ |
| 864 | write_scc(priv, R15, DCDIE); |
| 865 | |
| 866 | netif_start_queue(dev); |
| 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
| 871 | |
| 872 | static int scc_close(struct net_device *dev) |
| 873 | { |
| 874 | struct scc_priv *priv = dev->priv; |
| 875 | struct scc_info *info = priv->info; |
| 876 | int card_base = priv->card_base; |
| 877 | |
| 878 | netif_stop_queue(dev); |
| 879 | |
| 880 | if (priv->type == TYPE_TWIN) { |
| 881 | /* Drop DTR */ |
| 882 | outb((info->twin_serial_cfg &= |
| 883 | (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)), |
| 884 | card_base + TWIN_SERIAL_CFG); |
| 885 | } |
| 886 | |
| 887 | /* Reset channel, free DMA and IRQ */ |
| 888 | write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); |
| 889 | if (priv->param.dma >= 0) { |
| 890 | if (priv->type == TYPE_TWIN) |
| 891 | outb(0, card_base + TWIN_DMA_CFG); |
| 892 | free_dma(priv->param.dma); |
| 893 | } |
| 894 | if (--info->irq_used == 0) |
| 895 | free_irq(dev->irq, info); |
| 896 | |
| 897 | return 0; |
| 898 | } |
| 899 | |
| 900 | |
| 901 | static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 902 | { |
| 903 | struct scc_priv *priv = dev->priv; |
| 904 | |
| 905 | switch (cmd) { |
| 906 | case SIOCGSCCPARAM: |
| 907 | if (copy_to_user |
| 908 | (ifr->ifr_data, &priv->param, |
| 909 | sizeof(struct scc_param))) |
| 910 | return -EFAULT; |
| 911 | return 0; |
| 912 | case SIOCSSCCPARAM: |
| 913 | if (!capable(CAP_NET_ADMIN)) |
| 914 | return -EPERM; |
| 915 | if (netif_running(dev)) |
| 916 | return -EAGAIN; |
| 917 | if (copy_from_user |
| 918 | (&priv->param, ifr->ifr_data, |
| 919 | sizeof(struct scc_param))) |
| 920 | return -EFAULT; |
| 921 | return 0; |
| 922 | default: |
| 923 | return -EINVAL; |
| 924 | } |
| 925 | } |
| 926 | |
| 927 | |
| 928 | static int scc_send_packet(struct sk_buff *skb, struct net_device *dev) |
| 929 | { |
| 930 | struct scc_priv *priv = dev->priv; |
| 931 | unsigned long flags; |
| 932 | int i; |
| 933 | |
| 934 | /* Temporarily stop the scheduler feeding us packets */ |
| 935 | netif_stop_queue(dev); |
| 936 | |
| 937 | /* Transfer data to DMA buffer */ |
| 938 | i = priv->tx_head; |
| 939 | memcpy(priv->tx_buf[i], skb->data + 1, skb->len - 1); |
| 940 | priv->tx_len[i] = skb->len - 1; |
| 941 | |
| 942 | /* Clear interrupts while we touch our circular buffers */ |
| 943 | |
| 944 | spin_lock_irqsave(&priv->ring_lock, flags); |
| 945 | /* Move the ring buffer's head */ |
| 946 | priv->tx_head = (i + 1) % NUM_TX_BUF; |
| 947 | priv->tx_count++; |
| 948 | |
| 949 | /* If we just filled up the last buffer, leave queue stopped. |
| 950 | The higher layers must wait until we have a DMA buffer |
| 951 | to accept the data. */ |
| 952 | if (priv->tx_count < NUM_TX_BUF) |
| 953 | netif_wake_queue(dev); |
| 954 | |
| 955 | /* Set new TX state */ |
| 956 | if (priv->state == IDLE) { |
| 957 | /* Assert RTS, start timer */ |
| 958 | priv->state = TX_HEAD; |
| 959 | priv->tx_start = jiffies; |
| 960 | write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); |
| 961 | write_scc(priv, R15, 0); |
| 962 | start_timer(priv, priv->param.txdelay, 0); |
| 963 | } |
| 964 | |
| 965 | /* Turn interrupts back on and free buffer */ |
| 966 | spin_unlock_irqrestore(&priv->ring_lock, flags); |
| 967 | dev_kfree_skb(skb); |
| 968 | |
| 969 | return 0; |
| 970 | } |
| 971 | |
| 972 | |
| 973 | static struct net_device_stats *scc_get_stats(struct net_device *dev) |
| 974 | { |
| 975 | struct scc_priv *priv = dev->priv; |
| 976 | |
| 977 | return &priv->stats; |
| 978 | } |
| 979 | |
| 980 | |
| 981 | static int scc_set_mac_address(struct net_device *dev, void *sa) |
| 982 | { |
| 983 | memcpy(dev->dev_addr, ((struct sockaddr *) sa)->sa_data, |
| 984 | dev->addr_len); |
| 985 | return 0; |
| 986 | } |
| 987 | |
| 988 | |
| 989 | static inline void tx_on(struct scc_priv *priv) |
| 990 | { |
| 991 | int i, n; |
| 992 | unsigned long flags; |
| 993 | |
| 994 | if (priv->param.dma >= 0) { |
| 995 | n = (priv->chip == Z85230) ? 3 : 1; |
| 996 | /* Program DMA controller */ |
| 997 | flags = claim_dma_lock(); |
| 998 | set_dma_mode(priv->param.dma, DMA_MODE_WRITE); |
| 999 | set_dma_addr(priv->param.dma, |
| 1000 | (int) priv->tx_buf[priv->tx_tail] + n); |
| 1001 | set_dma_count(priv->param.dma, |
| 1002 | priv->tx_len[priv->tx_tail] - n); |
| 1003 | release_dma_lock(flags); |
| 1004 | /* Enable TX underrun interrupt */ |
| 1005 | write_scc(priv, R15, TxUIE); |
| 1006 | /* Configure DREQ */ |
| 1007 | if (priv->type == TYPE_TWIN) |
| 1008 | outb((priv->param.dma == |
| 1009 | 1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3, |
| 1010 | priv->card_base + TWIN_DMA_CFG); |
| 1011 | else |
| 1012 | write_scc(priv, R1, |
| 1013 | EXT_INT_ENAB | WT_FN_RDYFN | |
| 1014 | WT_RDY_ENAB); |
| 1015 | /* Write first byte(s) */ |
| 1016 | spin_lock_irqsave(priv->register_lock, flags); |
| 1017 | for (i = 0; i < n; i++) |
| 1018 | write_scc_data(priv, |
| 1019 | priv->tx_buf[priv->tx_tail][i], 1); |
| 1020 | enable_dma(priv->param.dma); |
| 1021 | spin_unlock_irqrestore(priv->register_lock, flags); |
| 1022 | } else { |
| 1023 | write_scc(priv, R15, TxUIE); |
| 1024 | write_scc(priv, R1, |
| 1025 | EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB); |
| 1026 | tx_isr(priv); |
| 1027 | } |
| 1028 | /* Reset EOM latch if we do not have the AUTOEOM feature */ |
| 1029 | if (priv->chip == Z8530) |
| 1030 | write_scc(priv, R0, RES_EOM_L); |
| 1031 | } |
| 1032 | |
| 1033 | |
| 1034 | static inline void rx_on(struct scc_priv *priv) |
| 1035 | { |
| 1036 | unsigned long flags; |
| 1037 | |
| 1038 | /* Clear RX FIFO */ |
| 1039 | while (read_scc(priv, R0) & Rx_CH_AV) |
| 1040 | read_scc_data(priv); |
| 1041 | priv->rx_over = 0; |
| 1042 | if (priv->param.dma >= 0) { |
| 1043 | /* Program DMA controller */ |
| 1044 | flags = claim_dma_lock(); |
| 1045 | set_dma_mode(priv->param.dma, DMA_MODE_READ); |
| 1046 | set_dma_addr(priv->param.dma, |
| 1047 | (int) priv->rx_buf[priv->rx_head]); |
| 1048 | set_dma_count(priv->param.dma, BUF_SIZE); |
| 1049 | release_dma_lock(flags); |
| 1050 | enable_dma(priv->param.dma); |
| 1051 | /* Configure PackeTwin DMA */ |
| 1052 | if (priv->type == TYPE_TWIN) { |
| 1053 | outb((priv->param.dma == |
| 1054 | 1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3, |
| 1055 | priv->card_base + TWIN_DMA_CFG); |
| 1056 | } |
| 1057 | /* Sp. cond. intr. only, ext int enable, RX DMA enable */ |
| 1058 | write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | |
| 1059 | WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB); |
| 1060 | } else { |
| 1061 | /* Reset current frame */ |
| 1062 | priv->rx_ptr = 0; |
| 1063 | /* Intr. on all Rx characters and Sp. cond., ext int enable */ |
| 1064 | write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | |
| 1065 | WT_FN_RDYFN); |
| 1066 | } |
| 1067 | write_scc(priv, R0, ERR_RES); |
| 1068 | write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); |
| 1069 | } |
| 1070 | |
| 1071 | |
| 1072 | static inline void rx_off(struct scc_priv *priv) |
| 1073 | { |
| 1074 | /* Disable receiver */ |
| 1075 | write_scc(priv, R3, Rx8); |
| 1076 | /* Disable DREQ / RX interrupt */ |
| 1077 | if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) |
| 1078 | outb(0, priv->card_base + TWIN_DMA_CFG); |
| 1079 | else |
| 1080 | write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); |
| 1081 | /* Disable DMA */ |
| 1082 | if (priv->param.dma >= 0) |
| 1083 | disable_dma(priv->param.dma); |
| 1084 | } |
| 1085 | |
| 1086 | |
| 1087 | static void start_timer(struct scc_priv *priv, int t, int r15) |
| 1088 | { |
| 1089 | unsigned long flags; |
| 1090 | |
| 1091 | outb(priv->tmr_mode, priv->tmr_ctrl); |
| 1092 | if (t == 0) { |
| 1093 | tm_isr(priv); |
| 1094 | } else if (t > 0) { |
| 1095 | save_flags(flags); |
| 1096 | cli(); |
| 1097 | outb(t & 0xFF, priv->tmr_cnt); |
| 1098 | outb((t >> 8) & 0xFF, priv->tmr_cnt); |
| 1099 | if (priv->type != TYPE_TWIN) { |
| 1100 | write_scc(priv, R15, r15 | CTSIE); |
| 1101 | priv->rr0 |= CTS; |
| 1102 | } |
| 1103 | restore_flags(flags); |
| 1104 | } |
| 1105 | } |
| 1106 | |
| 1107 | |
| 1108 | static inline unsigned char random(void) |
| 1109 | { |
| 1110 | /* See "Numerical Recipes in C", second edition, p. 284 */ |
| 1111 | rand = rand * 1664525L + 1013904223L; |
| 1112 | return (unsigned char) (rand >> 24); |
| 1113 | } |
| 1114 | |
| 1115 | static inline void z8530_isr(struct scc_info *info) |
| 1116 | { |
| 1117 | int is, i = 100; |
| 1118 | |
| 1119 | while ((is = read_scc(&info->priv[0], R3)) && i--) { |
| 1120 | if (is & CHARxIP) { |
| 1121 | rx_isr(&info->priv[0]); |
| 1122 | } else if (is & CHATxIP) { |
| 1123 | tx_isr(&info->priv[0]); |
| 1124 | } else if (is & CHAEXT) { |
| 1125 | es_isr(&info->priv[0]); |
| 1126 | } else if (is & CHBRxIP) { |
| 1127 | rx_isr(&info->priv[1]); |
| 1128 | } else if (is & CHBTxIP) { |
| 1129 | tx_isr(&info->priv[1]); |
| 1130 | } else { |
| 1131 | es_isr(&info->priv[1]); |
| 1132 | } |
| 1133 | write_scc(&info->priv[0], R0, RES_H_IUS); |
| 1134 | i++; |
| 1135 | } |
| 1136 | if (i < 0) { |
| 1137 | printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n", |
| 1138 | is); |
| 1139 | } |
| 1140 | /* Ok, no interrupts pending from this 8530. The INT line should |
| 1141 | be inactive now. */ |
| 1142 | } |
| 1143 | |
| 1144 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 1145 | static irqreturn_t scc_isr(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1146 | { |
| 1147 | struct scc_info *info = dev_id; |
| 1148 | |
| 1149 | spin_lock(info->priv[0].register_lock); |
| 1150 | /* At this point interrupts are enabled, and the interrupt under service |
| 1151 | is already acknowledged, but masked off. |
| 1152 | |
| 1153 | Interrupt processing: We loop until we know that the IRQ line is |
| 1154 | low. If another positive edge occurs afterwards during the ISR, |
| 1155 | another interrupt will be triggered by the interrupt controller |
| 1156 | as soon as the IRQ level is enabled again (see asm/irq.h). |
| 1157 | |
| 1158 | Bottom-half handlers will be processed after scc_isr(). This is |
| 1159 | important, since we only have small ringbuffers and want new data |
| 1160 | to be fetched/delivered immediately. */ |
| 1161 | |
| 1162 | if (info->priv[0].type == TYPE_TWIN) { |
| 1163 | int is, card_base = info->priv[0].card_base; |
| 1164 | while ((is = ~inb(card_base + TWIN_INT_REG)) & |
| 1165 | TWIN_INT_MSK) { |
| 1166 | if (is & TWIN_SCC_MSK) { |
| 1167 | z8530_isr(info); |
| 1168 | } else if (is & TWIN_TMR1_MSK) { |
| 1169 | inb(card_base + TWIN_CLR_TMR1); |
| 1170 | tm_isr(&info->priv[0]); |
| 1171 | } else { |
| 1172 | inb(card_base + TWIN_CLR_TMR2); |
| 1173 | tm_isr(&info->priv[1]); |
| 1174 | } |
| 1175 | } |
| 1176 | } else |
| 1177 | z8530_isr(info); |
| 1178 | spin_unlock(info->priv[0].register_lock); |
| 1179 | return IRQ_HANDLED; |
| 1180 | } |
| 1181 | |
| 1182 | |
| 1183 | static void rx_isr(struct scc_priv *priv) |
| 1184 | { |
| 1185 | if (priv->param.dma >= 0) { |
| 1186 | /* Check special condition and perform error reset. See 2.4.7.5. */ |
| 1187 | special_condition(priv, read_scc(priv, R1)); |
| 1188 | write_scc(priv, R0, ERR_RES); |
| 1189 | } else { |
| 1190 | /* Check special condition for each character. Error reset not necessary. |
| 1191 | Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */ |
| 1192 | int rc; |
| 1193 | while (read_scc(priv, R0) & Rx_CH_AV) { |
| 1194 | rc = read_scc(priv, R1); |
| 1195 | if (priv->rx_ptr < BUF_SIZE) |
| 1196 | priv->rx_buf[priv->rx_head][priv-> |
| 1197 | rx_ptr++] = |
| 1198 | read_scc_data(priv); |
| 1199 | else { |
| 1200 | priv->rx_over = 2; |
| 1201 | read_scc_data(priv); |
| 1202 | } |
| 1203 | special_condition(priv, rc); |
| 1204 | } |
| 1205 | } |
| 1206 | } |
| 1207 | |
| 1208 | |
| 1209 | static void special_condition(struct scc_priv *priv, int rc) |
| 1210 | { |
| 1211 | int cb; |
| 1212 | unsigned long flags; |
| 1213 | |
| 1214 | /* See Figure 2-15. Only overrun and EOF need to be checked. */ |
| 1215 | |
| 1216 | if (rc & Rx_OVR) { |
| 1217 | /* Receiver overrun */ |
| 1218 | priv->rx_over = 1; |
| 1219 | if (priv->param.dma < 0) |
| 1220 | write_scc(priv, R0, ERR_RES); |
| 1221 | } else if (rc & END_FR) { |
| 1222 | /* End of frame. Get byte count */ |
| 1223 | if (priv->param.dma >= 0) { |
| 1224 | flags = claim_dma_lock(); |
| 1225 | cb = BUF_SIZE - get_dma_residue(priv->param.dma) - |
| 1226 | 2; |
| 1227 | release_dma_lock(flags); |
| 1228 | } else { |
| 1229 | cb = priv->rx_ptr - 2; |
| 1230 | } |
| 1231 | if (priv->rx_over) { |
| 1232 | /* We had an overrun */ |
| 1233 | priv->stats.rx_errors++; |
| 1234 | if (priv->rx_over == 2) |
| 1235 | priv->stats.rx_length_errors++; |
| 1236 | else |
| 1237 | priv->stats.rx_fifo_errors++; |
| 1238 | priv->rx_over = 0; |
| 1239 | } else if (rc & CRC_ERR) { |
| 1240 | /* Count invalid CRC only if packet length >= minimum */ |
| 1241 | if (cb >= 15) { |
| 1242 | priv->stats.rx_errors++; |
| 1243 | priv->stats.rx_crc_errors++; |
| 1244 | } |
| 1245 | } else { |
| 1246 | if (cb >= 15) { |
| 1247 | if (priv->rx_count < NUM_RX_BUF - 1) { |
| 1248 | /* Put good frame in FIFO */ |
| 1249 | priv->rx_len[priv->rx_head] = cb; |
| 1250 | priv->rx_head = |
| 1251 | (priv->rx_head + |
| 1252 | 1) % NUM_RX_BUF; |
| 1253 | priv->rx_count++; |
| 1254 | schedule_work(&priv->rx_work); |
| 1255 | } else { |
| 1256 | priv->stats.rx_errors++; |
| 1257 | priv->stats.rx_over_errors++; |
| 1258 | } |
| 1259 | } |
| 1260 | } |
| 1261 | /* Get ready for new frame */ |
| 1262 | if (priv->param.dma >= 0) { |
| 1263 | flags = claim_dma_lock(); |
| 1264 | set_dma_addr(priv->param.dma, |
| 1265 | (int) priv->rx_buf[priv->rx_head]); |
| 1266 | set_dma_count(priv->param.dma, BUF_SIZE); |
| 1267 | release_dma_lock(flags); |
| 1268 | } else { |
| 1269 | priv->rx_ptr = 0; |
| 1270 | } |
| 1271 | } |
| 1272 | } |
| 1273 | |
| 1274 | |
Al Viro | 7a87b6c | 2006-12-06 18:51:40 +0000 | [diff] [blame^] | 1275 | static void rx_bh(struct work_struct *ugli_api) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1276 | { |
Al Viro | 7a87b6c | 2006-12-06 18:51:40 +0000 | [diff] [blame^] | 1277 | struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | int i = priv->rx_tail; |
| 1279 | int cb; |
| 1280 | unsigned long flags; |
| 1281 | struct sk_buff *skb; |
| 1282 | unsigned char *data; |
| 1283 | |
| 1284 | spin_lock_irqsave(&priv->ring_lock, flags); |
| 1285 | while (priv->rx_count) { |
| 1286 | spin_unlock_irqrestore(&priv->ring_lock, flags); |
| 1287 | cb = priv->rx_len[i]; |
| 1288 | /* Allocate buffer */ |
| 1289 | skb = dev_alloc_skb(cb + 1); |
| 1290 | if (skb == NULL) { |
| 1291 | /* Drop packet */ |
| 1292 | priv->stats.rx_dropped++; |
| 1293 | } else { |
| 1294 | /* Fill buffer */ |
| 1295 | data = skb_put(skb, cb + 1); |
| 1296 | data[0] = 0; |
| 1297 | memcpy(&data[1], priv->rx_buf[i], cb); |
Arnaldo Carvalho de Melo | 56cb515 | 2005-04-24 18:53:06 -0700 | [diff] [blame] | 1298 | skb->protocol = ax25_type_trans(skb, priv->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1299 | netif_rx(skb); |
| 1300 | priv->dev->last_rx = jiffies; |
| 1301 | priv->stats.rx_packets++; |
| 1302 | priv->stats.rx_bytes += cb; |
| 1303 | } |
| 1304 | spin_lock_irqsave(&priv->ring_lock, flags); |
| 1305 | /* Move tail */ |
| 1306 | priv->rx_tail = i = (i + 1) % NUM_RX_BUF; |
| 1307 | priv->rx_count--; |
| 1308 | } |
| 1309 | spin_unlock_irqrestore(&priv->ring_lock, flags); |
| 1310 | } |
| 1311 | |
| 1312 | |
| 1313 | static void tx_isr(struct scc_priv *priv) |
| 1314 | { |
| 1315 | int i = priv->tx_tail, p = priv->tx_ptr; |
| 1316 | |
| 1317 | /* Suspend TX interrupts if we don't want to send anything. |
| 1318 | See Figure 2-22. */ |
| 1319 | if (p == priv->tx_len[i]) { |
| 1320 | write_scc(priv, R0, RES_Tx_P); |
| 1321 | return; |
| 1322 | } |
| 1323 | |
| 1324 | /* Write characters */ |
| 1325 | while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) { |
| 1326 | write_scc_data(priv, priv->tx_buf[i][p++], 0); |
| 1327 | } |
| 1328 | |
| 1329 | /* Reset EOM latch of Z8530 */ |
| 1330 | if (!priv->tx_ptr && p && priv->chip == Z8530) |
| 1331 | write_scc(priv, R0, RES_EOM_L); |
| 1332 | |
| 1333 | priv->tx_ptr = p; |
| 1334 | } |
| 1335 | |
| 1336 | |
| 1337 | static void es_isr(struct scc_priv *priv) |
| 1338 | { |
| 1339 | int i, rr0, drr0, res; |
| 1340 | unsigned long flags; |
| 1341 | |
| 1342 | /* Read status, reset interrupt bit (open latches) */ |
| 1343 | rr0 = read_scc(priv, R0); |
| 1344 | write_scc(priv, R0, RES_EXT_INT); |
| 1345 | drr0 = priv->rr0 ^ rr0; |
| 1346 | priv->rr0 = rr0; |
| 1347 | |
| 1348 | /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since |
| 1349 | it might have already been cleared again by AUTOEOM. */ |
| 1350 | if (priv->state == TX_DATA) { |
| 1351 | /* Get remaining bytes */ |
| 1352 | i = priv->tx_tail; |
| 1353 | if (priv->param.dma >= 0) { |
| 1354 | disable_dma(priv->param.dma); |
| 1355 | flags = claim_dma_lock(); |
| 1356 | res = get_dma_residue(priv->param.dma); |
| 1357 | release_dma_lock(flags); |
| 1358 | } else { |
| 1359 | res = priv->tx_len[i] - priv->tx_ptr; |
| 1360 | priv->tx_ptr = 0; |
| 1361 | } |
| 1362 | /* Disable DREQ / TX interrupt */ |
| 1363 | if (priv->param.dma >= 0 && priv->type == TYPE_TWIN) |
| 1364 | outb(0, priv->card_base + TWIN_DMA_CFG); |
| 1365 | else |
| 1366 | write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); |
| 1367 | if (res) { |
| 1368 | /* Update packet statistics */ |
| 1369 | priv->stats.tx_errors++; |
| 1370 | priv->stats.tx_fifo_errors++; |
| 1371 | /* Other underrun interrupts may already be waiting */ |
| 1372 | write_scc(priv, R0, RES_EXT_INT); |
| 1373 | write_scc(priv, R0, RES_EXT_INT); |
| 1374 | } else { |
| 1375 | /* Update packet statistics */ |
| 1376 | priv->stats.tx_packets++; |
| 1377 | priv->stats.tx_bytes += priv->tx_len[i]; |
| 1378 | /* Remove frame from FIFO */ |
| 1379 | priv->tx_tail = (i + 1) % NUM_TX_BUF; |
| 1380 | priv->tx_count--; |
| 1381 | /* Inform upper layers */ |
| 1382 | netif_wake_queue(priv->dev); |
| 1383 | } |
| 1384 | /* Switch state */ |
| 1385 | write_scc(priv, R15, 0); |
| 1386 | if (priv->tx_count && |
| 1387 | (jiffies - priv->tx_start) < priv->param.txtimeout) { |
| 1388 | priv->state = TX_PAUSE; |
| 1389 | start_timer(priv, priv->param.txpause, 0); |
| 1390 | } else { |
| 1391 | priv->state = TX_TAIL; |
| 1392 | start_timer(priv, priv->param.txtail, 0); |
| 1393 | } |
| 1394 | } |
| 1395 | |
| 1396 | /* DCD transition */ |
| 1397 | if (drr0 & DCD) { |
| 1398 | if (rr0 & DCD) { |
| 1399 | switch (priv->state) { |
| 1400 | case IDLE: |
| 1401 | case WAIT: |
| 1402 | priv->state = DCD_ON; |
| 1403 | write_scc(priv, R15, 0); |
| 1404 | start_timer(priv, priv->param.dcdon, 0); |
| 1405 | } |
| 1406 | } else { |
| 1407 | switch (priv->state) { |
| 1408 | case RX_ON: |
| 1409 | rx_off(priv); |
| 1410 | priv->state = DCD_OFF; |
| 1411 | write_scc(priv, R15, 0); |
| 1412 | start_timer(priv, priv->param.dcdoff, 0); |
| 1413 | } |
| 1414 | } |
| 1415 | } |
| 1416 | |
| 1417 | /* CTS transition */ |
| 1418 | if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN) |
| 1419 | tm_isr(priv); |
| 1420 | |
| 1421 | } |
| 1422 | |
| 1423 | |
| 1424 | static void tm_isr(struct scc_priv *priv) |
| 1425 | { |
| 1426 | switch (priv->state) { |
| 1427 | case TX_HEAD: |
| 1428 | case TX_PAUSE: |
| 1429 | tx_on(priv); |
| 1430 | priv->state = TX_DATA; |
| 1431 | break; |
| 1432 | case TX_TAIL: |
| 1433 | write_scc(priv, R5, TxCRC_ENAB | Tx8); |
| 1434 | priv->state = RTS_OFF; |
| 1435 | if (priv->type != TYPE_TWIN) |
| 1436 | write_scc(priv, R15, 0); |
| 1437 | start_timer(priv, priv->param.rtsoff, 0); |
| 1438 | break; |
| 1439 | case RTS_OFF: |
| 1440 | write_scc(priv, R15, DCDIE); |
| 1441 | priv->rr0 = read_scc(priv, R0); |
| 1442 | if (priv->rr0 & DCD) { |
| 1443 | priv->stats.collisions++; |
| 1444 | rx_on(priv); |
| 1445 | priv->state = RX_ON; |
| 1446 | } else { |
| 1447 | priv->state = WAIT; |
| 1448 | start_timer(priv, priv->param.waittime, DCDIE); |
| 1449 | } |
| 1450 | break; |
| 1451 | case WAIT: |
| 1452 | if (priv->tx_count) { |
| 1453 | priv->state = TX_HEAD; |
| 1454 | priv->tx_start = jiffies; |
| 1455 | write_scc(priv, R5, |
| 1456 | TxCRC_ENAB | RTS | TxENAB | Tx8); |
| 1457 | write_scc(priv, R15, 0); |
| 1458 | start_timer(priv, priv->param.txdelay, 0); |
| 1459 | } else { |
| 1460 | priv->state = IDLE; |
| 1461 | if (priv->type != TYPE_TWIN) |
| 1462 | write_scc(priv, R15, DCDIE); |
| 1463 | } |
| 1464 | break; |
| 1465 | case DCD_ON: |
| 1466 | case DCD_OFF: |
| 1467 | write_scc(priv, R15, DCDIE); |
| 1468 | priv->rr0 = read_scc(priv, R0); |
| 1469 | if (priv->rr0 & DCD) { |
| 1470 | rx_on(priv); |
| 1471 | priv->state = RX_ON; |
| 1472 | } else { |
| 1473 | priv->state = WAIT; |
| 1474 | start_timer(priv, |
| 1475 | random() / priv->param.persist * |
| 1476 | priv->param.slottime, DCDIE); |
| 1477 | } |
| 1478 | break; |
| 1479 | } |
| 1480 | } |