Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Registers definition for DA9063 modules |
| 3 | * |
| 4 | * Copyright 2012 Dialog Semiconductor Ltd. |
| 5 | * |
Steve Twiss | 37778d8 | 2016-08-08 14:16:11 +0100 | [diff] [blame] | 6 | * Author: Michal Hajduk, Dialog Semiconductor |
| 7 | * Author: Krystian Garbaciak, Dialog Semiconductor |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify it |
| 10 | * under the terms of the GNU General Public License as published by the |
| 11 | * Free Software Foundation; either version 2 of the License, or (at your |
| 12 | * option) any later version. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #ifndef _DA9063_REG_H |
| 17 | #define _DA9063_REG_H |
| 18 | |
| 19 | #define DA9063_I2C_PAGE_SEL_SHIFT 1 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 20 | #define DA9063_EVENT_REG_NUM 4 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 21 | |
| 22 | /* Page selection I2C or SPI always in the begining of any page. */ |
| 23 | /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */ |
| 24 | /* Page 1 : SPI access 0x080 - 0x0FF */ |
| 25 | /* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */ |
| 26 | /* Page 3 : SPI access 0x180 - 0x1FF */ |
| 27 | #define DA9063_REG_PAGE_CON 0x00 |
| 28 | |
| 29 | /* System Control and Event Registers */ |
| 30 | #define DA9063_REG_STATUS_A 0x01 |
| 31 | #define DA9063_REG_STATUS_B 0x02 |
| 32 | #define DA9063_REG_STATUS_C 0x03 |
| 33 | #define DA9063_REG_STATUS_D 0x04 |
| 34 | #define DA9063_REG_FAULT_LOG 0x05 |
| 35 | #define DA9063_REG_EVENT_A 0x06 |
| 36 | #define DA9063_REG_EVENT_B 0x07 |
| 37 | #define DA9063_REG_EVENT_C 0x08 |
| 38 | #define DA9063_REG_EVENT_D 0x09 |
| 39 | #define DA9063_REG_IRQ_MASK_A 0x0A |
| 40 | #define DA9063_REG_IRQ_MASK_B 0x0B |
| 41 | #define DA9063_REG_IRQ_MASK_C 0x0C |
| 42 | #define DA9063_REG_IRQ_MASK_D 0x0D |
| 43 | #define DA9063_REG_CONTROL_A 0x0E |
| 44 | #define DA9063_REG_CONTROL_B 0x0F |
| 45 | #define DA9063_REG_CONTROL_C 0x10 |
| 46 | #define DA9063_REG_CONTROL_D 0x11 |
| 47 | #define DA9063_REG_CONTROL_E 0x12 |
| 48 | #define DA9063_REG_CONTROL_F 0x13 |
| 49 | #define DA9063_REG_PD_DIS 0x14 |
| 50 | |
| 51 | /* GPIO Control Registers */ |
| 52 | #define DA9063_REG_GPIO_0_1 0x15 |
| 53 | #define DA9063_REG_GPIO_2_3 0x16 |
| 54 | #define DA9063_REG_GPIO_4_5 0x17 |
| 55 | #define DA9063_REG_GPIO_6_7 0x18 |
| 56 | #define DA9063_REG_GPIO_8_9 0x19 |
| 57 | #define DA9063_REG_GPIO_10_11 0x1A |
| 58 | #define DA9063_REG_GPIO_12_13 0x1B |
| 59 | #define DA9063_REG_GPIO_14_15 0x1C |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 60 | #define DA9063_REG_GPIO_MODE0_7 0x1D |
| 61 | #define DA9063_REG_GPIO_MODE8_15 0x1E |
| 62 | #define DA9063_REG_SWITCH_CONT 0x1F |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 63 | |
| 64 | /* Regulator Control Registers */ |
| 65 | #define DA9063_REG_BCORE2_CONT 0x20 |
| 66 | #define DA9063_REG_BCORE1_CONT 0x21 |
| 67 | #define DA9063_REG_BPRO_CONT 0x22 |
| 68 | #define DA9063_REG_BMEM_CONT 0x23 |
| 69 | #define DA9063_REG_BIO_CONT 0x24 |
| 70 | #define DA9063_REG_BPERI_CONT 0x25 |
| 71 | #define DA9063_REG_LDO1_CONT 0x26 |
| 72 | #define DA9063_REG_LDO2_CONT 0x27 |
| 73 | #define DA9063_REG_LDO3_CONT 0x28 |
| 74 | #define DA9063_REG_LDO4_CONT 0x29 |
| 75 | #define DA9063_REG_LDO5_CONT 0x2A |
| 76 | #define DA9063_REG_LDO6_CONT 0x2B |
| 77 | #define DA9063_REG_LDO7_CONT 0x2C |
| 78 | #define DA9063_REG_LDO8_CONT 0x2D |
| 79 | #define DA9063_REG_LDO9_CONT 0x2E |
| 80 | #define DA9063_REG_LDO10_CONT 0x2F |
| 81 | #define DA9063_REG_LDO11_CONT 0x30 |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 82 | #define DA9063_REG_SUPPLIES 0x31 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 83 | #define DA9063_REG_DVC_1 0x32 |
| 84 | #define DA9063_REG_DVC_2 0x33 |
| 85 | |
| 86 | /* GP-ADC Control Registers */ |
| 87 | #define DA9063_REG_ADC_MAN 0x34 |
| 88 | #define DA9063_REG_ADC_CONT 0x35 |
| 89 | #define DA9063_REG_VSYS_MON 0x36 |
| 90 | #define DA9063_REG_ADC_RES_L 0x37 |
| 91 | #define DA9063_REG_ADC_RES_H 0x38 |
| 92 | #define DA9063_REG_VSYS_RES 0x39 |
| 93 | #define DA9063_REG_ADCIN1_RES 0x3A |
| 94 | #define DA9063_REG_ADCIN2_RES 0x3B |
| 95 | #define DA9063_REG_ADCIN3_RES 0x3C |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 96 | #define DA9063_REG_MON_A8_RES 0x3D |
| 97 | #define DA9063_REG_MON_A9_RES 0x3E |
| 98 | #define DA9063_REG_MON_A10_RES 0x3F |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 99 | |
| 100 | /* RTC Calendar and Alarm Registers */ |
| 101 | #define DA9063_REG_COUNT_S 0x40 |
| 102 | #define DA9063_REG_COUNT_MI 0x41 |
| 103 | #define DA9063_REG_COUNT_H 0x42 |
| 104 | #define DA9063_REG_COUNT_D 0x43 |
| 105 | #define DA9063_REG_COUNT_MO 0x44 |
| 106 | #define DA9063_REG_COUNT_Y 0x45 |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 107 | |
| 108 | #define DA9063_AD_REG_ALARM_MI 0x46 |
| 109 | #define DA9063_AD_REG_ALARM_H 0x47 |
| 110 | #define DA9063_AD_REG_ALARM_D 0x48 |
| 111 | #define DA9063_AD_REG_ALARM_MO 0x49 |
| 112 | #define DA9063_AD_REG_ALARM_Y 0x4A |
| 113 | #define DA9063_AD_REG_SECOND_A 0x4B |
| 114 | #define DA9063_AD_REG_SECOND_B 0x4C |
| 115 | #define DA9063_AD_REG_SECOND_C 0x4D |
| 116 | #define DA9063_AD_REG_SECOND_D 0x4E |
| 117 | |
| 118 | #define DA9063_BB_REG_ALARM_S 0x46 |
| 119 | #define DA9063_BB_REG_ALARM_MI 0x47 |
| 120 | #define DA9063_BB_REG_ALARM_H 0x48 |
| 121 | #define DA9063_BB_REG_ALARM_D 0x49 |
| 122 | #define DA9063_BB_REG_ALARM_MO 0x4A |
| 123 | #define DA9063_BB_REG_ALARM_Y 0x4B |
| 124 | #define DA9063_BB_REG_SECOND_A 0x4C |
| 125 | #define DA9063_BB_REG_SECOND_B 0x4D |
| 126 | #define DA9063_BB_REG_SECOND_C 0x4E |
| 127 | #define DA9063_BB_REG_SECOND_D 0x4F |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 128 | |
| 129 | /* Sequencer Control Registers */ |
| 130 | #define DA9063_REG_SEQ 0x81 |
| 131 | #define DA9063_REG_SEQ_TIMER 0x82 |
| 132 | #define DA9063_REG_ID_2_1 0x83 |
| 133 | #define DA9063_REG_ID_4_3 0x84 |
| 134 | #define DA9063_REG_ID_6_5 0x85 |
| 135 | #define DA9063_REG_ID_8_7 0x86 |
| 136 | #define DA9063_REG_ID_10_9 0x87 |
| 137 | #define DA9063_REG_ID_12_11 0x88 |
| 138 | #define DA9063_REG_ID_14_13 0x89 |
| 139 | #define DA9063_REG_ID_16_15 0x8A |
| 140 | #define DA9063_REG_ID_18_17 0x8B |
| 141 | #define DA9063_REG_ID_20_19 0x8C |
| 142 | #define DA9063_REG_ID_22_21 0x8D |
| 143 | #define DA9063_REG_ID_24_23 0x8E |
| 144 | #define DA9063_REG_ID_26_25 0x8F |
| 145 | #define DA9063_REG_ID_28_27 0x90 |
| 146 | #define DA9063_REG_ID_30_29 0x91 |
| 147 | #define DA9063_REG_ID_32_31 0x92 |
| 148 | #define DA9063_REG_SEQ_A 0x95 |
| 149 | #define DA9063_REG_SEQ_B 0x96 |
| 150 | #define DA9063_REG_WAIT 0x97 |
| 151 | #define DA9063_REG_EN_32K 0x98 |
| 152 | #define DA9063_REG_RESET 0x99 |
| 153 | |
| 154 | /* Regulator Setting Registers */ |
| 155 | #define DA9063_REG_BUCK_ILIM_A 0x9A |
| 156 | #define DA9063_REG_BUCK_ILIM_B 0x9B |
| 157 | #define DA9063_REG_BUCK_ILIM_C 0x9C |
| 158 | #define DA9063_REG_BCORE2_CFG 0x9D |
| 159 | #define DA9063_REG_BCORE1_CFG 0x9E |
| 160 | #define DA9063_REG_BPRO_CFG 0x9F |
| 161 | #define DA9063_REG_BIO_CFG 0xA0 |
| 162 | #define DA9063_REG_BMEM_CFG 0xA1 |
| 163 | #define DA9063_REG_BPERI_CFG 0xA2 |
| 164 | #define DA9063_REG_VBCORE2_A 0xA3 |
| 165 | #define DA9063_REG_VBCORE1_A 0xA4 |
| 166 | #define DA9063_REG_VBPRO_A 0xA5 |
| 167 | #define DA9063_REG_VBMEM_A 0xA6 |
| 168 | #define DA9063_REG_VBIO_A 0xA7 |
| 169 | #define DA9063_REG_VBPERI_A 0xA8 |
| 170 | #define DA9063_REG_VLDO1_A 0xA9 |
| 171 | #define DA9063_REG_VLDO2_A 0xAA |
| 172 | #define DA9063_REG_VLDO3_A 0xAB |
| 173 | #define DA9063_REG_VLDO4_A 0xAC |
| 174 | #define DA9063_REG_VLDO5_A 0xAD |
| 175 | #define DA9063_REG_VLDO6_A 0xAE |
| 176 | #define DA9063_REG_VLDO7_A 0xAF |
| 177 | #define DA9063_REG_VLDO8_A 0xB0 |
| 178 | #define DA9063_REG_VLDO9_A 0xB1 |
| 179 | #define DA9063_REG_VLDO10_A 0xB2 |
| 180 | #define DA9063_REG_VLDO11_A 0xB3 |
| 181 | #define DA9063_REG_VBCORE2_B 0xB4 |
| 182 | #define DA9063_REG_VBCORE1_B 0xB5 |
| 183 | #define DA9063_REG_VBPRO_B 0xB6 |
| 184 | #define DA9063_REG_VBMEM_B 0xB7 |
| 185 | #define DA9063_REG_VBIO_B 0xB8 |
| 186 | #define DA9063_REG_VBPERI_B 0xB9 |
| 187 | #define DA9063_REG_VLDO1_B 0xBA |
| 188 | #define DA9063_REG_VLDO2_B 0xBB |
| 189 | #define DA9063_REG_VLDO3_B 0xBC |
| 190 | #define DA9063_REG_VLDO4_B 0xBD |
| 191 | #define DA9063_REG_VLDO5_B 0xBE |
| 192 | #define DA9063_REG_VLDO6_B 0xBF |
| 193 | #define DA9063_REG_VLDO7_B 0xC0 |
| 194 | #define DA9063_REG_VLDO8_B 0xC1 |
| 195 | #define DA9063_REG_VLDO9_B 0xC2 |
| 196 | #define DA9063_REG_VLDO10_B 0xC3 |
| 197 | #define DA9063_REG_VLDO11_B 0xC4 |
| 198 | |
| 199 | /* Backup Battery Charger Control Register */ |
| 200 | #define DA9063_REG_BBAT_CONT 0xC5 |
| 201 | |
| 202 | /* GPIO PWM (LED) */ |
| 203 | #define DA9063_REG_GPO11_LED 0xC6 |
| 204 | #define DA9063_REG_GPO14_LED 0xC7 |
| 205 | #define DA9063_REG_GPO15_LED 0xC8 |
| 206 | |
| 207 | /* GP-ADC Threshold Registers */ |
| 208 | #define DA9063_REG_ADC_CFG 0xC9 |
| 209 | #define DA9063_REG_AUTO1_HIGH 0xCA |
| 210 | #define DA9063_REG_AUTO1_LOW 0xCB |
| 211 | #define DA9063_REG_AUTO2_HIGH 0xCC |
| 212 | #define DA9063_REG_AUTO2_LOW 0xCD |
| 213 | #define DA9063_REG_AUTO3_HIGH 0xCE |
| 214 | #define DA9063_REG_AUTO3_LOW 0xCF |
| 215 | |
| 216 | /* DA9063 Configuration registers */ |
| 217 | /* OTP */ |
| 218 | #define DA9063_REG_OPT_COUNT 0x101 |
| 219 | #define DA9063_REG_OPT_ADDR 0x102 |
| 220 | #define DA9063_REG_OPT_DATA 0x103 |
| 221 | |
| 222 | /* Customer Trim and Configuration */ |
| 223 | #define DA9063_REG_T_OFFSET 0x104 |
| 224 | #define DA9063_REG_INTERFACE 0x105 |
| 225 | #define DA9063_REG_CONFIG_A 0x106 |
| 226 | #define DA9063_REG_CONFIG_B 0x107 |
| 227 | #define DA9063_REG_CONFIG_C 0x108 |
| 228 | #define DA9063_REG_CONFIG_D 0x109 |
| 229 | #define DA9063_REG_CONFIG_E 0x10A |
| 230 | #define DA9063_REG_CONFIG_F 0x10B |
| 231 | #define DA9063_REG_CONFIG_G 0x10C |
| 232 | #define DA9063_REG_CONFIG_H 0x10D |
| 233 | #define DA9063_REG_CONFIG_I 0x10E |
| 234 | #define DA9063_REG_CONFIG_J 0x10F |
| 235 | #define DA9063_REG_CONFIG_K 0x110 |
| 236 | #define DA9063_REG_CONFIG_L 0x111 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 237 | |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 238 | #define DA9063_AD_REG_MON_REG_1 0x112 |
| 239 | #define DA9063_AD_REG_MON_REG_2 0x113 |
| 240 | #define DA9063_AD_REG_MON_REG_3 0x114 |
| 241 | #define DA9063_AD_REG_MON_REG_4 0x115 |
| 242 | #define DA9063_AD_REG_MON_REG_5 0x116 |
| 243 | #define DA9063_AD_REG_MON_REG_6 0x117 |
| 244 | #define DA9063_AD_REG_TRIM_CLDR 0x118 |
| 245 | |
| 246 | #define DA9063_AD_REG_GP_ID_0 0x119 |
| 247 | #define DA9063_AD_REG_GP_ID_1 0x11A |
| 248 | #define DA9063_AD_REG_GP_ID_2 0x11B |
| 249 | #define DA9063_AD_REG_GP_ID_3 0x11C |
| 250 | #define DA9063_AD_REG_GP_ID_4 0x11D |
| 251 | #define DA9063_AD_REG_GP_ID_5 0x11E |
| 252 | #define DA9063_AD_REG_GP_ID_6 0x11F |
| 253 | #define DA9063_AD_REG_GP_ID_7 0x120 |
| 254 | #define DA9063_AD_REG_GP_ID_8 0x121 |
| 255 | #define DA9063_AD_REG_GP_ID_9 0x122 |
| 256 | #define DA9063_AD_REG_GP_ID_10 0x123 |
| 257 | #define DA9063_AD_REG_GP_ID_11 0x124 |
| 258 | #define DA9063_AD_REG_GP_ID_12 0x125 |
| 259 | #define DA9063_AD_REG_GP_ID_13 0x126 |
| 260 | #define DA9063_AD_REG_GP_ID_14 0x127 |
| 261 | #define DA9063_AD_REG_GP_ID_15 0x128 |
| 262 | #define DA9063_AD_REG_GP_ID_16 0x129 |
| 263 | #define DA9063_AD_REG_GP_ID_17 0x12A |
| 264 | #define DA9063_AD_REG_GP_ID_18 0x12B |
| 265 | #define DA9063_AD_REG_GP_ID_19 0x12C |
| 266 | |
| 267 | #define DA9063_BB_REG_CONFIG_M 0x112 |
| 268 | #define DA9063_BB_REG_CONFIG_N 0x113 |
| 269 | |
| 270 | #define DA9063_BB_REG_MON_REG_1 0x114 |
| 271 | #define DA9063_BB_REG_MON_REG_2 0x115 |
| 272 | #define DA9063_BB_REG_MON_REG_3 0x116 |
| 273 | #define DA9063_BB_REG_MON_REG_4 0x117 |
| 274 | #define DA9063_BB_REG_MON_REG_5 0x11E |
| 275 | #define DA9063_BB_REG_MON_REG_6 0x11F |
| 276 | #define DA9063_BB_REG_TRIM_CLDR 0x120 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 277 | /* General Purpose Registers */ |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 278 | #define DA9063_BB_REG_GP_ID_0 0x121 |
| 279 | #define DA9063_BB_REG_GP_ID_1 0x122 |
| 280 | #define DA9063_BB_REG_GP_ID_2 0x123 |
| 281 | #define DA9063_BB_REG_GP_ID_3 0x124 |
| 282 | #define DA9063_BB_REG_GP_ID_4 0x125 |
| 283 | #define DA9063_BB_REG_GP_ID_5 0x126 |
| 284 | #define DA9063_BB_REG_GP_ID_6 0x127 |
| 285 | #define DA9063_BB_REG_GP_ID_7 0x128 |
| 286 | #define DA9063_BB_REG_GP_ID_8 0x129 |
| 287 | #define DA9063_BB_REG_GP_ID_9 0x12A |
| 288 | #define DA9063_BB_REG_GP_ID_10 0x12B |
| 289 | #define DA9063_BB_REG_GP_ID_11 0x12C |
| 290 | #define DA9063_BB_REG_GP_ID_12 0x12D |
| 291 | #define DA9063_BB_REG_GP_ID_13 0x12E |
| 292 | #define DA9063_BB_REG_GP_ID_14 0x12F |
| 293 | #define DA9063_BB_REG_GP_ID_15 0x130 |
| 294 | #define DA9063_BB_REG_GP_ID_16 0x131 |
| 295 | #define DA9063_BB_REG_GP_ID_17 0x132 |
| 296 | #define DA9063_BB_REG_GP_ID_18 0x133 |
| 297 | #define DA9063_BB_REG_GP_ID_19 0x134 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 298 | |
| 299 | /* Chip ID and variant */ |
| 300 | #define DA9063_REG_CHIP_ID 0x181 |
| 301 | #define DA9063_REG_CHIP_VARIANT 0x182 |
| 302 | |
| 303 | /* |
| 304 | * PMIC registers bits |
| 305 | */ |
| 306 | /* DA9063_REG_PAGE_CON (addr=0x00) */ |
| 307 | #define DA9063_PEG_PAGE_SHIFT 0 |
| 308 | #define DA9063_REG_PAGE_MASK 0x07 |
| 309 | #define DA9063_REG_PAGE0 0x00 |
| 310 | #define DA9063_REG_PAGE2 0x02 |
| 311 | #define DA9063_PAGE_WRITE_MODE 0x00 |
| 312 | #define DA9063_REPEAT_WRITE_MODE 0x40 |
| 313 | #define DA9063_PAGE_REVERT 0x80 |
| 314 | |
| 315 | /* DA9063_REG_STATUS_A (addr=0x01) */ |
| 316 | #define DA9063_NONKEY 0x01 |
| 317 | #define DA9063_WAKE 0x02 |
| 318 | #define DA9063_DVC_BUSY 0x04 |
| 319 | #define DA9063_COMP_1V2 0x08 |
| 320 | |
| 321 | /* DA9063_REG_STATUS_B (addr=0x02) */ |
| 322 | #define DA9063_GPI0 0x01 |
| 323 | #define DA9063_GPI1 0x02 |
| 324 | #define DA9063_GPI2 0x04 |
| 325 | #define DA9063_GPI3 0x08 |
| 326 | #define DA9063_GPI4 0x10 |
| 327 | #define DA9063_GPI5 0x20 |
| 328 | #define DA9063_GPI6 0x40 |
| 329 | #define DA9063_GPI7 0x80 |
| 330 | |
| 331 | /* DA9063_REG_STATUS_C (addr=0x03) */ |
| 332 | #define DA9063_GPI8 0x01 |
| 333 | #define DA9063_GPI9 0x02 |
| 334 | #define DA9063_GPI10 0x04 |
| 335 | #define DA9063_GPI11 0x08 |
| 336 | #define DA9063_GPI12 0x10 |
| 337 | #define DA9063_GPI13 0x20 |
| 338 | #define DA9063_GPI14 0x40 |
| 339 | #define DA9063_GPI15 0x80 |
| 340 | |
| 341 | /* DA9063_REG_STATUS_D (addr=0x04) */ |
| 342 | #define DA9063_LDO3_LIM 0x08 |
| 343 | #define DA9063_LDO4_LIM 0x10 |
| 344 | #define DA9063_LDO7_LIM 0x20 |
| 345 | #define DA9063_LDO8_LIM 0x40 |
| 346 | #define DA9063_LDO11_LIM 0x80 |
| 347 | |
| 348 | /* DA9063_REG_FAULT_LOG (addr=0x05) */ |
| 349 | #define DA9063_TWD_ERROR 0x01 |
| 350 | #define DA9063_POR 0x02 |
| 351 | #define DA9063_VDD_FAULT 0x04 |
| 352 | #define DA9063_VDD_START 0x08 |
| 353 | #define DA9063_TEMP_CRIT 0x10 |
| 354 | #define DA9063_KEY_RESET 0x20 |
| 355 | #define DA9063_NSHUTDOWN 0x40 |
| 356 | #define DA9063_WAIT_SHUT 0x80 |
| 357 | |
| 358 | /* DA9063_REG_EVENT_A (addr=0x06) */ |
| 359 | #define DA9063_E_NONKEY 0x01 |
| 360 | #define DA9063_E_ALARM 0x02 |
| 361 | #define DA9063_E_TICK 0x04 |
| 362 | #define DA9063_E_ADC_RDY 0x08 |
| 363 | #define DA9063_E_SEQ_RDY 0x10 |
| 364 | #define DA9063_EVENTS_B 0x20 |
| 365 | #define DA9063_EVENTS_C 0x40 |
| 366 | #define DA9063_EVENTS_D 0x80 |
| 367 | |
| 368 | /* DA9063_REG_EVENT_B (addr=0x07) */ |
| 369 | #define DA9063_E_WAKE 0x01 |
| 370 | #define DA9063_E_TEMP 0x02 |
| 371 | #define DA9063_E_COMP_1V2 0x04 |
| 372 | #define DA9063_E_LDO_LIM 0x08 |
| 373 | #define DA9063_E_REG_UVOV 0x10 |
| 374 | #define DA9063_E_DVC_RDY 0x20 |
| 375 | #define DA9063_E_VDD_MON 0x40 |
| 376 | #define DA9063_E_VDD_WARN 0x80 |
| 377 | |
| 378 | /* DA9063_REG_EVENT_C (addr=0x08) */ |
| 379 | #define DA9063_E_GPI0 0x01 |
| 380 | #define DA9063_E_GPI1 0x02 |
| 381 | #define DA9063_E_GPI2 0x04 |
| 382 | #define DA9063_E_GPI3 0x08 |
| 383 | #define DA9063_E_GPI4 0x10 |
| 384 | #define DA9063_E_GPI5 0x20 |
| 385 | #define DA9063_E_GPI6 0x40 |
| 386 | #define DA9063_E_GPI7 0x80 |
| 387 | |
| 388 | /* DA9063_REG_EVENT_D (addr=0x09) */ |
| 389 | #define DA9063_E_GPI8 0x01 |
| 390 | #define DA9063_E_GPI9 0x02 |
| 391 | #define DA9063_E_GPI10 0x04 |
| 392 | #define DA9063_E_GPI11 0x08 |
| 393 | #define DA9063_E_GPI12 0x10 |
| 394 | #define DA9063_E_GPI13 0x20 |
| 395 | #define DA9063_E_GPI14 0x40 |
| 396 | #define DA9063_E_GPI15 0x80 |
| 397 | |
| 398 | /* DA9063_REG_IRQ_MASK_A (addr=0x0A) */ |
| 399 | #define DA9063_M_ONKEY 0x01 |
| 400 | #define DA9063_M_ALARM 0x02 |
| 401 | #define DA9063_M_TICK 0x04 |
| 402 | #define DA9063_M_ADC_RDY 0x08 |
| 403 | #define DA9063_M_SEQ_RDY 0x10 |
| 404 | |
| 405 | /* DA9063_REG_IRQ_MASK_B (addr=0x0B) */ |
| 406 | #define DA9063_M_WAKE 0x01 |
| 407 | #define DA9063_M_TEMP 0x02 |
| 408 | #define DA9063_M_COMP_1V2 0x04 |
| 409 | #define DA9063_M_LDO_LIM 0x08 |
| 410 | #define DA9063_M_UVOV 0x10 |
| 411 | #define DA9063_M_DVC_RDY 0x20 |
| 412 | #define DA9063_M_VDD_MON 0x40 |
| 413 | #define DA9063_M_VDD_WARN 0x80 |
| 414 | |
| 415 | /* DA9063_REG_IRQ_MASK_C (addr=0x0C) */ |
| 416 | #define DA9063_M_GPI0 0x01 |
| 417 | #define DA9063_M_GPI1 0x02 |
| 418 | #define DA9063_M_GPI2 0x04 |
| 419 | #define DA9063_M_GPI3 0x08 |
| 420 | #define DA9063_M_GPI4 0x10 |
| 421 | #define DA9063_M_GPI5 0x20 |
| 422 | #define DA9063_M_GPI6 0x40 |
| 423 | #define DA9063_M_GPI7 0x80 |
| 424 | |
| 425 | /* DA9063_REG_IRQ_MASK_D (addr=0x0D) */ |
| 426 | #define DA9063_M_GPI8 0x01 |
| 427 | #define DA9063_M_GPI9 0x02 |
| 428 | #define DA9063_M_GPI10 0x04 |
| 429 | #define DA9063_M_GPI11 0x08 |
| 430 | #define DA9063_M_GPI12 0x10 |
| 431 | #define DA9063_M_GPI13 0x20 |
| 432 | #define DA9063_M_GPI14 0x40 |
| 433 | #define DA9063_M_GPI15 0x80 |
| 434 | |
| 435 | /* DA9063_REG_CONTROL_A (addr=0x0E) */ |
| 436 | #define DA9063_SYSTEM_EN 0x01 |
| 437 | #define DA9063_POWER_EN 0x02 |
| 438 | #define DA9063_POWER1_EN 0x04 |
| 439 | #define DA9063_STANDBY 0x08 |
| 440 | #define DA9063_M_SYSTEM_EN 0x10 |
| 441 | #define DA9063_M_POWER_EN 0x20 |
| 442 | #define DA9063_M_POWER1_EN 0x40 |
| 443 | #define DA9063_CP_EN 0x80 |
| 444 | |
| 445 | /* DA9063_REG_CONTROL_B (addr=0x0F) */ |
| 446 | #define DA9063_CHG_SEL 0x01 |
| 447 | #define DA9063_WATCHDOG_PD 0x02 |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 448 | #define DA9063_BB_RESET_BLINKING 0x04 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 449 | #define DA9063_NRES_MODE 0x08 |
| 450 | #define DA9063_NONKEY_LOCK 0x10 |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 451 | #define DA9063_BB_BUCK_SLOWSTART 0x80 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 452 | |
| 453 | /* DA9063_REG_CONTROL_C (addr=0x10) */ |
| 454 | #define DA9063_DEBOUNCING_MASK 0x07 |
| 455 | #define DA9063_DEBOUNCING_OFF 0x0 |
| 456 | #define DA9063_DEBOUNCING_0MS1 0x1 |
| 457 | #define DA9063_DEBOUNCING_1MS 0x2 |
| 458 | #define DA9063_DEBOUNCING_10MS24 0x3 |
| 459 | #define DA9063_DEBOUNCING_51MS2 0x4 |
| 460 | #define DA9063_DEBOUNCING_256MS 0x5 |
| 461 | #define DA9063_DEBOUNCING_512MS 0x6 |
| 462 | #define DA9063_DEBOUNCING_1024MS 0x7 |
| 463 | |
| 464 | #define DA9063_AUTO_BOOT 0x08 |
| 465 | #define DA9063_OTPREAD_EN 0x10 |
| 466 | #define DA9063_SLEW_RATE_MASK 0x60 |
| 467 | #define DA9063_SLEW_RATE_4US 0x00 |
| 468 | #define DA9063_SLEW_RATE_3US 0x20 |
| 469 | #define DA9063_SLEW_RATE_1US 0x40 |
| 470 | #define DA9063_SLEW_RATE_0US5 0x60 |
| 471 | #define DA9063_DEF_SUPPLY 0x80 |
| 472 | |
| 473 | /* DA9063_REG_CONTROL_D (addr=0x11) */ |
| 474 | #define DA9063_TWDSCALE_MASK 0x07 |
| 475 | #define DA9063_BLINK_FRQ_MASK 0x38 |
| 476 | #define DA9063_BLINK_FRQ_OFF 0x00 |
| 477 | #define DA9063_BLINK_FRQ_1S0 0x08 |
| 478 | #define DA9063_BLINK_FRQ_2S0 0x10 |
| 479 | #define DA9063_BLINK_FRQ_4S0 0x18 |
| 480 | #define DA9063_BLINK_FRQ_0S18 0x20 |
| 481 | #define DA9063_BLINK_FRQ_2S0_VDD 0x28 |
| 482 | #define DA9063_BLINK_FRQ_4S0_VDD 0x30 |
| 483 | #define DA9063_BLINK_FRQ_0S18_VDD 0x38 |
| 484 | |
| 485 | #define DA9063_BLINK_DUR_MASK 0xC0 |
| 486 | #define DA9063_BLINK_DUR_10MS 0x00 |
| 487 | #define DA9063_BLINK_DUR_20MS 0x40 |
| 488 | #define DA9063_BLINK_DUR_40MS 0x80 |
| 489 | #define DA9063_BLINK_DUR_20MSDBL 0xC0 |
| 490 | |
| 491 | /* DA9063_REG_CONTROL_E (addr=0x12) */ |
| 492 | #define DA9063_RTC_MODE_PD 0x01 |
| 493 | #define DA9063_RTC_MODE_SD 0x02 |
| 494 | #define DA9063_RTC_EN 0x04 |
| 495 | #define DA9063_ECO_MODE 0x08 |
| 496 | #define DA9063_PM_FB1_PIN 0x10 |
| 497 | #define DA9063_PM_FB2_PIN 0x20 |
| 498 | #define DA9063_PM_FB3_PIN 0x40 |
| 499 | #define DA9063_V_LOCK 0x80 |
| 500 | |
| 501 | /* DA9063_REG_CONTROL_F (addr=0x13) */ |
| 502 | #define DA9063_WATCHDOG 0x01 |
| 503 | #define DA9063_SHUTDOWN 0x02 |
| 504 | #define DA9063_WAKE_UP 0x04 |
| 505 | |
| 506 | /* DA9063_REG_PD_DIS (addr=0x14) */ |
| 507 | #define DA9063_GPI_DIS 0x01 |
| 508 | #define DA9063_GPADC_PAUSE 0x02 |
| 509 | #define DA9063_PMIF_DIS 0x04 |
| 510 | #define DA9063_HS2WIRE_DIS 0x08 |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 511 | #define DA9063_BB_CLDR_PAUSE 0x10 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 512 | #define DA9063_BBAT_DIS 0x20 |
| 513 | #define DA9063_OUT_32K_PAUSE 0x40 |
| 514 | #define DA9063_PMCONT_DIS 0x80 |
| 515 | |
| 516 | /* DA9063_REG_GPIO_0_1 (addr=0x15) */ |
| 517 | #define DA9063_GPIO0_PIN_MASK 0x03 |
| 518 | #define DA9063_GPIO0_PIN_ADCIN1 0x00 |
| 519 | #define DA9063_GPIO0_PIN_GPI 0x01 |
| 520 | #define DA9063_GPIO0_PIN_GPO_OD 0x02 |
| 521 | #define DA9063_GPIO0_PIN_GPO 0x03 |
| 522 | #define DA9063_GPIO0_TYPE 0x04 |
| 523 | #define DA9063_GPIO0_TYPE_GPI_ACT_LOW 0x00 |
| 524 | #define DA9063_GPIO0_TYPE_GPO_VDD_IO1 0x00 |
| 525 | #define DA9063_GPIO0_TYPE_GPI_ACT_HIGH 0x04 |
| 526 | #define DA9063_GPIO0_TYPE_GPO_VDD_IO2 0x04 |
| 527 | #define DA9063_GPIO0_NO_WAKEUP 0x08 |
| 528 | #define DA9063_GPIO1_PIN_MASK 0x30 |
| 529 | #define DA9063_GPIO1_PIN_ADCIN2_COMP 0x00 |
| 530 | #define DA9063_GPIO1_PIN_GPI 0x10 |
| 531 | #define DA9063_GPIO1_PIN_GPO_OD 0x20 |
| 532 | #define DA9063_GPIO1_PIN_GPO 0x30 |
| 533 | #define DA9063_GPIO1_TYPE 0x40 |
| 534 | #define DA9063_GPIO1_TYPE_GPI_ACT_LOW 0x00 |
| 535 | #define DA9063_GPIO1_TYPE_GPO_VDD_IO1 0x00 |
| 536 | #define DA9063_GPIO1_TYPE_GPI_ACT_HIGH 0x04 |
| 537 | #define DA9063_GPIO1_TYPE_GPO_VDD_IO2 0x04 |
| 538 | #define DA9063_GPIO1_NO_WAKEUP 0x80 |
| 539 | |
| 540 | /* DA9063_REG_GPIO_2_3 (addr=0x16) */ |
| 541 | #define DA9063_GPIO2_PIN_MASK 0x03 |
| 542 | #define DA9063_GPIO2_PIN_ADCIN3 0x00 |
| 543 | #define DA9063_GPIO2_PIN_GPI 0x01 |
| 544 | #define DA9063_GPIO2_PIN_GPO_PSS 0x02 |
| 545 | #define DA9063_GPIO2_PIN_GPO 0x03 |
| 546 | #define DA9063_GPIO2_TYPE 0x04 |
| 547 | #define DA9063_GPIO2_TYPE_GPI_ACT_LOW 0x00 |
| 548 | #define DA9063_GPIO2_TYPE_GPO_VDD_IO1 0x00 |
| 549 | #define DA9063_GPIO2_TYPE_GPI_ACT_HIGH 0x04 |
| 550 | #define DA9063_GPIO2_TYPE_GPO_VDD_IO2 0x04 |
| 551 | #define DA9063_GPIO2_NO_WAKEUP 0x08 |
| 552 | #define DA9063_GPIO3_PIN_MASK 0x30 |
| 553 | #define DA9063_GPIO3_PIN_CORE_SW_G 0x00 |
| 554 | #define DA9063_GPIO3_PIN_GPI 0x10 |
| 555 | #define DA9063_GPIO3_PIN_GPO_OD 0x20 |
| 556 | #define DA9063_GPIO3_PIN_GPO 0x30 |
| 557 | #define DA9063_GPIO3_TYPE 0x40 |
| 558 | #define DA9063_GPIO3_TYPE_GPI_ACT_LOW 0x00 |
| 559 | #define DA9063_GPIO3_TYPE_GPO_VDD_IO1 0x00 |
| 560 | #define DA9063_GPIO3_TYPE_GPI_ACT_HIGH 0x04 |
| 561 | #define DA9063_GPIO3_TYPE_GPO_VDD_IO2 0x04 |
| 562 | #define DA9063_GPIO3_NO_WAKEUP 0x80 |
| 563 | |
| 564 | /* DA9063_REG_GPIO_4_5 (addr=0x17) */ |
| 565 | #define DA9063_GPIO4_PIN_MASK 0x03 |
| 566 | #define DA9063_GPIO4_PIN_CORE_SW_S 0x00 |
| 567 | #define DA9063_GPIO4_PIN_GPI 0x01 |
| 568 | #define DA9063_GPIO4_PIN_GPO_OD 0x02 |
| 569 | #define DA9063_GPIO4_PIN_GPO 0x03 |
| 570 | #define DA9063_GPIO4_TYPE 0x04 |
| 571 | #define DA9063_GPIO4_TYPE_GPI_ACT_LOW 0x00 |
| 572 | #define DA9063_GPIO4_TYPE_GPO_VDD_IO1 0x00 |
| 573 | #define DA9063_GPIO4_TYPE_GPI_ACT_HIGH 0x04 |
| 574 | #define DA9063_GPIO4_TYPE_GPO_VDD_IO2 0x04 |
| 575 | #define DA9063_GPIO4_NO_WAKEUP 0x08 |
| 576 | #define DA9063_GPIO5_PIN_MASK 0x30 |
| 577 | #define DA9063_GPIO5_PIN_PERI_SW_G 0x00 |
| 578 | #define DA9063_GPIO5_PIN_GPI 0x10 |
| 579 | #define DA9063_GPIO5_PIN_GPO_OD 0x20 |
| 580 | #define DA9063_GPIO5_PIN_GPO 0x30 |
| 581 | #define DA9063_GPIO5_TYPE 0x40 |
| 582 | #define DA9063_GPIO5_TYPE_GPI_ACT_LOW 0x00 |
| 583 | #define DA9063_GPIO5_TYPE_GPO_VDD_IO1 0x00 |
| 584 | #define DA9063_GPIO5_TYPE_GPI_ACT_HIGH 0x04 |
| 585 | #define DA9063_GPIO5_TYPE_GPO_VDD_IO2 0x04 |
| 586 | #define DA9063_GPIO5_NO_WAKEUP 0x80 |
| 587 | |
| 588 | /* DA9063_REG_GPIO_6_7 (addr=0x18) */ |
| 589 | #define DA9063_GPIO6_PIN_MASK 0x03 |
| 590 | #define DA9063_GPIO6_PIN_PERI_SW_S 0x00 |
| 591 | #define DA9063_GPIO6_PIN_GPI 0x01 |
| 592 | #define DA9063_GPIO6_PIN_GPO_OD 0x02 |
| 593 | #define DA9063_GPIO6_PIN_GPO 0x03 |
| 594 | #define DA9063_GPIO6_TYPE 0x04 |
| 595 | #define DA9063_GPIO6_TYPE_GPI_ACT_LOW 0x00 |
| 596 | #define DA9063_GPIO6_TYPE_GPO_VDD_IO1 0x00 |
| 597 | #define DA9063_GPIO6_TYPE_GPI_ACT_HIGH 0x04 |
| 598 | #define DA9063_GPIO6_TYPE_GPO_VDD_IO2 0x04 |
| 599 | #define DA9063_GPIO6_NO_WAKEUP 0x08 |
| 600 | #define DA9063_GPIO7_PIN_MASK 0x30 |
| 601 | #define DA9063_GPIO7_PIN_GPI 0x10 |
| 602 | #define DA9063_GPIO7_PIN_GPO_PSS 0x20 |
| 603 | #define DA9063_GPIO7_PIN_GPO 0x30 |
| 604 | #define DA9063_GPIO7_TYPE 0x40 |
| 605 | #define DA9063_GPIO7_TYPE_GPI_ACT_LOW 0x00 |
| 606 | #define DA9063_GPIO7_TYPE_GPO_VDD_IO1 0x00 |
| 607 | #define DA9063_GPIO7_TYPE_GPI_ACT_HIGH 0x04 |
| 608 | #define DA9063_GPIO7_TYPE_GPO_VDD_IO2 0x04 |
| 609 | #define DA9063_GPIO7_NO_WAKEUP 0x80 |
| 610 | |
| 611 | /* DA9063_REG_GPIO_8_9 (addr=0x19) */ |
| 612 | #define DA9063_GPIO8_PIN_MASK 0x03 |
| 613 | #define DA9063_GPIO8_PIN_GPI_SYS_EN 0x00 |
| 614 | #define DA9063_GPIO8_PIN_GPI 0x01 |
| 615 | #define DA9063_GPIO8_PIN_GPO_PSS 0x02 |
| 616 | #define DA9063_GPIO8_PIN_GPO 0x03 |
| 617 | #define DA9063_GPIO8_TYPE 0x04 |
| 618 | #define DA9063_GPIO8_TYPE_GPI_ACT_LOW 0x00 |
| 619 | #define DA9063_GPIO8_TYPE_GPO_VDD_IO1 0x00 |
| 620 | #define DA9063_GPIO8_TYPE_GPI_ACT_HIGH 0x04 |
| 621 | #define DA9063_GPIO8_TYPE_GPO_VDD_IO2 0x04 |
| 622 | #define DA9063_GPIO8_NO_WAKEUP 0x08 |
| 623 | #define DA9063_GPIO9_PIN_MASK 0x30 |
| 624 | #define DA9063_GPIO9_PIN_GPI_PWR_EN 0x00 |
| 625 | #define DA9063_GPIO9_PIN_GPI 0x10 |
| 626 | #define DA9063_GPIO9_PIN_GPO_PSS 0x20 |
| 627 | #define DA9063_GPIO9_PIN_GPO 0x30 |
| 628 | #define DA9063_GPIO9_TYPE 0x40 |
| 629 | #define DA9063_GPIO9_TYPE_GPI_ACT_LOW 0x00 |
| 630 | #define DA9063_GPIO9_TYPE_GPO_VDD_IO1 0x00 |
| 631 | #define DA9063_GPIO9_TYPE_GPI_ACT_HIGH 0x04 |
| 632 | #define DA9063_GPIO9_TYPE_GPO_VDD_IO2 0x04 |
| 633 | #define DA9063_GPIO9_NO_WAKEUP 0x80 |
| 634 | |
| 635 | /* DA9063_REG_GPIO_10_11 (addr=0x1A) */ |
| 636 | #define DA9063_GPIO10_PIN_MASK 0x03 |
| 637 | #define DA9063_GPIO10_PIN_GPI_PWR1_EN 0x00 |
| 638 | #define DA9063_GPIO10_PIN_GPI 0x01 |
| 639 | #define DA9063_GPIO10_PIN_GPO_OD 0x02 |
| 640 | #define DA9063_GPIO10_PIN_GPO 0x03 |
| 641 | #define DA9063_GPIO10_TYPE 0x04 |
| 642 | #define DA9063_GPIO10_TYPE_GPI_ACT_LOW 0x00 |
| 643 | #define DA9063_GPIO10_TYPE_GPO_VDD_IO1 0x00 |
| 644 | #define DA9063_GPIO10_TYPE_GPI_ACT_HIGH 0x04 |
| 645 | #define DA9063_GPIO10_TYPE_GPO_VDD_IO2 0x04 |
| 646 | #define DA9063_GPIO10_NO_WAKEUP 0x08 |
| 647 | #define DA9063_GPIO11_PIN_MASK 0x30 |
| 648 | #define DA9063_GPIO11_PIN_GPO_OD 0x00 |
| 649 | #define DA9063_GPIO11_PIN_GPI 0x10 |
| 650 | #define DA9063_GPIO11_PIN_GPO_PSS 0x20 |
| 651 | #define DA9063_GPIO11_PIN_GPO 0x30 |
| 652 | #define DA9063_GPIO11_TYPE 0x40 |
| 653 | #define DA9063_GPIO11_TYPE_GPI_ACT_LOW 0x00 |
| 654 | #define DA9063_GPIO11_TYPE_GPO_VDD_IO1 0x00 |
| 655 | #define DA9063_GPIO11_TYPE_GPI_ACT_HIGH 0x04 |
| 656 | #define DA9063_GPIO11_TYPE_GPO_VDD_IO2 0x04 |
| 657 | #define DA9063_GPIO11_NO_WAKEUP 0x80 |
| 658 | |
| 659 | /* DA9063_REG_GPIO_12_13 (addr=0x1B) */ |
| 660 | #define DA9063_GPIO12_PIN_MASK 0x03 |
| 661 | #define DA9063_GPIO12_PIN_NVDDFLT_OUT 0x00 |
| 662 | #define DA9063_GPIO12_PIN_GPI 0x01 |
| 663 | #define DA9063_GPIO12_PIN_VSYSMON_OUT 0x02 |
| 664 | #define DA9063_GPIO12_PIN_GPO 0x03 |
| 665 | #define DA9063_GPIO12_TYPE 0x04 |
| 666 | #define DA9063_GPIO12_TYPE_GPI_ACT_LOW 0x00 |
| 667 | #define DA9063_GPIO12_TYPE_GPO_VDD_IO1 0x00 |
| 668 | #define DA9063_GPIO12_TYPE_GPI_ACT_HIGH 0x04 |
| 669 | #define DA9063_GPIO12_TYPE_GPO_VDD_IO2 0x04 |
| 670 | #define DA9063_GPIO12_NO_WAKEUP 0x08 |
| 671 | #define DA9063_GPIO13_PIN_MASK 0x30 |
| 672 | #define DA9063_GPIO13_PIN_GPFB1_OUT 0x00 |
| 673 | #define DA9063_GPIO13_PIN_GPI 0x10 |
| 674 | #define DA9063_GPIO13_PIN_GPFB1_OUTOD 0x20 |
| 675 | #define DA9063_GPIO13_PIN_GPO 0x30 |
| 676 | #define DA9063_GPIO13_TYPE 0x40 |
| 677 | #define DA9063_GPIO13_TYPE_GPFB1_OUT 0x00 |
| 678 | #define DA9063_GPIO13_TYPE_GPI 0x00 |
| 679 | #define DA9063_GPIO13_TYPE_GPFB1_OUTOD 0x04 |
| 680 | #define DA9063_GPIO13_TYPE_GPO 0x04 |
| 681 | #define DA9063_GPIO13_NO_WAKEUP 0x80 |
| 682 | |
| 683 | /* DA9063_REG_GPIO_14_15 (addr=0x1C) */ |
| 684 | #define DA9063_GPIO14_PIN_MASK 0x03 |
| 685 | #define DA9063_GPIO14_PIN_GPO_OD 0x00 |
| 686 | #define DA9063_GPIO14_PIN_GPI 0x01 |
| 687 | #define DA9063_GPIO14_PIN_HS2DATA 0x02 |
| 688 | #define DA9063_GPIO14_PIN_GPO 0x03 |
| 689 | #define DA9063_GPIO14_TYPE 0x04 |
| 690 | #define DA9063_GPIO14_TYPE_GPI_ACT_LOW 0x00 |
| 691 | #define DA9063_GPIO14_TYPE_GPO_VDD_IO1 0x00 |
| 692 | #define DA9063_GPIO14_TYPE_GPI_ACT_HIGH 0x04 |
| 693 | #define DA9063_GPIO14_TYPE_GPO_VDD_IO2 0x04 |
| 694 | #define DA9063_GPIO14_NO_WAKEUP 0x08 |
| 695 | #define DA9063_GPIO15_PIN_MASK 0x30 |
| 696 | #define DA9063_GPIO15_PIN_GPO_OD 0x00 |
| 697 | #define DA9063_GPIO15_PIN_GPI 0x10 |
| 698 | #define DA9063_GPIO15_PIN_GPO 0x30 |
| 699 | #define DA9063_GPIO15_TYPE 0x40 |
| 700 | #define DA9063_GPIO15_TYPE_GPFB1_OUT 0x00 |
| 701 | #define DA9063_GPIO15_TYPE_GPI 0x00 |
| 702 | #define DA9063_GPIO15_TYPE_GPFB1_OUTOD 0x04 |
| 703 | #define DA9063_GPIO15_TYPE_GPO 0x04 |
| 704 | #define DA9063_GPIO15_NO_WAKEUP 0x80 |
| 705 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 706 | /* DA9063_REG_GPIO_MODE0_7 (addr=0x1D) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 707 | #define DA9063_GPIO0_MODE 0x01 |
| 708 | #define DA9063_GPIO1_MODE 0x02 |
| 709 | #define DA9063_GPIO2_MODE 0x04 |
| 710 | #define DA9063_GPIO3_MODE 0x08 |
| 711 | #define DA9063_GPIO4_MODE 0x10 |
| 712 | #define DA9063_GPIO5_MODE 0x20 |
| 713 | #define DA9063_GPIO6_MODE 0x40 |
| 714 | #define DA9063_GPIO7_MODE 0x80 |
| 715 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 716 | /* DA9063_REG_GPIO_MODE8_15 (addr=0x1E) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 717 | #define DA9063_GPIO8_MODE 0x01 |
| 718 | #define DA9063_GPIO9_MODE 0x02 |
| 719 | #define DA9063_GPIO10_MODE 0x04 |
| 720 | #define DA9063_GPIO11_MODE 0x08 |
| 721 | #define DA9063_GPIO11_MODE_LED_ACT_HIGH 0x00 |
| 722 | #define DA9063_GPIO11_MODE_LED_ACT_LOW 0x08 |
| 723 | #define DA9063_GPIO12_MODE 0x10 |
| 724 | #define DA9063_GPIO13_MODE 0x20 |
| 725 | #define DA9063_GPIO14_MODE 0x40 |
| 726 | #define DA9063_GPIO14_MODE_LED_ACT_HIGH 0x00 |
| 727 | #define DA9063_GPIO14_MODE_LED_ACT_LOW 0x40 |
| 728 | #define DA9063_GPIO15_MODE 0x80 |
| 729 | #define DA9063_GPIO15_MODE_LED_ACT_HIGH 0x00 |
| 730 | #define DA9063_GPIO15_MODE_LED_ACT_LOW 0x80 |
| 731 | |
| 732 | /* DA9063_REG_SWITCH_CONT (addr=0x1F) */ |
| 733 | #define DA9063_CORE_SW_GPI_MASK 0x03 |
| 734 | #define DA9063_CORE_SW_GPI_OFF 0x00 |
| 735 | #define DA9063_CORE_SW_GPI_GPIO1 0x01 |
| 736 | #define DA9063_CORE_SW_GPI_GPIO2 0x02 |
| 737 | #define DA9063_CORE_SW_GPI_GPIO13 0x03 |
| 738 | #define DA9063_PERI_SW_GPI_MASK 0x0C |
| 739 | #define DA9063_PERI_SW_GPI_OFF 0x00 |
| 740 | #define DA9063_PERI_SW_GPI_GPIO1 0x04 |
| 741 | #define DA9063_PERI_SW_GPI_GPIO2 0x08 |
| 742 | #define DA9063_PERI_SW_GPI_GPIO13 0x0C |
| 743 | #define DA9063_SWITCH_SR_MASK 0x30 |
| 744 | #define DA9063_SWITCH_SR_1MV 0x00 |
| 745 | #define DA9063_SWITCH_SR_5MV 0x10 |
| 746 | #define DA9063_SWITCH_SR_10MV 0x20 |
| 747 | #define DA9063_SWITCH_SR_50MV 0x30 |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 748 | #define DA9063_CORE_SW_INTERNAL 0x40 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 749 | #define DA9063_CP_EN_MODE 0x80 |
| 750 | |
| 751 | /* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */ |
| 752 | #define DA9063_BUCK_EN 0x01 |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 753 | #define DA9063_BUCK_GPI_MASK 0x06 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 754 | #define DA9063_BUCK_GPI_OFF 0x00 |
| 755 | #define DA9063_BUCK_GPI_GPIO1 0x02 |
| 756 | #define DA9063_BUCK_GPI_GPIO2 0x04 |
| 757 | #define DA9063_BUCK_GPI_GPIO13 0x06 |
| 758 | #define DA9063_BUCK_CONF 0x08 |
| 759 | #define DA9063_VBUCK_GPI_MASK 0x60 |
| 760 | #define DA9063_VBUCK_GPI_OFF 0x00 |
| 761 | #define DA9063_VBUCK_GPI_GPIO1 0x20 |
| 762 | #define DA9063_VBUCK_GPI_GPIO2 0x40 |
| 763 | #define DA9063_VBUCK_GPI_GPIO13 0x60 |
| 764 | |
| 765 | /* DA9063_REG_BCORE1_CONT specific bits (addr=0x21) */ |
| 766 | #define DA9063_CORE_SW_EN 0x10 |
| 767 | #define DA9063_CORE_SW_CONF 0x80 |
| 768 | |
| 769 | /* DA9063_REG_BPERI_CONT specific bits (addr=0x25) */ |
| 770 | #define DA9063_PERI_SW_EN 0x10 |
| 771 | #define DA9063_PERI_SW_CONF 0x80 |
| 772 | |
| 773 | /* DA9063_REG_LDOx_CONT common bits (addr=0x26-0x30) */ |
| 774 | #define DA9063_LDO_EN 0x01 |
| 775 | #define DA9063_LDO_GPI_MASK 0x06 |
| 776 | #define DA9063_LDO_GPI_OFF 0x00 |
| 777 | #define DA9063_LDO_GPI_GPIO1 0x02 |
| 778 | #define DA9063_LDO_GPI_GPIO2 0x04 |
| 779 | #define DA9063_LDO_GPI_GPIO13 0x06 |
| 780 | #define DA9063_LDO_PD_DIS 0x08 |
| 781 | #define DA9063_VLDO_GPI_MASK 0x60 |
| 782 | #define DA9063_VLDO_GPI_OFF 0x00 |
| 783 | #define DA9063_VLDO_GPI_GPIO1 0x20 |
| 784 | #define DA9063_VLDO_GPI_GPIO2 0x40 |
| 785 | #define DA9063_VLDO_GPI_GPIO13 0x60 |
| 786 | #define DA9063_LDO_CONF 0x80 |
| 787 | |
| 788 | /* DA9063_REG_LDO5_CONT specific bits (addr=0x2A) */ |
| 789 | #define DA9063_VLDO5_SEL 0x10 |
| 790 | |
| 791 | /* DA9063_REG_LDO6_CONT specific bits (addr=0x2B) */ |
| 792 | #define DA9063_VLDO6_SEL 0x10 |
| 793 | |
| 794 | /* DA9063_REG_LDO7_CONT specific bits (addr=0x2C) */ |
| 795 | #define DA9063_VLDO7_SEL 0x10 |
| 796 | |
| 797 | /* DA9063_REG_LDO8_CONT specific bits (addr=0x2D) */ |
| 798 | #define DA9063_VLDO8_SEL 0x10 |
| 799 | |
| 800 | /* DA9063_REG_LDO9_CONT specific bits (addr=0x2E) */ |
| 801 | #define DA9063_VLDO9_SEL 0x10 |
| 802 | |
| 803 | /* DA9063_REG_LDO10_CONT specific bits (addr=0x2F) */ |
| 804 | #define DA9063_VLDO10_SEL 0x10 |
| 805 | |
| 806 | /* DA9063_REG_LDO11_CONT specific bits (addr=0x30) */ |
| 807 | #define DA9063_VLDO11_SEL 0x10 |
| 808 | |
| 809 | /* DA9063_REG_VIB (addr=0x31) */ |
| 810 | #define DA9063_VIB_SET_MASK 0x3F |
| 811 | #define DA9063_VIB_SET_OFF 0 |
| 812 | #define DA9063_VIB_SET_MAX 0x3F |
| 813 | |
| 814 | /* DA9063_REG_DVC_1 (addr=0x32) */ |
| 815 | #define DA9063_VBCORE1_SEL 0x01 |
| 816 | #define DA9063_VBCORE2_SEL 0x02 |
| 817 | #define DA9063_VBPRO_SEL 0x04 |
| 818 | #define DA9063_VBMEM_SEL 0x08 |
| 819 | #define DA9063_VBPERI_SEL 0x10 |
| 820 | #define DA9063_VLDO1_SEL 0x20 |
| 821 | #define DA9063_VLDO2_SEL 0x40 |
| 822 | #define DA9063_VLDO3_SEL 0x80 |
| 823 | |
| 824 | /* DA9063_REG_DVC_2 (addr=0x33) */ |
| 825 | #define DA9063_VBIO_SEL 0x01 |
| 826 | #define DA9063_VLDO4_SEL 0x80 |
| 827 | |
| 828 | /* DA9063_REG_ADC_MAN (addr=0x34) */ |
| 829 | #define DA9063_ADC_MUX_MASK 0x0F |
| 830 | #define DA9063_ADC_MUX_VSYS 0x00 |
| 831 | #define DA9063_ADC_MUX_ADCIN1 0x01 |
| 832 | #define DA9063_ADC_MUX_ADCIN2 0x02 |
| 833 | #define DA9063_ADC_MUX_ADCIN3 0x03 |
| 834 | #define DA9063_ADC_MUX_T_SENSE 0x04 |
| 835 | #define DA9063_ADC_MUX_VBBAT 0x05 |
| 836 | #define DA9063_ADC_MUX_LDO_G1 0x08 |
| 837 | #define DA9063_ADC_MUX_LDO_G2 0x09 |
| 838 | #define DA9063_ADC_MUX_LDO_G3 0x0A |
| 839 | #define DA9063_ADC_MAN 0x10 |
| 840 | #define DA9063_ADC_MODE 0x20 |
| 841 | |
| 842 | /* DA9063_REG_ADC_CONT (addr=0x35) */ |
| 843 | #define DA9063_ADC_AUTO_VSYS_EN 0x01 |
| 844 | #define DA9063_ADC_AUTO_AD1_EN 0x02 |
| 845 | #define DA9063_ADC_AUTO_AD2_EN 0x04 |
| 846 | #define DA9063_ADC_AUTO_AD3_EN 0x08 |
| 847 | #define DA9063_ADC_AD1_ISRC_EN 0x10 |
| 848 | #define DA9063_ADC_AD2_ISRC_EN 0x20 |
| 849 | #define DA9063_ADC_AD3_ISRC_EN 0x40 |
| 850 | #define DA9063_COMP1V2_EN 0x80 |
| 851 | |
| 852 | /* DA9063_REG_VSYS_MON (addr=0x36) */ |
| 853 | #define DA9063_VSYS_VAL_MASK 0xFF |
| 854 | #define DA9063_VSYS_VAL_BASE 0x00 |
| 855 | |
| 856 | /* DA9063_REG_ADC_RES_L (addr=0x37) */ |
| 857 | #define DA9063_ADC_RES_L_BITS 2 |
| 858 | #define DA9063_ADC_RES_L_MASK 0xC0 |
| 859 | |
| 860 | /* DA9063_REG_ADC_RES_H (addr=0x38) */ |
| 861 | #define DA9063_ADC_RES_M_BITS 8 |
| 862 | #define DA9063_ADC_RES_M_MASK 0xFF |
| 863 | |
| 864 | /* DA9063_REG_(xxx_RES/ADC_RES_H) (addr=0x39-0x3F) */ |
| 865 | #define DA9063_ADC_VAL_MASK 0xFF |
| 866 | |
| 867 | /* DA9063_REG_COUNT_S (addr=0x40) */ |
| 868 | #define DA9063_RTC_READ 0x80 |
| 869 | #define DA9063_COUNT_SEC_MASK 0x3F |
| 870 | |
| 871 | /* DA9063_REG_COUNT_MI (addr=0x41) */ |
| 872 | #define DA9063_COUNT_MIN_MASK 0x3F |
| 873 | |
| 874 | /* DA9063_REG_COUNT_H (addr=0x42) */ |
| 875 | #define DA9063_COUNT_HOUR_MASK 0x1F |
| 876 | |
| 877 | /* DA9063_REG_COUNT_D (addr=0x43) */ |
| 878 | #define DA9063_COUNT_DAY_MASK 0x1F |
| 879 | |
| 880 | /* DA9063_REG_COUNT_MO (addr=0x44) */ |
| 881 | #define DA9063_COUNT_MONTH_MASK 0x0F |
| 882 | |
| 883 | /* DA9063_REG_COUNT_Y (addr=0x45) */ |
| 884 | #define DA9063_COUNT_YEAR_MASK 0x3F |
| 885 | #define DA9063_MONITOR 0x40 |
| 886 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 887 | /* DA9063_REG_ALARM_S (addr=0x46) */ |
Opensource [Steve Twiss] | 9cb42e2 | 2014-07-21 11:39:33 +0100 | [diff] [blame] | 888 | #define DA9063_BB_ALARM_S_MASK 0x3F |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 889 | #define DA9063_ALARM_STATUS_ALARM 0x80 |
| 890 | #define DA9063_ALARM_STATUS_TICK 0x40 |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 891 | /* DA9063_REG_ALARM_MI (addr=0x47) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 892 | #define DA9063_ALARM_MIN_MASK 0x3F |
| 893 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 894 | /* DA9063_REG_ALARM_H (addr=0x48) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 895 | #define DA9063_ALARM_HOUR_MASK 0x1F |
| 896 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 897 | /* DA9063_REG_ALARM_D (addr=0x49) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 898 | #define DA9063_ALARM_DAY_MASK 0x1F |
| 899 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 900 | /* DA9063_REG_ALARM_MO (addr=0x4A) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 901 | #define DA9063_TICK_WAKE 0x20 |
| 902 | #define DA9063_TICK_TYPE 0x10 |
| 903 | #define DA9063_TICK_TYPE_SEC 0x00 |
| 904 | #define DA9063_TICK_TYPE_MIN 0x10 |
| 905 | #define DA9063_ALARM_MONTH_MASK 0x0F |
| 906 | |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 907 | /* DA9063_REG_ALARM_Y (addr=0x4B) */ |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 908 | #define DA9063_TICK_ON 0x80 |
| 909 | #define DA9063_ALARM_ON 0x40 |
| 910 | #define DA9063_ALARM_YEAR_MASK 0x3F |
| 911 | |
| 912 | /* DA9063_REG_WAIT (addr=0x97)*/ |
| 913 | #define DA9063_REG_WAIT_TIME_MASK 0xF |
| 914 | #define DA9063_WAIT_TIME_0_US 0x0 |
| 915 | #define DA9063_WAIT_TIME_512_US 0x1 |
| 916 | #define DA9063_WAIT_TIME_1_MS 0x2 |
| 917 | #define DA9063_WAIT_TIME_2_MS 0x3 |
| 918 | #define DA9063_WAIT_TIME_4_1_MS 0x4 |
| 919 | #define DA9063_WAIT_TIME_8_2_MS 0x5 |
| 920 | #define DA9063_WAIT_TIME_16_4_MS 0x6 |
| 921 | #define DA9063_WAIT_TIME_32_8_MS 0x7 |
| 922 | #define DA9063_WAIT_TIME_65_5_MS 0x8 |
| 923 | #define DA9063_WAIT_TIME_128_MS 0x9 |
| 924 | #define DA9063_WAIT_TIME_256_MS 0xA |
| 925 | #define DA9063_WAIT_TIME_512_MS 0xB |
| 926 | #define DA9063_WAIT_TIME_1_S 0xC |
| 927 | #define DA9063_WAIT_TIME_2_1_S 0xD |
| 928 | |
| 929 | /* DA9063_REG_EN_32K (addr=0x98)*/ |
| 930 | #define DA9063_STABILIZ_TIME_MASK 0x7 |
| 931 | #define DA9063_CRYSTAL 0x08 |
| 932 | #define DA9063_DELAY_MODE 0x10 |
| 933 | #define DA9063_OUT_CLOCK 0x20 |
| 934 | #define DA9063_RTC_CLOCK 0x40 |
| 935 | #define DA9063_OUT_32K_EN 0x80 |
| 936 | |
| 937 | /* DA9063_REG_CHIP_VARIANT */ |
| 938 | #define DA9063_CHIP_VARIANT_SHIFT 4 |
| 939 | |
| 940 | /* DA9063_REG_BUCK_ILIM_A (addr=0x9A) */ |
| 941 | #define DA9063_BIO_ILIM_MASK 0x0F |
| 942 | #define DA9063_BMEM_ILIM_MASK 0xF0 |
| 943 | |
| 944 | /* DA9063_REG_BUCK_ILIM_B (addr=0x9B) */ |
| 945 | #define DA9063_BPRO_ILIM_MASK 0x0F |
| 946 | #define DA9063_BPERI_ILIM_MASK 0xF0 |
| 947 | |
| 948 | /* DA9063_REG_BUCK_ILIM_C (addr=0x9C) */ |
| 949 | #define DA9063_BCORE1_ILIM_MASK 0x0F |
| 950 | #define DA9063_BCORE2_ILIM_MASK 0xF0 |
| 951 | |
| 952 | /* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */ |
| 953 | #define DA9063_BUCK_FB_MASK 0x07 |
Opensource [Steve Twiss] | 9fc2b9c | 2014-03-06 16:40:02 +0000 | [diff] [blame] | 954 | #define DA9063_BUCK_PD_DIS_MASK 0x20 |
Krystian Garbaciak | 36ec66e | 2013-07-29 19:00:42 +0200 | [diff] [blame] | 955 | #define DA9063_BUCK_MODE_MASK 0xC0 |
| 956 | #define DA9063_BUCK_MODE_MANUAL 0x00 |
| 957 | #define DA9063_BUCK_MODE_SLEEP 0x40 |
| 958 | #define DA9063_BUCK_MODE_SYNC 0x80 |
| 959 | #define DA9063_BUCK_MODE_AUTO 0xC0 |
| 960 | |
| 961 | /* DA9063_REG_BPRO_CFG (addr=0x9F) */ |
| 962 | #define DA9063_BPRO_VTTR_EN 0x08 |
| 963 | #define DA9063_BPRO_VTT_EN 0x10 |
| 964 | |
| 965 | /* DA9063_REG_VBxxxx_A/B (addr=0xA3-0xA8, 0xB4-0xB9) */ |
| 966 | #define DA9063_VBUCK_MASK 0x7F |
| 967 | #define DA9063_VBUCK_BIAS 0 |
| 968 | #define DA9063_BUCK_SL 0x80 |
| 969 | |
| 970 | /* DA9063_REG_VLDOx_A/B (addr=0xA9-0x3, 0xBA-0xC4) */ |
| 971 | #define DA9063_LDO_SL 0x80 |
| 972 | |
| 973 | /* DA9063_REG_VLDO1_A/B (addr=0xA9, 0xBA) */ |
| 974 | #define DA9063_VLDO1_MASK 0x3F |
| 975 | #define DA9063_VLDO1_BIAS 0 |
| 976 | |
| 977 | /* DA9063_REG_VLDO2_A/B (addr=0xAA, 0xBB) */ |
| 978 | #define DA9063_VLDO2_MASK 0x3F |
| 979 | #define DA9063_VLDO2_BIAS 0 |
| 980 | |
| 981 | /* DA9063_REG_VLDO3_A/B (addr=0xAB, 0xBC) */ |
| 982 | #define DA9063_VLDO3_MASK 0x7F |
| 983 | #define DA9063_VLDO3_BIAS 0 |
| 984 | |
| 985 | /* DA9063_REG_VLDO4_A/B (addr=0xAC, 0xBD) */ |
| 986 | #define DA9063_VLDO4_MASK 0x7F |
| 987 | #define DA9063_VLDO4_BIAS 0 |
| 988 | |
| 989 | /* DA9063_REG_VLDO5_A/B (addr=0xAD, 0xBE) */ |
| 990 | #define DA9063_VLDO5_MASK 0x3F |
| 991 | #define DA9063_VLDO5_BIAS 2 |
| 992 | |
| 993 | /* DA9063_REG_VLDO6_A/B (addr=0xAE, 0xBF) */ |
| 994 | #define DA9063_VLDO6_MASK 0x3F |
| 995 | #define DA9063_VLDO6_BIAS 2 |
| 996 | |
| 997 | /* DA9063_REG_VLDO7_A/B (addr=0xAF, 0xC0) */ |
| 998 | #define DA9063_VLDO7_MASK 0x3F |
| 999 | #define DA9063_VLDO7_BIAS 2 |
| 1000 | |
| 1001 | /* DA9063_REG_VLDO8_A/B (addr=0xB0, 0xC1) */ |
| 1002 | #define DA9063_VLDO8_MASK 0x3F |
| 1003 | #define DA9063_VLDO8_BIAS 2 |
| 1004 | |
| 1005 | /* DA9063_REG_VLDO9_A/B (addr=0xB1, 0xC2) */ |
| 1006 | #define DA9063_VLDO9_MASK 0x3F |
| 1007 | #define DA9063_VLDO9_BIAS 3 |
| 1008 | |
| 1009 | /* DA9063_REG_VLDO10_A/B (addr=0xB2, 0xC3) */ |
| 1010 | #define DA9063_VLDO10_MASK 0x3F |
| 1011 | #define DA9063_VLDO10_BIAS 2 |
| 1012 | |
| 1013 | /* DA9063_REG_VLDO11_A/B (addr=0xB3, 0xC4) */ |
| 1014 | #define DA9063_VLDO11_MASK 0x3F |
| 1015 | #define DA9063_VLDO11_BIAS 2 |
| 1016 | |
| 1017 | /* DA9063_REG_GPO11_LED (addr=0xC6) */ |
| 1018 | /* DA9063_REG_GPO14_LED (addr=0xC7) */ |
| 1019 | /* DA9063_REG_GPO15_LED (addr=0xC8) */ |
| 1020 | #define DA9063_GPIO_DIM 0x80 |
| 1021 | #define DA9063_GPIO_PWM_MASK 0x7F |
| 1022 | |
| 1023 | /* DA9063_REG_CONFIG_H (addr=0x10D) */ |
| 1024 | #define DA9063_PWM_CLK_MASK 0x01 |
| 1025 | #define DA9063_PWM_CLK_PWM2MHZ 0x00 |
| 1026 | #define DA9063_PWM_CLK_PWM1MHZ 0x01 |
| 1027 | #define DA9063_LDO8_MODE_MASK 0x02 |
| 1028 | #define DA9063_LDO8_MODE_LDO 0 |
| 1029 | #define DA9063_LDO8_MODE_VIBR 0x02 |
| 1030 | #define DA9063_MERGE_SENSE_MASK 0x04 |
| 1031 | #define DA9063_MERGE_SENSE_GP_FB2 0x00 |
| 1032 | #define DA9063_MERGE_SENSE_GPIO4 0x04 |
| 1033 | #define DA9063_BCORE_MERGE 0x08 |
| 1034 | #define DA9063_BPRO_OD 0x10 |
| 1035 | #define DA9063_BCORE2_OD 0x20 |
| 1036 | #define DA9063_BCORE1_OD 0x40 |
| 1037 | #define DA9063_BUCK_MERGE 0x80 |
| 1038 | |
| 1039 | /* DA9063_REG_CONFIG_I (addr=0x10E) */ |
| 1040 | #define DA9063_NONKEY_PIN_MASK 0x03 |
| 1041 | #define DA9063_NONKEY_PIN_PORT 0x00 |
| 1042 | #define DA9063_NONKEY_PIN_SWDOWN 0x01 |
| 1043 | #define DA9063_NONKEY_PIN_AUTODOWN 0x02 |
| 1044 | #define DA9063_NONKEY_PIN_AUTOFLPRT 0x03 |
| 1045 | |
| 1046 | /* DA9063_REG_MON_REG_5 (addr=0x116) */ |
| 1047 | #define DA9063_MON_A8_IDX_MASK 0x07 |
| 1048 | #define DA9063_MON_A8_IDX_NONE 0x00 |
| 1049 | #define DA9063_MON_A8_IDX_BCORE1 0x01 |
| 1050 | #define DA9063_MON_A8_IDX_BCORE2 0x02 |
| 1051 | #define DA9063_MON_A8_IDX_BPRO 0x03 |
| 1052 | #define DA9063_MON_A8_IDX_LDO3 0x04 |
| 1053 | #define DA9063_MON_A8_IDX_LDO4 0x05 |
| 1054 | #define DA9063_MON_A8_IDX_LDO11 0x06 |
| 1055 | #define DA9063_MON_A9_IDX_MASK 0x70 |
| 1056 | #define DA9063_MON_A9_IDX_NONE 0x00 |
| 1057 | #define DA9063_MON_A9_IDX_BIO 0x01 |
| 1058 | #define DA9063_MON_A9_IDX_BMEM 0x02 |
| 1059 | #define DA9063_MON_A9_IDX_BPERI 0x03 |
| 1060 | #define DA9063_MON_A9_IDX_LDO1 0x04 |
| 1061 | #define DA9063_MON_A9_IDX_LDO2 0x05 |
| 1062 | #define DA9063_MON_A9_IDX_LDO5 0x06 |
| 1063 | |
| 1064 | /* DA9063_REG_MON_REG_6 (addr=0x117) */ |
| 1065 | #define DA9063_MON_A10_IDX_MASK 0x07 |
| 1066 | #define DA9063_MON_A10_IDX_NONE 0x00 |
| 1067 | #define DA9063_MON_A10_IDX_LDO6 0x01 |
| 1068 | #define DA9063_MON_A10_IDX_LDO7 0x02 |
| 1069 | #define DA9063_MON_A10_IDX_LDO8 0x03 |
| 1070 | #define DA9063_MON_A10_IDX_LDO9 0x04 |
| 1071 | #define DA9063_MON_A10_IDX_LDO10 0x05 |
| 1072 | |
| 1073 | #endif /* _DA9063_REG_H */ |