David Daney | e8635b4 | 2009-04-23 17:44:38 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2005-2007 Cavium Networks |
| 7 | */ |
| 8 | #include <linux/kernel.h> |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/pci.h> |
| 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/time.h> |
| 13 | #include <linux/delay.h> |
| 14 | |
| 15 | #include <asm/time.h> |
| 16 | |
| 17 | #include <asm/octeon/octeon.h> |
| 18 | #include <asm/octeon/cvmx-npi-defs.h> |
| 19 | #include <asm/octeon/cvmx-pci-defs.h> |
| 20 | |
| 21 | #include "pci-common.h" |
| 22 | |
| 23 | #define USE_OCTEON_INTERNAL_ARBITER |
| 24 | |
| 25 | /* |
| 26 | * Octeon's PCI controller uses did=3, subdid=2 for PCI IO |
| 27 | * addresses. Use PCI endian swapping 1 so no address swapping is |
| 28 | * necessary. The Linux io routines will endian swap the data. |
| 29 | */ |
| 30 | #define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull |
| 31 | #define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) |
| 32 | |
| 33 | /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ |
| 34 | #define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) |
| 35 | |
| 36 | /** |
| 37 | * This is the bit decoding used for the Octeon PCI controller addresses |
| 38 | */ |
| 39 | union octeon_pci_address { |
| 40 | uint64_t u64; |
| 41 | struct { |
| 42 | uint64_t upper:2; |
| 43 | uint64_t reserved:13; |
| 44 | uint64_t io:1; |
| 45 | uint64_t did:5; |
| 46 | uint64_t subdid:3; |
| 47 | uint64_t reserved2:4; |
| 48 | uint64_t endian_swap:2; |
| 49 | uint64_t reserved3:10; |
| 50 | uint64_t bus:8; |
| 51 | uint64_t dev:5; |
| 52 | uint64_t func:3; |
| 53 | uint64_t reg:8; |
| 54 | } s; |
| 55 | }; |
| 56 | |
| 57 | /** |
| 58 | * Return the mapping of PCI device number to IRQ line. Each |
| 59 | * character in the return string represents the interrupt |
| 60 | * line for the device at that position. Device 1 maps to the |
| 61 | * first character, etc. The characters A-D are used for PCI |
| 62 | * interrupts. |
| 63 | * |
| 64 | * Returns PCI interrupt mapping |
| 65 | */ |
| 66 | const char *octeon_get_pci_interrupts(void) |
| 67 | { |
| 68 | /* |
| 69 | * Returning an empty string causes the interrupts to be |
| 70 | * routed based on the PCI specification. From the PCI spec: |
| 71 | * |
| 72 | * INTA# of Device Number 0 is connected to IRQW on the system |
| 73 | * board. (Device Number has no significance regarding being |
| 74 | * located on the system board or in a connector.) INTA# of |
| 75 | * Device Number 1 is connected to IRQX on the system |
| 76 | * board. INTA# of Device Number 2 is connected to IRQY on the |
| 77 | * system board. INTA# of Device Number 3 is connected to IRQZ |
| 78 | * on the system board. The table below describes how each |
| 79 | * agent's INTx# lines are connected to the system board |
| 80 | * interrupt lines. The following equation can be used to |
| 81 | * determine to which INTx# signal on the system board a given |
| 82 | * device's INTx# line(s) is connected. |
| 83 | * |
| 84 | * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0, |
| 85 | * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I = |
| 86 | * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and |
| 87 | * INTD# = 3) |
| 88 | */ |
| 89 | switch (octeon_bootinfo->board_type) { |
| 90 | case CVMX_BOARD_TYPE_NAO38: |
| 91 | /* This is really the NAC38 */ |
| 92 | return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; |
| 93 | case CVMX_BOARD_TYPE_THUNDER: |
| 94 | return ""; |
| 95 | case CVMX_BOARD_TYPE_EBH3000: |
| 96 | return ""; |
| 97 | case CVMX_BOARD_TYPE_EBH3100: |
| 98 | case CVMX_BOARD_TYPE_CN3010_EVB_HS5: |
| 99 | case CVMX_BOARD_TYPE_CN3005_EVB_HS5: |
| 100 | return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; |
| 101 | case CVMX_BOARD_TYPE_BBGW_REF: |
| 102 | return "AABCD"; |
| 103 | default: |
| 104 | return ""; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | /** |
| 109 | * Map a PCI device to the appropriate interrupt line |
| 110 | * |
| 111 | * @dev: The Linux PCI device structure for the device to map |
| 112 | * @slot: The slot number for this device on __BUS 0__. Linux |
| 113 | * enumerates through all the bridges and figures out the |
| 114 | * slot on Bus 0 where this device eventually hooks to. |
| 115 | * @pin: The PCI interrupt pin read from the device, then swizzled |
| 116 | * as it goes through each bridge. |
| 117 | * Returns Interrupt number for the device |
| 118 | */ |
| 119 | int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, |
| 120 | u8 slot, u8 pin) |
| 121 | { |
| 122 | int irq_num; |
| 123 | const char *interrupts; |
| 124 | int dev_num; |
| 125 | |
| 126 | /* Get the board specific interrupt mapping */ |
| 127 | interrupts = octeon_get_pci_interrupts(); |
| 128 | |
| 129 | dev_num = dev->devfn >> 3; |
| 130 | if (dev_num < strlen(interrupts)) |
| 131 | irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) + |
| 132 | OCTEON_IRQ_PCI_INT0; |
| 133 | else |
| 134 | irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0; |
| 135 | return irq_num; |
| 136 | } |
| 137 | |
| 138 | |
| 139 | /** |
| 140 | * Read a value from configuration space |
| 141 | * |
| 142 | */ |
| 143 | static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, |
| 144 | int reg, int size, u32 *val) |
| 145 | { |
| 146 | union octeon_pci_address pci_addr; |
| 147 | |
| 148 | pci_addr.u64 = 0; |
| 149 | pci_addr.s.upper = 2; |
| 150 | pci_addr.s.io = 1; |
| 151 | pci_addr.s.did = 3; |
| 152 | pci_addr.s.subdid = 1; |
| 153 | pci_addr.s.endian_swap = 1; |
| 154 | pci_addr.s.bus = bus->number; |
| 155 | pci_addr.s.dev = devfn >> 3; |
| 156 | pci_addr.s.func = devfn & 0x7; |
| 157 | pci_addr.s.reg = reg; |
| 158 | |
| 159 | #if PCI_CONFIG_SPACE_DELAY |
| 160 | udelay(PCI_CONFIG_SPACE_DELAY); |
| 161 | #endif |
| 162 | switch (size) { |
| 163 | case 4: |
| 164 | *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); |
| 165 | return PCIBIOS_SUCCESSFUL; |
| 166 | case 2: |
| 167 | *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); |
| 168 | return PCIBIOS_SUCCESSFUL; |
| 169 | case 1: |
| 170 | *val = cvmx_read64_uint8(pci_addr.u64); |
| 171 | return PCIBIOS_SUCCESSFUL; |
| 172 | } |
| 173 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
| 174 | } |
| 175 | |
| 176 | |
| 177 | /** |
| 178 | * Write a value to PCI configuration space |
| 179 | * |
| 180 | * @bus: |
| 181 | * @devfn: |
| 182 | * @reg: |
| 183 | * @size: |
| 184 | * @val: |
| 185 | * Returns |
| 186 | */ |
| 187 | static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, |
| 188 | int reg, int size, u32 val) |
| 189 | { |
| 190 | union octeon_pci_address pci_addr; |
| 191 | |
| 192 | pci_addr.u64 = 0; |
| 193 | pci_addr.s.upper = 2; |
| 194 | pci_addr.s.io = 1; |
| 195 | pci_addr.s.did = 3; |
| 196 | pci_addr.s.subdid = 1; |
| 197 | pci_addr.s.endian_swap = 1; |
| 198 | pci_addr.s.bus = bus->number; |
| 199 | pci_addr.s.dev = devfn >> 3; |
| 200 | pci_addr.s.func = devfn & 0x7; |
| 201 | pci_addr.s.reg = reg; |
| 202 | |
| 203 | #if PCI_CONFIG_SPACE_DELAY |
| 204 | udelay(PCI_CONFIG_SPACE_DELAY); |
| 205 | #endif |
| 206 | switch (size) { |
| 207 | case 4: |
| 208 | cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); |
| 209 | return PCIBIOS_SUCCESSFUL; |
| 210 | case 2: |
| 211 | cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); |
| 212 | return PCIBIOS_SUCCESSFUL; |
| 213 | case 1: |
| 214 | cvmx_write64_uint8(pci_addr.u64, val); |
| 215 | return PCIBIOS_SUCCESSFUL; |
| 216 | } |
| 217 | return PCIBIOS_FUNC_NOT_SUPPORTED; |
| 218 | } |
| 219 | |
| 220 | |
| 221 | static struct pci_ops octeon_pci_ops = { |
| 222 | octeon_read_config, |
| 223 | octeon_write_config, |
| 224 | }; |
| 225 | |
| 226 | static struct resource octeon_pci_mem_resource = { |
| 227 | .start = 0, |
| 228 | .end = 0, |
| 229 | .name = "Octeon PCI MEM", |
| 230 | .flags = IORESOURCE_MEM, |
| 231 | }; |
| 232 | |
| 233 | /* |
| 234 | * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI |
| 235 | * bridge |
| 236 | */ |
| 237 | static struct resource octeon_pci_io_resource = { |
| 238 | .start = 0x4000, |
| 239 | .end = OCTEON_PCI_IOSPACE_SIZE - 1, |
| 240 | .name = "Octeon PCI IO", |
| 241 | .flags = IORESOURCE_IO, |
| 242 | }; |
| 243 | |
| 244 | static struct pci_controller octeon_pci_controller = { |
| 245 | .pci_ops = &octeon_pci_ops, |
| 246 | .mem_resource = &octeon_pci_mem_resource, |
| 247 | .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET, |
| 248 | .io_resource = &octeon_pci_io_resource, |
| 249 | .io_offset = 0, |
| 250 | .io_map_base = OCTEON_PCI_IOSPACE_BASE, |
| 251 | }; |
| 252 | |
| 253 | |
| 254 | /** |
| 255 | * Low level initialize the Octeon PCI controller |
| 256 | * |
| 257 | * Returns |
| 258 | */ |
| 259 | static void octeon_pci_initialize(void) |
| 260 | { |
| 261 | union cvmx_pci_cfg01 cfg01; |
| 262 | union cvmx_npi_ctl_status ctl_status; |
| 263 | union cvmx_pci_ctl_status_2 ctl_status_2; |
| 264 | union cvmx_pci_cfg19 cfg19; |
| 265 | union cvmx_pci_cfg16 cfg16; |
| 266 | union cvmx_pci_cfg22 cfg22; |
| 267 | union cvmx_pci_cfg56 cfg56; |
| 268 | |
| 269 | /* Reset the PCI Bus */ |
| 270 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); |
| 271 | cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
| 272 | |
| 273 | udelay(2000); /* Hold PCI reset for 2 ms */ |
| 274 | |
| 275 | ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */ |
| 276 | ctl_status.s.max_word = 1; |
| 277 | ctl_status.s.timer = 1; |
| 278 | cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); |
| 279 | |
| 280 | /* Deassert PCI reset and advertize PCX Host Mode Device Capability |
| 281 | (64b) */ |
| 282 | cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); |
| 283 | cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
| 284 | |
| 285 | udelay(2000); /* Wait 2 ms after deasserting PCI reset */ |
| 286 | |
| 287 | ctl_status_2.u32 = 0; |
| 288 | ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set |
| 289 | before any PCI reads. */ |
| 290 | ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ |
| 291 | ctl_status_2.s.bar2_enb = 1; |
| 292 | ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ |
| 293 | ctl_status_2.s.bar2_esx = 1; |
| 294 | ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ |
| 295 | if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { |
| 296 | /* BAR1 hole */ |
| 297 | ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; |
| 298 | ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ |
| 299 | ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ |
| 300 | ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ |
| 301 | ctl_status_2.s.bb1 = 1; /* BAR1 is big */ |
| 302 | ctl_status_2.s.bb0 = 1; /* BAR0 is big */ |
| 303 | } |
| 304 | |
| 305 | octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); |
| 306 | udelay(2000); /* Wait 2 ms before doing PCI reads */ |
| 307 | |
| 308 | ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); |
| 309 | pr_notice("PCI Status: %s %s-bit\n", |
| 310 | ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", |
| 311 | ctl_status_2.s.ap_64ad ? "64" : "32"); |
| 312 | |
| 313 | if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { |
| 314 | union cvmx_pci_cnt_reg cnt_reg_start; |
| 315 | union cvmx_pci_cnt_reg cnt_reg_end; |
| 316 | unsigned long cycles, pci_clock; |
| 317 | |
| 318 | cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); |
| 319 | cycles = read_c0_cvmcount(); |
| 320 | udelay(1000); |
| 321 | cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); |
| 322 | cycles = read_c0_cvmcount() - cycles; |
| 323 | pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / |
| 324 | (cycles / (mips_hpt_frequency / 1000000)); |
| 325 | pr_notice("PCI Clock: %lu MHz\n", pci_clock); |
| 326 | } |
| 327 | |
| 328 | /* |
| 329 | * TDOMC must be set to one in PCI mode. TDOMC should be set to 4 |
| 330 | * in PCI-X mode to allow four oustanding splits. Otherwise, |
| 331 | * should not change from its reset value. Don't write PCI_CFG19 |
| 332 | * in PCI mode (0x82000001 reset value), write it to 0x82000004 |
| 333 | * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. |
| 334 | * MRBCM -> must be one. |
| 335 | */ |
| 336 | if (ctl_status_2.s.ap_pcix) { |
| 337 | cfg19.u32 = 0; |
| 338 | /* |
| 339 | * Target Delayed/Split request outstanding maximum |
| 340 | * count. [1..31] and 0=32. NOTE: If the user |
| 341 | * programs these bits beyond the Designed Maximum |
| 342 | * outstanding count, then the designed maximum table |
| 343 | * depth will be used instead. No additional |
| 344 | * Deferred/Split transactions will be accepted if |
| 345 | * this outstanding maximum count is |
| 346 | * reached. Furthermore, no additional deferred/split |
| 347 | * transactions will be accepted if the I/O delay/ I/O |
| 348 | * Split Request outstanding maximum is reached. |
| 349 | */ |
| 350 | cfg19.s.tdomc = 4; |
| 351 | /* |
| 352 | * Master Deferred Read Request Outstanding Max Count |
| 353 | * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC |
| 354 | * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 |
| 355 | * 5 2 110 6 3 111 7 3 For example, if these bits are |
| 356 | * programmed to 100, the core can support 2 DAC |
| 357 | * cycles, 4 SAC cycles or a combination of 1 DAC and |
| 358 | * 2 SAC cycles. NOTE: For the PCI-X maximum |
| 359 | * outstanding split transactions, refer to |
| 360 | * CRE0[22:20]. |
| 361 | */ |
| 362 | cfg19.s.mdrrmc = 2; |
| 363 | /* |
| 364 | * Master Request (Memory Read) Byte Count/Byte Enable |
| 365 | * select. 0 = Byte Enables valid. In PCI mode, a |
| 366 | * burst transaction cannot be performed using Memory |
| 367 | * Read command=4?h6. 1 = DWORD Byte Count valid |
| 368 | * (default). In PCI Mode, the memory read byte |
| 369 | * enables are automatically generated by the |
| 370 | * core. Note: N3 Master Request transaction sizes are |
| 371 | * always determined through the |
| 372 | * am_attr[<35:32>|<7:0>] field. |
| 373 | */ |
| 374 | cfg19.s.mrbcm = 1; |
| 375 | octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32); |
| 376 | } |
| 377 | |
| 378 | |
| 379 | cfg01.u32 = 0; |
| 380 | cfg01.s.msae = 1; /* Memory Space Access Enable */ |
| 381 | cfg01.s.me = 1; /* Master Enable */ |
| 382 | cfg01.s.pee = 1; /* PERR# Enable */ |
| 383 | cfg01.s.see = 1; /* System Error Enable */ |
| 384 | cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ |
| 385 | |
| 386 | octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
| 387 | |
| 388 | #ifdef USE_OCTEON_INTERNAL_ARBITER |
| 389 | /* |
| 390 | * When OCTEON is a PCI host, most systems will use OCTEON's |
| 391 | * internal arbiter, so must enable it before any PCI/PCI-X |
| 392 | * traffic can occur. |
| 393 | */ |
| 394 | { |
| 395 | union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg; |
| 396 | |
| 397 | pci_int_arb_cfg.u64 = 0; |
| 398 | pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ |
| 399 | cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); |
| 400 | } |
| 401 | #endif /* USE_OCTEON_INTERNAL_ARBITER */ |
| 402 | |
| 403 | /* |
| 404 | * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE, |
| 405 | * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to |
| 406 | * 1..7. |
| 407 | */ |
| 408 | cfg16.u32 = 0; |
| 409 | cfg16.s.mltd = 1; /* Master Latency Timer Disable */ |
| 410 | octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32); |
| 411 | |
| 412 | /* |
| 413 | * Should be written to 0x4ff00. MTTV -> must be zero. |
| 414 | * FLUSH -> must be 1. MRV -> should be 0xFF. |
| 415 | */ |
| 416 | cfg22.u32 = 0; |
| 417 | /* Master Retry Value [1..255] and 0=infinite */ |
| 418 | cfg22.s.mrv = 0xff; |
| 419 | /* |
| 420 | * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper |
| 421 | * N3K operation. |
| 422 | */ |
| 423 | cfg22.s.flush = 1; |
| 424 | octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32); |
| 425 | |
| 426 | /* |
| 427 | * MOST Indicates the maximum number of outstanding splits (in -1 |
| 428 | * notation) when OCTEON is in PCI-X mode. PCI-X performance is |
| 429 | * affected by the MOST selection. Should generally be written |
| 430 | * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807, |
| 431 | * depending on the desired MOST of 3, 2, 1, or 0, respectively. |
| 432 | */ |
| 433 | cfg56.u32 = 0; |
| 434 | cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ |
| 435 | cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ |
| 436 | cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ |
| 437 | cfg56.s.roe = 1; /* Relaxed Ordering Enable */ |
| 438 | cfg56.s.mmbc = 1; /* Maximum Memory Byte Count |
| 439 | [0=512B,1=1024B,2=2048B,3=4096B] */ |
| 440 | cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 |
| 441 | .. 7=32] */ |
| 442 | |
| 443 | octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); |
| 444 | |
| 445 | /* |
| 446 | * Affects PCI performance when OCTEON services reads to its |
| 447 | * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are |
| 448 | * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and |
| 449 | * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, |
| 450 | * these values need to be changed so they won't possibly prefetch off |
| 451 | * of the end of memory if PCI is DMAing a buffer at the end of |
| 452 | * memory. Note that these values differ from their reset values. |
| 453 | */ |
| 454 | octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21); |
| 455 | octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31); |
| 456 | octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31); |
| 457 | } |
| 458 | |
| 459 | |
| 460 | /** |
| 461 | * Initialize the Octeon PCI controller |
| 462 | * |
| 463 | * Returns |
| 464 | */ |
| 465 | static int __init octeon_pci_setup(void) |
| 466 | { |
| 467 | union cvmx_npi_mem_access_subidx mem_access; |
| 468 | int index; |
| 469 | |
| 470 | /* Only these chips have PCI */ |
| 471 | if (octeon_has_feature(OCTEON_FEATURE_PCIE)) |
| 472 | return 0; |
| 473 | |
| 474 | /* Point pcibios_map_irq() to the PCI version of it */ |
| 475 | octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; |
| 476 | |
| 477 | /* Only use the big bars on chips that support it */ |
| 478 | if (OCTEON_IS_MODEL(OCTEON_CN31XX) || |
| 479 | OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || |
| 480 | OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) |
| 481 | octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; |
| 482 | else |
| 483 | octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; |
| 484 | |
| 485 | /* PCI I/O and PCI MEM values */ |
| 486 | set_io_port_base(OCTEON_PCI_IOSPACE_BASE); |
| 487 | ioport_resource.start = 0; |
| 488 | ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; |
| 489 | if (!octeon_is_pci_host()) { |
| 490 | pr_notice("Not in host mode, PCI Controller not initialized\n"); |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | pr_notice("%s Octeon big bar support\n", |
| 495 | (octeon_dma_bar_type == |
| 496 | OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); |
| 497 | |
| 498 | octeon_pci_initialize(); |
| 499 | |
| 500 | mem_access.u64 = 0; |
| 501 | mem_access.s.esr = 1; /* Endian-Swap on read. */ |
| 502 | mem_access.s.esw = 1; /* Endian-Swap on write. */ |
| 503 | mem_access.s.nsr = 0; /* No-Snoop on read. */ |
| 504 | mem_access.s.nsw = 0; /* No-Snoop on write. */ |
| 505 | mem_access.s.ror = 0; /* Relax Read on read. */ |
| 506 | mem_access.s.row = 0; /* Relax Order on write. */ |
| 507 | mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ |
| 508 | cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); |
| 509 | |
| 510 | /* |
| 511 | * Remap the Octeon BAR 2 above all 32 bit devices |
| 512 | * (0x8000000000ul). This is done here so it is remapped |
| 513 | * before the readl()'s below. We don't want BAR2 overlapping |
| 514 | * with BAR0/BAR1 during these reads. |
| 515 | */ |
| 516 | octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0); |
| 517 | octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80); |
| 518 | |
| 519 | /* Disable the BAR1 movable mappings */ |
| 520 | for (index = 0; index < 32; index++) |
| 521 | octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0); |
| 522 | |
| 523 | if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { |
| 524 | /* Remap the Octeon BAR 0 to 0-2GB */ |
| 525 | octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); |
| 526 | octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); |
| 527 | |
| 528 | /* |
| 529 | * Remap the Octeon BAR 1 to map 2GB-4GB (minus the |
| 530 | * BAR 1 hole). |
| 531 | */ |
| 532 | octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); |
| 533 | octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); |
| 534 | |
| 535 | /* Devices go after BAR1 */ |
| 536 | octeon_pci_mem_resource.start = |
| 537 | OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - |
| 538 | (OCTEON_PCI_BAR1_HOLE_SIZE << 20); |
| 539 | octeon_pci_mem_resource.end = |
| 540 | octeon_pci_mem_resource.start + (1ul << 30); |
| 541 | } else { |
| 542 | /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */ |
| 543 | octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20); |
| 544 | octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); |
| 545 | |
| 546 | /* Remap the Octeon BAR 1 to map 0-128MB */ |
| 547 | octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); |
| 548 | octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); |
| 549 | |
| 550 | /* Devices go after BAR0 */ |
| 551 | octeon_pci_mem_resource.start = |
| 552 | OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + |
| 553 | (4ul << 10); |
| 554 | octeon_pci_mem_resource.end = |
| 555 | octeon_pci_mem_resource.start + (1ul << 30); |
| 556 | } |
| 557 | |
| 558 | register_pci_controller(&octeon_pci_controller); |
| 559 | |
| 560 | /* |
| 561 | * Clear any errors that might be pending from before the bus |
| 562 | * was setup properly. |
| 563 | */ |
| 564 | cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); |
| 565 | return 0; |
| 566 | } |
| 567 | |
| 568 | arch_initcall(octeon_pci_setup); |