Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2009 Intel Corporation |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 22 | * DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: |
| 25 | * Eric Anholt <eric@anholt.net> |
| 26 | * Jesse Barnes <jesse.barnes@intel.com> |
| 27 | */ |
| 28 | |
| 29 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 31 | #include <linux/delay.h> |
| 32 | #include "drmP.h" |
| 33 | #include "drm.h" |
| 34 | #include "drm_crtc.h" |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 35 | #include "drm_edid.h" |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 36 | #include "intel_drv.h" |
| 37 | #include "i915_drm.h" |
| 38 | #include "i915_drv.h" |
| 39 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 40 | struct intel_hdmi { |
| 41 | struct intel_encoder base; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 42 | u32 sdvox_reg; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 43 | int ddc_bus; |
Eugeni Dodonov | 7ceae0a | 2012-05-09 15:37:28 -0300 | [diff] [blame^] | 44 | int ddi_port; |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 45 | uint32_t color_range; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 46 | bool has_hdmi_sink; |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 47 | bool has_audio; |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 48 | enum hdmi_force_audio force_audio; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 49 | void (*write_infoframe)(struct drm_encoder *encoder, |
| 50 | struct dip_infoframe *frame); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 51 | }; |
| 52 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 53 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
| 54 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 55 | return container_of(encoder, struct intel_hdmi, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 56 | } |
| 57 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 58 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
| 59 | { |
| 60 | return container_of(intel_attached_encoder(connector), |
| 61 | struct intel_hdmi, base); |
| 62 | } |
| 63 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 64 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 65 | { |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 66 | uint8_t *data = (uint8_t *)frame; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 67 | uint8_t sum = 0; |
| 68 | unsigned i; |
| 69 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 70 | frame->checksum = 0; |
| 71 | frame->ecc = 0; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 72 | |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 73 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 74 | sum += data[i]; |
| 75 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 76 | frame->checksum = 0x100 - sum; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 77 | } |
| 78 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 79 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 80 | { |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 81 | u32 flags = 0; |
| 82 | |
| 83 | switch (frame->type) { |
| 84 | case DIP_TYPE_AVI: |
| 85 | flags |= VIDEO_DIP_SELECT_AVI; |
| 86 | break; |
| 87 | case DIP_TYPE_SPD: |
| 88 | flags |= VIDEO_DIP_SELECT_SPD; |
| 89 | break; |
| 90 | default: |
| 91 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 92 | break; |
| 93 | } |
| 94 | |
| 95 | return flags; |
| 96 | } |
| 97 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 98 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 99 | { |
| 100 | u32 flags = 0; |
| 101 | |
| 102 | switch (frame->type) { |
| 103 | case DIP_TYPE_AVI: |
Paulo Zanoni | fa193ff | 2012-05-04 17:18:20 -0300 | [diff] [blame] | 104 | flags |= VIDEO_DIP_ENABLE_AVI; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 105 | break; |
| 106 | case DIP_TYPE_SPD: |
Paulo Zanoni | fa193ff | 2012-05-04 17:18:20 -0300 | [diff] [blame] | 107 | flags |= VIDEO_DIP_ENABLE_SPD; |
| 108 | break; |
| 109 | default: |
| 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); |
| 111 | break; |
| 112 | } |
| 113 | |
| 114 | return flags; |
| 115 | } |
| 116 | |
Daniel Vetter | a3da1df | 2012-05-08 15:19:06 +0200 | [diff] [blame] | 117 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
| 118 | struct dip_infoframe *frame) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 119 | { |
| 120 | uint32_t *data = (uint32_t *)frame; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 121 | struct drm_device *dev = encoder->dev; |
| 122 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 123 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 124 | u32 val = I915_READ(VIDEO_DIP_CTL); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 125 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 126 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 127 | |
| 128 | /* XXX first guess at handling video port, is this corrent? */ |
Paulo Zanoni | 3e6e639 | 2012-05-04 17:18:19 -0300 | [diff] [blame] | 129 | val &= ~VIDEO_DIP_PORT_MASK; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 130 | if (intel_hdmi->sdvox_reg == SDVOB) |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 131 | val |= VIDEO_DIP_PORT_B; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 132 | else if (intel_hdmi->sdvox_reg == SDVOC) |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 133 | val |= VIDEO_DIP_PORT_C; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 134 | else |
| 135 | return; |
| 136 | |
Paulo Zanoni | 1d4f85a | 2012-05-04 17:18:18 -0300 | [diff] [blame] | 137 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 138 | val |= g4x_infoframe_index(frame); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 139 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 140 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 141 | val |= VIDEO_DIP_ENABLE; |
| 142 | |
| 143 | I915_WRITE(VIDEO_DIP_CTL, val); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 144 | |
| 145 | for (i = 0; i < len; i += 4) { |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 146 | I915_WRITE(VIDEO_DIP_DATA, *data); |
| 147 | data++; |
| 148 | } |
| 149 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 150 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 151 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 152 | val |= VIDEO_DIP_FREQ_VSYNC; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 153 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 154 | I915_WRITE(VIDEO_DIP_CTL, val); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 155 | } |
| 156 | |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 157 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
| 158 | struct dip_infoframe *frame) |
| 159 | { |
| 160 | uint32_t *data = (uint32_t *)frame; |
| 161 | struct drm_device *dev = encoder->dev; |
| 162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 163 | struct drm_crtc *crtc = encoder->crtc; |
| 164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 4e89ee1 | 2012-05-04 17:18:26 -0300 | [diff] [blame] | 165 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 166 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 167 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
| 168 | u32 val = I915_READ(reg); |
| 169 | |
Paulo Zanoni | 4e89ee1 | 2012-05-04 17:18:26 -0300 | [diff] [blame] | 170 | val &= ~VIDEO_DIP_PORT_MASK; |
| 171 | switch (intel_hdmi->sdvox_reg) { |
| 172 | case HDMIB: |
| 173 | val |= VIDEO_DIP_PORT_B; |
| 174 | break; |
| 175 | case HDMIC: |
| 176 | val |= VIDEO_DIP_PORT_C; |
| 177 | break; |
| 178 | case HDMID: |
| 179 | val |= VIDEO_DIP_PORT_D; |
| 180 | break; |
| 181 | default: |
| 182 | return; |
| 183 | } |
| 184 | |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 185 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 186 | |
| 187 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 188 | val |= g4x_infoframe_index(frame); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 189 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 190 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 191 | val |= VIDEO_DIP_ENABLE; |
| 192 | |
| 193 | I915_WRITE(reg, val); |
| 194 | |
| 195 | for (i = 0; i < len; i += 4) { |
| 196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 197 | data++; |
| 198 | } |
| 199 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 200 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 201 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 202 | val |= VIDEO_DIP_FREQ_VSYNC; |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 203 | |
| 204 | I915_WRITE(reg, val); |
| 205 | } |
| 206 | |
| 207 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
| 208 | struct dip_infoframe *frame) |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 209 | { |
| 210 | uint32_t *data = (uint32_t *)frame; |
| 211 | struct drm_device *dev = encoder->dev; |
| 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 213 | struct drm_crtc *crtc = encoder->crtc; |
| 214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 215 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 216 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 217 | u32 val = I915_READ(reg); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 218 | |
| 219 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 220 | |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 221 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 222 | val |= g4x_infoframe_index(frame); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 223 | |
Paulo Zanoni | ecb9785 | 2012-05-04 17:18:21 -0300 | [diff] [blame] | 224 | /* The DIP control register spec says that we need to update the AVI |
| 225 | * infoframe without clearing its enable bit */ |
| 226 | if (frame->type == DIP_TYPE_AVI) |
| 227 | val |= VIDEO_DIP_ENABLE_AVI; |
| 228 | else |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 229 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | ecb9785 | 2012-05-04 17:18:21 -0300 | [diff] [blame] | 230 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 231 | val |= VIDEO_DIP_ENABLE; |
| 232 | |
| 233 | I915_WRITE(reg, val); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 234 | |
| 235 | for (i = 0; i < len; i += 4) { |
| 236 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 237 | data++; |
| 238 | } |
| 239 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 240 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 243 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 244 | I915_WRITE(reg, val); |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 245 | } |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 246 | |
| 247 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
| 248 | struct dip_infoframe *frame) |
| 249 | { |
| 250 | uint32_t *data = (uint32_t *)frame; |
| 251 | struct drm_device *dev = encoder->dev; |
| 252 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 253 | struct drm_crtc *crtc = encoder->crtc; |
| 254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 255 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
| 256 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 257 | u32 val = I915_READ(reg); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 258 | |
| 259 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 260 | |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 262 | val |= g4x_infoframe_index(frame); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 263 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 264 | val &= ~g4x_infoframe_enable(frame); |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 265 | val |= VIDEO_DIP_ENABLE; |
| 266 | |
| 267 | I915_WRITE(reg, val); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 268 | |
| 269 | for (i = 0; i < len; i += 4) { |
| 270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
| 271 | data++; |
| 272 | } |
| 273 | |
Daniel Vetter | bc2481f | 2012-05-08 15:18:32 +0200 | [diff] [blame] | 274 | val |= g4x_infoframe_enable(frame); |
Paulo Zanoni | 60c5ea2 | 2012-05-04 17:18:22 -0300 | [diff] [blame] | 275 | val &= ~VIDEO_DIP_FREQ_MASK; |
Daniel Vetter | 4b24c93 | 2012-05-08 14:41:00 +0200 | [diff] [blame] | 276 | val |= VIDEO_DIP_FREQ_VSYNC; |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 277 | |
Paulo Zanoni | 22509ec | 2012-05-04 17:18:17 -0300 | [diff] [blame] | 278 | I915_WRITE(reg, val); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 279 | } |
| 280 | |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 281 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
| 282 | struct dip_infoframe *frame) |
| 283 | { |
| 284 | /* Not implemented yet, so avoid doing anything at all. |
| 285 | * This is the placeholder for Paulo Zanoni's infoframe writing patch |
| 286 | */ |
| 287 | DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n"); |
| 288 | |
| 289 | return; |
| 290 | |
| 291 | } |
| 292 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 293 | static void intel_set_infoframe(struct drm_encoder *encoder, |
| 294 | struct dip_infoframe *frame) |
| 295 | { |
| 296 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
| 297 | |
| 298 | if (!intel_hdmi->has_hdmi_sink) |
| 299 | return; |
| 300 | |
| 301 | intel_dip_infoframe_csum(frame); |
| 302 | intel_hdmi->write_infoframe(encoder, frame); |
| 303 | } |
| 304 | |
Paulo Zanoni | c846b61 | 2012-04-13 16:31:41 -0300 | [diff] [blame] | 305 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
| 306 | struct drm_display_mode *adjusted_mode) |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 307 | { |
| 308 | struct dip_infoframe avi_if = { |
| 309 | .type = DIP_TYPE_AVI, |
| 310 | .ver = DIP_VERSION_AVI, |
| 311 | .len = DIP_LEN_AVI, |
| 312 | }; |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 313 | |
Paulo Zanoni | c846b61 | 2012-04-13 16:31:41 -0300 | [diff] [blame] | 314 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 315 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; |
| 316 | |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 317 | intel_set_infoframe(encoder, &avi_if); |
Jesse Barnes | b055c8f | 2011-07-08 11:31:57 -0700 | [diff] [blame] | 318 | } |
| 319 | |
Jesse Barnes | c0864cb | 2011-08-03 09:22:56 -0700 | [diff] [blame] | 320 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
| 321 | { |
| 322 | struct dip_infoframe spd_if; |
| 323 | |
| 324 | memset(&spd_if, 0, sizeof(spd_if)); |
| 325 | spd_if.type = DIP_TYPE_SPD; |
| 326 | spd_if.ver = DIP_VERSION_SPD; |
| 327 | spd_if.len = DIP_LEN_SPD; |
| 328 | strcpy(spd_if.body.spd.vn, "Intel"); |
| 329 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); |
| 330 | spd_if.body.spd.sdi = DIP_SPD_PC; |
| 331 | |
| 332 | intel_set_infoframe(encoder, &spd_if); |
| 333 | } |
| 334 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 335 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
| 336 | struct drm_display_mode *mode, |
| 337 | struct drm_display_mode *adjusted_mode) |
| 338 | { |
| 339 | struct drm_device *dev = encoder->dev; |
| 340 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 341 | struct drm_crtc *crtc = encoder->crtc; |
| 342 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 344 | u32 sdvox; |
| 345 | |
Adam Jackson | b599c0b | 2010-07-16 14:46:31 -0400 | [diff] [blame] | 346 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
Jesse Barnes | 5d4fac9 | 2011-06-24 12:19:19 -0700 | [diff] [blame] | 347 | if (!HAS_PCH_SPLIT(dev)) |
| 348 | sdvox |= intel_hdmi->color_range; |
Adam Jackson | b599c0b | 2010-07-16 14:46:31 -0400 | [diff] [blame] | 349 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 350 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 351 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 352 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 353 | |
Jesse Barnes | 020f670 | 2011-06-24 12:19:25 -0700 | [diff] [blame] | 354 | if (intel_crtc->bpp > 24) |
| 355 | sdvox |= COLOR_FORMAT_12bpc; |
| 356 | else |
| 357 | sdvox |= COLOR_FORMAT_8bpc; |
| 358 | |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 359 | /* Required on CPT */ |
| 360 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) |
| 361 | sdvox |= HDMI_MODE_SELECT; |
| 362 | |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 363 | if (intel_hdmi->has_audio) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 364 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
| 365 | pipe_name(intel_crtc->pipe)); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 366 | sdvox |= SDVO_AUDIO_ENABLE; |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 367 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 368 | intel_write_eld(encoder, adjusted_mode); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 369 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 370 | |
Jesse Barnes | 7577056 | 2011-10-12 09:01:58 -0700 | [diff] [blame] | 371 | if (HAS_PCH_CPT(dev)) |
| 372 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); |
| 373 | else if (intel_crtc->pipe == 1) |
| 374 | sdvox |= SDVO_PIPE_B_SELECT; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 375 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 376 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
| 377 | POSTING_READ(intel_hdmi->sdvox_reg); |
David Härdeman | 3c17fe4 | 2010-09-24 21:44:32 +0200 | [diff] [blame] | 378 | |
Paulo Zanoni | c846b61 | 2012-04-13 16:31:41 -0300 | [diff] [blame] | 379 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
Jesse Barnes | c0864cb | 2011-08-03 09:22:56 -0700 | [diff] [blame] | 380 | intel_hdmi_set_spd_infoframe(encoder); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 381 | } |
| 382 | |
| 383 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) |
| 384 | { |
| 385 | struct drm_device *dev = encoder->dev; |
| 386 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 387 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 388 | u32 temp; |
Wu Fengguang | 2deed76 | 2011-12-09 20:42:20 +0800 | [diff] [blame] | 389 | u32 enable_bits = SDVO_ENABLE; |
| 390 | |
| 391 | if (intel_hdmi->has_audio) |
| 392 | enable_bits |= SDVO_AUDIO_ENABLE; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 393 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 394 | temp = I915_READ(intel_hdmi->sdvox_reg); |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 395 | |
| 396 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
| 397 | * we do this anyway which shows more stable in testing. |
| 398 | */ |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 399 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 400 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
| 401 | POSTING_READ(intel_hdmi->sdvox_reg); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 402 | } |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 403 | |
| 404 | if (mode != DRM_MODE_DPMS_ON) { |
Wu Fengguang | 2deed76 | 2011-12-09 20:42:20 +0800 | [diff] [blame] | 405 | temp &= ~enable_bits; |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 406 | } else { |
Wu Fengguang | 2deed76 | 2011-12-09 20:42:20 +0800 | [diff] [blame] | 407 | temp |= enable_bits; |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 408 | } |
| 409 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 410 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 411 | POSTING_READ(intel_hdmi->sdvox_reg); |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 412 | |
| 413 | /* HW workaround, need to write this twice for issue that may result |
| 414 | * in first write getting masked. |
| 415 | */ |
Eric Anholt | c619eed | 2010-01-28 16:45:52 -0800 | [diff] [blame] | 416 | if (HAS_PCH_SPLIT(dev)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 417 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
| 418 | POSTING_READ(intel_hdmi->sdvox_reg); |
Zhenyu Wang | d8a2d0e | 2009-11-02 07:52:30 +0000 | [diff] [blame] | 419 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 420 | } |
| 421 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 422 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
| 423 | struct drm_display_mode *mode) |
| 424 | { |
| 425 | if (mode->clock > 165000) |
| 426 | return MODE_CLOCK_HIGH; |
| 427 | if (mode->clock < 20000) |
Nicolas Kaiser | 5cbba41 | 2011-05-30 12:48:26 +0200 | [diff] [blame] | 428 | return MODE_CLOCK_LOW; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 429 | |
| 430 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 431 | return MODE_NO_DBLESCAN; |
| 432 | |
| 433 | return MODE_OK; |
| 434 | } |
| 435 | |
| 436 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
| 437 | struct drm_display_mode *mode, |
| 438 | struct drm_display_mode *adjusted_mode) |
| 439 | { |
| 440 | return true; |
| 441 | } |
| 442 | |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 443 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 444 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 445 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 446 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 447 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 448 | struct edid *edid; |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 449 | enum drm_connector_status status = connector_status_disconnected; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 450 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 451 | intel_hdmi->has_hdmi_sink = false; |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 452 | intel_hdmi->has_audio = false; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 453 | edid = drm_get_edid(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 454 | intel_gmbus_get_adapter(dev_priv, |
| 455 | intel_hdmi->ddc_bus)); |
ling.ma@intel.com | 2ded9e2 | 2009-07-16 17:23:09 +0800 | [diff] [blame] | 456 | |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 457 | if (edid) { |
Eric Anholt | be9f1c4 | 2009-06-21 22:14:55 -0700 | [diff] [blame] | 458 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 459 | status = connector_status_connected; |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 460 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
| 461 | intel_hdmi->has_hdmi_sink = |
| 462 | drm_detect_hdmi_monitor(edid); |
Zhenyu Wang | 2e3d600 | 2010-09-10 10:39:40 +0800 | [diff] [blame] | 463 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 464 | } |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 465 | connector->display_info.raw_edid = NULL; |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 466 | kfree(edid); |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 467 | } |
ling.ma@intel.com | 2ded9e2 | 2009-07-16 17:23:09 +0800 | [diff] [blame] | 468 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 469 | if (status == connector_status_connected) { |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 470 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
| 471 | intel_hdmi->has_audio = |
| 472 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 473 | } |
| 474 | |
Keith Packard | aa93d63 | 2009-05-05 09:52:46 -0700 | [diff] [blame] | 475 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 476 | } |
| 477 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 478 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
| 479 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 480 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 481 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 482 | |
| 483 | /* We should parse the EDID data and find out if it's an HDMI sink so |
| 484 | * we can send audio to it. |
| 485 | */ |
| 486 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 487 | return intel_ddc_get_modes(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 488 | intel_gmbus_get_adapter(dev_priv, |
| 489 | intel_hdmi->ddc_bus)); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 490 | } |
| 491 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 492 | static bool |
| 493 | intel_hdmi_detect_audio(struct drm_connector *connector) |
| 494 | { |
| 495 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
| 496 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 497 | struct edid *edid; |
| 498 | bool has_audio = false; |
| 499 | |
| 500 | edid = drm_get_edid(connector, |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 501 | intel_gmbus_get_adapter(dev_priv, |
| 502 | intel_hdmi->ddc_bus)); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 503 | if (edid) { |
| 504 | if (edid->input & DRM_EDID_INPUT_DIGITAL) |
| 505 | has_audio = drm_detect_monitor_audio(edid); |
| 506 | |
| 507 | connector->display_info.raw_edid = NULL; |
| 508 | kfree(edid); |
| 509 | } |
| 510 | |
| 511 | return has_audio; |
| 512 | } |
| 513 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 514 | static int |
| 515 | intel_hdmi_set_property(struct drm_connector *connector, |
| 516 | struct drm_property *property, |
| 517 | uint64_t val) |
| 518 | { |
| 519 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 520 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 521 | int ret; |
| 522 | |
| 523 | ret = drm_connector_property_set_value(connector, property, val); |
| 524 | if (ret) |
| 525 | return ret; |
| 526 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 527 | if (property == dev_priv->force_audio_property) { |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 528 | enum hdmi_force_audio i = val; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 529 | bool has_audio; |
| 530 | |
| 531 | if (i == intel_hdmi->force_audio) |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 532 | return 0; |
| 533 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 534 | intel_hdmi->force_audio = i; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 535 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 536 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 537 | has_audio = intel_hdmi_detect_audio(connector); |
| 538 | else |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 539 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 540 | |
Wu Fengguang | b1d7e4b | 2012-02-14 11:45:36 +0800 | [diff] [blame] | 541 | if (i == HDMI_AUDIO_OFF_DVI) |
| 542 | intel_hdmi->has_hdmi_sink = 0; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 543 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 544 | intel_hdmi->has_audio = has_audio; |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 545 | goto done; |
| 546 | } |
| 547 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 548 | if (property == dev_priv->broadcast_rgb_property) { |
| 549 | if (val == !!intel_hdmi->color_range) |
| 550 | return 0; |
| 551 | |
| 552 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
| 553 | goto done; |
| 554 | } |
| 555 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 556 | return -EINVAL; |
| 557 | |
| 558 | done: |
| 559 | if (intel_hdmi->base.base.crtc) { |
| 560 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; |
| 561 | drm_crtc_helper_set_mode(crtc, &crtc->mode, |
| 562 | crtc->x, crtc->y, |
| 563 | crtc->fb); |
| 564 | } |
| 565 | |
| 566 | return 0; |
| 567 | } |
| 568 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 569 | static void intel_hdmi_destroy(struct drm_connector *connector) |
| 570 | { |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 571 | drm_sysfs_connector_remove(connector); |
| 572 | drm_connector_cleanup(connector); |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 573 | kfree(connector); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 574 | } |
| 575 | |
| 576 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
| 577 | .dpms = intel_hdmi_dpms, |
| 578 | .mode_fixup = intel_hdmi_mode_fixup, |
| 579 | .prepare = intel_encoder_prepare, |
| 580 | .mode_set = intel_hdmi_mode_set, |
| 581 | .commit = intel_encoder_commit, |
| 582 | }; |
| 583 | |
| 584 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 585 | .dpms = drm_helper_connector_dpms, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 586 | .detect = intel_hdmi_detect, |
| 587 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 588 | .set_property = intel_hdmi_set_property, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 589 | .destroy = intel_hdmi_destroy, |
| 590 | }; |
| 591 | |
| 592 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { |
| 593 | .get_modes = intel_hdmi_get_modes, |
| 594 | .mode_valid = intel_hdmi_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 595 | .best_encoder = intel_best_encoder, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 596 | }; |
| 597 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 598 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 599 | .destroy = intel_encoder_destroy, |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 600 | }; |
| 601 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 602 | static void |
| 603 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) |
| 604 | { |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 605 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 606 | intel_attach_broadcast_rgb_property(connector); |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 607 | } |
| 608 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 609 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
| 610 | { |
| 611 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 612 | struct drm_connector *connector; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 613 | struct intel_encoder *intel_encoder; |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 614 | struct intel_connector *intel_connector; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 615 | struct intel_hdmi *intel_hdmi; |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 616 | int i; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 617 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 618 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
| 619 | if (!intel_hdmi) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 620 | return; |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 621 | |
| 622 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 623 | if (!intel_connector) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 624 | kfree(intel_hdmi); |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 625 | return; |
| 626 | } |
| 627 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 628 | intel_encoder = &intel_hdmi->base; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 629 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
| 630 | DRM_MODE_ENCODER_TMDS); |
| 631 | |
Zhenyu Wang | 674e2d0 | 2010-03-29 15:57:42 +0800 | [diff] [blame] | 632 | connector = &intel_connector->base; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 633 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
Adam Jackson | 8d91104 | 2009-09-23 15:08:29 -0400 | [diff] [blame] | 634 | DRM_MODE_CONNECTOR_HDMIA); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 635 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
| 636 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 637 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 638 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 639 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
Peter Ross | c3febcc | 2012-01-28 14:49:26 +0100 | [diff] [blame] | 640 | connector->interlace_allowed = 1; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 641 | connector->doublescan_allowed = 0; |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 642 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 643 | |
| 644 | /* Set up the DDC bus. */ |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 645 | if (sdvox_reg == SDVOB) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 646 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 647 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 648 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 649 | } else if (sdvox_reg == SDVOC) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 650 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 651 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 652 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 653 | } else if (sdvox_reg == HDMIB) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 654 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 655 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 656 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 657 | } else if (sdvox_reg == HDMIC) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 658 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 659 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 660 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 661 | } else if (sdvox_reg == HDMID) { |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 662 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 663 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 664 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
Eugeni Dodonov | 7ceae0a | 2012-05-09 15:37:28 -0300 | [diff] [blame^] | 665 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
| 666 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); |
| 667 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
| 668 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
| 669 | intel_hdmi->ddi_port = PORT_B; |
| 670 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
| 671 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { |
| 672 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); |
| 673 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
| 674 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
| 675 | intel_hdmi->ddi_port = PORT_C; |
| 676 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
| 677 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { |
| 678 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); |
| 679 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
| 680 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
| 681 | intel_hdmi->ddi_port = PORT_D; |
| 682 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
Eugeni Dodonov | 6e4c167 | 2012-05-09 15:37:13 -0300 | [diff] [blame] | 683 | } else { |
| 684 | /* If we got an unknown sdvox_reg, things are pretty much broken |
| 685 | * in a way that we should let the kernel know about it */ |
| 686 | BUG(); |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 687 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 688 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 689 | intel_hdmi->sdvox_reg = sdvox_reg; |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 690 | |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 691 | if (!HAS_PCH_SPLIT(dev)) { |
Daniel Vetter | a3da1df | 2012-05-08 15:19:06 +0200 | [diff] [blame] | 692 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 693 | I915_WRITE(VIDEO_DIP_CTL, 0); |
Shobhit Kumar | 90b107c | 2012-03-28 13:39:32 -0700 | [diff] [blame] | 694 | } else if (IS_VALLEYVIEW(dev)) { |
| 695 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
| 696 | for_each_pipe(i) |
| 697 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); |
Eugeni Dodonov | 8c5f5f7 | 2012-05-10 10:18:02 -0300 | [diff] [blame] | 698 | } else if (IS_HASWELL(dev)) { |
| 699 | /* FIXME: Haswell has a new set of DIP frame registers, but we are |
| 700 | * just doing the minimal required for HDMI to work at this stage. |
| 701 | */ |
| 702 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
| 703 | for_each_pipe(i) |
| 704 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); |
Paulo Zanoni | fdf1250 | 2012-05-04 17:18:24 -0300 | [diff] [blame] | 705 | } else if (HAS_PCH_IBX(dev)) { |
| 706 | intel_hdmi->write_infoframe = ibx_write_infoframe; |
| 707 | for_each_pipe(i) |
| 708 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
| 709 | } else { |
| 710 | intel_hdmi->write_infoframe = cpt_write_infoframe; |
Jesse Barnes | 64a8fc0 | 2011-09-22 11:16:00 +0530 | [diff] [blame] | 711 | for_each_pipe(i) |
| 712 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); |
| 713 | } |
Jesse Barnes | 45187ac | 2011-08-03 09:22:55 -0700 | [diff] [blame] | 714 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 715 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 716 | |
Chris Wilson | 55b7d6e8 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 717 | intel_hdmi_add_properties(intel_hdmi, connector); |
| 718 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 719 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 720 | drm_sysfs_connector_add(connector); |
| 721 | |
| 722 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 723 | * 0xd. Failure to do so will result in spurious interrupts being |
| 724 | * generated on the port when a cable is not attached. |
| 725 | */ |
| 726 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 727 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 728 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 729 | } |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 730 | } |