blob: a2e8fb889ef11c46a37779307dca6e20c665233d [file] [log] [blame]
Ben Skeggs3f204642014-02-24 11:28:37 +10001/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/bios.h>
26#include <subdev/bus.h>
27#include <subdev/gpio.h>
28#include <subdev/i2c.h>
29#include <subdev/clock.h>
30#include <subdev/therm.h>
31#include <subdev/mxm.h>
32#include <subdev/devinit.h>
33#include <subdev/mc.h>
34#include <subdev/timer.h>
35#include <subdev/fb.h>
36#include <subdev/ltcg.h>
37#include <subdev/ibus.h>
38#include <subdev/instmem.h>
39#include <subdev/vm.h>
40#include <subdev/bar.h>
41#include <subdev/pwr.h>
42#include <subdev/volt.h>
43
44#include <engine/device.h>
45#include <engine/dmaobj.h>
46#include <engine/fifo.h>
47#include <engine/software.h>
48#include <engine/graph.h>
49#include <engine/disp.h>
50#include <engine/copy.h>
51#include <engine/bsp.h>
52#include <engine/vp.h>
53#include <engine/ppp.h>
54#include <engine/perfmon.h>
55
56int
57gm100_identify(struct nouveau_device *device)
58{
59 switch (device->chipset) {
60 case 0x117:
61 device->cname = "GM107";
62 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggsd93174e2014-05-12 14:18:06 +100063 device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
Ben Skeggsc26fe842014-05-13 13:59:26 +100064 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100065 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
66#if 0
67 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
68#endif
69 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
70 device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
Ben Skeggs7d155da2014-06-12 22:15:21 +100071 device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100072 device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
73 device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
74 device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
75 device->oclass[NVDEV_SUBDEV_LTCG ] = gm107_ltcg_oclass;
76 device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
77 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
78 device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
79 device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
80#if 0
Ben Skeggsadec9bc2014-06-12 18:31:32 +100081 device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100082 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
83#endif
84 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
85 device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass;
86 device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
Ben Skeggs6f1e9b92014-03-04 11:00:41 +100087 device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass;
Ben Skeggs3f204642014-02-24 11:28:37 +100088 device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass;
89 device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
90#if 0
91 device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
92#endif
93 device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
94#if 0
95 device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
96 device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
97 device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
98#endif
99 break;
100 default:
101 nv_fatal(device, "unknown Maxwell chipset\n");
102 return -EINVAL;
103 }
104
105 return 0;
106}