blob: 53feb90c840ca5c2868671b4dcdb9e942f49521d [file] [log] [blame]
Russell King0462b442011-01-19 10:24:56 +00001/*
2 * linux/arch/arm/plat-versatile/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/errno.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/jiffies.h>
16#include <linux/smp.h>
17
18#include <asm/cacheflush.h>
Will Deaconeb504392012-01-20 12:01:12 +010019#include <asm/smp_plat.h>
Russell King0462b442011-01-19 10:24:56 +000020
21/*
Russell King0462b442011-01-19 10:24:56 +000022 * Write pen_release in a way that is guaranteed to be visible to all
23 * observers, irrespective of whether they're taking part in coherency
24 * or not. This is necessary for the hotplug code to work reliably.
25 */
Paul Gortmaker8bd26e32013-06-17 15:43:14 -040026static void write_pen_release(int val)
Russell King0462b442011-01-19 10:24:56 +000027{
28 pen_release = val;
29 smp_wmb();
Nicolas Pitref45913f2013-12-05 14:26:16 -050030 sync_cache_w(&pen_release);
Russell King0462b442011-01-19 10:24:56 +000031}
32
33static DEFINE_SPINLOCK(boot_lock);
34
Paul Gortmaker8bd26e32013-06-17 15:43:14 -040035void versatile_secondary_init(unsigned int cpu)
Russell King0462b442011-01-19 10:24:56 +000036{
37 /*
Russell King0462b442011-01-19 10:24:56 +000038 * let the primary processor know we're out of the
39 * pen, then head off into the C entry point
40 */
41 write_pen_release(-1);
42
43 /*
44 * Synchronise with the boot thread.
45 */
46 spin_lock(&boot_lock);
47 spin_unlock(&boot_lock);
48}
49
Paul Gortmaker8bd26e32013-06-17 15:43:14 -040050int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
Russell King0462b442011-01-19 10:24:56 +000051{
52 unsigned long timeout;
53
54 /*
55 * Set synchronisation state between this boot processor
56 * and the secondary one
57 */
58 spin_lock(&boot_lock);
59
60 /*
61 * This is really belt and braces; we hold unintended secondary
62 * CPUs in the holding pen until we're ready for them. However,
63 * since we haven't sent them a soft interrupt, they shouldn't
64 * be there.
65 */
Will Deacon4a139b62011-08-09 12:24:07 +010066 write_pen_release(cpu_logical_map(cpu));
Russell King0462b442011-01-19 10:24:56 +000067
68 /*
69 * Send the secondary CPU a soft interrupt, thereby causing
70 * the boot monitor to read the system wide flags register,
71 * and branch to the address found there.
72 */
Rob Herringb1cffeb2012-11-26 15:05:48 -060073 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
Russell King0462b442011-01-19 10:24:56 +000074
75 timeout = jiffies + (1 * HZ);
76 while (time_before(jiffies, timeout)) {
77 smp_rmb();
78 if (pen_release == -1)
79 break;
80
81 udelay(10);
82 }
83
84 /*
85 * now the secondary core is starting up let it run its
86 * calibrations, then wait for it to finish
87 */
88 spin_unlock(&boot_lock);
89
90 return pen_release != -1 ? -ENOSYS : 0;
91}