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Vitaly Bordugb0c110b2006-09-21 22:18:53 +04001/*
2 * Platform information definitions.
3 *
4 * Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
5 * to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
6 *
7 * Author: Vitaly Bordug <vbordug@ru.mvista.com>
8 *
9 * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
10 * 2006 (c) MontaVista Software, Inc.
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17/* The CPM2 internal interrupt controller. It is usually
18 * the only interrupt controller.
19 * There are two 32-bit registers (high/low) for up to 64
20 * possible interrupts.
21 *
22 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
23 * in a simple arithmetic fashion to mask or pending registers.
24 * That is, interrupt 4 does not map to bit position 4.
25 * We create two tables, indexed by vector number, to indicate
26 * which register to use and which bit in the register to use.
27 */
28
29#include <linux/stddef.h>
30#include <linux/init.h>
31#include <linux/sched.h>
32#include <linux/signal.h>
33#include <linux/irq.h>
34
35#include <asm/immap_cpm2.h>
36#include <asm/mpc8260.h>
37#include <asm/io.h>
38#include <asm/prom.h>
Vitaly Bordug73844ec2007-01-31 02:08:54 +030039#include <asm/fs_pd.h>
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040040
41#include "cpm2_pic.h"
42
Vitaly Bordug73844ec2007-01-31 02:08:54 +030043/* External IRQS */
44#define CPM2_IRQ_EXT1 19
45#define CPM2_IRQ_EXT7 25
46
47/* Port C IRQS */
48#define CPM2_IRQ_PORTC15 48
49#define CPM2_IRQ_PORTC0 63
50
Scott Wood449012d2007-09-14 15:30:44 -050051static intctl_cpm2_t __iomem *cpm2_intctl;
Vitaly Bordug73844ec2007-01-31 02:08:54 +030052
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040053static struct irq_host *cpm2_pic_host;
54#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
55static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
56
57static const u_char irq_to_siureg[] = {
58 1, 1, 1, 1, 1, 1, 1, 1,
59 1, 1, 1, 1, 1, 1, 1, 1,
60 0, 0, 0, 0, 0, 0, 0, 0,
61 0, 0, 0, 0, 0, 0, 0, 0,
62 1, 1, 1, 1, 1, 1, 1, 1,
63 1, 1, 1, 1, 1, 1, 1, 1,
64 0, 0, 0, 0, 0, 0, 0, 0,
65 0, 0, 0, 0, 0, 0, 0, 0
66};
67
68/* bit numbers do not match the docs, these are precomputed so the bit for
69 * a given irq is (1 << irq_to_siubit[irq]) */
70static const u_char irq_to_siubit[] = {
71 0, 15, 14, 13, 12, 11, 10, 9,
72 8, 7, 6, 5, 4, 3, 2, 1,
73 2, 1, 0, 14, 13, 12, 11, 10,
74 9, 8, 7, 6, 5, 4, 3, 0,
75 31, 30, 29, 28, 27, 26, 25, 24,
76 23, 22, 21, 20, 19, 18, 17, 16,
77 16, 17, 18, 19, 20, 21, 22, 23,
78 24, 25, 26, 27, 28, 29, 30, 31,
79};
80
Lennert Buytenhekc47eefa2011-03-07 13:59:51 +000081static void cpm2_mask_irq(struct irq_data *d)
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040082{
83 int bit, word;
Grant Likely476eb492011-05-04 15:02:15 +100084 unsigned int irq_nr = irqd_to_hwirq(d);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040085
86 bit = irq_to_siubit[irq_nr];
87 word = irq_to_siureg[irq_nr];
88
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040089 ppc_cached_irq_mask[word] &= ~(1 << bit);
Vitaly Bordug73844ec2007-01-31 02:08:54 +030090 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040091}
92
Lennert Buytenhekc47eefa2011-03-07 13:59:51 +000093static void cpm2_unmask_irq(struct irq_data *d)
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040094{
95 int bit, word;
Grant Likely476eb492011-05-04 15:02:15 +100096 unsigned int irq_nr = irqd_to_hwirq(d);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +040097
98 bit = irq_to_siubit[irq_nr];
99 word = irq_to_siureg[irq_nr];
100
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400101 ppc_cached_irq_mask[word] |= 1 << bit;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300102 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400103}
104
Lennert Buytenhekc47eefa2011-03-07 13:59:51 +0000105static void cpm2_ack(struct irq_data *d)
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400106{
107 int bit, word;
Grant Likely476eb492011-05-04 15:02:15 +1000108 unsigned int irq_nr = irqd_to_hwirq(d);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400109
110 bit = irq_to_siubit[irq_nr];
111 word = irq_to_siureg[irq_nr];
112
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300113 out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400114}
115
Lennert Buytenhekc47eefa2011-03-07 13:59:51 +0000116static void cpm2_end_irq(struct irq_data *d)
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400117{
118 int bit, word;
Grant Likely476eb492011-05-04 15:02:15 +1000119 unsigned int irq_nr = irqd_to_hwirq(d);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400120
Thomas Gleixner7bf811a82011-03-25 16:13:38 +0100121 bit = irq_to_siubit[irq_nr];
122 word = irq_to_siureg[irq_nr];
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400123
Thomas Gleixner7bf811a82011-03-25 16:13:38 +0100124 ppc_cached_irq_mask[word] |= 1 << bit;
125 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400126
Thomas Gleixner7bf811a82011-03-25 16:13:38 +0100127 /*
128 * Work around large numbers of spurious IRQs on PowerPC 82xx
129 * systems.
130 */
131 mb();
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400132}
133
Lennert Buytenhekc47eefa2011-03-07 13:59:51 +0000134static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300135{
Grant Likely476eb492011-05-04 15:02:15 +1000136 unsigned int src = irqd_to_hwirq(d);
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300137 unsigned int vold, vnew, edibit;
138
Mark Wareb22b97c2009-12-10 22:14:34 +1100139 /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
140 * IRQ_TYPE_EDGE_BOTH (default). All others are IRQ_TYPE_EDGE_FALLING
141 * or IRQ_TYPE_LEVEL_LOW (default)
142 */
143 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) {
144 if (flow_type == IRQ_TYPE_NONE)
145 flow_type = IRQ_TYPE_EDGE_BOTH;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300146
Mark Wareb22b97c2009-12-10 22:14:34 +1100147 if (flow_type != IRQ_TYPE_EDGE_BOTH &&
148 flow_type != IRQ_TYPE_EDGE_FALLING)
149 goto err_sense;
150 } else {
151 if (flow_type == IRQ_TYPE_NONE)
152 flow_type = IRQ_TYPE_LEVEL_LOW;
153
154 if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
155 goto err_sense;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300156 }
157
Thomas Gleixnera28ab382011-03-25 16:07:51 +0100158 irqd_set_trigger_type(d, flow_type);
159 if (flow_type & IRQ_TYPE_LEVEL_LOW)
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100160 __irq_set_handler_locked(d->irq, handle_level_irq);
Thomas Gleixnera28ab382011-03-25 16:07:51 +0100161 else
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100162 __irq_set_handler_locked(d->irq, handle_edge_irq);
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300163
164 /* internal IRQ senses are LEVEL_LOW
165 * EXT IRQ and Port C IRQ senses are programmable
166 */
167 if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
168 edibit = (14 - (src - CPM2_IRQ_EXT1));
169 else
170 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
paulfax7f3ea172009-01-27 02:44:07 -0600171 edibit = (31 - (CPM2_IRQ_PORTC0 - src));
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300172 else
Thomas Gleixnera28ab382011-03-25 16:07:51 +0100173 return (flow_type & IRQ_TYPE_LEVEL_LOW) ?
174 IRQ_SET_MASK_OK_NOCOPY : -EINVAL;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300175
176 vold = in_be32(&cpm2_intctl->ic_siexr);
177
178 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
179 vnew = vold | (1 << edibit);
180 else
181 vnew = vold & ~(1 << edibit);
182
183 if (vold != vnew)
184 out_be32(&cpm2_intctl->ic_siexr, vnew);
Thomas Gleixnera28ab382011-03-25 16:07:51 +0100185 return IRQ_SET_MASK_OK_NOCOPY;
Mark Wareb22b97c2009-12-10 22:14:34 +1100186
187err_sense:
188 pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
189 return -EINVAL;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300190}
191
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400192static struct irq_chip cpm2_pic = {
Anton Blanchardfc380c02010-01-31 20:33:41 +0000193 .name = "CPM2 SIU",
Lennert Buytenhekc47eefa2011-03-07 13:59:51 +0000194 .irq_mask = cpm2_mask_irq,
195 .irq_unmask = cpm2_unmask_irq,
196 .irq_ack = cpm2_ack,
197 .irq_eoi = cpm2_end_irq,
198 .irq_set_type = cpm2_set_irq_type,
Thomas Gleixner7bf811a82011-03-25 16:13:38 +0100199 .flags = IRQCHIP_EOI_IF_HANDLED,
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400200};
201
Olaf Hering35a84c22006-10-07 22:08:26 +1000202unsigned int cpm2_get_irq(void)
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400203{
204 int irq;
205 unsigned long bits;
206
Vitaly Bordugfc8e50e2006-09-21 22:37:58 +0400207 /* For CPM2, read the SIVEC register and shift the bits down
208 * to get the irq number. */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300209 bits = in_be32(&cpm2_intctl->ic_sivec);
Vitaly Bordugfc8e50e2006-09-21 22:37:58 +0400210 irq = bits >> 26;
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400211
212 if (irq == 0)
213 return(-1);
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300214 return irq_linear_revmap(cpm2_pic_host, irq);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400215}
216
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400217static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
218 irq_hw_number_t hw)
219{
220 pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
221
Thomas Gleixner98488db2011-03-25 15:43:57 +0100222 irq_set_status_flags(virq, IRQ_LEVEL);
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100223 irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400224 return 0;
225}
226
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400227static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
Roman Fietze40d50cf2009-12-08 02:39:50 +0000228 const u32 *intspec, unsigned int intsize,
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400229 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
230{
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400231 *out_hwirq = intspec[0];
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300232 if (intsize > 1)
233 *out_flags = intspec[1];
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400234 else
235 *out_flags = IRQ_TYPE_NONE;
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400236 return 0;
237}
238
239static struct irq_host_ops cpm2_pic_host_ops = {
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400240 .map = cpm2_pic_host_map,
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400241 .xlate = cpm2_pic_host_xlate,
242};
243
244void cpm2_pic_init(struct device_node *node)
245{
246 int i;
247
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300248 cpm2_intctl = cpm2_map(im_intctl);
249
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400250 /* Clear the CPM IRQ controller, in case it has any bits set
251 * from the bootloader
252 */
253
254 /* Mask out everything */
255
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300256 out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
257 out_be32(&cpm2_intctl->ic_simrl, 0x00000000);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400258
259 wmb();
260
261 /* Ack everything */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300262 out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
263 out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400264 wmb();
265
266 /* Dummy read of the vector */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300267 i = in_be32(&cpm2_intctl->ic_sivec);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400268 rmb();
269
270 /* Initialize the default interrupt mapping priorities,
271 * in case the boot rom changed something on us.
272 */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300273 out_be16(&cpm2_intctl->ic_sicr, 0);
274 out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
275 out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400276
277 /* create a legacy host */
Michael Ellerman19fc65b2008-05-26 12:12:32 +1000278 cpm2_pic_host = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
Michael Ellerman52964f82007-08-28 18:47:54 +1000279 64, &cpm2_pic_host_ops, 64);
Vitaly Bordugb0c110b2006-09-21 22:18:53 +0400280 if (cpm2_pic_host == NULL) {
281 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
282 return;
283 }
284}