raghavendra ambadas | a46d388 | 2019-05-22 17:14:21 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/io.h> |
| 19 | #include <linux/of_device.h> |
| 20 | #include <linux/of_gpio.h> |
| 21 | #include <linux/gpio.h> |
| 22 | #include <linux/err.h> |
| 23 | #include <linux/regulator/consumer.h> |
| 24 | #include <linux/leds-qpnp-wled.h> |
| 25 | #include <linux/clk.h> |
| 26 | #include <linux/uaccess.h> |
| 27 | #include <linux/msm-bus.h> |
| 28 | #include <linux/pm_qos.h> |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 29 | #include <linux/mdss_io_util.h> |
Sandeep Panda | 812f500 | 2017-02-24 11:36:59 +0530 | [diff] [blame] | 30 | #include <linux/dma-buf.h> |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 31 | |
| 32 | #include "mdss.h" |
| 33 | #include "mdss_panel.h" |
| 34 | #include "mdss_dsi.h" |
| 35 | #include "mdss_debug.h" |
| 36 | #include "mdss_dsi_phy.h" |
| 37 | #include "mdss_dba_utils.h" |
| 38 | |
jialongjhan | 7dfbf87 | 2020-04-21 20:24:23 +0800 | [diff] [blame^] | 39 | //[Arima_8901][LCM][Jialongjhan] Add LCM_vendor file node for PCBA function test begin |
| 40 | #include <linux/proc_fs.h> |
| 41 | //[Arima_8901][LCM][Jialongjhan] Add LCM_vendor file node for PCBA function test end |
| 42 | |
| 43 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 44 | #define XO_CLK_RATE 19200000 |
| 45 | #define CMDLINE_DSI_CTL_NUM_STRING_LEN 2 |
| 46 | |
| 47 | /* Master structure to hold all the information about the DSI/panel */ |
| 48 | static struct mdss_dsi_data *mdss_dsi_res; |
| 49 | |
| 50 | #define DSI_DISABLE_PC_LATENCY 100 |
| 51 | #define DSI_ENABLE_PC_LATENCY PM_QOS_DEFAULT_VALUE |
| 52 | |
| 53 | static struct pm_qos_request mdss_dsi_pm_qos_request; |
| 54 | |
Sandeep Panda | 812f500 | 2017-02-24 11:36:59 +0530 | [diff] [blame] | 55 | void mdss_dump_dsi_debug_bus(u32 bus_dump_flag, |
| 56 | u32 **dump_mem) |
| 57 | { |
| 58 | struct mdss_dsi_data *sdata = mdss_dsi_res; |
| 59 | struct mdss_dsi_ctrl_pdata *m_ctrl, *s_ctrl; |
| 60 | bool in_log, in_mem; |
| 61 | u32 *dump_addr = NULL; |
| 62 | u32 status0 = 0, status1 = 0; |
| 63 | phys_addr_t phys = 0; |
| 64 | int list_size = 0; |
| 65 | int i; |
| 66 | bool dsi0_active = false, dsi1_active = false; |
| 67 | |
| 68 | if (!sdata || !sdata->dbg_bus || !sdata->dbg_bus_size) |
| 69 | return; |
| 70 | |
| 71 | m_ctrl = sdata->ctrl_pdata[0]; |
| 72 | s_ctrl = sdata->ctrl_pdata[1]; |
| 73 | |
| 74 | if (!m_ctrl) |
| 75 | return; |
| 76 | |
| 77 | if (m_ctrl && m_ctrl->shared_data->dsi0_active) |
| 78 | dsi0_active = true; |
| 79 | if (s_ctrl && s_ctrl->shared_data->dsi1_active) |
| 80 | dsi1_active = true; |
| 81 | |
| 82 | list_size = (sdata->dbg_bus_size * sizeof(sdata->dbg_bus[0]) * 4); |
| 83 | |
| 84 | in_log = (bus_dump_flag & MDSS_DBG_DUMP_IN_LOG); |
| 85 | in_mem = (bus_dump_flag & MDSS_DBG_DUMP_IN_MEM); |
| 86 | |
| 87 | if (in_mem) { |
| 88 | if (!(*dump_mem)) |
| 89 | *dump_mem = dma_alloc_coherent(&sdata->pdev->dev, |
| 90 | list_size, &phys, GFP_KERNEL); |
| 91 | |
| 92 | if (*dump_mem) { |
| 93 | dump_addr = *dump_mem; |
| 94 | pr_info("%s: start_addr:0x%pK end_addr:0x%pK\n", |
| 95 | __func__, dump_addr, dump_addr + list_size); |
| 96 | } else { |
| 97 | in_mem = false; |
| 98 | pr_err("dump_mem: allocation fails\n"); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | pr_info("========= Start DSI Debug Bus =========\n"); |
| 103 | |
| 104 | mdss_dsi_clk_ctrl(m_ctrl, m_ctrl->dsi_clk_handle, |
| 105 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON); |
| 106 | |
| 107 | for (i = 0; i < sdata->dbg_bus_size; i++) { |
| 108 | if (dsi0_active) { |
| 109 | writel_relaxed(sdata->dbg_bus[i], |
| 110 | m_ctrl->ctrl_base + 0x124); |
| 111 | wmb(); /* ensure regsiter is committed */ |
| 112 | } |
| 113 | if (dsi1_active) { |
| 114 | writel_relaxed(sdata->dbg_bus[i], |
| 115 | s_ctrl->ctrl_base + 0x124); |
| 116 | wmb(); /* ensure register is committed */ |
| 117 | } |
| 118 | |
| 119 | if (dsi0_active) { |
| 120 | status0 = readl_relaxed(m_ctrl->ctrl_base + 0x128); |
| 121 | if (in_log) |
| 122 | pr_err("CTRL:0 bus_ctrl: 0x%x status: 0x%x\n", |
| 123 | sdata->dbg_bus[i], status0); |
| 124 | } |
| 125 | if (dsi1_active) { |
| 126 | status1 = readl_relaxed(s_ctrl->ctrl_base + 0x128); |
| 127 | if (in_log) |
| 128 | pr_err("CTRL:1 bus_ctrl: 0x%x status: 0x%x\n", |
| 129 | sdata->dbg_bus[i], status1); |
| 130 | } |
| 131 | |
| 132 | if (dump_addr && in_mem) { |
| 133 | dump_addr[i*4] = sdata->dbg_bus[i]; |
| 134 | dump_addr[i*4 + 1] = status0; |
| 135 | dump_addr[i*4 + 2] = status1; |
| 136 | dump_addr[i*4 + 3] = 0x0; |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | mdss_dsi_clk_ctrl(m_ctrl, m_ctrl->dsi_clk_handle, |
| 141 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF); |
| 142 | |
| 143 | pr_info("========End DSI Debug Bus=========\n"); |
| 144 | } |
| 145 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 146 | static void mdss_dsi_pm_qos_add_request(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 147 | { |
| 148 | struct irq_info *irq_info; |
| 149 | |
| 150 | if (!ctrl_pdata || !ctrl_pdata->shared_data) |
| 151 | return; |
| 152 | |
| 153 | irq_info = ctrl_pdata->dsi_hw->irq_info; |
| 154 | |
| 155 | if (!irq_info) |
| 156 | return; |
| 157 | |
| 158 | mutex_lock(&ctrl_pdata->shared_data->pm_qos_lock); |
| 159 | if (!ctrl_pdata->shared_data->pm_qos_req_cnt) { |
| 160 | pr_debug("%s: add request irq\n", __func__); |
| 161 | |
| 162 | mdss_dsi_pm_qos_request.type = PM_QOS_REQ_AFFINE_IRQ; |
| 163 | mdss_dsi_pm_qos_request.irq = irq_info->irq; |
| 164 | pm_qos_add_request(&mdss_dsi_pm_qos_request, |
| 165 | PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
| 166 | } |
| 167 | ctrl_pdata->shared_data->pm_qos_req_cnt++; |
| 168 | mutex_unlock(&ctrl_pdata->shared_data->pm_qos_lock); |
| 169 | } |
| 170 | |
| 171 | static void mdss_dsi_pm_qos_remove_request(struct dsi_shared_data *sdata) |
| 172 | { |
| 173 | if (!sdata) |
| 174 | return; |
| 175 | |
| 176 | mutex_lock(&sdata->pm_qos_lock); |
| 177 | if (sdata->pm_qos_req_cnt) { |
| 178 | sdata->pm_qos_req_cnt--; |
| 179 | if (!sdata->pm_qos_req_cnt) { |
| 180 | pr_debug("%s: remove request", __func__); |
| 181 | pm_qos_remove_request(&mdss_dsi_pm_qos_request); |
| 182 | } |
| 183 | } else { |
| 184 | pr_warn("%s: unbalanced pm_qos ref count\n", __func__); |
| 185 | } |
| 186 | mutex_unlock(&sdata->pm_qos_lock); |
| 187 | } |
| 188 | |
| 189 | static void mdss_dsi_pm_qos_update_request(int val) |
| 190 | { |
| 191 | pr_debug("%s: update request %d", __func__, val); |
| 192 | pm_qos_update_request(&mdss_dsi_pm_qos_request, val); |
| 193 | } |
| 194 | |
| 195 | static int mdss_dsi_pinctrl_set_state(struct mdss_dsi_ctrl_pdata *ctrl_pdata, |
| 196 | bool active); |
| 197 | |
| 198 | static struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl(u32 ctrl_id) |
| 199 | { |
| 200 | if (ctrl_id >= DSI_CTRL_MAX || !mdss_dsi_res) |
| 201 | return NULL; |
| 202 | |
| 203 | return mdss_dsi_res->ctrl_pdata[ctrl_id]; |
| 204 | } |
| 205 | |
| 206 | static void mdss_dsi_config_clk_src(struct platform_device *pdev) |
| 207 | { |
| 208 | struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev); |
| 209 | struct dsi_shared_data *sdata = dsi_res->shared_data; |
| 210 | |
| 211 | if (!sdata->ext_byte0_clk || !sdata->ext_pixel0_clk) { |
| 212 | pr_debug("%s: DSI-0 ext. clocks not present\n", __func__); |
| 213 | return; |
| 214 | } |
| 215 | |
| 216 | if (mdss_dsi_is_pll_src_default(sdata)) { |
| 217 | /* |
| 218 | * Default Mapping: |
| 219 | * 1. dual-dsi/single-dsi: |
| 220 | * DSI0 <--> PLL0 |
| 221 | * DSI1 <--> PLL1 |
| 222 | * 2. split-dsi: |
| 223 | * DSI0 <--> PLL0 |
| 224 | * DSI1 <--> PLL0 |
| 225 | */ |
| 226 | sdata->byte0_parent = sdata->ext_byte0_clk; |
| 227 | sdata->pixel0_parent = sdata->ext_pixel0_clk; |
| 228 | |
| 229 | if (mdss_dsi_is_hw_config_split(sdata)) { |
| 230 | sdata->byte1_parent = sdata->byte0_parent; |
| 231 | sdata->pixel1_parent = sdata->pixel0_parent; |
| 232 | } else if (sdata->ext_byte1_clk && sdata->ext_pixel1_clk) { |
| 233 | sdata->byte1_parent = sdata->ext_byte1_clk; |
| 234 | sdata->pixel1_parent = sdata->ext_pixel1_clk; |
| 235 | } else { |
| 236 | pr_debug("%s: DSI-1 external clocks not present\n", |
| 237 | __func__); |
| 238 | return; |
| 239 | } |
| 240 | |
| 241 | pr_debug("%s: default: DSI0 <--> PLL0, DSI1 <--> %s", __func__, |
| 242 | mdss_dsi_is_hw_config_split(sdata) ? "PLL0" : "PLL1"); |
| 243 | } else { |
| 244 | /* |
| 245 | * For split-dsi and single-dsi use cases, map the PLL source |
| 246 | * based on the pll source configuration. It is possible that |
| 247 | * for split-dsi case, the only supported config is to source |
| 248 | * the clocks from PLL0. This is not explicitly checked here as |
| 249 | * it should have been already enforced when validating the |
| 250 | * board configuration. |
| 251 | */ |
| 252 | if (mdss_dsi_is_pll_src_pll0(sdata)) { |
| 253 | pr_debug("%s: single source: PLL0", __func__); |
| 254 | sdata->byte0_parent = sdata->ext_byte0_clk; |
| 255 | sdata->pixel0_parent = sdata->ext_pixel0_clk; |
| 256 | } else if (mdss_dsi_is_pll_src_pll1(sdata)) { |
| 257 | if (sdata->ext_byte1_clk && sdata->ext_pixel1_clk) { |
| 258 | pr_debug("%s: single source: PLL1", __func__); |
| 259 | sdata->byte0_parent = sdata->ext_byte1_clk; |
| 260 | sdata->pixel0_parent = sdata->ext_pixel1_clk; |
| 261 | } else { |
| 262 | pr_err("%s: DSI-1 external clocks not present\n", |
| 263 | __func__); |
| 264 | return; |
| 265 | } |
| 266 | } |
| 267 | sdata->byte1_parent = sdata->byte0_parent; |
| 268 | sdata->pixel1_parent = sdata->pixel0_parent; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | static char const *mdss_dsi_get_clk_src(struct mdss_dsi_ctrl_pdata *ctrl) |
| 273 | { |
| 274 | struct dsi_shared_data *sdata; |
| 275 | |
| 276 | if (!ctrl) { |
| 277 | pr_err("%s: Invalid input data\n", __func__); |
| 278 | return "????"; |
| 279 | } |
| 280 | |
| 281 | sdata = ctrl->shared_data; |
| 282 | |
| 283 | if (mdss_dsi_is_left_ctrl(ctrl)) { |
| 284 | if (sdata->byte0_parent == sdata->ext_byte0_clk) |
| 285 | return "PLL0"; |
| 286 | else |
| 287 | return "PLL1"; |
| 288 | } else { |
| 289 | if (sdata->byte1_parent == sdata->ext_byte0_clk) |
| 290 | return "PLL0"; |
| 291 | else |
| 292 | return "PLL1"; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | static int mdss_dsi_set_clk_src(struct mdss_dsi_ctrl_pdata *ctrl) |
| 297 | { |
| 298 | int rc; |
| 299 | struct dsi_shared_data *sdata; |
| 300 | struct clk *byte_parent, *pixel_parent; |
| 301 | |
| 302 | if (!ctrl) { |
| 303 | pr_err("%s: Invalid input data\n", __func__); |
| 304 | return -EINVAL; |
| 305 | } |
| 306 | |
| 307 | sdata = ctrl->shared_data; |
| 308 | |
| 309 | if (!ctrl->byte_clk_rcg || !ctrl->pixel_clk_rcg) { |
| 310 | pr_debug("%s: set_clk_src not needed\n", __func__); |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | if (mdss_dsi_is_left_ctrl(ctrl)) { |
| 315 | byte_parent = sdata->byte0_parent; |
| 316 | pixel_parent = sdata->pixel0_parent; |
| 317 | } else { |
| 318 | byte_parent = sdata->byte1_parent; |
| 319 | pixel_parent = sdata->pixel1_parent; |
| 320 | } |
| 321 | |
| 322 | rc = clk_set_parent(ctrl->byte_clk_rcg, byte_parent); |
| 323 | if (rc) { |
| 324 | pr_err("%s: failed to set parent for byte clk for ctrl%d. rc=%d\n", |
| 325 | __func__, ctrl->ndx, rc); |
| 326 | goto error; |
| 327 | } |
| 328 | |
| 329 | rc = clk_set_parent(ctrl->pixel_clk_rcg, pixel_parent); |
| 330 | if (rc) { |
| 331 | pr_err("%s: failed to set parent for pixel clk for ctrl%d. rc=%d\n", |
| 332 | __func__, ctrl->ndx, rc); |
| 333 | goto error; |
| 334 | } |
| 335 | |
| 336 | pr_debug("%s: ctrl%d clock source set to %s", __func__, ctrl->ndx, |
| 337 | mdss_dsi_get_clk_src(ctrl)); |
| 338 | |
| 339 | error: |
| 340 | return rc; |
| 341 | } |
| 342 | |
| 343 | static int mdss_dsi_regulator_init(struct platform_device *pdev, |
| 344 | struct dsi_shared_data *sdata) |
| 345 | { |
| 346 | int rc = 0, i = 0, j = 0; |
| 347 | |
| 348 | if (!pdev || !sdata) { |
| 349 | pr_err("%s: invalid input\n", __func__); |
| 350 | return -EINVAL; |
| 351 | } |
| 352 | |
| 353 | for (i = DSI_CORE_PM; !rc && (i < DSI_MAX_PM); i++) { |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 354 | rc = msm_mdss_config_vreg(&pdev->dev, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 355 | sdata->power_data[i].vreg_config, |
| 356 | sdata->power_data[i].num_vreg, 1); |
| 357 | if (rc) { |
| 358 | pr_err("%s: failed to init vregs for %s\n", |
| 359 | __func__, __mdss_dsi_pm_name(i)); |
| 360 | for (j = i-1; j >= DSI_CORE_PM; j--) { |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 361 | msm_mdss_config_vreg(&pdev->dev, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 362 | sdata->power_data[j].vreg_config, |
| 363 | sdata->power_data[j].num_vreg, 0); |
| 364 | } |
| 365 | } |
| 366 | } |
| 367 | |
| 368 | return rc; |
| 369 | } |
| 370 | |
| 371 | static int mdss_dsi_panel_power_off(struct mdss_panel_data *pdata) |
| 372 | { |
| 373 | int ret = 0; |
| 374 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 375 | |
| 376 | if (pdata == NULL) { |
| 377 | pr_err("%s: Invalid input data\n", __func__); |
| 378 | ret = -EINVAL; |
| 379 | goto end; |
| 380 | } |
| 381 | |
| 382 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 383 | panel_data); |
| 384 | |
| 385 | ret = mdss_dsi_panel_reset(pdata, 0); |
| 386 | if (ret) { |
| 387 | pr_warn("%s: Panel reset failed. rc=%d\n", __func__, ret); |
| 388 | ret = 0; |
| 389 | } |
| 390 | |
Narender Ankam | 4fcd689 | 2018-06-11 13:09:00 +0530 | [diff] [blame] | 391 | if (gpio_is_valid(ctrl_pdata->vdd_ext_gpio)) { |
| 392 | ret = gpio_direction_output( |
| 393 | ctrl_pdata->vdd_ext_gpio, 0); |
| 394 | if (ret) |
| 395 | pr_err("%s: unable to set dir for vdd gpio\n", |
| 396 | __func__); |
| 397 | } |
| 398 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 399 | if (mdss_dsi_pinctrl_set_state(ctrl_pdata, false)) |
| 400 | pr_debug("reset disable: pinctrl not enabled\n"); |
| 401 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 402 | ret = msm_mdss_enable_vreg( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 403 | ctrl_pdata->panel_power_data.vreg_config, |
| 404 | ctrl_pdata->panel_power_data.num_vreg, 0); |
| 405 | if (ret) |
| 406 | pr_err("%s: failed to disable vregs for %s\n", |
| 407 | __func__, __mdss_dsi_pm_name(DSI_PANEL_PM)); |
| 408 | |
| 409 | end: |
| 410 | return ret; |
| 411 | } |
| 412 | |
| 413 | static int mdss_dsi_panel_power_on(struct mdss_panel_data *pdata) |
| 414 | { |
| 415 | int ret = 0; |
| 416 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 417 | |
jialongjhan | 7dfbf87 | 2020-04-21 20:24:23 +0800 | [diff] [blame^] | 418 | /*[Fairphone_8901][Jialong]To avoid fuzzy screen,pull high Touch reset pin when panel on start*/ |
| 419 | gpio_direction_output(64, 1); |
| 420 | /*[Fairphone_8901][Jialong]To avoid fuzzy screen,pull high Touch reset pin when panel on end*/ |
| 421 | |
| 422 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 423 | if (pdata == NULL) { |
| 424 | pr_err("%s: Invalid input data\n", __func__); |
| 425 | return -EINVAL; |
| 426 | } |
| 427 | |
| 428 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 429 | panel_data); |
| 430 | |
Narender Ankam | 4fcd689 | 2018-06-11 13:09:00 +0530 | [diff] [blame] | 431 | if (gpio_is_valid(ctrl_pdata->vdd_ext_gpio)) { |
| 432 | ret = gpio_direction_output( |
| 433 | ctrl_pdata->vdd_ext_gpio, 1); |
| 434 | usleep_range(3000, 4000); /* h/w recommended delay */ |
| 435 | if (ret) |
| 436 | pr_err("%s: unable to set dir for vdd gpio\n", |
| 437 | __func__); |
| 438 | } |
| 439 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 440 | ret = msm_mdss_enable_vreg( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 441 | ctrl_pdata->panel_power_data.vreg_config, |
| 442 | ctrl_pdata->panel_power_data.num_vreg, 1); |
| 443 | if (ret) { |
| 444 | pr_err("%s: failed to enable vregs for %s\n", |
| 445 | __func__, __mdss_dsi_pm_name(DSI_PANEL_PM)); |
| 446 | return ret; |
| 447 | } |
| 448 | |
| 449 | /* |
| 450 | * If continuous splash screen feature is enabled, then we need to |
| 451 | * request all the GPIOs that have already been configured in the |
| 452 | * bootloader. This needs to be done irresepective of whether |
| 453 | * the lp11_init flag is set or not. |
| 454 | */ |
| 455 | if (pdata->panel_info.cont_splash_enabled || |
| 456 | !pdata->panel_info.mipi.lp11_init) { |
| 457 | if (mdss_dsi_pinctrl_set_state(ctrl_pdata, true)) |
| 458 | pr_debug("reset enable: pinctrl not enabled\n"); |
| 459 | |
| 460 | ret = mdss_dsi_panel_reset(pdata, 1); |
| 461 | if (ret) |
| 462 | pr_err("%s: Panel reset failed. rc=%d\n", |
| 463 | __func__, ret); |
| 464 | } |
| 465 | |
| 466 | return ret; |
| 467 | } |
| 468 | |
| 469 | static int mdss_dsi_panel_power_lp(struct mdss_panel_data *pdata, int enable) |
| 470 | { |
| 471 | /* Panel power control when entering/exiting lp mode */ |
| 472 | return 0; |
| 473 | } |
| 474 | |
| 475 | static int mdss_dsi_panel_power_ulp(struct mdss_panel_data *pdata, |
| 476 | int enable) |
| 477 | { |
| 478 | int ret = 0, i; |
| 479 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 480 | u32 mode = enable ? DSS_REG_MODE_ULP : DSS_REG_MODE_ENABLE; |
| 481 | struct dsi_shared_data *sdata; |
| 482 | |
| 483 | pr_debug("%s: +\n", __func__); |
| 484 | if (pdata == NULL) { |
| 485 | pr_err("%s: Invalid input data\n", __func__); |
| 486 | return -EINVAL; |
| 487 | } |
| 488 | |
| 489 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 490 | panel_data); |
| 491 | sdata = ctrl_pdata->shared_data; |
| 492 | |
| 493 | for (i = 0; i < DSI_MAX_PM; i++) { |
| 494 | /* |
| 495 | * Core power module need to be controlled along with |
| 496 | * DSI core clocks. |
| 497 | */ |
| 498 | if (i == DSI_CORE_PM) |
| 499 | continue; |
| 500 | if (i == DSI_PANEL_PM) |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 501 | ret = msm_mdss_config_vreg_opt_mode( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 502 | ctrl_pdata->panel_power_data.vreg_config, |
| 503 | ctrl_pdata->panel_power_data.num_vreg, mode); |
| 504 | else |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 505 | ret = msm_mdss_config_vreg_opt_mode( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 506 | sdata->power_data[i].vreg_config, |
| 507 | sdata->power_data[i].num_vreg, mode); |
| 508 | if (ret) { |
| 509 | pr_err("%s: failed to config ulp opt mode for %s.rc=%d\n", |
| 510 | __func__, __mdss_dsi_pm_name(i), ret); |
| 511 | break; |
| 512 | } |
| 513 | } |
| 514 | |
| 515 | if (ret) { |
| 516 | mode = enable ? DSS_REG_MODE_ENABLE : DSS_REG_MODE_ULP; |
| 517 | for (; i >= 0; i--) |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 518 | msm_mdss_config_vreg_opt_mode( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 519 | ctrl_pdata->power_data[i].vreg_config, |
| 520 | ctrl_pdata->power_data[i].num_vreg, mode); |
| 521 | } |
| 522 | return ret; |
| 523 | } |
| 524 | |
| 525 | int mdss_dsi_panel_power_ctrl(struct mdss_panel_data *pdata, |
| 526 | int power_state) |
| 527 | { |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 528 | int ret = 0; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 529 | struct mdss_panel_info *pinfo; |
| 530 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 531 | |
| 532 | if (pdata == NULL) { |
| 533 | pr_err("%s: Invalid input data\n", __func__); |
| 534 | return -EINVAL; |
| 535 | } |
| 536 | |
| 537 | pinfo = &pdata->panel_info; |
| 538 | pr_debug("%pS-->%s: cur_power_state=%d req_power_state=%d\n", |
| 539 | __builtin_return_address(0), __func__, |
| 540 | pinfo->panel_power_state, power_state); |
| 541 | |
| 542 | if (pinfo->panel_power_state == power_state) { |
| 543 | pr_debug("%s: no change needed\n", __func__); |
| 544 | return 0; |
| 545 | } |
| 546 | |
| 547 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 548 | panel_data); |
| 549 | |
| 550 | /* |
| 551 | * If a dynamic mode switch is pending, the regulators should not |
| 552 | * be turned off or on. |
| 553 | */ |
| 554 | if (pdata->panel_info.dynamic_switch_pending) |
| 555 | return 0; |
| 556 | |
| 557 | switch (power_state) { |
| 558 | case MDSS_PANEL_POWER_OFF: |
| 559 | ret = mdss_dsi_panel_power_off(pdata); |
| 560 | break; |
| 561 | case MDSS_PANEL_POWER_ON: |
| 562 | if (mdss_dsi_is_panel_on_ulp(pdata)) { |
| 563 | ret = mdss_dsi_panel_power_ulp(pdata, false); |
| 564 | goto end; |
| 565 | } else if (mdss_dsi_is_panel_on_lp(pdata)) { |
| 566 | ret = mdss_dsi_panel_power_lp(pdata, false); |
| 567 | goto end; |
| 568 | } else { |
| 569 | ret = mdss_dsi_panel_power_on(pdata); |
| 570 | } |
| 571 | break; |
| 572 | case MDSS_PANEL_POWER_LP1: |
| 573 | if (mdss_dsi_is_panel_on_ulp(pdata)) |
| 574 | ret = mdss_dsi_panel_power_ulp(pdata, false); |
| 575 | else |
| 576 | ret = mdss_dsi_panel_power_lp(pdata, true); |
| 577 | /* |
| 578 | * temp workaround until framework issues pertaining to LP2 |
| 579 | * power state transitions are fixed. For now, we internally |
| 580 | * transition to LP2 state whenever core power is turned off |
| 581 | * in LP1 state |
| 582 | */ |
| 583 | break; |
| 584 | case MDSS_PANEL_POWER_LP2: |
| 585 | if (!ctrl_pdata->core_power) |
| 586 | ret = mdss_dsi_panel_power_ulp(pdata, true); |
| 587 | break; |
| 588 | default: |
| 589 | pr_err("%s: unknown panel power state requested (%d)\n", |
| 590 | __func__, power_state); |
| 591 | ret = -EINVAL; |
| 592 | } |
| 593 | |
| 594 | if (!ret) |
| 595 | pinfo->panel_power_state = power_state; |
| 596 | end: |
| 597 | return ret; |
| 598 | } |
| 599 | |
| 600 | static void mdss_dsi_put_dt_vreg_data(struct device *dev, |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 601 | struct mdss_module_power *module_power) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 602 | { |
| 603 | if (!module_power) { |
| 604 | pr_err("%s: invalid input\n", __func__); |
| 605 | return; |
| 606 | } |
| 607 | |
| 608 | if (module_power->vreg_config) { |
| 609 | devm_kfree(dev, module_power->vreg_config); |
| 610 | module_power->vreg_config = NULL; |
| 611 | } |
| 612 | module_power->num_vreg = 0; |
| 613 | } |
| 614 | |
| 615 | static int mdss_dsi_get_dt_vreg_data(struct device *dev, |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 616 | struct device_node *of_node, struct mdss_module_power *mp, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 617 | enum dsi_pm_type module) |
| 618 | { |
| 619 | int i = 0, rc = 0; |
| 620 | u32 tmp = 0; |
| 621 | struct device_node *supply_node = NULL; |
| 622 | const char *pm_supply_name = NULL; |
| 623 | struct device_node *supply_root_node = NULL; |
| 624 | |
| 625 | if (!dev || !mp) { |
| 626 | pr_err("%s: invalid input\n", __func__); |
| 627 | rc = -EINVAL; |
| 628 | return rc; |
| 629 | } |
| 630 | |
| 631 | mp->num_vreg = 0; |
| 632 | pm_supply_name = __mdss_dsi_pm_supply_node_name(module); |
| 633 | supply_root_node = of_get_child_by_name(of_node, pm_supply_name); |
| 634 | if (!supply_root_node) { |
| 635 | /* |
| 636 | * Try to get the root node for panel power supply using |
| 637 | * of_parse_phandle() API if of_get_child_by_name() API fails. |
| 638 | */ |
| 639 | supply_root_node = of_parse_phandle(of_node, pm_supply_name, 0); |
| 640 | if (!supply_root_node) { |
| 641 | pr_err("no supply entry present: %s\n", pm_supply_name); |
| 642 | goto novreg; |
| 643 | } |
| 644 | } |
| 645 | |
| 646 | |
| 647 | for_each_child_of_node(supply_root_node, supply_node) { |
| 648 | mp->num_vreg++; |
| 649 | } |
| 650 | |
| 651 | if (mp->num_vreg == 0) { |
| 652 | pr_debug("%s: no vreg\n", __func__); |
| 653 | goto novreg; |
| 654 | } else { |
| 655 | pr_debug("%s: vreg found. count=%d\n", __func__, mp->num_vreg); |
| 656 | } |
| 657 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 658 | mp->vreg_config = devm_kzalloc(dev, sizeof(struct mdss_vreg) * |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 659 | mp->num_vreg, GFP_KERNEL); |
| 660 | if (!mp->vreg_config) { |
| 661 | rc = -ENOMEM; |
| 662 | goto error; |
| 663 | } |
| 664 | |
| 665 | for_each_child_of_node(supply_root_node, supply_node) { |
| 666 | const char *st = NULL; |
| 667 | /* vreg-name */ |
| 668 | rc = of_property_read_string(supply_node, |
| 669 | "qcom,supply-name", &st); |
| 670 | if (rc) { |
| 671 | pr_err("%s: error reading name. rc=%d\n", |
| 672 | __func__, rc); |
| 673 | goto error; |
| 674 | } |
| 675 | snprintf(mp->vreg_config[i].vreg_name, |
| 676 | ARRAY_SIZE((mp->vreg_config[i].vreg_name)), "%s", st); |
| 677 | /* vreg-min-voltage */ |
| 678 | rc = of_property_read_u32(supply_node, |
| 679 | "qcom,supply-min-voltage", &tmp); |
| 680 | if (rc) { |
| 681 | pr_err("%s: error reading min volt. rc=%d\n", |
| 682 | __func__, rc); |
| 683 | goto error; |
| 684 | } |
| 685 | mp->vreg_config[i].min_voltage = tmp; |
| 686 | |
| 687 | /* vreg-max-voltage */ |
| 688 | rc = of_property_read_u32(supply_node, |
| 689 | "qcom,supply-max-voltage", &tmp); |
| 690 | if (rc) { |
| 691 | pr_err("%s: error reading max volt. rc=%d\n", |
| 692 | __func__, rc); |
| 693 | goto error; |
| 694 | } |
| 695 | mp->vreg_config[i].max_voltage = tmp; |
| 696 | |
| 697 | /* enable-load */ |
| 698 | rc = of_property_read_u32(supply_node, |
| 699 | "qcom,supply-enable-load", &tmp); |
| 700 | if (rc) { |
| 701 | pr_err("%s: error reading enable load. rc=%d\n", |
| 702 | __func__, rc); |
| 703 | goto error; |
| 704 | } |
| 705 | mp->vreg_config[i].load[DSS_REG_MODE_ENABLE] = tmp; |
| 706 | |
| 707 | /* disable-load */ |
| 708 | rc = of_property_read_u32(supply_node, |
| 709 | "qcom,supply-disable-load", &tmp); |
| 710 | if (rc) { |
| 711 | pr_err("%s: error reading disable load. rc=%d\n", |
| 712 | __func__, rc); |
| 713 | goto error; |
| 714 | } |
| 715 | mp->vreg_config[i].load[DSS_REG_MODE_DISABLE] = tmp; |
| 716 | |
| 717 | /* ulp-load */ |
| 718 | rc = of_property_read_u32(supply_node, |
| 719 | "qcom,supply-ulp-load", &tmp); |
| 720 | if (rc) { |
| 721 | pr_warn("%s: error reading ulp load. rc=%d\n", |
| 722 | __func__, rc); |
| 723 | rc = 0; |
| 724 | } |
| 725 | mp->vreg_config[i].load[DSS_REG_MODE_ULP] = (!rc ? tmp : |
| 726 | mp->vreg_config[i].load[DSS_REG_MODE_ENABLE]); |
| 727 | |
| 728 | /* pre-sleep */ |
| 729 | rc = of_property_read_u32(supply_node, |
| 730 | "qcom,supply-pre-on-sleep", &tmp); |
| 731 | if (rc) { |
| 732 | pr_debug("%s: error reading supply pre sleep value. rc=%d\n", |
| 733 | __func__, rc); |
| 734 | rc = 0; |
| 735 | } else { |
| 736 | mp->vreg_config[i].pre_on_sleep = tmp; |
| 737 | } |
| 738 | |
| 739 | rc = of_property_read_u32(supply_node, |
| 740 | "qcom,supply-pre-off-sleep", &tmp); |
| 741 | if (rc) { |
| 742 | pr_debug("%s: error reading supply pre sleep value. rc=%d\n", |
| 743 | __func__, rc); |
| 744 | rc = 0; |
| 745 | } else { |
| 746 | mp->vreg_config[i].pre_off_sleep = tmp; |
| 747 | } |
| 748 | |
| 749 | /* post-sleep */ |
| 750 | rc = of_property_read_u32(supply_node, |
| 751 | "qcom,supply-post-on-sleep", &tmp); |
| 752 | if (rc) { |
| 753 | pr_debug("%s: error reading supply post sleep value. rc=%d\n", |
| 754 | __func__, rc); |
| 755 | rc = 0; |
| 756 | } else { |
| 757 | mp->vreg_config[i].post_on_sleep = tmp; |
| 758 | } |
| 759 | |
| 760 | rc = of_property_read_u32(supply_node, |
| 761 | "qcom,supply-post-off-sleep", &tmp); |
| 762 | if (rc) { |
| 763 | pr_debug("%s: error reading supply post sleep value. rc=%d\n", |
| 764 | __func__, rc); |
| 765 | rc = 0; |
| 766 | } else { |
| 767 | mp->vreg_config[i].post_off_sleep = tmp; |
| 768 | } |
| 769 | |
| 770 | pr_debug("%s: %s min=%d, max=%d, enable=%d, disable=%d, ulp_load=%d preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n", |
| 771 | __func__, |
| 772 | mp->vreg_config[i].vreg_name, |
| 773 | mp->vreg_config[i].min_voltage, |
| 774 | mp->vreg_config[i].max_voltage, |
| 775 | mp->vreg_config[i].load[DSS_REG_MODE_ENABLE], |
| 776 | mp->vreg_config[i].load[DSS_REG_MODE_DISABLE], |
| 777 | mp->vreg_config[i].load[DSS_REG_MODE_ULP], |
| 778 | mp->vreg_config[i].pre_on_sleep, |
| 779 | mp->vreg_config[i].post_on_sleep, |
| 780 | mp->vreg_config[i].pre_off_sleep, |
| 781 | mp->vreg_config[i].post_off_sleep |
| 782 | ); |
| 783 | ++i; |
| 784 | } |
| 785 | |
| 786 | return rc; |
| 787 | |
| 788 | error: |
| 789 | if (mp->vreg_config) { |
| 790 | devm_kfree(dev, mp->vreg_config); |
| 791 | mp->vreg_config = NULL; |
| 792 | } |
| 793 | novreg: |
| 794 | mp->num_vreg = 0; |
| 795 | |
| 796 | return rc; |
| 797 | } |
| 798 | |
| 799 | static int mdss_dsi_get_panel_cfg(char *panel_cfg, |
| 800 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 801 | { |
| 802 | int rc; |
| 803 | struct mdss_panel_cfg *pan_cfg = NULL; |
| 804 | |
| 805 | if (!panel_cfg) |
| 806 | return MDSS_PANEL_INTF_INVALID; |
| 807 | |
| 808 | pan_cfg = ctrl->mdss_util->panel_intf_type(MDSS_PANEL_INTF_DSI); |
| 809 | if (IS_ERR(pan_cfg)) { |
| 810 | return PTR_ERR(pan_cfg); |
| 811 | } else if (!pan_cfg) { |
| 812 | panel_cfg[0] = 0; |
| 813 | return 0; |
| 814 | } |
| 815 | |
| 816 | pr_debug("%s:%d: cfg:[%s]\n", __func__, __LINE__, |
| 817 | pan_cfg->arg_cfg); |
| 818 | rc = strlcpy(panel_cfg, pan_cfg->arg_cfg, |
| 819 | sizeof(pan_cfg->arg_cfg)); |
| 820 | return rc; |
| 821 | } |
| 822 | |
| 823 | struct buf_data { |
| 824 | char *buf; /* cmd buf */ |
| 825 | int blen; /* cmd buf length */ |
| 826 | char *string_buf; /* cmd buf as string, 3 bytes per number */ |
| 827 | int sblen; /* string buffer length */ |
| 828 | int sync_flag; |
| 829 | struct mutex dbg_mutex; /* mutex to synchronize read/write/flush */ |
| 830 | }; |
| 831 | |
| 832 | struct mdss_dsi_debugfs_info { |
| 833 | struct dentry *root; |
| 834 | struct mdss_dsi_ctrl_pdata ctrl_pdata; |
| 835 | struct buf_data on_cmd; |
| 836 | struct buf_data off_cmd; |
| 837 | u32 override_flag; |
| 838 | }; |
| 839 | |
| 840 | static int mdss_dsi_cmd_state_open(struct inode *inode, struct file *file) |
| 841 | { |
| 842 | /* non-seekable */ |
| 843 | file->private_data = inode->i_private; |
| 844 | return nonseekable_open(inode, file); |
| 845 | } |
| 846 | |
| 847 | static ssize_t mdss_dsi_cmd_state_read(struct file *file, char __user *buf, |
| 848 | size_t count, loff_t *ppos) |
| 849 | { |
| 850 | int *link_state = file->private_data; |
| 851 | char buffer[32]; |
| 852 | int blen = 0; |
| 853 | |
| 854 | if (*ppos) |
| 855 | return 0; |
| 856 | |
| 857 | if ((*link_state) == DSI_HS_MODE) |
| 858 | blen = snprintf(buffer, sizeof(buffer), "dsi_hs_mode\n"); |
| 859 | else |
| 860 | blen = snprintf(buffer, sizeof(buffer), "dsi_lp_mode\n"); |
| 861 | |
| 862 | if (blen < 0) |
| 863 | return 0; |
| 864 | |
Rashi Bindra | 1dba452 | 2018-04-04 17:58:15 +0530 | [diff] [blame] | 865 | if (copy_to_user(buf, buffer, min(count, (size_t)blen+1))) |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 866 | return -EFAULT; |
| 867 | |
| 868 | *ppos += blen; |
| 869 | return blen; |
| 870 | } |
| 871 | |
| 872 | static ssize_t mdss_dsi_cmd_state_write(struct file *file, |
| 873 | const char __user *p, size_t count, loff_t *ppos) |
| 874 | { |
| 875 | int *link_state = file->private_data; |
| 876 | char *input; |
| 877 | |
| 878 | if (!count) { |
| 879 | pr_err("%s: Zero bytes to be written\n", __func__); |
| 880 | return -EINVAL; |
| 881 | } |
| 882 | |
| 883 | input = kmalloc(count, GFP_KERNEL); |
| 884 | if (!input) |
| 885 | return -ENOMEM; |
| 886 | |
| 887 | if (copy_from_user(input, p, count)) { |
| 888 | kfree(input); |
| 889 | return -EFAULT; |
| 890 | } |
| 891 | input[count-1] = '\0'; |
| 892 | |
| 893 | if (strnstr(input, "dsi_hs_mode", strlen("dsi_hs_mode"))) |
| 894 | *link_state = DSI_HS_MODE; |
| 895 | else |
| 896 | *link_state = DSI_LP_MODE; |
| 897 | |
| 898 | kfree(input); |
| 899 | return count; |
| 900 | } |
| 901 | |
| 902 | static const struct file_operations mdss_dsi_cmd_state_fop = { |
| 903 | .open = mdss_dsi_cmd_state_open, |
| 904 | .read = mdss_dsi_cmd_state_read, |
| 905 | .write = mdss_dsi_cmd_state_write, |
| 906 | }; |
| 907 | |
| 908 | static int mdss_dsi_cmd_open(struct inode *inode, struct file *file) |
| 909 | { |
| 910 | /* non-seekable */ |
| 911 | file->private_data = inode->i_private; |
| 912 | return nonseekable_open(inode, file); |
| 913 | } |
| 914 | |
| 915 | static ssize_t mdss_dsi_cmd_read(struct file *file, char __user *buf, |
| 916 | size_t count, loff_t *ppos) |
| 917 | { |
| 918 | struct buf_data *pcmds = file->private_data; |
| 919 | char *bp; |
| 920 | ssize_t ret = 0; |
| 921 | |
| 922 | mutex_lock(&pcmds->dbg_mutex); |
| 923 | if (*ppos == 0) { |
| 924 | kfree(pcmds->string_buf); |
| 925 | pcmds->string_buf = NULL; |
| 926 | pcmds->sblen = 0; |
| 927 | } |
| 928 | |
| 929 | if (!pcmds->string_buf) { |
| 930 | /* |
| 931 | * Buffer size is the sum of cmd length (3 bytes per number) |
| 932 | * with NULL terminater |
| 933 | */ |
| 934 | int bsize = ((pcmds->blen)*3 + 1); |
| 935 | int blen = 0; |
| 936 | char *buffer; |
| 937 | |
| 938 | buffer = kmalloc(bsize, GFP_KERNEL); |
| 939 | if (!buffer) { |
| 940 | mutex_unlock(&pcmds->dbg_mutex); |
| 941 | return -ENOMEM; |
| 942 | } |
| 943 | |
| 944 | bp = pcmds->buf; |
| 945 | while ((blen < (bsize-1)) && |
| 946 | (bp < ((pcmds->buf) + (pcmds->blen)))) { |
| 947 | struct dsi_ctrl_hdr dchdr = |
| 948 | *((struct dsi_ctrl_hdr *)bp); |
| 949 | int dhrlen = sizeof(dchdr), dlen; |
| 950 | char *tmp = (char *)(&dchdr); |
| 951 | |
| 952 | dlen = dchdr.dlen; |
| 953 | dchdr.dlen = htons(dchdr.dlen); |
| 954 | while (dhrlen--) |
| 955 | blen += snprintf(buffer+blen, bsize-blen, |
| 956 | "%02x ", (*tmp++)); |
| 957 | |
| 958 | bp += sizeof(dchdr); |
| 959 | while (dlen--) |
| 960 | blen += snprintf(buffer+blen, bsize-blen, |
| 961 | "%02x ", (*bp++)); |
| 962 | buffer[blen-1] = '\n'; |
| 963 | } |
| 964 | buffer[blen] = '\0'; |
| 965 | pcmds->string_buf = buffer; |
| 966 | pcmds->sblen = blen; |
| 967 | } |
| 968 | |
| 969 | /* |
| 970 | * The max value of count is PAGE_SIZE(4096). |
| 971 | * It may need multiple times of reading if string buf is too large |
| 972 | */ |
| 973 | if (*ppos >= (pcmds->sblen)) { |
| 974 | kfree(pcmds->string_buf); |
| 975 | pcmds->string_buf = NULL; |
| 976 | pcmds->sblen = 0; |
| 977 | mutex_unlock(&pcmds->dbg_mutex); |
| 978 | return 0; /* the end */ |
| 979 | } |
| 980 | ret = simple_read_from_buffer(buf, count, ppos, pcmds->string_buf, |
| 981 | pcmds->sblen); |
| 982 | mutex_unlock(&pcmds->dbg_mutex); |
| 983 | return ret; |
| 984 | } |
| 985 | |
| 986 | static ssize_t mdss_dsi_cmd_write(struct file *file, const char __user *p, |
| 987 | size_t count, loff_t *ppos) |
| 988 | { |
| 989 | struct buf_data *pcmds = file->private_data; |
| 990 | ssize_t ret = 0; |
Nirmal Abraham | 6d32cea | 2019-08-16 16:39:17 +0530 | [diff] [blame] | 991 | unsigned int blen = 0; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 992 | char *string_buf; |
| 993 | |
| 994 | mutex_lock(&pcmds->dbg_mutex); |
| 995 | if (*ppos == 0) { |
| 996 | kfree(pcmds->string_buf); |
| 997 | pcmds->string_buf = NULL; |
| 998 | pcmds->sblen = 0; |
| 999 | } |
| 1000 | |
| 1001 | /* Allocate memory for the received string */ |
| 1002 | blen = count + (pcmds->sblen); |
Nirmal Abraham | 6d32cea | 2019-08-16 16:39:17 +0530 | [diff] [blame] | 1003 | if (blen > U32_MAX - 1) { |
| 1004 | mutex_unlock(&pcmds->dbg_mutex); |
| 1005 | return -EINVAL; |
| 1006 | } |
| 1007 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1008 | string_buf = krealloc(pcmds->string_buf, blen + 1, GFP_KERNEL); |
| 1009 | if (!string_buf) { |
| 1010 | pr_err("%s: Failed to allocate memory\n", __func__); |
| 1011 | mutex_unlock(&pcmds->dbg_mutex); |
| 1012 | return -ENOMEM; |
| 1013 | } |
| 1014 | |
Nirmal Abraham | 6d32cea | 2019-08-16 16:39:17 +0530 | [diff] [blame] | 1015 | pcmds->string_buf = string_buf; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1016 | /* Writing in batches is possible */ |
| 1017 | ret = simple_write_to_buffer(string_buf, blen, ppos, p, count); |
| 1018 | if (ret < 0) { |
| 1019 | pr_err("%s: Failed to copy data\n", __func__); |
| 1020 | mutex_unlock(&pcmds->dbg_mutex); |
| 1021 | return -EINVAL; |
| 1022 | } |
| 1023 | |
| 1024 | string_buf[ret] = '\0'; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1025 | pcmds->sblen = count; |
| 1026 | mutex_unlock(&pcmds->dbg_mutex); |
| 1027 | return ret; |
| 1028 | } |
| 1029 | |
| 1030 | static int mdss_dsi_cmd_flush(struct file *file, fl_owner_t id) |
| 1031 | { |
| 1032 | struct buf_data *pcmds = file->private_data; |
raghavendra ambadas | a46d388 | 2019-05-22 17:14:21 +0530 | [diff] [blame] | 1033 | unsigned int len; |
| 1034 | int blen, i; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1035 | char *buf, *bufp, *bp; |
| 1036 | struct dsi_ctrl_hdr *dchdr; |
| 1037 | |
| 1038 | mutex_lock(&pcmds->dbg_mutex); |
| 1039 | |
| 1040 | if (!pcmds->string_buf) { |
| 1041 | mutex_unlock(&pcmds->dbg_mutex); |
| 1042 | return 0; |
| 1043 | } |
| 1044 | |
| 1045 | /* |
| 1046 | * Allocate memory for command buffer |
| 1047 | * 3 bytes per number, and 2 bytes for the last one |
| 1048 | */ |
| 1049 | blen = ((pcmds->sblen) + 2) / 3; |
| 1050 | buf = kcalloc(1, blen, GFP_KERNEL); |
| 1051 | if (!buf) { |
| 1052 | pr_err("%s: Failed to allocate memory\n", __func__); |
| 1053 | kfree(pcmds->string_buf); |
| 1054 | pcmds->string_buf = NULL; |
| 1055 | pcmds->sblen = 0; |
| 1056 | mutex_unlock(&pcmds->dbg_mutex); |
| 1057 | return -ENOMEM; |
| 1058 | } |
| 1059 | |
| 1060 | /* Translate the input string to command array */ |
| 1061 | bufp = pcmds->string_buf; |
| 1062 | for (i = 0; i < blen; i++) { |
| 1063 | uint32_t value = 0; |
| 1064 | int step = 0; |
| 1065 | |
| 1066 | if (sscanf(bufp, "%02x%n", &value, &step) > 0) { |
| 1067 | *(buf+i) = (char)value; |
| 1068 | bufp += step; |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | /* Scan dcs commands */ |
| 1073 | bp = buf; |
| 1074 | len = blen; |
| 1075 | while (len >= sizeof(*dchdr)) { |
| 1076 | dchdr = (struct dsi_ctrl_hdr *)bp; |
| 1077 | dchdr->dlen = ntohs(dchdr->dlen); |
raghavendra ambadas | a46d388 | 2019-05-22 17:14:21 +0530 | [diff] [blame] | 1078 | if (dchdr->dlen > (len - sizeof(*dchdr)) || dchdr->dlen < 0) { |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1079 | pr_err("%s: dtsi cmd=%x error, len=%d\n", |
| 1080 | __func__, dchdr->dtype, dchdr->dlen); |
| 1081 | kfree(buf); |
| 1082 | mutex_unlock(&pcmds->dbg_mutex); |
| 1083 | return -EINVAL; |
| 1084 | } |
| 1085 | bp += sizeof(*dchdr); |
| 1086 | len -= sizeof(*dchdr); |
| 1087 | bp += dchdr->dlen; |
| 1088 | len -= dchdr->dlen; |
| 1089 | } |
| 1090 | if (len != 0) { |
| 1091 | pr_err("%s: dcs_cmd=%x len=%d error!\n", __func__, |
| 1092 | bp[0], len); |
| 1093 | kfree(buf); |
| 1094 | mutex_unlock(&pcmds->dbg_mutex); |
| 1095 | return -EINVAL; |
| 1096 | } |
| 1097 | |
| 1098 | if (pcmds->sync_flag) { |
| 1099 | pcmds->buf = buf; |
| 1100 | pcmds->blen = blen; |
| 1101 | pcmds->sync_flag = 0; |
| 1102 | } else { |
| 1103 | kfree(pcmds->buf); |
| 1104 | pcmds->buf = buf; |
| 1105 | pcmds->blen = blen; |
| 1106 | } |
| 1107 | mutex_unlock(&pcmds->dbg_mutex); |
| 1108 | return 0; |
| 1109 | } |
| 1110 | |
| 1111 | static const struct file_operations mdss_dsi_cmd_fop = { |
| 1112 | .open = mdss_dsi_cmd_open, |
| 1113 | .read = mdss_dsi_cmd_read, |
| 1114 | .write = mdss_dsi_cmd_write, |
| 1115 | .flush = mdss_dsi_cmd_flush, |
| 1116 | }; |
| 1117 | |
| 1118 | struct dentry *dsi_debugfs_create_dcs_cmd(const char *name, umode_t mode, |
| 1119 | struct dentry *parent, struct buf_data *cmd, |
| 1120 | struct dsi_panel_cmds ctrl_cmds) |
| 1121 | { |
| 1122 | mutex_init(&cmd->dbg_mutex); |
| 1123 | cmd->buf = ctrl_cmds.buf; |
| 1124 | cmd->blen = ctrl_cmds.blen; |
| 1125 | cmd->string_buf = NULL; |
| 1126 | cmd->sblen = 0; |
| 1127 | cmd->sync_flag = 1; |
| 1128 | |
| 1129 | return debugfs_create_file(name, mode, parent, |
| 1130 | cmd, &mdss_dsi_cmd_fop); |
| 1131 | } |
| 1132 | |
| 1133 | #define DEBUGFS_CREATE_DCS_CMD(name, node, cmd, ctrl_cmd) \ |
| 1134 | dsi_debugfs_create_dcs_cmd(name, 0644, node, cmd, ctrl_cmd) |
| 1135 | |
| 1136 | static int mdss_dsi_debugfs_setup(struct mdss_panel_data *pdata, |
| 1137 | struct dentry *parent) |
| 1138 | { |
| 1139 | struct mdss_dsi_ctrl_pdata *ctrl_pdata, *dfs_ctrl; |
| 1140 | struct mdss_dsi_debugfs_info *dfs; |
| 1141 | |
| 1142 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1143 | panel_data); |
| 1144 | |
| 1145 | dfs = kcalloc(1, sizeof(*dfs), GFP_KERNEL); |
| 1146 | if (!dfs) |
| 1147 | return -ENOMEM; |
| 1148 | |
| 1149 | dfs->root = debugfs_create_dir("dsi_ctrl_pdata", parent); |
| 1150 | if (IS_ERR_OR_NULL(dfs->root)) { |
| 1151 | pr_err("%s: debugfs_create_dir dsi fail, error %ld\n", |
| 1152 | __func__, PTR_ERR(dfs->root)); |
| 1153 | kfree(dfs); |
| 1154 | return -ENODEV; |
| 1155 | } |
| 1156 | |
| 1157 | dfs_ctrl = &dfs->ctrl_pdata; |
| 1158 | debugfs_create_u32("override_flag", 0644, dfs->root, |
| 1159 | &dfs->override_flag); |
| 1160 | |
| 1161 | debugfs_create_bool("cmd_sync_wait_broadcast", 0644, dfs->root, |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 1162 | &dfs_ctrl->cmd_sync_wait_broadcast); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1163 | debugfs_create_bool("cmd_sync_wait_trigger", 0644, dfs->root, |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 1164 | &dfs_ctrl->cmd_sync_wait_trigger); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1165 | |
| 1166 | debugfs_create_file("dsi_on_cmd_state", 0644, dfs->root, |
| 1167 | &dfs_ctrl->on_cmds.link_state, &mdss_dsi_cmd_state_fop); |
| 1168 | debugfs_create_file("dsi_off_cmd_state", 0644, dfs->root, |
| 1169 | &dfs_ctrl->off_cmds.link_state, &mdss_dsi_cmd_state_fop); |
| 1170 | |
| 1171 | DEBUGFS_CREATE_DCS_CMD("dsi_on_cmd", dfs->root, &dfs->on_cmd, |
| 1172 | ctrl_pdata->on_cmds); |
| 1173 | DEBUGFS_CREATE_DCS_CMD("dsi_off_cmd", dfs->root, &dfs->off_cmd, |
| 1174 | ctrl_pdata->off_cmds); |
| 1175 | |
| 1176 | debugfs_create_u32("dsi_err_counter", 0644, dfs->root, |
| 1177 | &dfs_ctrl->err_cont.max_err_index); |
| 1178 | debugfs_create_u32("dsi_err_time_delta", 0644, dfs->root, |
| 1179 | &dfs_ctrl->err_cont.err_time_delta); |
| 1180 | |
| 1181 | dfs->override_flag = 0; |
| 1182 | dfs->ctrl_pdata = *ctrl_pdata; |
| 1183 | ctrl_pdata->debugfs_info = dfs; |
| 1184 | return 0; |
| 1185 | } |
| 1186 | |
| 1187 | static int mdss_dsi_debugfs_init(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1188 | { |
| 1189 | int rc; |
| 1190 | struct mdss_panel_data *pdata; |
| 1191 | struct mdss_panel_info panel_info; |
| 1192 | |
| 1193 | if (!ctrl_pdata) { |
| 1194 | pr_warn_once("%s: Invalid pdata!\n", __func__); |
| 1195 | return -EINVAL; |
| 1196 | } |
| 1197 | |
| 1198 | pdata = &ctrl_pdata->panel_data; |
| 1199 | if (!pdata) |
| 1200 | return -EINVAL; |
| 1201 | |
| 1202 | panel_info = pdata->panel_info; |
| 1203 | rc = mdss_dsi_debugfs_setup(pdata, panel_info.debugfs_info->root); |
| 1204 | if (rc) { |
| 1205 | pr_err("%s: Error in initilizing dsi ctrl debugfs\n", |
| 1206 | __func__); |
| 1207 | return rc; |
| 1208 | } |
| 1209 | |
| 1210 | pr_debug("%s: Initialized mdss_dsi_debugfs_init\n", __func__); |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
| 1214 | static void mdss_dsi_debugfs_cleanup(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1215 | { |
| 1216 | struct mdss_panel_data *pdata = &ctrl_pdata->panel_data; |
| 1217 | |
| 1218 | do { |
| 1219 | struct mdss_dsi_ctrl_pdata *ctrl = container_of(pdata, |
| 1220 | struct mdss_dsi_ctrl_pdata, panel_data); |
| 1221 | struct mdss_dsi_debugfs_info *dfs = ctrl->debugfs_info; |
| 1222 | |
| 1223 | if (dfs && dfs->root) |
| 1224 | debugfs_remove_recursive(dfs->root); |
| 1225 | kfree(dfs); |
| 1226 | pdata = pdata->next; |
| 1227 | } while (pdata); |
| 1228 | pr_debug("%s: Cleaned up mdss_dsi_debugfs_info\n", __func__); |
| 1229 | } |
| 1230 | |
| 1231 | static int _mdss_dsi_refresh_cmd(struct buf_data *new_cmds, |
| 1232 | struct dsi_panel_cmds *original_pcmds) |
| 1233 | { |
| 1234 | char *bp; |
| 1235 | int len, cnt, i; |
| 1236 | struct dsi_ctrl_hdr *dchdr; |
| 1237 | struct dsi_cmd_desc *cmds; |
| 1238 | |
| 1239 | if (new_cmds->sync_flag) |
| 1240 | return 0; |
| 1241 | |
| 1242 | bp = new_cmds->buf; |
| 1243 | len = new_cmds->blen; |
| 1244 | cnt = 0; |
| 1245 | /* Scan dcs commands and get dcs command count */ |
| 1246 | while (len >= sizeof(*dchdr)) { |
| 1247 | dchdr = (struct dsi_ctrl_hdr *)bp; |
| 1248 | if (dchdr->dlen > len) { |
| 1249 | pr_err("%s: dtsi cmd=%x error, len=%d\n", |
| 1250 | __func__, dchdr->dtype, dchdr->dlen); |
| 1251 | return -EINVAL; |
| 1252 | } |
| 1253 | bp += sizeof(*dchdr) + dchdr->dlen; |
| 1254 | len -= sizeof(*dchdr) + dchdr->dlen; |
| 1255 | cnt++; |
| 1256 | } |
| 1257 | |
| 1258 | if (len != 0) { |
| 1259 | pr_err("%s: dcs_cmd=%x len=%d error!\n", __func__, |
| 1260 | bp[0], len); |
| 1261 | return -EINVAL; |
| 1262 | } |
| 1263 | |
| 1264 | /* Reallocate space for dcs commands */ |
| 1265 | cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL); |
| 1266 | if (!cmds) |
| 1267 | return -ENOMEM; |
| 1268 | |
| 1269 | kfree(original_pcmds->buf); |
| 1270 | kfree(original_pcmds->cmds); |
| 1271 | original_pcmds->cmd_cnt = cnt; |
| 1272 | original_pcmds->cmds = cmds; |
| 1273 | original_pcmds->buf = new_cmds->buf; |
| 1274 | original_pcmds->blen = new_cmds->blen; |
| 1275 | |
| 1276 | bp = original_pcmds->buf; |
| 1277 | len = original_pcmds->blen; |
| 1278 | for (i = 0; i < cnt; i++) { |
| 1279 | dchdr = (struct dsi_ctrl_hdr *)bp; |
| 1280 | len -= sizeof(*dchdr); |
| 1281 | bp += sizeof(*dchdr); |
| 1282 | original_pcmds->cmds[i].dchdr = *dchdr; |
| 1283 | original_pcmds->cmds[i].payload = bp; |
| 1284 | bp += dchdr->dlen; |
| 1285 | len -= dchdr->dlen; |
| 1286 | } |
| 1287 | |
| 1288 | new_cmds->sync_flag = 1; |
| 1289 | return 0; |
| 1290 | } |
| 1291 | |
| 1292 | static void mdss_dsi_debugfsinfo_to_dsictrl_info( |
| 1293 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1294 | { |
| 1295 | struct mdss_dsi_debugfs_info *dfs = ctrl_pdata->debugfs_info; |
| 1296 | struct dsi_err_container *dfs_err_cont = &dfs->ctrl_pdata.err_cont; |
| 1297 | struct dsi_err_container *err_cont = &ctrl_pdata->err_cont; |
| 1298 | |
| 1299 | ctrl_pdata->cmd_sync_wait_broadcast = |
| 1300 | dfs->ctrl_pdata.cmd_sync_wait_broadcast; |
| 1301 | ctrl_pdata->cmd_sync_wait_trigger = |
| 1302 | dfs->ctrl_pdata.cmd_sync_wait_trigger; |
| 1303 | |
| 1304 | _mdss_dsi_refresh_cmd(&dfs->on_cmd, &ctrl_pdata->on_cmds); |
| 1305 | _mdss_dsi_refresh_cmd(&dfs->off_cmd, &ctrl_pdata->off_cmds); |
| 1306 | |
| 1307 | ctrl_pdata->on_cmds.link_state = |
| 1308 | dfs->ctrl_pdata.on_cmds.link_state; |
| 1309 | ctrl_pdata->off_cmds.link_state = |
| 1310 | dfs->ctrl_pdata.off_cmds.link_state; |
| 1311 | |
| 1312 | /* keep error counter between 2 to 10 */ |
| 1313 | if (dfs_err_cont->max_err_index >= 2 && |
| 1314 | dfs_err_cont->max_err_index <= MAX_ERR_INDEX) { |
| 1315 | err_cont->max_err_index = dfs_err_cont->max_err_index; |
| 1316 | } else { |
| 1317 | dfs_err_cont->max_err_index = err_cont->max_err_index; |
| 1318 | pr_warn("resetting the dsi error counter to %d\n", |
| 1319 | err_cont->max_err_index); |
| 1320 | } |
| 1321 | |
| 1322 | /* keep error duration between 16 ms to 100 seconds */ |
| 1323 | if (dfs_err_cont->err_time_delta >= 16 && |
| 1324 | dfs_err_cont->err_time_delta <= 100000) { |
| 1325 | err_cont->err_time_delta = dfs_err_cont->err_time_delta; |
| 1326 | } else { |
| 1327 | dfs_err_cont->err_time_delta = err_cont->err_time_delta; |
| 1328 | pr_warn("resetting the dsi error time delta to %d ms\n", |
| 1329 | err_cont->err_time_delta); |
| 1330 | } |
| 1331 | } |
| 1332 | |
| 1333 | static void mdss_dsi_validate_debugfs_info( |
| 1334 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1335 | { |
| 1336 | struct mdss_dsi_debugfs_info *dfs = ctrl_pdata->debugfs_info; |
| 1337 | |
| 1338 | if (dfs->override_flag) { |
| 1339 | pr_debug("%s: Overriding dsi ctrl_pdata with debugfs data\n", |
| 1340 | __func__); |
| 1341 | dfs->override_flag = 0; |
| 1342 | mdss_dsi_debugfsinfo_to_dsictrl_info(ctrl_pdata); |
| 1343 | } |
| 1344 | } |
| 1345 | |
| 1346 | static int mdss_dsi_off(struct mdss_panel_data *pdata, int power_state) |
| 1347 | { |
| 1348 | int ret = 0; |
| 1349 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1350 | struct mdss_panel_info *panel_info = NULL; |
| 1351 | |
| 1352 | if (pdata == NULL) { |
| 1353 | pr_err("%s: Invalid input data\n", __func__); |
| 1354 | return -EINVAL; |
| 1355 | } |
| 1356 | |
| 1357 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1358 | panel_data); |
| 1359 | |
| 1360 | panel_info = &ctrl_pdata->panel_data.panel_info; |
| 1361 | |
| 1362 | pr_debug("%s+: ctrl=%pK ndx=%d power_state=%d\n", |
| 1363 | __func__, ctrl_pdata, ctrl_pdata->ndx, power_state); |
| 1364 | |
| 1365 | if (power_state == panel_info->panel_power_state) { |
| 1366 | pr_debug("%s: No change in power state %d -> %d\n", __func__, |
| 1367 | panel_info->panel_power_state, power_state); |
| 1368 | goto end; |
| 1369 | } |
| 1370 | |
| 1371 | if (mdss_panel_is_power_on(power_state)) { |
| 1372 | pr_debug("%s: dsi_off with panel always on\n", __func__); |
| 1373 | goto panel_power_ctrl; |
| 1374 | } |
| 1375 | |
| 1376 | /* |
| 1377 | * Link clocks should be turned off before PHY can be disabled. |
| 1378 | * For command mode panels, all clocks are turned off prior to reaching |
| 1379 | * here, so core clocks should be turned on before accessing hardware |
| 1380 | * registers. For video mode panel, turn off link clocks and then |
| 1381 | * disable PHY |
| 1382 | */ |
| 1383 | if (pdata->panel_info.type == MIPI_CMD_PANEL) |
| 1384 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1385 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON); |
| 1386 | else |
| 1387 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1388 | MDSS_DSI_LINK_CLK, MDSS_DSI_CLK_OFF); |
| 1389 | |
| 1390 | if (!pdata->panel_info.ulps_suspend_enabled) { |
| 1391 | /* disable DSI controller */ |
| 1392 | mdss_dsi_controller_cfg(0, pdata); |
| 1393 | |
| 1394 | /* disable DSI phy */ |
| 1395 | mdss_dsi_phy_disable(ctrl_pdata); |
| 1396 | } |
| 1397 | ctrl_pdata->ctrl_state &= ~CTRL_STATE_DSI_ACTIVE; |
| 1398 | |
| 1399 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1400 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF); |
| 1401 | |
| 1402 | panel_power_ctrl: |
| 1403 | ret = mdss_dsi_panel_power_ctrl(pdata, power_state); |
| 1404 | if (ret) { |
| 1405 | pr_err("%s: Panel power off failed\n", __func__); |
| 1406 | goto end; |
| 1407 | } |
| 1408 | |
| 1409 | if (panel_info->dynamic_fps |
| 1410 | && (panel_info->dfps_update == DFPS_SUSPEND_RESUME_MODE) |
| 1411 | && (panel_info->new_fps != panel_info->mipi.frame_rate)) |
| 1412 | panel_info->mipi.frame_rate = panel_info->new_fps; |
| 1413 | |
| 1414 | /* Initialize Max Packet size for DCS reads */ |
| 1415 | ctrl_pdata->cur_max_pkt_size = 0; |
| 1416 | end: |
| 1417 | pr_debug("%s-:\n", __func__); |
| 1418 | |
| 1419 | return ret; |
| 1420 | } |
| 1421 | |
| 1422 | int mdss_dsi_switch_mode(struct mdss_panel_data *pdata, int mode) |
| 1423 | { |
| 1424 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1425 | struct mipi_panel_info *pinfo; |
| 1426 | bool dsi_ctrl_setup_needed = false; |
| 1427 | |
| 1428 | if (!pdata) { |
| 1429 | pr_err("%s: Invalid input data\n", __func__); |
| 1430 | return -EINVAL; |
| 1431 | } |
| 1432 | pr_debug("%s, start\n", __func__); |
| 1433 | |
| 1434 | pinfo = &pdata->panel_info.mipi; |
| 1435 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1436 | panel_data); |
| 1437 | |
| 1438 | if ((pinfo->dms_mode != DYNAMIC_MODE_RESOLUTION_SWITCH_IMMEDIATE) && |
| 1439 | (pinfo->dms_mode != DYNAMIC_MODE_SWITCH_IMMEDIATE)) { |
| 1440 | pr_debug("%s: Dynamic mode switch not enabled.\n", __func__); |
| 1441 | return -EPERM; |
| 1442 | } |
| 1443 | |
| 1444 | if (mode == MIPI_VIDEO_PANEL) { |
| 1445 | mode = SWITCH_TO_VIDEO_MODE; |
| 1446 | } else if (mode == MIPI_CMD_PANEL) { |
| 1447 | mode = SWITCH_TO_CMD_MODE; |
| 1448 | } else if (mode == SWITCH_RESOLUTION) { |
| 1449 | dsi_ctrl_setup_needed = true; |
| 1450 | pr_debug("Resolution switch mode selected\n"); |
| 1451 | } else { |
| 1452 | pr_err("Invalid mode selected, mode=%d\n", mode); |
| 1453 | return -EINVAL; |
| 1454 | } |
| 1455 | |
| 1456 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1457 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 1458 | if (dsi_ctrl_setup_needed) |
| 1459 | mdss_dsi_ctrl_setup(ctrl_pdata); |
| 1460 | ctrl_pdata->switch_mode(pdata, mode); |
| 1461 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1462 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1463 | |
| 1464 | pr_debug("%s, end\n", __func__); |
| 1465 | return 0; |
| 1466 | } |
| 1467 | |
| 1468 | static int mdss_dsi_reconfig(struct mdss_panel_data *pdata, int mode) |
| 1469 | { |
| 1470 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1471 | struct mipi_panel_info *pinfo; |
| 1472 | |
| 1473 | if (!pdata) { |
| 1474 | pr_err("%s: Invalid input data\n", __func__); |
| 1475 | return -EINVAL; |
| 1476 | } |
| 1477 | pr_debug("%s, start\n", __func__); |
| 1478 | |
| 1479 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1480 | panel_data); |
| 1481 | pinfo = &pdata->panel_info.mipi; |
| 1482 | |
| 1483 | if (pinfo->dms_mode == DYNAMIC_MODE_SWITCH_IMMEDIATE) { |
| 1484 | /* reset DSI */ |
| 1485 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1486 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 1487 | mdss_dsi_sw_reset(ctrl_pdata, true); |
| 1488 | mdss_dsi_ctrl_setup(ctrl_pdata); |
| 1489 | mdss_dsi_controller_cfg(true, pdata); |
| 1490 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1491 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1492 | } |
| 1493 | |
| 1494 | pr_debug("%s, end\n", __func__); |
| 1495 | return 0; |
| 1496 | } |
| 1497 | static int mdss_dsi_update_panel_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata, |
| 1498 | int mode) |
| 1499 | { |
| 1500 | int ret = 0; |
| 1501 | struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info); |
| 1502 | |
| 1503 | if (mode == DSI_CMD_MODE) { |
| 1504 | pinfo->mipi.mode = DSI_CMD_MODE; |
| 1505 | pinfo->type = MIPI_CMD_PANEL; |
| 1506 | pinfo->mipi.vsync_enable = 1; |
| 1507 | pinfo->mipi.hw_vsync_mode = 1; |
| 1508 | pinfo->partial_update_enabled = pinfo->partial_update_supported; |
| 1509 | } else { /*video mode*/ |
| 1510 | pinfo->mipi.mode = DSI_VIDEO_MODE; |
| 1511 | pinfo->type = MIPI_VIDEO_PANEL; |
| 1512 | pinfo->mipi.vsync_enable = 0; |
| 1513 | pinfo->mipi.hw_vsync_mode = 0; |
| 1514 | pinfo->partial_update_enabled = 0; |
| 1515 | } |
| 1516 | |
| 1517 | ctrl_pdata->panel_mode = pinfo->mipi.mode; |
| 1518 | mdss_panel_get_dst_fmt(pinfo->bpp, pinfo->mipi.mode, |
| 1519 | pinfo->mipi.pixel_packing, &(pinfo->mipi.dst_format)); |
| 1520 | return ret; |
| 1521 | } |
| 1522 | |
| 1523 | int mdss_dsi_on(struct mdss_panel_data *pdata) |
| 1524 | { |
| 1525 | int ret = 0; |
| 1526 | struct mdss_panel_info *pinfo; |
| 1527 | struct mipi_panel_info *mipi; |
| 1528 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1529 | int cur_power_state; |
| 1530 | |
| 1531 | if (pdata == NULL) { |
| 1532 | pr_err("%s: Invalid input data\n", __func__); |
| 1533 | return -EINVAL; |
| 1534 | } |
| 1535 | |
| 1536 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1537 | panel_data); |
| 1538 | |
| 1539 | if (ctrl_pdata->debugfs_info) |
| 1540 | mdss_dsi_validate_debugfs_info(ctrl_pdata); |
| 1541 | |
| 1542 | cur_power_state = pdata->panel_info.panel_power_state; |
| 1543 | pr_debug("%s+: ctrl=%pK ndx=%d cur_power_state=%d\n", __func__, |
| 1544 | ctrl_pdata, ctrl_pdata->ndx, cur_power_state); |
| 1545 | |
| 1546 | pinfo = &pdata->panel_info; |
| 1547 | mipi = &pdata->panel_info.mipi; |
| 1548 | |
| 1549 | if (mdss_dsi_is_panel_on_interactive(pdata)) { |
| 1550 | /* |
| 1551 | * all interrupts are disabled at LK |
| 1552 | * for cont_splash case, intr mask bits need |
| 1553 | * to be restored to allow dcs command be |
| 1554 | * sent to panel |
| 1555 | */ |
| 1556 | mdss_dsi_restore_intr_mask(ctrl_pdata); |
| 1557 | pr_debug("%s: panel already on\n", __func__); |
| 1558 | goto end; |
| 1559 | } |
| 1560 | |
| 1561 | ret = mdss_dsi_panel_power_ctrl(pdata, MDSS_PANEL_POWER_ON); |
| 1562 | if (ret) { |
| 1563 | pr_err("%s:Panel power on failed. rc=%d\n", __func__, ret); |
| 1564 | goto end; |
| 1565 | } |
| 1566 | |
| 1567 | if (mdss_panel_is_power_on(cur_power_state)) { |
| 1568 | pr_debug("%s: dsi_on from panel low power state\n", __func__); |
| 1569 | goto end; |
| 1570 | } |
| 1571 | |
| 1572 | ret = mdss_dsi_set_clk_src(ctrl_pdata); |
| 1573 | if (ret) { |
| 1574 | pr_err("%s: failed to set clk src. rc=%d\n", __func__, ret); |
| 1575 | goto end; |
| 1576 | } |
| 1577 | |
| 1578 | /* |
| 1579 | * Enable DSI core clocks prior to resetting and initializing DSI |
| 1580 | * Phy. Phy and ctrl setup need to be done before enabling the link |
| 1581 | * clocks. |
| 1582 | */ |
| 1583 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1584 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON); |
| 1585 | |
| 1586 | /* |
| 1587 | * If ULPS during suspend feature is enabled, then DSI PHY was |
| 1588 | * left on during suspend. In this case, we do not need to reset/init |
| 1589 | * PHY. This would have already been done when the CORE clocks are |
| 1590 | * turned on. However, if cont splash is disabled, the first time DSI |
| 1591 | * is powered on, phy init needs to be done unconditionally. |
| 1592 | */ |
| 1593 | if (!pdata->panel_info.ulps_suspend_enabled || !ctrl_pdata->ulps) { |
| 1594 | mdss_dsi_phy_sw_reset(ctrl_pdata); |
| 1595 | mdss_dsi_phy_init(ctrl_pdata); |
| 1596 | mdss_dsi_ctrl_setup(ctrl_pdata); |
| 1597 | } |
| 1598 | ctrl_pdata->ctrl_state |= CTRL_STATE_DSI_ACTIVE; |
| 1599 | |
| 1600 | /* DSI link clocks need to be on prior to ctrl sw reset */ |
| 1601 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1602 | MDSS_DSI_LINK_CLK, MDSS_DSI_CLK_ON); |
| 1603 | mdss_dsi_sw_reset(ctrl_pdata, true); |
| 1604 | |
| 1605 | /* |
| 1606 | * Issue hardware reset line after enabling the DSI clocks and data |
| 1607 | * data lanes for LP11 init |
| 1608 | */ |
| 1609 | if (mipi->lp11_init) { |
| 1610 | if (mdss_dsi_pinctrl_set_state(ctrl_pdata, true)) |
| 1611 | pr_debug("reset enable: pinctrl not enabled\n"); |
| 1612 | mdss_dsi_panel_reset(pdata, 1); |
| 1613 | } |
| 1614 | |
| 1615 | if (mipi->init_delay) |
| 1616 | usleep_range(mipi->init_delay, mipi->init_delay + 10); |
| 1617 | |
| 1618 | if (mipi->force_clk_lane_hs) { |
| 1619 | u32 tmp; |
| 1620 | |
| 1621 | tmp = MIPI_INP((ctrl_pdata->ctrl_base) + 0xac); |
| 1622 | tmp |= (1<<28); |
| 1623 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0xac, tmp); |
| 1624 | wmb(); /* ensure write is finished before progressing */ |
| 1625 | } |
| 1626 | |
| 1627 | if (pdata->panel_info.type == MIPI_CMD_PANEL) |
| 1628 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1629 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1630 | |
| 1631 | end: |
| 1632 | pr_debug("%s-:\n", __func__); |
| 1633 | return ret; |
| 1634 | } |
| 1635 | |
| 1636 | static int mdss_dsi_pinctrl_set_state( |
| 1637 | struct mdss_dsi_ctrl_pdata *ctrl_pdata, |
| 1638 | bool active) |
| 1639 | { |
| 1640 | struct pinctrl_state *pin_state; |
| 1641 | struct mdss_panel_info *pinfo = NULL; |
| 1642 | int rc = -EFAULT; |
| 1643 | |
| 1644 | if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.pinctrl)) |
| 1645 | return PTR_ERR(ctrl_pdata->pin_res.pinctrl); |
| 1646 | |
| 1647 | pinfo = &ctrl_pdata->panel_data.panel_info; |
| 1648 | if ((mdss_dsi_is_right_ctrl(ctrl_pdata) && |
| 1649 | mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data)) || |
| 1650 | pinfo->is_dba_panel) { |
| 1651 | pr_debug("%s:%d, right ctrl pinctrl config not needed\n", |
| 1652 | __func__, __LINE__); |
| 1653 | return 0; |
| 1654 | } |
| 1655 | |
| 1656 | pin_state = active ? ctrl_pdata->pin_res.gpio_state_active |
| 1657 | : ctrl_pdata->pin_res.gpio_state_suspend; |
| 1658 | if (!IS_ERR_OR_NULL(pin_state)) { |
| 1659 | rc = pinctrl_select_state(ctrl_pdata->pin_res.pinctrl, |
| 1660 | pin_state); |
| 1661 | if (rc) |
| 1662 | pr_err("%s: can not set %s pins\n", __func__, |
| 1663 | active ? MDSS_PINCTRL_STATE_DEFAULT |
| 1664 | : MDSS_PINCTRL_STATE_SLEEP); |
| 1665 | } else { |
| 1666 | pr_err("%s: invalid '%s' pinstate\n", __func__, |
| 1667 | active ? MDSS_PINCTRL_STATE_DEFAULT |
| 1668 | : MDSS_PINCTRL_STATE_SLEEP); |
| 1669 | } |
| 1670 | return rc; |
| 1671 | } |
| 1672 | |
| 1673 | static int mdss_dsi_pinctrl_init(struct platform_device *pdev) |
| 1674 | { |
| 1675 | struct mdss_dsi_ctrl_pdata *ctrl_pdata; |
| 1676 | |
| 1677 | ctrl_pdata = platform_get_drvdata(pdev); |
| 1678 | ctrl_pdata->pin_res.pinctrl = devm_pinctrl_get(&pdev->dev); |
| 1679 | if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.pinctrl)) { |
| 1680 | pr_err("%s: failed to get pinctrl\n", __func__); |
| 1681 | return PTR_ERR(ctrl_pdata->pin_res.pinctrl); |
| 1682 | } |
| 1683 | |
| 1684 | ctrl_pdata->pin_res.gpio_state_active |
| 1685 | = pinctrl_lookup_state(ctrl_pdata->pin_res.pinctrl, |
| 1686 | MDSS_PINCTRL_STATE_DEFAULT); |
| 1687 | if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.gpio_state_active)) |
| 1688 | pr_warn("%s: can not get default pinstate\n", __func__); |
| 1689 | |
| 1690 | ctrl_pdata->pin_res.gpio_state_suspend |
| 1691 | = pinctrl_lookup_state(ctrl_pdata->pin_res.pinctrl, |
| 1692 | MDSS_PINCTRL_STATE_SLEEP); |
| 1693 | if (IS_ERR_OR_NULL(ctrl_pdata->pin_res.gpio_state_suspend)) |
| 1694 | pr_warn("%s: can not get sleep pinstate\n", __func__); |
| 1695 | |
| 1696 | return 0; |
| 1697 | } |
| 1698 | |
| 1699 | static int mdss_dsi_unblank(struct mdss_panel_data *pdata) |
| 1700 | { |
| 1701 | int ret = 0; |
| 1702 | struct mipi_panel_info *mipi; |
| 1703 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1704 | struct mdss_dsi_ctrl_pdata *sctrl = NULL; |
| 1705 | |
| 1706 | if (pdata == NULL) { |
| 1707 | pr_err("%s: Invalid input data\n", __func__); |
| 1708 | return -EINVAL; |
| 1709 | } |
| 1710 | |
| 1711 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1712 | panel_data); |
| 1713 | mipi = &pdata->panel_info.mipi; |
| 1714 | |
| 1715 | pr_debug("%s+: ctrl=%pK ndx=%d cur_power_state=%d ctrl_state=%x\n", |
| 1716 | __func__, ctrl_pdata, ctrl_pdata->ndx, |
| 1717 | pdata->panel_info.panel_power_state, ctrl_pdata->ctrl_state); |
| 1718 | |
| 1719 | mdss_dsi_pm_qos_update_request(DSI_DISABLE_PC_LATENCY); |
| 1720 | |
| 1721 | if (mdss_dsi_is_ctrl_clk_master(ctrl_pdata)) |
| 1722 | sctrl = mdss_dsi_get_ctrl_clk_slave(); |
| 1723 | |
| 1724 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1725 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 1726 | if (sctrl) |
| 1727 | mdss_dsi_clk_ctrl(sctrl, sctrl->dsi_clk_handle, |
| 1728 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 1729 | |
| 1730 | if (ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_LP) { |
| 1731 | pr_debug("%s: dsi_unblank with panel always on\n", __func__); |
| 1732 | if (ctrl_pdata->low_power_config) |
| 1733 | ret = ctrl_pdata->low_power_config(pdata, false); |
| 1734 | if (!ret) |
| 1735 | ctrl_pdata->ctrl_state &= ~CTRL_STATE_PANEL_LP; |
| 1736 | goto error; |
| 1737 | } |
| 1738 | |
| 1739 | if (!(ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_INIT)) { |
| 1740 | if (!pdata->panel_info.dynamic_switch_pending) { |
| 1741 | ATRACE_BEGIN("dsi_panel_on"); |
| 1742 | ret = ctrl_pdata->on(pdata); |
| 1743 | if (ret) { |
| 1744 | pr_err("%s: unable to initialize the panel\n", |
| 1745 | __func__); |
| 1746 | goto error; |
| 1747 | } |
| 1748 | ATRACE_END("dsi_panel_on"); |
| 1749 | } |
| 1750 | } |
| 1751 | |
| 1752 | if ((pdata->panel_info.type == MIPI_CMD_PANEL) && |
| 1753 | mipi->vsync_enable && mipi->hw_vsync_mode) { |
| 1754 | mdss_dsi_set_tear_on(ctrl_pdata); |
| 1755 | } |
| 1756 | |
| 1757 | ctrl_pdata->ctrl_state |= CTRL_STATE_PANEL_INIT; |
| 1758 | |
| 1759 | error: |
| 1760 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1761 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1762 | if (sctrl) |
| 1763 | mdss_dsi_clk_ctrl(sctrl, sctrl->dsi_clk_handle, |
| 1764 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1765 | |
| 1766 | mdss_dsi_pm_qos_update_request(DSI_ENABLE_PC_LATENCY); |
| 1767 | |
| 1768 | pr_debug("%s-:\n", __func__); |
| 1769 | |
| 1770 | return ret; |
| 1771 | } |
| 1772 | |
| 1773 | static int mdss_dsi_blank(struct mdss_panel_data *pdata, int power_state) |
| 1774 | { |
| 1775 | int ret = 0; |
| 1776 | struct mipi_panel_info *mipi; |
| 1777 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1778 | |
| 1779 | if (pdata == NULL) { |
| 1780 | pr_err("%s: Invalid input data\n", __func__); |
| 1781 | return -EINVAL; |
| 1782 | } |
| 1783 | |
| 1784 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1785 | panel_data); |
| 1786 | mipi = &pdata->panel_info.mipi; |
| 1787 | |
| 1788 | pr_debug("%s+: ctrl=%pK ndx=%d power_state=%d\n", |
| 1789 | __func__, ctrl_pdata, ctrl_pdata->ndx, power_state); |
| 1790 | |
| 1791 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1792 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 1793 | |
| 1794 | if (mdss_panel_is_power_on_lp(power_state)) { |
| 1795 | pr_debug("%s: low power state requested\n", __func__); |
| 1796 | if (ctrl_pdata->low_power_config) |
| 1797 | ret = ctrl_pdata->low_power_config(pdata, true); |
| 1798 | if (!ret) |
| 1799 | ctrl_pdata->ctrl_state |= CTRL_STATE_PANEL_LP; |
| 1800 | goto error; |
| 1801 | } |
| 1802 | |
| 1803 | if (pdata->panel_info.type == MIPI_VIDEO_PANEL && |
| 1804 | ctrl_pdata->off_cmds.link_state == DSI_LP_MODE) { |
| 1805 | mdss_dsi_sw_reset(ctrl_pdata, false); |
| 1806 | mdss_dsi_host_init(pdata); |
| 1807 | } |
| 1808 | |
| 1809 | mdss_dsi_op_mode_config(DSI_CMD_MODE, pdata); |
| 1810 | |
| 1811 | if (pdata->panel_info.dynamic_switch_pending) { |
| 1812 | pr_info("%s: switching to %s mode\n", __func__, |
| 1813 | (pdata->panel_info.mipi.mode ? "video" : "command")); |
| 1814 | if (pdata->panel_info.type == MIPI_CMD_PANEL) { |
| 1815 | ctrl_pdata->switch_mode(pdata, SWITCH_TO_VIDEO_MODE); |
| 1816 | } else if (pdata->panel_info.type == MIPI_VIDEO_PANEL) { |
| 1817 | ctrl_pdata->switch_mode(pdata, SWITCH_TO_CMD_MODE); |
| 1818 | mdss_dsi_set_tear_off(ctrl_pdata); |
| 1819 | } |
| 1820 | } |
| 1821 | |
| 1822 | if ((pdata->panel_info.type == MIPI_CMD_PANEL) && |
| 1823 | mipi->vsync_enable && mipi->hw_vsync_mode) { |
| 1824 | mdss_dsi_set_tear_off(ctrl_pdata); |
| 1825 | } |
| 1826 | |
| 1827 | if (ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_INIT) { |
| 1828 | if (!pdata->panel_info.dynamic_switch_pending) { |
| 1829 | ATRACE_BEGIN("dsi_panel_off"); |
| 1830 | ret = ctrl_pdata->off(pdata); |
| 1831 | if (ret) { |
Arun kumar | 162db22 | 2018-05-09 17:28:40 +0530 | [diff] [blame] | 1832 | pr_err("%s: Panel OFF failed\n", |
| 1833 | __func__); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1834 | goto error; |
| 1835 | } |
| 1836 | ATRACE_END("dsi_panel_off"); |
| 1837 | } |
| 1838 | ctrl_pdata->ctrl_state &= ~(CTRL_STATE_PANEL_INIT | |
| 1839 | CTRL_STATE_PANEL_LP); |
| 1840 | } |
| 1841 | |
| 1842 | error: |
| 1843 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1844 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1845 | pr_debug("%s-:End\n", __func__); |
| 1846 | return ret; |
| 1847 | } |
| 1848 | |
| 1849 | static int mdss_dsi_post_panel_on(struct mdss_panel_data *pdata) |
| 1850 | { |
| 1851 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1852 | |
| 1853 | if (pdata == NULL) { |
| 1854 | pr_err("%s: Invalid input data\n", __func__); |
| 1855 | return -EINVAL; |
| 1856 | } |
| 1857 | |
| 1858 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1859 | panel_data); |
| 1860 | |
| 1861 | pr_debug("%s+: ctrl=%pK ndx=%d\n", __func__, |
| 1862 | ctrl_pdata, ctrl_pdata->ndx); |
| 1863 | |
| 1864 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1865 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 1866 | |
| 1867 | if (ctrl_pdata->post_panel_on) |
| 1868 | ctrl_pdata->post_panel_on(pdata); |
| 1869 | |
| 1870 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 1871 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 1872 | pr_debug("%s-:\n", __func__); |
| 1873 | |
| 1874 | return 0; |
| 1875 | } |
| 1876 | |
| 1877 | static irqreturn_t test_hw_vsync_handler(int irq, void *data) |
| 1878 | { |
| 1879 | struct mdss_panel_data *pdata = (struct mdss_panel_data *)data; |
| 1880 | |
| 1881 | pr_debug("HW VSYNC\n"); |
| 1882 | MDSS_XLOG(0xaaa, irq); |
| 1883 | complete_all(&pdata->te_done); |
| 1884 | if (pdata->next) |
| 1885 | complete_all(&pdata->next->te_done); |
| 1886 | return IRQ_HANDLED; |
| 1887 | } |
| 1888 | |
| 1889 | int mdss_dsi_cont_splash_on(struct mdss_panel_data *pdata) |
| 1890 | { |
| 1891 | int ret = 0; |
| 1892 | struct mipi_panel_info *mipi; |
| 1893 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1894 | |
| 1895 | pr_info("%s:%d DSI on for continuous splash.\n", __func__, __LINE__); |
| 1896 | |
| 1897 | if (pdata == NULL) { |
| 1898 | pr_err("%s: Invalid input data\n", __func__); |
| 1899 | return -EINVAL; |
| 1900 | } |
| 1901 | |
| 1902 | mipi = &pdata->panel_info.mipi; |
| 1903 | |
| 1904 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1905 | panel_data); |
| 1906 | |
| 1907 | pr_debug("%s+: ctrl=%pK ndx=%d\n", __func__, |
| 1908 | ctrl_pdata, ctrl_pdata->ndx); |
| 1909 | |
| 1910 | WARN((ctrl_pdata->ctrl_state & CTRL_STATE_PANEL_INIT), |
| 1911 | "Incorrect Ctrl state=0x%x\n", ctrl_pdata->ctrl_state); |
| 1912 | |
| 1913 | mdss_dsi_ctrl_setup(ctrl_pdata); |
| 1914 | mdss_dsi_sw_reset(ctrl_pdata, true); |
| 1915 | pr_debug("%s-:End\n", __func__); |
| 1916 | return ret; |
| 1917 | } |
| 1918 | |
| 1919 | static void __mdss_dsi_mask_dfps_errors(struct mdss_dsi_ctrl_pdata *ctrl, |
| 1920 | bool mask) |
| 1921 | { |
| 1922 | u32 data = 0; |
| 1923 | |
| 1924 | /* |
| 1925 | * Assumption is that the DSI clocks will be enabled |
| 1926 | * when this API is called from dfps thread |
| 1927 | */ |
| 1928 | if (mask) { |
| 1929 | /* mask FIFO underflow and PLL unlock bits */ |
| 1930 | mdss_dsi_set_reg(ctrl, 0x10c, 0x7c000000, 0x7c000000); |
| 1931 | } else { |
| 1932 | data = MIPI_INP((ctrl->ctrl_base) + 0x0120); |
| 1933 | if (data & BIT(16)) { |
| 1934 | pr_debug("pll unlocked: 0x%x\n", data); |
| 1935 | /* clear PLL unlock bit */ |
| 1936 | MIPI_OUTP((ctrl->ctrl_base) + 0x120, BIT(16)); |
| 1937 | } |
| 1938 | |
| 1939 | data = MIPI_INP((ctrl->ctrl_base) + 0x00c); |
| 1940 | if (data & 0x88880000) { |
| 1941 | pr_debug("dsi fifo underflow: 0x%x\n", data); |
| 1942 | /* clear DSI FIFO underflow and empty */ |
| 1943 | MIPI_OUTP((ctrl->ctrl_base) + 0x00c, 0x99990000); |
| 1944 | } |
| 1945 | |
| 1946 | /* restore FIFO underflow and PLL unlock bits */ |
| 1947 | mdss_dsi_set_reg(ctrl, 0x10c, 0x7c000000, 0x0); |
| 1948 | } |
| 1949 | } |
| 1950 | |
| 1951 | static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata, |
| 1952 | int new_fps) |
| 1953 | { |
| 1954 | u32 hsync_period, vsync_period; |
| 1955 | u32 new_dsi_v_total, current_dsi_v_total; |
| 1956 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 1957 | |
| 1958 | if (pdata == NULL) { |
| 1959 | pr_err("%s Invalid pdata\n", __func__); |
| 1960 | return; |
| 1961 | } |
| 1962 | |
| 1963 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 1964 | panel_data); |
| 1965 | if (ctrl_pdata == NULL) { |
| 1966 | pr_err("%s Invalid ctrl_pdata\n", __func__); |
| 1967 | return; |
| 1968 | } |
| 1969 | |
Benjamin Chan | abc9f3c | 2016-06-06 16:50:55 -0400 | [diff] [blame] | 1970 | if (ctrl_pdata->timing_db_mode) |
| 1971 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1); |
| 1972 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1973 | vsync_period = |
| 1974 | mdss_panel_get_vtotal(&pdata->panel_info); |
| 1975 | hsync_period = |
| 1976 | mdss_panel_get_htotal(&pdata->panel_info, true); |
| 1977 | current_dsi_v_total = |
| 1978 | MIPI_INP((ctrl_pdata->ctrl_base) + 0x2C); |
| 1979 | new_dsi_v_total = |
| 1980 | ((vsync_period - 1) << 16) | (hsync_period - 1); |
| 1981 | |
Benjamin Chan | abc9f3c | 2016-06-06 16:50:55 -0400 | [diff] [blame] | 1982 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x2C, new_dsi_v_total); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1983 | |
| 1984 | if (ctrl_pdata->timing_db_mode) |
| 1985 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1); |
| 1986 | |
Benjamin Chan | abc9f3c | 2016-06-06 16:50:55 -0400 | [diff] [blame] | 1987 | pr_debug("%s new_fps:%d new_vtotal:0x%X cur_vtotal:0x%X frame_rate:%d\n", |
| 1988 | __func__, new_fps, new_dsi_v_total, current_dsi_v_total, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 1989 | ctrl_pdata->panel_data.panel_info.mipi.frame_rate); |
| 1990 | |
| 1991 | ctrl_pdata->panel_data.panel_info.current_fps = new_fps; |
| 1992 | MDSS_XLOG(current_dsi_v_total, new_dsi_v_total, new_fps, |
| 1993 | ctrl_pdata->timing_db_mode); |
| 1994 | |
| 1995 | } |
| 1996 | |
| 1997 | static void __mdss_dsi_dyn_refresh_config( |
| 1998 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 1999 | { |
| 2000 | int reg_data = 0; |
| 2001 | u32 phy_rev = ctrl_pdata->shared_data->phy_rev; |
| 2002 | |
| 2003 | /* configure only for master control in split display */ |
| 2004 | if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 2005 | mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) |
| 2006 | return; |
| 2007 | |
| 2008 | switch (phy_rev) { |
| 2009 | case DSI_PHY_REV_10: |
| 2010 | reg_data = MIPI_INP((ctrl_pdata->ctrl_base) + |
| 2011 | DSI_DYNAMIC_REFRESH_CTRL); |
| 2012 | reg_data &= ~BIT(12); |
| 2013 | MIPI_OUTP((ctrl_pdata->ctrl_base) |
| 2014 | + DSI_DYNAMIC_REFRESH_CTRL, reg_data); |
| 2015 | break; |
| 2016 | case DSI_PHY_REV_20: |
| 2017 | reg_data = BIT(13); |
| 2018 | MIPI_OUTP((ctrl_pdata->ctrl_base) |
| 2019 | + DSI_DYNAMIC_REFRESH_CTRL, reg_data); |
| 2020 | break; |
| 2021 | default: |
| 2022 | pr_err("Phy rev %d unsupported\n", phy_rev); |
| 2023 | break; |
| 2024 | } |
| 2025 | |
| 2026 | pr_debug("Dynamic fps ctrl = 0x%x\n", reg_data); |
| 2027 | } |
| 2028 | |
| 2029 | static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata) |
| 2030 | { |
| 2031 | u32 esc_clk_rate = XO_CLK_RATE; |
| 2032 | u32 pipe_delay, pipe_delay2 = 0, pll_delay; |
| 2033 | u32 hsync_period = 0; |
| 2034 | u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio; |
| 2035 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2036 | struct mdss_panel_info *pinfo = NULL; |
| 2037 | struct mdss_dsi_phy_ctrl *pd = NULL; |
| 2038 | |
| 2039 | if (pdata == NULL) { |
| 2040 | pr_err("%s Invalid pdata\n", __func__); |
| 2041 | return; |
| 2042 | } |
| 2043 | |
| 2044 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2045 | panel_data); |
| 2046 | if (ctrl_pdata == NULL) { |
| 2047 | pr_err("%s Invalid ctrl_pdata\n", __func__); |
| 2048 | return; |
| 2049 | } |
| 2050 | |
| 2051 | if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 2052 | mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) |
| 2053 | return; |
| 2054 | |
| 2055 | pinfo = &pdata->panel_info; |
| 2056 | pd = &(pinfo->mipi.dsi_phy_db); |
| 2057 | |
| 2058 | pclk_to_esc_ratio = (ctrl_pdata->pclk_rate / esc_clk_rate); |
| 2059 | byte_to_esc_ratio = (ctrl_pdata->byte_clk_rate / esc_clk_rate); |
| 2060 | hr_bit_to_esc_ratio = ((ctrl_pdata->byte_clk_rate * 4) / esc_clk_rate); |
| 2061 | |
| 2062 | hsync_period = mdss_panel_get_htotal(pinfo, true); |
| 2063 | pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio; |
| 2064 | if (pinfo->mipi.eof_bllp_power_stop == 0) |
| 2065 | pipe_delay += (17 / pclk_to_esc_ratio) + |
| 2066 | ((21 + (pinfo->mipi.t_clk_pre + 1) + |
| 2067 | (pinfo->mipi.t_clk_post + 1)) / |
| 2068 | byte_to_esc_ratio) + |
| 2069 | ((((pd->timing[8] >> 1) + 1) + |
| 2070 | ((pd->timing[6] >> 1) + 1) + |
| 2071 | ((pd->timing[3] * 4) + (pd->timing[5] >> 1) + 1) + |
| 2072 | ((pd->timing[7] >> 1) + 1) + |
| 2073 | ((pd->timing[1] >> 1) + 1) + |
| 2074 | ((pd->timing[4] >> 1) + 1)) / hr_bit_to_esc_ratio); |
| 2075 | |
| 2076 | if (pinfo->mipi.force_clk_lane_hs) |
| 2077 | pipe_delay2 = (6 / byte_to_esc_ratio) + |
| 2078 | ((((pd->timing[1] >> 1) + 1) + |
| 2079 | ((pd->timing[4] >> 1) + 1)) / hr_bit_to_esc_ratio); |
| 2080 | |
| 2081 | /* 130 us pll delay recommended by h/w doc */ |
| 2082 | pll_delay = ((130 * esc_clk_rate) / 1000000) * 2; |
| 2083 | |
| 2084 | MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PIPE_DELAY, |
| 2085 | pipe_delay); |
| 2086 | MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PIPE_DELAY2, |
| 2087 | pipe_delay2); |
| 2088 | MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PLL_DELAY, |
| 2089 | pll_delay); |
| 2090 | } |
| 2091 | |
| 2092 | static int __mdss_dsi_dfps_calc_clks(struct mdss_panel_data *pdata, |
| 2093 | int new_fps) |
| 2094 | { |
| 2095 | int rc = 0; |
| 2096 | u64 clk_rate; |
| 2097 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2098 | struct mdss_panel_info *pinfo; |
| 2099 | u32 phy_rev; |
| 2100 | |
| 2101 | if (pdata == NULL) { |
| 2102 | pr_err("%s Invalid pdata\n", __func__); |
| 2103 | return -EINVAL; |
| 2104 | } |
| 2105 | |
| 2106 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2107 | panel_data); |
| 2108 | if (ctrl_pdata == NULL) { |
| 2109 | pr_err("%s Invalid ctrl_pdata\n", __func__); |
| 2110 | return -EINVAL; |
| 2111 | } |
| 2112 | |
| 2113 | pinfo = &pdata->panel_info; |
| 2114 | phy_rev = ctrl_pdata->shared_data->phy_rev; |
| 2115 | |
| 2116 | rc = mdss_dsi_clk_div_config |
| 2117 | (&ctrl_pdata->panel_data.panel_info, new_fps); |
| 2118 | if (rc) { |
| 2119 | pr_err("%s: unable to initialize the clk dividers\n", |
| 2120 | __func__); |
| 2121 | return rc; |
| 2122 | } |
| 2123 | |
| 2124 | __mdss_dsi_dyn_refresh_config(ctrl_pdata); |
| 2125 | |
| 2126 | if (phy_rev == DSI_PHY_REV_20) |
| 2127 | mdss_dsi_dfps_config_8996(ctrl_pdata); |
| 2128 | |
| 2129 | __mdss_dsi_calc_dfps_delay(pdata); |
| 2130 | |
| 2131 | /* take a backup of current clk rates */ |
| 2132 | ctrl_pdata->pclk_rate_bkp = ctrl_pdata->pclk_rate; |
| 2133 | ctrl_pdata->byte_clk_rate_bkp = ctrl_pdata->byte_clk_rate; |
| 2134 | |
| 2135 | ctrl_pdata->pclk_rate = pinfo->mipi.dsi_pclk_rate; |
| 2136 | clk_rate = pinfo->clk_rate; |
| 2137 | do_div(clk_rate, 8U); |
| 2138 | ctrl_pdata->byte_clk_rate = (u32) clk_rate; |
| 2139 | |
| 2140 | pr_debug("byte_rate=%i\n", ctrl_pdata->byte_clk_rate); |
| 2141 | pr_debug("pclk_rate=%i\n", ctrl_pdata->pclk_rate); |
| 2142 | |
| 2143 | return rc; |
| 2144 | } |
| 2145 | |
| 2146 | static int __mdss_dsi_dfps_update_clks(struct mdss_panel_data *pdata, |
| 2147 | int new_fps) |
| 2148 | { |
| 2149 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2150 | struct mdss_dsi_ctrl_pdata *sctrl_pdata = NULL; |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 2151 | struct mdss_panel_info *pinfo, *spinfo = NULL; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 2152 | int rc = 0; |
| 2153 | |
| 2154 | if (pdata == NULL) { |
| 2155 | pr_err("%s Invalid pdata\n", __func__); |
| 2156 | return -EINVAL; |
| 2157 | } |
| 2158 | |
| 2159 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2160 | panel_data); |
| 2161 | if (IS_ERR_OR_NULL(ctrl_pdata)) { |
| 2162 | pr_err("Invalid sctrl_pdata = %lu\n", PTR_ERR(ctrl_pdata)); |
| 2163 | return PTR_ERR(ctrl_pdata); |
| 2164 | } |
| 2165 | |
| 2166 | pinfo = &ctrl_pdata->panel_data.panel_info; |
| 2167 | |
| 2168 | /* |
| 2169 | * In split display case, configure and enable dynamic refresh |
| 2170 | * register only after both the ctrl data is programmed. So, |
| 2171 | * ignore enabling dynamic refresh for the master control and |
| 2172 | * configure only when it is slave control. |
| 2173 | */ |
| 2174 | if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 2175 | mdss_dsi_is_ctrl_clk_master(ctrl_pdata)) |
| 2176 | return 0; |
| 2177 | |
| 2178 | if (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 2179 | mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) { |
| 2180 | sctrl_pdata = ctrl_pdata; |
| 2181 | spinfo = pinfo; |
| 2182 | ctrl_pdata = mdss_dsi_get_ctrl_clk_master(); |
| 2183 | if (IS_ERR_OR_NULL(ctrl_pdata)) { |
| 2184 | pr_err("Invalid ctrl_pdata = %lu\n", |
| 2185 | PTR_ERR(ctrl_pdata)); |
| 2186 | return PTR_ERR(ctrl_pdata); |
| 2187 | } |
| 2188 | |
| 2189 | pinfo = &ctrl_pdata->panel_data.panel_info; |
| 2190 | } |
| 2191 | |
| 2192 | /* |
| 2193 | * For programming dynamic refresh registers, we need to change |
| 2194 | * the parent to shadow clocks for the software byte and pixel mux. |
| 2195 | * After switching to shadow clocks, if there is no ref count on |
| 2196 | * main byte and pixel clocks, clock driver may shutdown those |
| 2197 | * unreferenced byte and pixel clocks. Hence add an extra reference |
| 2198 | * count to avoid shutting down the main byte and pixel clocks. |
| 2199 | */ |
| 2200 | rc = clk_prepare_enable(ctrl_pdata->pll_byte_clk); |
| 2201 | if (rc) { |
| 2202 | pr_err("Unable to add extra refcnt for byte clock\n"); |
| 2203 | goto error_byte; |
| 2204 | } |
| 2205 | |
| 2206 | rc = clk_prepare_enable(ctrl_pdata->pll_pixel_clk); |
| 2207 | if (rc) { |
| 2208 | pr_err("Unable to add extra refcnt for pixel clock\n"); |
| 2209 | goto error_pixel; |
| 2210 | } |
| 2211 | |
| 2212 | /* change the parent to shadow clocks*/ |
| 2213 | rc = clk_set_parent(ctrl_pdata->mux_byte_clk, |
| 2214 | ctrl_pdata->shadow_byte_clk); |
| 2215 | if (rc) { |
| 2216 | pr_err("Unable to set parent to shadow byte clock\n"); |
| 2217 | goto error_shadow_byte; |
| 2218 | } |
| 2219 | |
| 2220 | rc = clk_set_parent(ctrl_pdata->mux_pixel_clk, |
| 2221 | ctrl_pdata->shadow_pixel_clk); |
| 2222 | if (rc) { |
| 2223 | pr_err("Unable to set parent to shadow pixel clock\n"); |
| 2224 | goto error_shadow_pixel; |
| 2225 | } |
| 2226 | |
| 2227 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 2228 | MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate, 0); |
| 2229 | if (rc) { |
| 2230 | pr_err("%s: dsi_byte_clk - clk_set_rate failed\n", |
| 2231 | __func__); |
| 2232 | goto error_byte_link; |
| 2233 | } |
| 2234 | |
| 2235 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 2236 | MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate, 0); |
| 2237 | if (rc) { |
| 2238 | pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n", |
| 2239 | __func__); |
| 2240 | goto error_pixel_link; |
| 2241 | } |
| 2242 | |
| 2243 | if (sctrl_pdata) { |
| 2244 | rc = mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle, |
| 2245 | MDSS_DSI_LINK_BYTE_CLK, sctrl_pdata->byte_clk_rate, 0); |
| 2246 | if (rc) { |
| 2247 | pr_err("%s: slv dsi_byte_clk - clk_set_rate failed\n", |
| 2248 | __func__); |
| 2249 | goto error_sbyte_link; |
| 2250 | } |
| 2251 | |
| 2252 | rc = mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle, |
| 2253 | MDSS_DSI_LINK_PIX_CLK, sctrl_pdata->pclk_rate, 0); |
| 2254 | if (rc) { |
| 2255 | pr_err("%s: slv dsi_pixel_clk - clk_set_rate failed\n", |
| 2256 | __func__); |
| 2257 | goto error_spixel_link; |
| 2258 | } |
| 2259 | } |
| 2260 | |
| 2261 | rc = mdss_dsi_en_wait4dynamic_done(ctrl_pdata); |
| 2262 | if (rc < 0) { |
| 2263 | pr_err("Unsuccessful dynamic fps change"); |
| 2264 | goto dfps_timeout; |
| 2265 | } |
| 2266 | |
| 2267 | MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_CTRL, 0x00); |
| 2268 | if (sctrl_pdata) |
| 2269 | MIPI_OUTP((sctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_CTRL, |
| 2270 | 0x00); |
| 2271 | |
| 2272 | rc = mdss_dsi_phy_pll_reset_status(ctrl_pdata); |
| 2273 | if (rc) { |
| 2274 | pr_err("%s: pll cannot be locked reset core ready failed %d\n", |
| 2275 | __func__, rc); |
| 2276 | goto dfps_timeout; |
| 2277 | } |
| 2278 | |
| 2279 | __mdss_dsi_mask_dfps_errors(ctrl_pdata, false); |
| 2280 | if (sctrl_pdata) |
| 2281 | __mdss_dsi_mask_dfps_errors(sctrl_pdata, false); |
| 2282 | |
| 2283 | /* Move the mux clocks to main byte and pixel clocks */ |
| 2284 | rc = clk_set_parent(ctrl_pdata->mux_byte_clk, |
| 2285 | ctrl_pdata->pll_byte_clk); |
| 2286 | if (rc) |
| 2287 | pr_err("Unable to set parent back to main byte clock\n"); |
| 2288 | |
| 2289 | rc = clk_set_parent(ctrl_pdata->mux_pixel_clk, |
| 2290 | ctrl_pdata->pll_pixel_clk); |
| 2291 | if (rc) |
| 2292 | pr_err("Unable to set parent back to main pixel clock\n"); |
| 2293 | |
| 2294 | /* Remove extra ref count on parent clocks */ |
| 2295 | clk_disable_unprepare(ctrl_pdata->pll_byte_clk); |
| 2296 | clk_disable_unprepare(ctrl_pdata->pll_pixel_clk); |
| 2297 | |
| 2298 | /* update new fps that at this point is already updated in hw */ |
| 2299 | pinfo->current_fps = new_fps; |
| 2300 | if (sctrl_pdata) |
| 2301 | spinfo->current_fps = new_fps; |
| 2302 | |
| 2303 | return rc; |
| 2304 | |
| 2305 | dfps_timeout: |
| 2306 | if (sctrl_pdata) |
| 2307 | mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle, |
| 2308 | MDSS_DSI_LINK_PIX_CLK, |
| 2309 | sctrl_pdata->pclk_rate_bkp, 0); |
| 2310 | error_spixel_link: |
| 2311 | if (sctrl_pdata) |
| 2312 | mdss_dsi_clk_set_link_rate(sctrl_pdata->dsi_clk_handle, |
| 2313 | MDSS_DSI_LINK_BYTE_CLK, |
| 2314 | sctrl_pdata->byte_clk_rate_bkp, 0); |
| 2315 | error_sbyte_link: |
| 2316 | mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 2317 | MDSS_DSI_LINK_PIX_CLK, ctrl_pdata->pclk_rate_bkp, 0); |
| 2318 | error_pixel_link: |
| 2319 | mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 2320 | MDSS_DSI_LINK_BYTE_CLK, ctrl_pdata->byte_clk_rate_bkp, 0); |
| 2321 | error_byte_link: |
| 2322 | clk_set_parent(ctrl_pdata->mux_pixel_clk, ctrl_pdata->pll_pixel_clk); |
| 2323 | error_shadow_pixel: |
| 2324 | clk_set_parent(ctrl_pdata->mux_byte_clk, ctrl_pdata->pll_byte_clk); |
| 2325 | error_shadow_byte: |
| 2326 | clk_disable_unprepare(ctrl_pdata->pll_pixel_clk); |
| 2327 | error_pixel: |
| 2328 | clk_disable_unprepare(ctrl_pdata->pll_byte_clk); |
| 2329 | error_byte: |
| 2330 | return rc; |
| 2331 | } |
| 2332 | |
| 2333 | static int mdss_dsi_check_params(struct mdss_dsi_ctrl_pdata *ctrl, void *arg) |
| 2334 | { |
| 2335 | struct mdss_panel_info *var_pinfo, *pinfo; |
| 2336 | int rc = 0; |
| 2337 | |
| 2338 | if (!ctrl || !arg) |
| 2339 | return 0; |
| 2340 | |
| 2341 | pinfo = &ctrl->panel_data.panel_info; |
| 2342 | if (!pinfo->is_pluggable) |
| 2343 | return 0; |
| 2344 | |
| 2345 | var_pinfo = (struct mdss_panel_info *)arg; |
| 2346 | |
| 2347 | pr_debug("%s: reconfig xres: %d yres: %d, current xres: %d yres: %d\n", |
| 2348 | __func__, var_pinfo->xres, var_pinfo->yres, |
| 2349 | pinfo->xres, pinfo->yres); |
| 2350 | if ((var_pinfo->xres != pinfo->xres) || |
| 2351 | (var_pinfo->yres != pinfo->yres) || |
| 2352 | (var_pinfo->lcdc.h_back_porch != pinfo->lcdc.h_back_porch) || |
| 2353 | (var_pinfo->lcdc.h_front_porch != pinfo->lcdc.h_front_porch) || |
| 2354 | (var_pinfo->lcdc.h_pulse_width != pinfo->lcdc.h_pulse_width) || |
| 2355 | (var_pinfo->lcdc.v_back_porch != pinfo->lcdc.v_back_porch) || |
| 2356 | (var_pinfo->lcdc.v_front_porch != pinfo->lcdc.v_front_porch) || |
| 2357 | (var_pinfo->lcdc.v_pulse_width != pinfo->lcdc.v_pulse_width) |
| 2358 | ) |
| 2359 | rc = 1; |
| 2360 | |
| 2361 | return rc; |
| 2362 | } |
| 2363 | |
| 2364 | #ifdef TARGET_HW_MDSS_HDMI |
| 2365 | static void mdss_dsi_update_params(struct mdss_dsi_ctrl_pdata *ctrl, void *arg) |
| 2366 | { |
| 2367 | struct mdss_panel_info *pinfo; |
| 2368 | |
| 2369 | if (!ctrl || !arg) |
| 2370 | return; |
| 2371 | |
| 2372 | pinfo = &ctrl->panel_data.panel_info; |
| 2373 | mdss_dba_update_lane_cfg(pinfo); |
| 2374 | } |
| 2375 | #else |
| 2376 | static void mdss_dsi_update_params(struct mdss_dsi_ctrl_pdata *ctrl, void *arg) |
| 2377 | { |
| 2378 | } |
| 2379 | #endif |
| 2380 | |
| 2381 | static int mdss_dsi_dfps_config(struct mdss_panel_data *pdata, int new_fps) |
| 2382 | { |
| 2383 | int rc = 0; |
| 2384 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2385 | struct mdss_panel_info *pinfo; |
| 2386 | u32 phy_rev; |
| 2387 | u32 frame_rate_bkp; |
| 2388 | |
| 2389 | pr_debug("%s+:\n", __func__); |
| 2390 | |
| 2391 | if (pdata == NULL) { |
| 2392 | pr_err("%s: Invalid input data\n", __func__); |
| 2393 | return -EINVAL; |
| 2394 | } |
| 2395 | |
| 2396 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2397 | panel_data); |
| 2398 | |
| 2399 | if (!ctrl_pdata->panel_data.panel_info.dynamic_fps) { |
| 2400 | pr_err("Dynamic fps not enabled for this panel\n"); |
| 2401 | return -EINVAL; |
| 2402 | } |
| 2403 | |
| 2404 | phy_rev = ctrl_pdata->shared_data->phy_rev; |
| 2405 | pinfo = &pdata->panel_info; |
| 2406 | |
| 2407 | /* get the fps configured in HW */ |
| 2408 | frame_rate_bkp = pinfo->current_fps; |
| 2409 | |
| 2410 | if (new_fps == pinfo->current_fps) { |
| 2411 | /* |
| 2412 | * This is unlikely as mdss driver checks for previously |
| 2413 | * configured frame rate. |
| 2414 | */ |
| 2415 | pr_debug("Panel is already at this FPS\n"); |
| 2416 | goto end_update; |
| 2417 | } |
| 2418 | |
| 2419 | if (pinfo->dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_HFP || |
| 2420 | pinfo->dfps_update == DFPS_IMMEDIATE_PORCH_UPDATE_MODE_VFP) { |
| 2421 | /* Porch method */ |
| 2422 | __mdss_dsi_update_video_mode_total(pdata, new_fps); |
| 2423 | } else if (pinfo->dfps_update == DFPS_IMMEDIATE_CLK_UPDATE_MODE) { |
| 2424 | /* Clock update method */ |
| 2425 | |
| 2426 | __mdss_dsi_mask_dfps_errors(ctrl_pdata, true); |
| 2427 | |
| 2428 | if (phy_rev == DSI_PHY_REV_20) { |
| 2429 | rc = mdss_dsi_phy_calc_timing_param(pinfo, phy_rev, |
| 2430 | new_fps); |
| 2431 | if (rc) { |
| 2432 | pr_err("PHY calculations failed-%d\n", new_fps); |
| 2433 | goto end_update; |
| 2434 | } |
| 2435 | } |
| 2436 | |
| 2437 | rc = __mdss_dsi_dfps_calc_clks(pdata, new_fps); |
| 2438 | if (rc) { |
| 2439 | pr_err("error calculating clocks for %d\n", new_fps); |
| 2440 | goto error_clks; |
| 2441 | } |
| 2442 | |
| 2443 | rc = __mdss_dsi_dfps_update_clks(pdata, new_fps); |
| 2444 | if (rc) { |
| 2445 | pr_err("Dynamic refresh failed-%d\n", new_fps); |
| 2446 | goto error_dfps; |
| 2447 | } |
| 2448 | } |
| 2449 | |
| 2450 | return rc; |
| 2451 | error_dfps: |
| 2452 | if (__mdss_dsi_dfps_calc_clks(pdata, frame_rate_bkp)) |
| 2453 | pr_err("error reverting clock calculations for %d\n", |
| 2454 | frame_rate_bkp); |
| 2455 | error_clks: |
| 2456 | if (mdss_dsi_phy_calc_timing_param(pinfo, phy_rev, frame_rate_bkp)) |
| 2457 | pr_err("Unable to revert phy timing-%d\n", frame_rate_bkp); |
| 2458 | end_update: |
| 2459 | return rc; |
| 2460 | } |
| 2461 | |
| 2462 | static int mdss_dsi_ctl_partial_roi(struct mdss_panel_data *pdata) |
| 2463 | { |
| 2464 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2465 | int rc = -EINVAL; |
| 2466 | |
| 2467 | if (pdata == NULL) { |
| 2468 | pr_err("%s: Invalid input data\n", __func__); |
| 2469 | return -EINVAL; |
| 2470 | } |
| 2471 | |
| 2472 | if (!pdata->panel_info.partial_update_enabled) |
| 2473 | return 0; |
| 2474 | |
| 2475 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2476 | panel_data); |
| 2477 | |
| 2478 | if (ctrl_pdata->set_col_page_addr) |
| 2479 | rc = ctrl_pdata->set_col_page_addr(pdata, false); |
| 2480 | |
| 2481 | return rc; |
| 2482 | } |
| 2483 | |
| 2484 | static int mdss_dsi_set_stream_size(struct mdss_panel_data *pdata) |
| 2485 | { |
| 2486 | u32 stream_ctrl, stream_total, idle; |
| 2487 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2488 | struct mdss_panel_info *pinfo; |
| 2489 | struct dsc_desc *dsc = NULL; |
| 2490 | struct mdss_rect *roi; |
| 2491 | struct panel_horizontal_idle *pidle; |
| 2492 | int i; |
| 2493 | |
| 2494 | if (pdata == NULL) { |
| 2495 | pr_err("%s: Invalid input data\n", __func__); |
| 2496 | return -EINVAL; |
| 2497 | } |
| 2498 | |
| 2499 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2500 | panel_data); |
| 2501 | |
| 2502 | pinfo = &pdata->panel_info; |
| 2503 | |
| 2504 | if (!pinfo->partial_update_supported) |
| 2505 | return -EINVAL; |
| 2506 | |
| 2507 | if (pinfo->compression_mode == COMPRESSION_DSC) |
| 2508 | dsc = &pinfo->dsc; |
| 2509 | |
| 2510 | roi = &pinfo->roi; |
| 2511 | |
| 2512 | /* DSI_COMMAND_MODE_MDP_STREAM_CTRL */ |
| 2513 | if (dsc) { |
| 2514 | u16 byte_num = dsc->bytes_per_pkt; |
| 2515 | |
| 2516 | if (pinfo->mipi.insert_dcs_cmd) |
| 2517 | byte_num++; |
| 2518 | |
| 2519 | stream_ctrl = (byte_num << 16) | (pinfo->mipi.vc << 8) | |
| 2520 | DTYPE_DCS_LWRITE; |
| 2521 | stream_total = dsc->pic_height << 16 | dsc->pclk_per_line; |
| 2522 | } else { |
| 2523 | |
| 2524 | stream_ctrl = (((roi->w * 3) + 1) << 16) | |
| 2525 | (pdata->panel_info.mipi.vc << 8) | DTYPE_DCS_LWRITE; |
| 2526 | stream_total = roi->h << 16 | roi->w; |
| 2527 | } |
| 2528 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x60, stream_ctrl); |
| 2529 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x58, stream_ctrl); |
| 2530 | |
| 2531 | /* DSI_COMMAND_MODE_MDP_STREAM_TOTAL */ |
| 2532 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x64, stream_total); |
| 2533 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, stream_total); |
| 2534 | |
| 2535 | /* set idle control -- dsi clk cycle */ |
| 2536 | idle = 0; |
| 2537 | pidle = ctrl_pdata->line_idle; |
| 2538 | for (i = 0; i < ctrl_pdata->horizontal_idle_cnt; i++) { |
| 2539 | if (roi->w > pidle->min && roi->w <= pidle->max) { |
| 2540 | idle = pidle->idle; |
| 2541 | pr_debug("%s: ndx=%d w=%d range=%d-%d idle=%d\n", |
| 2542 | __func__, ctrl_pdata->ndx, roi->w, |
| 2543 | pidle->min, pidle->max, pidle->idle); |
| 2544 | break; |
| 2545 | } |
| 2546 | pidle++; |
| 2547 | } |
| 2548 | |
| 2549 | if (idle) |
| 2550 | idle |= BIT(12); /* enable */ |
| 2551 | |
| 2552 | MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x194, idle); |
| 2553 | |
| 2554 | if (dsc) |
| 2555 | mdss_dsi_dsc_config(ctrl_pdata, dsc); |
| 2556 | |
| 2557 | return 0; |
| 2558 | } |
| 2559 | |
| 2560 | #ifdef TARGET_HW_MDSS_HDMI |
| 2561 | static void mdss_dsi_dba_work(struct work_struct *work) |
| 2562 | { |
| 2563 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2564 | struct delayed_work *dw = to_delayed_work(work); |
| 2565 | struct mdss_dba_utils_init_data utils_init_data; |
| 2566 | struct mdss_panel_info *pinfo; |
| 2567 | |
| 2568 | ctrl_pdata = container_of(dw, struct mdss_dsi_ctrl_pdata, dba_work); |
| 2569 | if (!ctrl_pdata) { |
| 2570 | pr_err("%s: invalid ctrl data\n", __func__); |
| 2571 | return; |
| 2572 | } |
| 2573 | |
| 2574 | pinfo = &ctrl_pdata->panel_data.panel_info; |
| 2575 | if (!pinfo) { |
| 2576 | pr_err("%s: invalid ctrl data\n", __func__); |
| 2577 | return; |
| 2578 | } |
| 2579 | |
| 2580 | memset(&utils_init_data, 0, sizeof(utils_init_data)); |
| 2581 | |
| 2582 | utils_init_data.chip_name = ctrl_pdata->bridge_name; |
| 2583 | utils_init_data.client_name = "dsi"; |
| 2584 | utils_init_data.instance_id = ctrl_pdata->bridge_index; |
| 2585 | utils_init_data.fb_node = ctrl_pdata->fb_node; |
| 2586 | utils_init_data.kobj = ctrl_pdata->kobj; |
| 2587 | utils_init_data.pinfo = pinfo; |
| 2588 | if (ctrl_pdata->mdss_util) |
| 2589 | utils_init_data.cont_splash_enabled = |
| 2590 | ctrl_pdata->mdss_util->panel_intf_status( |
| 2591 | ctrl_pdata->panel_data.panel_info.pdest, |
| 2592 | MDSS_PANEL_INTF_DSI) ? true : false; |
| 2593 | else |
| 2594 | utils_init_data.cont_splash_enabled = false; |
| 2595 | |
| 2596 | pinfo->dba_data = mdss_dba_utils_init(&utils_init_data); |
| 2597 | |
| 2598 | if (!IS_ERR_OR_NULL(pinfo->dba_data)) { |
| 2599 | ctrl_pdata->ds_registered = true; |
| 2600 | } else { |
| 2601 | pr_debug("%s: dba device not ready, queue again\n", __func__); |
| 2602 | queue_delayed_work(ctrl_pdata->workq, |
| 2603 | &ctrl_pdata->dba_work, HZ); |
| 2604 | } |
| 2605 | } |
| 2606 | #else |
| 2607 | static void mdss_dsi_dba_work(struct work_struct *work) |
| 2608 | { |
| 2609 | (void)(*work); |
| 2610 | } |
| 2611 | #endif |
| 2612 | static int mdss_dsi_reset_write_ptr(struct mdss_panel_data *pdata) |
| 2613 | { |
| 2614 | |
| 2615 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2616 | struct mdss_panel_info *pinfo; |
| 2617 | int rc = 0; |
| 2618 | |
| 2619 | if (pdata == NULL) { |
| 2620 | pr_err("%s: Invalid input data\n", __func__); |
| 2621 | return -EINVAL; |
| 2622 | } |
| 2623 | |
| 2624 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2625 | panel_data); |
| 2626 | |
| 2627 | pinfo = &ctrl_pdata->panel_data.panel_info; |
| 2628 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 2629 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 2630 | /* Need to reset the DSI core since the pixel stream was stopped. */ |
| 2631 | mdss_dsi_sw_reset(ctrl_pdata, true); |
| 2632 | |
| 2633 | /* |
| 2634 | * Reset the partial update co-ordinates to the panel height and |
| 2635 | * width |
| 2636 | */ |
| 2637 | if (pinfo->dcs_cmd_by_left && (ctrl_pdata->ndx == 1)) |
| 2638 | goto skip_cmd_send; |
| 2639 | |
| 2640 | pinfo->roi.x = 0; |
| 2641 | pinfo->roi.y = 0; |
| 2642 | pinfo->roi.w = pinfo->xres; |
| 2643 | if (pinfo->dcs_cmd_by_left) |
| 2644 | pinfo->roi.w = pinfo->xres; |
| 2645 | if (pdata->next) |
| 2646 | pinfo->roi.w += pdata->next->panel_info.xres; |
| 2647 | pinfo->roi.h = pinfo->yres; |
| 2648 | |
| 2649 | mdss_dsi_set_stream_size(pdata); |
| 2650 | |
| 2651 | if (ctrl_pdata->set_col_page_addr) |
| 2652 | rc = ctrl_pdata->set_col_page_addr(pdata, true); |
| 2653 | |
| 2654 | skip_cmd_send: |
| 2655 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 2656 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_OFF); |
| 2657 | |
| 2658 | pr_debug("%s: DSI%d write ptr reset finished\n", __func__, |
| 2659 | ctrl_pdata->ndx); |
| 2660 | |
| 2661 | return rc; |
| 2662 | } |
| 2663 | |
| 2664 | int mdss_dsi_register_recovery_handler(struct mdss_dsi_ctrl_pdata *ctrl, |
| 2665 | struct mdss_intf_recovery *recovery) |
| 2666 | { |
| 2667 | mutex_lock(&ctrl->mutex); |
| 2668 | ctrl->recovery = recovery; |
| 2669 | mutex_unlock(&ctrl->mutex); |
| 2670 | return 0; |
| 2671 | } |
| 2672 | |
| 2673 | static int mdss_dsi_register_mdp_callback(struct mdss_dsi_ctrl_pdata *ctrl, |
| 2674 | struct mdss_intf_recovery *mdp_callback) |
| 2675 | { |
| 2676 | mutex_lock(&ctrl->mutex); |
| 2677 | ctrl->mdp_callback = mdp_callback; |
| 2678 | mutex_unlock(&ctrl->mutex); |
| 2679 | return 0; |
| 2680 | } |
| 2681 | |
| 2682 | static struct device_node *mdss_dsi_get_fb_node_cb(struct platform_device *pdev) |
| 2683 | { |
| 2684 | struct device_node *fb_node; |
| 2685 | struct platform_device *dsi_dev; |
| 2686 | struct mdss_dsi_ctrl_pdata *ctrl_pdata; |
| 2687 | |
| 2688 | if (pdev == NULL) { |
| 2689 | pr_err("%s: Invalid input data\n", __func__); |
| 2690 | return NULL; |
| 2691 | } |
| 2692 | |
| 2693 | ctrl_pdata = platform_get_drvdata(pdev); |
| 2694 | dsi_dev = of_find_device_by_node(pdev->dev.of_node->parent); |
| 2695 | if (!dsi_dev) { |
| 2696 | pr_err("Unable to find dsi master device: %s\n", |
| 2697 | pdev->dev.of_node->full_name); |
| 2698 | return NULL; |
| 2699 | } |
| 2700 | |
| 2701 | fb_node = of_parse_phandle(dsi_dev->dev.of_node, |
| 2702 | mdss_dsi_get_fb_name(ctrl_pdata), 0); |
| 2703 | if (!fb_node) { |
| 2704 | pr_err("Unable to find fb node for device: %s\n", pdev->name); |
| 2705 | return NULL; |
| 2706 | } |
| 2707 | |
| 2708 | return fb_node; |
| 2709 | } |
| 2710 | |
| 2711 | static int mdss_dsi_event_handler(struct mdss_panel_data *pdata, |
| 2712 | int event, void *arg) |
| 2713 | { |
| 2714 | int rc = 0; |
| 2715 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 2716 | struct fb_info *fbi; |
| 2717 | int power_state; |
| 2718 | u32 mode; |
| 2719 | struct mdss_panel_info *pinfo; |
| 2720 | |
| 2721 | if (pdata == NULL) { |
| 2722 | pr_err("%s: Invalid input data\n", __func__); |
| 2723 | return -EINVAL; |
| 2724 | } |
| 2725 | pinfo = &pdata->panel_info; |
| 2726 | ctrl_pdata = container_of(pdata, struct mdss_dsi_ctrl_pdata, |
| 2727 | panel_data); |
| 2728 | pr_debug("%s+: ctrl=%d event=%d\n", __func__, ctrl_pdata->ndx, event); |
| 2729 | |
| 2730 | MDSS_XLOG(event, arg, ctrl_pdata->ndx, 0x3333); |
| 2731 | |
| 2732 | switch (event) { |
| 2733 | case MDSS_EVENT_UPDATE_PARAMS: |
| 2734 | pr_debug("%s:Entered Case MDSS_EVENT_UPDATE_PARAMS\n", |
| 2735 | __func__); |
| 2736 | mdss_dsi_update_params(ctrl_pdata, arg); |
| 2737 | break; |
| 2738 | case MDSS_EVENT_CHECK_PARAMS: |
| 2739 | pr_debug("%s:Entered Case MDSS_EVENT_CHECK_PARAMS\n", __func__); |
| 2740 | if (mdss_dsi_check_params(ctrl_pdata, arg)) { |
| 2741 | ctrl_pdata->update_phy_timing = true; |
| 2742 | /* |
| 2743 | * Call to MDSS_EVENT_CHECK_PARAMS expects |
| 2744 | * the return value of 1, if there is a change |
| 2745 | * in panel timing parameters. |
| 2746 | */ |
| 2747 | rc = 1; |
| 2748 | } |
| 2749 | ctrl_pdata->refresh_clk_rate = true; |
| 2750 | break; |
| 2751 | case MDSS_EVENT_LINK_READY: |
| 2752 | if (ctrl_pdata->refresh_clk_rate) |
| 2753 | rc = mdss_dsi_clk_refresh(pdata, |
| 2754 | ctrl_pdata->update_phy_timing); |
| 2755 | |
| 2756 | rc = mdss_dsi_on(pdata); |
| 2757 | mdss_dsi_op_mode_config(pdata->panel_info.mipi.mode, |
| 2758 | pdata); |
| 2759 | break; |
| 2760 | case MDSS_EVENT_UNBLANK: |
| 2761 | if (ctrl_pdata->on_cmds.link_state == DSI_LP_MODE) |
| 2762 | rc = mdss_dsi_unblank(pdata); |
| 2763 | break; |
| 2764 | case MDSS_EVENT_POST_PANEL_ON: |
| 2765 | rc = mdss_dsi_post_panel_on(pdata); |
| 2766 | break; |
| 2767 | case MDSS_EVENT_PANEL_ON: |
| 2768 | ctrl_pdata->ctrl_state |= CTRL_STATE_MDP_ACTIVE; |
| 2769 | if (ctrl_pdata->on_cmds.link_state == DSI_HS_MODE) |
| 2770 | rc = mdss_dsi_unblank(pdata); |
| 2771 | pdata->panel_info.esd_rdy = true; |
| 2772 | break; |
| 2773 | case MDSS_EVENT_BLANK: |
| 2774 | power_state = (int) (unsigned long) arg; |
| 2775 | if (ctrl_pdata->off_cmds.link_state == DSI_HS_MODE) |
| 2776 | rc = mdss_dsi_blank(pdata, power_state); |
| 2777 | break; |
| 2778 | case MDSS_EVENT_PANEL_OFF: |
| 2779 | power_state = (int) (unsigned long) arg; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 2780 | ctrl_pdata->ctrl_state &= ~CTRL_STATE_MDP_ACTIVE; |
| 2781 | if (ctrl_pdata->off_cmds.link_state == DSI_LP_MODE) |
| 2782 | rc = mdss_dsi_blank(pdata, power_state); |
| 2783 | rc = mdss_dsi_off(pdata, power_state); |
| 2784 | break; |
| 2785 | case MDSS_EVENT_CONT_SPLASH_FINISH: |
| 2786 | if (ctrl_pdata->off_cmds.link_state == DSI_LP_MODE) |
| 2787 | rc = mdss_dsi_blank(pdata, MDSS_PANEL_POWER_OFF); |
| 2788 | ctrl_pdata->ctrl_state &= ~CTRL_STATE_MDP_ACTIVE; |
| 2789 | rc = mdss_dsi_cont_splash_on(pdata); |
| 2790 | break; |
| 2791 | case MDSS_EVENT_PANEL_CLK_CTRL: |
| 2792 | mdss_dsi_clk_req(ctrl_pdata, |
| 2793 | (struct dsi_panel_clk_ctrl *) arg); |
| 2794 | break; |
| 2795 | case MDSS_EVENT_DSI_CMDLIST_KOFF: |
| 2796 | mdss_dsi_cmdlist_commit(ctrl_pdata, 1); |
| 2797 | break; |
| 2798 | case MDSS_EVENT_PANEL_UPDATE_FPS: |
| 2799 | if (arg != NULL) { |
| 2800 | rc = mdss_dsi_dfps_config(pdata, |
| 2801 | (int) (unsigned long) arg); |
| 2802 | if (rc) |
| 2803 | pr_err("unable to change fps-%d, error-%d\n", |
| 2804 | (int) (unsigned long) arg, rc); |
| 2805 | else |
| 2806 | pr_debug("panel frame rate changed to %d\n", |
| 2807 | (int) (unsigned long) arg); |
| 2808 | } |
| 2809 | break; |
| 2810 | case MDSS_EVENT_CONT_SPLASH_BEGIN: |
| 2811 | if (ctrl_pdata->off_cmds.link_state == DSI_HS_MODE) { |
| 2812 | /* Panel is Enabled in Bootloader */ |
| 2813 | rc = mdss_dsi_blank(pdata, MDSS_PANEL_POWER_OFF); |
| 2814 | } |
| 2815 | break; |
| 2816 | case MDSS_EVENT_DSC_PPS_SEND: |
| 2817 | if (pinfo->compression_mode == COMPRESSION_DSC) |
| 2818 | mdss_dsi_panel_dsc_pps_send(ctrl_pdata, pinfo); |
| 2819 | break; |
| 2820 | case MDSS_EVENT_ENABLE_PARTIAL_ROI: |
| 2821 | rc = mdss_dsi_ctl_partial_roi(pdata); |
| 2822 | break; |
| 2823 | case MDSS_EVENT_DSI_RESET_WRITE_PTR: |
| 2824 | rc = mdss_dsi_reset_write_ptr(pdata); |
| 2825 | break; |
| 2826 | case MDSS_EVENT_DSI_STREAM_SIZE: |
| 2827 | rc = mdss_dsi_set_stream_size(pdata); |
| 2828 | break; |
| 2829 | case MDSS_EVENT_DSI_UPDATE_PANEL_DATA: |
| 2830 | rc = mdss_dsi_update_panel_config(ctrl_pdata, |
| 2831 | (int)(unsigned long) arg); |
| 2832 | break; |
| 2833 | case MDSS_EVENT_REGISTER_RECOVERY_HANDLER: |
| 2834 | rc = mdss_dsi_register_recovery_handler(ctrl_pdata, |
| 2835 | (struct mdss_intf_recovery *)arg); |
| 2836 | break; |
| 2837 | case MDSS_EVENT_REGISTER_MDP_CALLBACK: |
| 2838 | rc = mdss_dsi_register_mdp_callback(ctrl_pdata, |
| 2839 | (struct mdss_intf_recovery *)arg); |
| 2840 | break; |
| 2841 | case MDSS_EVENT_DSI_DYNAMIC_SWITCH: |
| 2842 | mode = (u32)(unsigned long) arg; |
| 2843 | mdss_dsi_switch_mode(pdata, mode); |
| 2844 | break; |
| 2845 | case MDSS_EVENT_DSI_RECONFIG_CMD: |
| 2846 | mode = (u32)(unsigned long) arg; |
| 2847 | rc = mdss_dsi_reconfig(pdata, mode); |
| 2848 | break; |
| 2849 | case MDSS_EVENT_DSI_PANEL_STATUS: |
| 2850 | if (ctrl_pdata->check_status) |
| 2851 | rc = ctrl_pdata->check_status(ctrl_pdata); |
| 2852 | else |
| 2853 | rc = true; |
| 2854 | break; |
| 2855 | case MDSS_EVENT_PANEL_TIMING_SWITCH: |
| 2856 | rc = mdss_dsi_panel_timing_switch(ctrl_pdata, arg); |
| 2857 | break; |
| 2858 | case MDSS_EVENT_FB_REGISTERED: |
| 2859 | mdss_dsi_debugfs_init(ctrl_pdata); |
| 2860 | |
| 2861 | fbi = (struct fb_info *)arg; |
| 2862 | if (!fbi || !fbi->dev) |
| 2863 | break; |
| 2864 | |
| 2865 | ctrl_pdata->kobj = &fbi->dev->kobj; |
| 2866 | ctrl_pdata->fb_node = fbi->node; |
| 2867 | |
| 2868 | if (IS_ENABLED(CONFIG_MSM_DBA) && |
| 2869 | pdata->panel_info.is_dba_panel) { |
| 2870 | queue_delayed_work(ctrl_pdata->workq, |
| 2871 | &ctrl_pdata->dba_work, HZ); |
| 2872 | } |
| 2873 | break; |
| 2874 | default: |
| 2875 | pr_debug("%s: unhandled event=%d\n", __func__, event); |
| 2876 | break; |
| 2877 | } |
| 2878 | pr_debug("%s-:event=%d, rc=%d\n", __func__, event, rc); |
| 2879 | return rc; |
| 2880 | } |
| 2881 | |
| 2882 | static int mdss_dsi_set_override_cfg(char *override_cfg, |
| 2883 | struct mdss_dsi_ctrl_pdata *ctrl_pdata, char *panel_cfg) |
| 2884 | { |
| 2885 | struct mdss_panel_info *pinfo = &ctrl_pdata->panel_data.panel_info; |
| 2886 | char *token = NULL; |
| 2887 | |
| 2888 | pr_debug("%s: override config:%s\n", __func__, override_cfg); |
| 2889 | while ((token = strsep(&override_cfg, ":"))) { |
| 2890 | if (!strcmp(token, OVERRIDE_CFG)) { |
| 2891 | continue; |
| 2892 | } else if (!strcmp(token, SIM_HW_TE_PANEL)) { |
| 2893 | pinfo->sim_panel_mode = SIM_HW_TE_MODE; |
| 2894 | } else if (!strcmp(token, SIM_SW_TE_PANEL)) { |
| 2895 | pinfo->sim_panel_mode = SIM_SW_TE_MODE; |
| 2896 | } else if (!strcmp(token, SIM_PANEL)) { |
| 2897 | pinfo->sim_panel_mode = SIM_MODE; |
| 2898 | } else { |
| 2899 | pr_err("%s: invalid override_cfg token: %s\n", |
| 2900 | __func__, token); |
| 2901 | return -EINVAL; |
| 2902 | } |
| 2903 | } |
| 2904 | pr_debug("%s:sim_panel_mode:%d\n", __func__, pinfo->sim_panel_mode); |
| 2905 | |
| 2906 | return 0; |
| 2907 | } |
| 2908 | |
| 2909 | static struct device_node *mdss_dsi_pref_prim_panel( |
| 2910 | struct platform_device *pdev) |
| 2911 | { |
| 2912 | struct device_node *dsi_pan_node = NULL; |
| 2913 | |
| 2914 | pr_debug("%s:%d: Select primary panel from dt\n", |
| 2915 | __func__, __LINE__); |
| 2916 | dsi_pan_node = of_parse_phandle(pdev->dev.of_node, |
| 2917 | "qcom,dsi-pref-prim-pan", 0); |
| 2918 | if (!dsi_pan_node) |
| 2919 | pr_err("%s:can't find panel phandle\n", __func__); |
| 2920 | |
| 2921 | return dsi_pan_node; |
| 2922 | } |
| 2923 | |
| 2924 | /** |
| 2925 | * mdss_dsi_find_panel_of_node(): find device node of dsi panel |
| 2926 | * @pdev: platform_device of the dsi ctrl node |
| 2927 | * @panel_cfg: string containing intf specific config data |
| 2928 | * |
| 2929 | * Function finds the panel device node using the interface |
| 2930 | * specific configuration data. This configuration data is |
| 2931 | * could be derived from the result of bootloader's GCDB |
| 2932 | * panel detection mechanism. If such config data doesn't |
| 2933 | * exist then this panel returns the default panel configured |
| 2934 | * in the device tree. |
| 2935 | * |
| 2936 | * returns pointer to panel node on success, NULL on error. |
| 2937 | */ |
| 2938 | static struct device_node *mdss_dsi_find_panel_of_node( |
| 2939 | struct platform_device *pdev, char *panel_cfg) |
| 2940 | { |
| 2941 | int len, i = 0; |
| 2942 | int ctrl_id = pdev->id - 1; |
| 2943 | char panel_name[MDSS_MAX_PANEL_LEN] = ""; |
| 2944 | char ctrl_id_stream[3] = "0:"; |
| 2945 | char *str1 = NULL, *str2 = NULL, *override_cfg = NULL; |
| 2946 | char cfg_np_name[MDSS_MAX_PANEL_LEN] = ""; |
| 2947 | struct device_node *dsi_pan_node = NULL, *mdss_node = NULL; |
| 2948 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev); |
| 2949 | struct mdss_panel_info *pinfo = &ctrl_pdata->panel_data.panel_info; |
| 2950 | |
| 2951 | len = strlen(panel_cfg); |
| 2952 | ctrl_pdata->panel_data.dsc_cfg_np_name[0] = '\0'; |
| 2953 | if (!len) { |
| 2954 | /* no panel cfg chg, parse dt */ |
| 2955 | pr_debug("%s:%d: no cmd line cfg present\n", |
| 2956 | __func__, __LINE__); |
| 2957 | goto end; |
| 2958 | } else { |
| 2959 | /* check if any override parameters are set */ |
| 2960 | pinfo->sim_panel_mode = 0; |
| 2961 | override_cfg = strnstr(panel_cfg, "#" OVERRIDE_CFG, len); |
| 2962 | if (override_cfg) { |
| 2963 | *override_cfg = '\0'; |
| 2964 | if (mdss_dsi_set_override_cfg(override_cfg + 1, |
| 2965 | ctrl_pdata, panel_cfg)) |
| 2966 | return NULL; |
| 2967 | len = strlen(panel_cfg); |
| 2968 | } |
| 2969 | |
| 2970 | if (ctrl_id == 1) |
| 2971 | strlcpy(ctrl_id_stream, "1:", 3); |
| 2972 | |
| 2973 | /* get controller number */ |
| 2974 | str1 = strnstr(panel_cfg, ctrl_id_stream, len); |
| 2975 | if (!str1) { |
| 2976 | pr_err("%s: controller %s is not present in %s\n", |
| 2977 | __func__, ctrl_id_stream, panel_cfg); |
| 2978 | goto end; |
| 2979 | } |
| 2980 | if ((str1 != panel_cfg) && (*(str1-1) != ':')) { |
| 2981 | str1 += CMDLINE_DSI_CTL_NUM_STRING_LEN; |
| 2982 | pr_debug("false match with config node name in \"%s\". search again in \"%s\"\n", |
| 2983 | panel_cfg, str1); |
| 2984 | str1 = strnstr(str1, ctrl_id_stream, len); |
| 2985 | if (!str1) { |
| 2986 | pr_err("%s: 2. controller %s is not present in %s\n", |
| 2987 | __func__, ctrl_id_stream, str1); |
| 2988 | goto end; |
| 2989 | } |
| 2990 | } |
| 2991 | str1 += CMDLINE_DSI_CTL_NUM_STRING_LEN; |
| 2992 | |
| 2993 | /* get panel name */ |
| 2994 | str2 = strnchr(str1, strlen(str1), ':'); |
| 2995 | if (!str2) { |
| 2996 | strlcpy(panel_name, str1, MDSS_MAX_PANEL_LEN); |
| 2997 | } else { |
| 2998 | for (i = 0; (str1 + i) < str2; i++) |
| 2999 | panel_name[i] = *(str1 + i); |
| 3000 | panel_name[i] = 0; |
| 3001 | } |
| 3002 | pr_info("%s: cmdline:%s panel_name:%s\n", |
| 3003 | __func__, panel_cfg, panel_name); |
| 3004 | if (!strcmp(panel_name, NONE_PANEL)) |
| 3005 | goto exit; |
| 3006 | |
| 3007 | mdss_node = of_parse_phandle(pdev->dev.of_node, |
| 3008 | "qcom,mdss-mdp", 0); |
| 3009 | if (!mdss_node) { |
| 3010 | pr_err("%s: %d: mdss_node null\n", |
| 3011 | __func__, __LINE__); |
| 3012 | return NULL; |
| 3013 | } |
| 3014 | dsi_pan_node = of_find_node_by_name(mdss_node, panel_name); |
| 3015 | if (!dsi_pan_node) { |
| 3016 | pr_err("%s: invalid pan node \"%s\"\n", |
| 3017 | __func__, panel_name); |
| 3018 | goto end; |
| 3019 | } else { |
| 3020 | /* extract config node name if present */ |
| 3021 | str1 += i; |
| 3022 | str2 = strnstr(str1, "config", strlen(str1)); |
| 3023 | if (str2) { |
| 3024 | str1 = strnchr(str2, strlen(str2), ':'); |
| 3025 | if (str1) { |
| 3026 | for (i = 0; ((str2 + i) < str1) && |
| 3027 | i < (MDSS_MAX_PANEL_LEN - 1); i++) |
| 3028 | cfg_np_name[i] = *(str2 + i); |
| 3029 | if ((i >= 0) |
| 3030 | && (i < MDSS_MAX_PANEL_LEN)) |
| 3031 | cfg_np_name[i] = 0; |
| 3032 | } else { |
| 3033 | strlcpy(cfg_np_name, str2, |
| 3034 | MDSS_MAX_PANEL_LEN); |
| 3035 | } |
| 3036 | strlcpy(ctrl_pdata->panel_data.dsc_cfg_np_name, |
| 3037 | cfg_np_name, MDSS_MAX_PANEL_LEN); |
| 3038 | } |
| 3039 | } |
| 3040 | |
| 3041 | return dsi_pan_node; |
| 3042 | } |
| 3043 | end: |
| 3044 | if (strcmp(panel_name, NONE_PANEL)) |
| 3045 | dsi_pan_node = mdss_dsi_pref_prim_panel(pdev); |
| 3046 | exit: |
| 3047 | return dsi_pan_node; |
| 3048 | } |
| 3049 | |
| 3050 | static struct device_node *mdss_dsi_config_panel(struct platform_device *pdev, |
| 3051 | int ndx) |
| 3052 | { |
| 3053 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev); |
| 3054 | char panel_cfg[MDSS_MAX_PANEL_LEN]; |
| 3055 | struct device_node *dsi_pan_node = NULL; |
| 3056 | int rc = 0; |
| 3057 | |
| 3058 | if (!ctrl_pdata) { |
| 3059 | pr_err("%s: Unable to get the ctrl_pdata\n", __func__); |
| 3060 | return NULL; |
| 3061 | } |
| 3062 | |
| 3063 | /* DSI panels can be different between controllers */ |
| 3064 | rc = mdss_dsi_get_panel_cfg(panel_cfg, ctrl_pdata); |
| 3065 | if (!rc) |
| 3066 | /* dsi panel cfg not present */ |
| 3067 | pr_warn("%s:%d:dsi specific cfg not present\n", |
| 3068 | __func__, __LINE__); |
| 3069 | |
| 3070 | /* find panel device node */ |
| 3071 | dsi_pan_node = mdss_dsi_find_panel_of_node(pdev, panel_cfg); |
| 3072 | if (!dsi_pan_node) { |
| 3073 | pr_err("%s: can't find panel node %s\n", __func__, panel_cfg); |
| 3074 | of_node_put(dsi_pan_node); |
| 3075 | return NULL; |
| 3076 | } |
| 3077 | |
| 3078 | rc = mdss_dsi_panel_init(dsi_pan_node, ctrl_pdata, ndx); |
| 3079 | if (rc) { |
| 3080 | pr_err("%s: dsi panel init failed\n", __func__); |
| 3081 | of_node_put(dsi_pan_node); |
| 3082 | return NULL; |
| 3083 | } |
| 3084 | |
| 3085 | return dsi_pan_node; |
| 3086 | } |
| 3087 | |
| 3088 | static int mdss_dsi_ctrl_clock_init(struct platform_device *ctrl_pdev, |
| 3089 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 3090 | { |
| 3091 | int rc = 0; |
| 3092 | struct mdss_dsi_clk_info info; |
| 3093 | struct mdss_dsi_clk_client client1 = {"dsi_clk_client"}; |
| 3094 | struct mdss_dsi_clk_client client2 = {"mdp_event_client"}; |
| 3095 | void *handle; |
| 3096 | |
| 3097 | if (mdss_dsi_link_clk_init(ctrl_pdev, ctrl_pdata)) { |
| 3098 | pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__); |
| 3099 | return -EPERM; |
| 3100 | } |
| 3101 | |
| 3102 | memset(&info, 0x0, sizeof(info)); |
| 3103 | |
| 3104 | info.core_clks.mdp_core_clk = ctrl_pdata->shared_data->mdp_core_clk; |
| 3105 | info.core_clks.ahb_clk = ctrl_pdata->shared_data->ahb_clk; |
| 3106 | info.core_clks.axi_clk = ctrl_pdata->shared_data->axi_clk; |
| 3107 | info.core_clks.mmss_misc_ahb_clk = |
| 3108 | ctrl_pdata->shared_data->mmss_misc_ahb_clk; |
| 3109 | |
Padmanabhan Komanduru | b0008fd | 2018-04-12 16:25:43 +0530 | [diff] [blame] | 3110 | info.link_lp_clks.esc_clk = ctrl_pdata->esc_clk; |
| 3111 | info.link_hs_clks.byte_clk = ctrl_pdata->byte_clk; |
| 3112 | info.link_hs_clks.pixel_clk = ctrl_pdata->pixel_clk; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3113 | |
| 3114 | info.pre_clkoff_cb = mdss_dsi_pre_clkoff_cb; |
| 3115 | info.post_clkon_cb = mdss_dsi_post_clkon_cb; |
| 3116 | info.pre_clkon_cb = mdss_dsi_pre_clkon_cb; |
| 3117 | info.post_clkoff_cb = mdss_dsi_post_clkoff_cb; |
| 3118 | info.priv_data = ctrl_pdata; |
| 3119 | snprintf(info.name, DSI_CLK_NAME_LEN, "DSI%d", ctrl_pdata->ndx); |
| 3120 | ctrl_pdata->clk_mngr = mdss_dsi_clk_init(&info); |
| 3121 | if (IS_ERR_OR_NULL(ctrl_pdata->clk_mngr)) { |
| 3122 | rc = PTR_ERR(ctrl_pdata->clk_mngr); |
| 3123 | ctrl_pdata->clk_mngr = NULL; |
| 3124 | pr_err("dsi clock registration failed, rc = %d\n", rc); |
| 3125 | goto error_link_clk_deinit; |
| 3126 | } |
| 3127 | |
| 3128 | /* |
| 3129 | * There are two clients that control dsi clocks. MDP driver controls |
| 3130 | * the clock through MDSS_PANEL_EVENT_CLK_CTRL event and dsi driver |
| 3131 | * through clock interface. To differentiate between the votes from the |
| 3132 | * two clients, dsi driver will use two different handles to vote for |
| 3133 | * clock states from dsi and mdp driver. |
| 3134 | */ |
| 3135 | handle = mdss_dsi_clk_register(ctrl_pdata->clk_mngr, &client1); |
| 3136 | if (IS_ERR_OR_NULL(handle)) { |
| 3137 | rc = PTR_ERR(handle); |
| 3138 | pr_err("failed to register %s client, rc = %d\n", |
| 3139 | client1.client_name, rc); |
| 3140 | goto error_clk_deinit; |
| 3141 | } else { |
| 3142 | ctrl_pdata->dsi_clk_handle = handle; |
| 3143 | } |
| 3144 | |
| 3145 | handle = mdss_dsi_clk_register(ctrl_pdata->clk_mngr, &client2); |
| 3146 | if (IS_ERR_OR_NULL(handle)) { |
| 3147 | rc = PTR_ERR(handle); |
| 3148 | pr_err("failed to register %s client, rc = %d\n", |
| 3149 | client2.client_name, rc); |
| 3150 | goto error_clk_client_deregister; |
| 3151 | } else { |
| 3152 | ctrl_pdata->mdp_clk_handle = handle; |
| 3153 | } |
| 3154 | |
| 3155 | return rc; |
| 3156 | error_clk_client_deregister: |
| 3157 | mdss_dsi_clk_deregister(ctrl_pdata->dsi_clk_handle); |
| 3158 | error_clk_deinit: |
| 3159 | mdss_dsi_clk_deinit(ctrl_pdata->clk_mngr); |
| 3160 | error_link_clk_deinit: |
| 3161 | mdss_dsi_link_clk_deinit(&ctrl_pdev->dev, ctrl_pdata); |
| 3162 | return rc; |
| 3163 | } |
| 3164 | |
| 3165 | static int mdss_dsi_set_clk_rates(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 3166 | { |
| 3167 | int rc = 0; |
| 3168 | |
| 3169 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 3170 | MDSS_DSI_LINK_BYTE_CLK, |
| 3171 | ctrl_pdata->byte_clk_rate, |
| 3172 | MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON); |
| 3173 | if (rc) { |
| 3174 | pr_err("%s: dsi_byte_clk - clk_set_rate failed\n", |
| 3175 | __func__); |
| 3176 | return rc; |
| 3177 | } |
| 3178 | |
| 3179 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 3180 | MDSS_DSI_LINK_PIX_CLK, |
| 3181 | ctrl_pdata->pclk_rate, |
| 3182 | MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON); |
| 3183 | if (rc) { |
| 3184 | pr_err("%s: dsi_pixel_clk - clk_set_rate failed\n", |
| 3185 | __func__); |
| 3186 | return rc; |
| 3187 | } |
| 3188 | |
| 3189 | rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle, |
| 3190 | MDSS_DSI_LINK_ESC_CLK, |
| 3191 | 19200000, |
| 3192 | MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON); |
| 3193 | if (rc) { |
| 3194 | pr_err("%s: dsi_esc_clk - clk_set_rate failed\n", |
| 3195 | __func__); |
| 3196 | return rc; |
| 3197 | } |
| 3198 | |
| 3199 | return rc; |
| 3200 | } |
| 3201 | |
| 3202 | static int mdss_dsi_cont_splash_config(struct mdss_panel_info *pinfo, |
| 3203 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 3204 | { |
| 3205 | void *clk_handle; |
| 3206 | int rc = 0; |
| 3207 | |
| 3208 | if (pinfo->cont_splash_enabled) { |
| 3209 | rc = mdss_dsi_panel_power_ctrl(&(ctrl_pdata->panel_data), |
| 3210 | MDSS_PANEL_POWER_ON); |
| 3211 | if (rc) { |
| 3212 | pr_err("%s: Panel power on failed\n", __func__); |
| 3213 | return rc; |
| 3214 | } |
| 3215 | if (ctrl_pdata->bklt_ctrl == BL_PWM) |
| 3216 | mdss_dsi_panel_pwm_enable(ctrl_pdata); |
| 3217 | ctrl_pdata->ctrl_state |= (CTRL_STATE_PANEL_INIT | |
| 3218 | CTRL_STATE_MDP_ACTIVE | CTRL_STATE_DSI_ACTIVE); |
| 3219 | |
| 3220 | /* |
| 3221 | * MDP client removes this extra vote during splash reconfigure |
| 3222 | * for command mode panel from interface. DSI removes the vote |
| 3223 | * during suspend-resume for video mode panel. |
| 3224 | */ |
| 3225 | if (ctrl_pdata->panel_data.panel_info.type == MIPI_CMD_PANEL) |
| 3226 | clk_handle = ctrl_pdata->mdp_clk_handle; |
| 3227 | else |
| 3228 | clk_handle = ctrl_pdata->dsi_clk_handle; |
| 3229 | |
| 3230 | mdss_dsi_clk_ctrl(ctrl_pdata, clk_handle, |
| 3231 | MDSS_DSI_ALL_CLKS, MDSS_DSI_CLK_ON); |
| 3232 | mdss_dsi_read_hw_revision(ctrl_pdata); |
| 3233 | mdss_dsi_read_phy_revision(ctrl_pdata); |
| 3234 | ctrl_pdata->is_phyreg_enabled = 1; |
| 3235 | if (pinfo->type == MIPI_CMD_PANEL) |
| 3236 | mdss_dsi_set_burst_mode(ctrl_pdata); |
| 3237 | } else { |
| 3238 | /* Turn on the clocks to read the DSI and PHY revision */ |
| 3239 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 3240 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_ON); |
| 3241 | mdss_dsi_read_hw_revision(ctrl_pdata); |
| 3242 | mdss_dsi_read_phy_revision(ctrl_pdata); |
| 3243 | mdss_dsi_clk_ctrl(ctrl_pdata, ctrl_pdata->dsi_clk_handle, |
| 3244 | MDSS_DSI_CORE_CLK, MDSS_DSI_CLK_OFF); |
| 3245 | pinfo->panel_power_state = MDSS_PANEL_POWER_OFF; |
| 3246 | } |
| 3247 | |
| 3248 | return rc; |
| 3249 | } |
| 3250 | |
| 3251 | static int mdss_dsi_get_bridge_chip_params(struct mdss_panel_info *pinfo, |
| 3252 | struct mdss_dsi_ctrl_pdata *ctrl_pdata, |
| 3253 | struct platform_device *pdev) |
| 3254 | { |
| 3255 | int rc = 0; |
| 3256 | u32 temp_val = 0; |
| 3257 | |
| 3258 | if (!ctrl_pdata || !pdev || !pinfo) { |
| 3259 | pr_err("%s: Invalid Params ctrl_pdata=%pK, pdev=%pK\n", |
| 3260 | __func__, ctrl_pdata, pdev); |
| 3261 | rc = -EINVAL; |
| 3262 | goto end; |
| 3263 | } |
| 3264 | |
| 3265 | if (pinfo->is_dba_panel) { |
| 3266 | rc = of_property_read_u32(pdev->dev.of_node, |
| 3267 | "qcom,bridge-index", &temp_val); |
| 3268 | if (rc) { |
| 3269 | pr_err("%s:%d Unable to read qcom,bridge-index, ret=%d\n", |
| 3270 | __func__, __LINE__, rc); |
| 3271 | goto end; |
| 3272 | } |
| 3273 | pr_debug("%s: DT property %s is %X\n", __func__, |
| 3274 | "qcom,bridge-index", temp_val); |
| 3275 | ctrl_pdata->bridge_index = temp_val; |
| 3276 | } |
| 3277 | end: |
| 3278 | return rc; |
| 3279 | } |
| 3280 | |
jialongjhan | 7dfbf87 | 2020-04-21 20:24:23 +0800 | [diff] [blame^] | 3281 | /*[Arima_8901][Jialongjhan] Add LCM_vendor file node for PCBA function test 20181114 begin*/ |
| 3282 | extern void seq_printf(struct seq_file *m, const char *f, ...); |
| 3283 | extern int single_open(struct file *, int (*)(struct seq_file *, void *), void *); |
| 3284 | extern ssize_t seq_read(struct file *, char __user *, size_t, loff_t *); |
| 3285 | extern loff_t seq_lseek(struct file *, loff_t, int); |
| 3286 | extern int single_release(struct inode *, struct file *); |
| 3287 | |
| 3288 | static int proc_lcm_vendor_show(struct seq_file *m, void *v) |
| 3289 | { |
| 3290 | int lcm_id; |
| 3291 | |
| 3292 | lcm_id = gpio_request(59, "lcm_id"); |
| 3293 | |
| 3294 | if(lcm_id == 1) |
| 3295 | { |
| 3296 | //For another's LCM module |
| 3297 | seq_printf(m, "2nd LCM\n"); |
| 3298 | } |
| 3299 | else |
| 3300 | { //DJN's LCM module id is 0. |
| 3301 | seq_printf(m, "DJN , HX83112B\n"); |
| 3302 | } |
| 3303 | |
| 3304 | return 0; |
| 3305 | } |
| 3306 | |
| 3307 | static int proc_lcm_vendor_open(struct inode *inode, struct file *file) |
| 3308 | { |
| 3309 | return single_open(file, proc_lcm_vendor_show, NULL); |
| 3310 | } |
| 3311 | |
| 3312 | static const struct file_operations proc_lcm_vendor_fops = { |
| 3313 | .open = proc_lcm_vendor_open, |
| 3314 | .read = seq_read, |
| 3315 | .llseek = seq_lseek, |
| 3316 | .release = single_release, |
| 3317 | }; |
| 3318 | /*[Arima_8901][Jialongjhan] Add LCM_vendor file node for PCBA function test 20181114 End*/ |
| 3319 | |
| 3320 | /*[Arima_8901][Jialongjhan] Expose display revision 20190326 begin*/ |
| 3321 | |
| 3322 | static int proc_lcm_revision_show(struct seq_file *m, void *v) |
| 3323 | { |
| 3324 | int lcm_id; |
| 3325 | extern int RDDID_HWINFO[3]; |
| 3326 | |
| 3327 | lcm_id = gpio_request(59, "lcm_id"); |
| 3328 | |
| 3329 | if(lcm_id == 1) |
| 3330 | { |
| 3331 | //For another's LCM module |
| 3332 | seq_printf(m, "2nd Source not ready.\n"); |
| 3333 | } |
| 3334 | else |
| 3335 | { //DJN's LCM module id is 0. |
| 3336 | seq_printf(m, "DJN , HX%x%x%x\n", RDDID_HWINFO[0],RDDID_HWINFO[1],RDDID_HWINFO[2]); |
| 3337 | } |
| 3338 | |
| 3339 | return 0; |
| 3340 | } |
| 3341 | |
| 3342 | static int proc_lcm_revision_fops_open(struct inode *inode, struct file *file) |
| 3343 | { |
| 3344 | return single_open(file, proc_lcm_revision_show, NULL); |
| 3345 | } |
| 3346 | |
| 3347 | static const struct file_operations proc_lcm_revision_fops = { |
| 3348 | .open = proc_lcm_revision_fops_open, |
| 3349 | .read = seq_read, |
| 3350 | .llseek = seq_lseek, |
| 3351 | .release = single_release, |
| 3352 | }; |
| 3353 | |
| 3354 | /*[Arima_8901][Jialongjhan] Expose display revision 20190326 end*/ |
| 3355 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3356 | static int mdss_dsi_ctrl_probe(struct platform_device *pdev) |
| 3357 | { |
| 3358 | int rc = 0; |
| 3359 | u32 index; |
| 3360 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = NULL; |
| 3361 | struct mdss_panel_info *pinfo = NULL; |
| 3362 | struct device_node *dsi_pan_node = NULL; |
| 3363 | const char *ctrl_name; |
| 3364 | struct mdss_util_intf *util; |
| 3365 | static int te_irq_registered; |
| 3366 | struct mdss_panel_data *pdata; |
Arun kumar | db96281 | 2018-05-30 16:31:52 +0530 | [diff] [blame] | 3367 | struct mdss_panel_cfg *pan_cfg = NULL; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3368 | |
| 3369 | if (!pdev || !pdev->dev.of_node) { |
| 3370 | pr_err("%s: pdev not found for DSI controller\n", __func__); |
| 3371 | return -ENODEV; |
| 3372 | } |
| 3373 | rc = of_property_read_u32(pdev->dev.of_node, |
| 3374 | "cell-index", &index); |
| 3375 | if (rc) { |
| 3376 | dev_err(&pdev->dev, "%s: Cell-index not specified, rc=%d\n", |
| 3377 | __func__, rc); |
| 3378 | return rc; |
| 3379 | } |
| 3380 | |
| 3381 | if (index == 0) |
| 3382 | pdev->id = 1; |
| 3383 | else |
| 3384 | pdev->id = 2; |
| 3385 | |
| 3386 | ctrl_pdata = mdss_dsi_get_ctrl(index); |
| 3387 | if (!ctrl_pdata) { |
| 3388 | pr_err("%s: Unable to get the ctrl_pdata\n", __func__); |
| 3389 | return -EINVAL; |
| 3390 | } |
| 3391 | |
| 3392 | platform_set_drvdata(pdev, ctrl_pdata); |
| 3393 | |
| 3394 | util = mdss_get_util_intf(); |
| 3395 | if (util == NULL) { |
| 3396 | pr_err("Failed to get mdss utility functions\n"); |
| 3397 | return -ENODEV; |
| 3398 | } |
| 3399 | |
Arun kumar | db96281 | 2018-05-30 16:31:52 +0530 | [diff] [blame] | 3400 | pan_cfg = util->panel_intf_type(MDSS_PANEL_INTF_SPI); |
| 3401 | if (IS_ERR(pan_cfg)) { |
| 3402 | return PTR_ERR(pan_cfg); |
| 3403 | } else if (pan_cfg) { |
| 3404 | pr_debug("%s: SPI is primary\n", __func__); |
| 3405 | return -ENODEV; |
| 3406 | } |
| 3407 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3408 | ctrl_pdata->mdss_util = util; |
| 3409 | atomic_set(&ctrl_pdata->te_irq_ready, 0); |
| 3410 | |
| 3411 | ctrl_name = of_get_property(pdev->dev.of_node, "label", NULL); |
| 3412 | if (!ctrl_name) |
| 3413 | pr_info("%s:%d, DSI Ctrl name not specified\n", |
| 3414 | __func__, __LINE__); |
| 3415 | else |
| 3416 | pr_info("%s: DSI Ctrl name = %s\n", |
| 3417 | __func__, ctrl_name); |
| 3418 | |
| 3419 | rc = mdss_dsi_pinctrl_init(pdev); |
| 3420 | if (rc) |
| 3421 | pr_warn("%s: failed to get pin resources\n", __func__); |
| 3422 | |
| 3423 | if (index == 0) { |
| 3424 | ctrl_pdata->panel_data.panel_info.pdest = DISPLAY_1; |
| 3425 | ctrl_pdata->ndx = DSI_CTRL_0; |
| 3426 | } else { |
| 3427 | ctrl_pdata->panel_data.panel_info.pdest = DISPLAY_2; |
| 3428 | ctrl_pdata->ndx = DSI_CTRL_1; |
| 3429 | } |
| 3430 | |
| 3431 | if (mdss_dsi_ctrl_clock_init(pdev, ctrl_pdata)) { |
| 3432 | pr_err("%s: unable to initialize dsi clk manager\n", __func__); |
| 3433 | return -EPERM; |
| 3434 | } |
| 3435 | |
| 3436 | dsi_pan_node = mdss_dsi_config_panel(pdev, index); |
| 3437 | if (!dsi_pan_node) { |
| 3438 | pr_err("%s: panel configuration failed\n", __func__); |
| 3439 | return -EINVAL; |
| 3440 | } |
| 3441 | |
| 3442 | if (!mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) || |
| 3443 | (mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 3444 | (ctrl_pdata->panel_data.panel_info.pdest == DISPLAY_1))) { |
| 3445 | rc = mdss_panel_parse_bl_settings(dsi_pan_node, ctrl_pdata); |
| 3446 | if (rc) { |
| 3447 | pr_warn("%s: dsi bl settings parse failed\n", __func__); |
| 3448 | /* Panels like AMOLED and dsi2hdmi chip |
| 3449 | * does not need backlight control. |
| 3450 | * So we should not fail probe here. |
| 3451 | */ |
| 3452 | ctrl_pdata->bklt_ctrl = UNKNOWN_CTRL; |
| 3453 | } |
| 3454 | } else { |
| 3455 | ctrl_pdata->bklt_ctrl = UNKNOWN_CTRL; |
| 3456 | } |
| 3457 | |
| 3458 | rc = dsi_panel_device_register(pdev, dsi_pan_node, ctrl_pdata); |
| 3459 | if (rc) { |
| 3460 | pr_err("%s: dsi panel dev reg failed\n", __func__); |
| 3461 | goto error_pan_node; |
| 3462 | } |
| 3463 | |
| 3464 | pinfo = &(ctrl_pdata->panel_data.panel_info); |
| 3465 | if (!(mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 3466 | mdss_dsi_is_ctrl_clk_slave(ctrl_pdata)) && |
| 3467 | pinfo->dynamic_fps) { |
| 3468 | rc = mdss_dsi_shadow_clk_init(pdev, ctrl_pdata); |
| 3469 | |
| 3470 | if (rc) { |
| 3471 | pr_err("%s: unable to initialize shadow ctrl clks\n", |
| 3472 | __func__); |
| 3473 | rc = -EPERM; |
| 3474 | } |
| 3475 | } |
| 3476 | |
| 3477 | rc = mdss_dsi_set_clk_rates(ctrl_pdata); |
| 3478 | if (rc) { |
| 3479 | pr_err("%s: Failed to set dsi clk rates\n", __func__); |
| 3480 | return rc; |
| 3481 | } |
| 3482 | |
| 3483 | rc = mdss_dsi_cont_splash_config(pinfo, ctrl_pdata); |
| 3484 | if (rc) { |
| 3485 | pr_err("%s: Failed to set dsi splash config\n", __func__); |
| 3486 | return rc; |
| 3487 | } |
| 3488 | |
| 3489 | if (mdss_dsi_is_te_based_esd(ctrl_pdata)) { |
| 3490 | init_completion(&ctrl_pdata->te_irq_comp); |
| 3491 | rc = devm_request_irq(&pdev->dev, |
| 3492 | gpio_to_irq(ctrl_pdata->disp_te_gpio), |
| 3493 | hw_vsync_handler, IRQF_TRIGGER_FALLING, |
| 3494 | "VSYNC_GPIO", ctrl_pdata); |
| 3495 | if (rc) { |
| 3496 | pr_err("%s: TE request_irq failed for ESD\n", __func__); |
| 3497 | goto error_shadow_clk_deinit; |
| 3498 | } |
| 3499 | te_irq_registered = 1; |
| 3500 | disable_irq(gpio_to_irq(ctrl_pdata->disp_te_gpio)); |
| 3501 | } |
| 3502 | |
| 3503 | pdata = &ctrl_pdata->panel_data; |
| 3504 | init_completion(&pdata->te_done); |
| 3505 | if (pdata->panel_info.type == MIPI_CMD_PANEL) { |
| 3506 | if (!te_irq_registered) { |
| 3507 | rc = devm_request_irq(&pdev->dev, |
| 3508 | gpio_to_irq(pdata->panel_te_gpio), |
| 3509 | test_hw_vsync_handler, IRQF_TRIGGER_FALLING, |
| 3510 | "VSYNC_GPIO", &ctrl_pdata->panel_data); |
| 3511 | if (rc) { |
| 3512 | pr_err("%s: TE request_irq failed\n", __func__); |
| 3513 | goto error_shadow_clk_deinit; |
| 3514 | } |
| 3515 | te_irq_registered = 1; |
| 3516 | disable_irq_nosync(gpio_to_irq(pdata->panel_te_gpio)); |
| 3517 | } |
| 3518 | } |
| 3519 | |
| 3520 | rc = mdss_dsi_get_bridge_chip_params(pinfo, ctrl_pdata, pdev); |
| 3521 | if (rc) { |
| 3522 | pr_err("%s: Failed to get bridge params\n", __func__); |
| 3523 | goto error_shadow_clk_deinit; |
| 3524 | } |
| 3525 | |
| 3526 | ctrl_pdata->workq = create_workqueue("mdss_dsi_dba"); |
| 3527 | if (!ctrl_pdata->workq) { |
| 3528 | pr_err("%s: Error creating workqueue\n", __func__); |
| 3529 | rc = -EPERM; |
| 3530 | goto error_pan_node; |
| 3531 | } |
| 3532 | |
| 3533 | INIT_DELAYED_WORK(&ctrl_pdata->dba_work, mdss_dsi_dba_work); |
| 3534 | |
| 3535 | pr_info("%s: Dsi Ctrl->%d initialized, DSI rev:0x%x, PHY rev:0x%x\n", |
| 3536 | __func__, index, ctrl_pdata->shared_data->hw_rev, |
| 3537 | ctrl_pdata->shared_data->phy_rev); |
| 3538 | mdss_dsi_pm_qos_add_request(ctrl_pdata); |
| 3539 | |
| 3540 | if (index == 0) |
| 3541 | ctrl_pdata->shared_data->dsi0_active = true; |
| 3542 | else |
| 3543 | ctrl_pdata->shared_data->dsi1_active = true; |
| 3544 | |
Sandeep Panda | 812f500 | 2017-02-24 11:36:59 +0530 | [diff] [blame] | 3545 | mdss_dsi_debug_bus_init(mdss_dsi_res); |
| 3546 | |
jialongjhan | 7dfbf87 | 2020-04-21 20:24:23 +0800 | [diff] [blame^] | 3547 | //[Arima_8901][LCM][Jialongjhan] Add LCM_vendor file node for PCBA function test begin |
| 3548 | proc_create("lcm_vendor", 0, NULL, &proc_lcm_vendor_fops); |
| 3549 | //[Arima_8901][LCM][Jialongjhan] Add LCM_vendor file node for PCBA function test end |
| 3550 | |
| 3551 | //[Arima_8901][Jialongjhan] Expose display revision 20190326 begin |
| 3552 | proc_create("lcm_revision", 0666, NULL, &proc_lcm_revision_fops); |
| 3553 | //[Arima_8901][Jialongjhan] Expose display revision 20190326 end |
| 3554 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3555 | return 0; |
| 3556 | |
| 3557 | error_shadow_clk_deinit: |
| 3558 | mdss_dsi_shadow_clk_deinit(&pdev->dev, ctrl_pdata); |
| 3559 | error_pan_node: |
| 3560 | mdss_dsi_unregister_bl_settings(ctrl_pdata); |
| 3561 | of_node_put(dsi_pan_node); |
| 3562 | return rc; |
| 3563 | } |
| 3564 | |
| 3565 | static int mdss_dsi_bus_scale_init(struct platform_device *pdev, |
| 3566 | struct dsi_shared_data *sdata) |
| 3567 | { |
| 3568 | int rc = 0; |
| 3569 | |
| 3570 | sdata->bus_scale_table = msm_bus_cl_get_pdata(pdev); |
| 3571 | if (IS_ERR_OR_NULL(sdata->bus_scale_table)) { |
| 3572 | rc = PTR_ERR(sdata->bus_scale_table); |
| 3573 | pr_err("%s: msm_bus_cl_get_pdata() failed, rc=%d\n", __func__, |
| 3574 | rc); |
| 3575 | return rc; |
| 3576 | sdata->bus_scale_table = NULL; |
| 3577 | } |
| 3578 | |
| 3579 | sdata->bus_handle = |
| 3580 | msm_bus_scale_register_client(sdata->bus_scale_table); |
| 3581 | |
| 3582 | if (!sdata->bus_handle) { |
| 3583 | rc = -EINVAL; |
| 3584 | pr_err("%sbus_client register failed\n", __func__); |
| 3585 | } |
| 3586 | |
| 3587 | return rc; |
| 3588 | } |
| 3589 | |
| 3590 | static void mdss_dsi_bus_scale_deinit(struct dsi_shared_data *sdata) |
| 3591 | { |
| 3592 | if (sdata->bus_handle) { |
| 3593 | if (sdata->bus_refcount) |
| 3594 | msm_bus_scale_client_update_request(sdata->bus_handle, |
| 3595 | 0); |
| 3596 | |
| 3597 | sdata->bus_refcount = 0; |
| 3598 | msm_bus_scale_unregister_client(sdata->bus_handle); |
| 3599 | sdata->bus_handle = 0; |
| 3600 | } |
| 3601 | } |
| 3602 | |
| 3603 | static int mdss_dsi_parse_dt_params(struct platform_device *pdev, |
| 3604 | struct dsi_shared_data *sdata) |
| 3605 | { |
| 3606 | int rc = 0; |
| 3607 | |
| 3608 | rc = of_property_read_u32(pdev->dev.of_node, |
| 3609 | "qcom,mmss-ulp-clamp-ctrl-offset", |
| 3610 | &sdata->ulps_clamp_ctrl_off); |
| 3611 | if (!rc) { |
| 3612 | rc = of_property_read_u32(pdev->dev.of_node, |
| 3613 | "qcom,mmss-phyreset-ctrl-offset", |
| 3614 | &sdata->ulps_phyrst_ctrl_off); |
| 3615 | } |
| 3616 | |
| 3617 | sdata->cmd_clk_ln_recovery_en = |
| 3618 | of_property_read_bool(pdev->dev.of_node, |
| 3619 | "qcom,dsi-clk-ln-recovery"); |
| 3620 | |
Xipeng Gu | 28b6d15 | 2019-09-11 10:54:17 +0800 | [diff] [blame] | 3621 | sdata->skip_clamp = |
| 3622 | of_property_read_bool(pdev->dev.of_node, |
| 3623 | "qcom,mdss-skip-clamp"); |
| 3624 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3625 | return 0; |
| 3626 | } |
| 3627 | |
| 3628 | #ifdef TARGET_HW_MDSS_HDMI |
| 3629 | static void mdss_dsi_res_deinit_hdmi(struct platform_device *pdev, int val) |
| 3630 | { |
| 3631 | struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev); |
| 3632 | |
| 3633 | if (dsi_res->ctrl_pdata[val]->ds_registered) { |
| 3634 | struct mdss_panel_info *pinfo = |
| 3635 | &dsi_res->ctrl_pdata[val]-> |
| 3636 | panel_data.panel_info; |
| 3637 | if (pinfo) |
| 3638 | mdss_dba_utils_deinit(pinfo->dba_data); |
| 3639 | } |
| 3640 | } |
| 3641 | #else |
| 3642 | static void mdss_dsi_res_deinit_hdmi(struct platform_device *pdev, int val) |
| 3643 | { |
| 3644 | (void)(*pdev); |
| 3645 | (void)(val); |
| 3646 | } |
| 3647 | #endif |
| 3648 | |
| 3649 | static void mdss_dsi_res_deinit(struct platform_device *pdev) |
| 3650 | { |
| 3651 | int i; |
| 3652 | struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev); |
| 3653 | struct dsi_shared_data *sdata; |
| 3654 | |
| 3655 | if (!dsi_res) { |
| 3656 | pr_err("%s: DSI root device drvdata not found\n", __func__); |
| 3657 | return; |
| 3658 | } |
| 3659 | |
| 3660 | for (i = 0; i < DSI_CTRL_MAX; i++) { |
| 3661 | if (dsi_res->ctrl_pdata[i]) { |
| 3662 | mdss_dsi_res_deinit_hdmi(pdev, i); |
| 3663 | devm_kfree(&pdev->dev, dsi_res->ctrl_pdata[i]); |
| 3664 | } |
| 3665 | } |
| 3666 | |
| 3667 | sdata = dsi_res->shared_data; |
| 3668 | if (!sdata) |
| 3669 | goto res_release; |
| 3670 | |
| 3671 | for (i = (DSI_MAX_PM - 1); i >= DSI_CORE_PM; i--) { |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 3672 | if (msm_mdss_config_vreg(&pdev->dev, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3673 | sdata->power_data[i].vreg_config, |
| 3674 | sdata->power_data[i].num_vreg, 1) < 0) |
| 3675 | pr_err("%s: failed to de-init vregs for %s\n", |
| 3676 | __func__, __mdss_dsi_pm_name(i)); |
| 3677 | mdss_dsi_put_dt_vreg_data(&pdev->dev, |
| 3678 | &sdata->power_data[i]); |
| 3679 | } |
| 3680 | |
| 3681 | mdss_dsi_bus_scale_deinit(sdata); |
| 3682 | mdss_dsi_core_clk_deinit(&pdev->dev, sdata); |
| 3683 | |
| 3684 | if (sdata) |
| 3685 | devm_kfree(&pdev->dev, sdata); |
| 3686 | |
| 3687 | res_release: |
| 3688 | if (dsi_res) |
| 3689 | devm_kfree(&pdev->dev, dsi_res); |
| 3690 | |
| 3691 | } |
| 3692 | |
| 3693 | static int mdss_dsi_res_init(struct platform_device *pdev) |
| 3694 | { |
| 3695 | int rc = 0, i; |
| 3696 | struct dsi_shared_data *sdata; |
| 3697 | |
| 3698 | mdss_dsi_res = platform_get_drvdata(pdev); |
| 3699 | if (!mdss_dsi_res) { |
| 3700 | mdss_dsi_res = devm_kzalloc(&pdev->dev, |
| 3701 | sizeof(struct mdss_dsi_data), |
| 3702 | GFP_KERNEL); |
| 3703 | if (!mdss_dsi_res) { |
| 3704 | pr_err("%s: FAILED: cannot alloc dsi data\n", |
| 3705 | __func__); |
| 3706 | rc = -ENOMEM; |
| 3707 | goto mem_fail; |
| 3708 | } |
| 3709 | |
| 3710 | mdss_dsi_res->shared_data = devm_kzalloc(&pdev->dev, |
| 3711 | sizeof(struct dsi_shared_data), |
| 3712 | GFP_KERNEL); |
| 3713 | pr_debug("%s Allocated shared_data=%pK\n", __func__, |
| 3714 | mdss_dsi_res->shared_data); |
| 3715 | if (!mdss_dsi_res->shared_data) { |
| 3716 | pr_err("%s Unable to alloc mem for shared_data\n", |
| 3717 | __func__); |
| 3718 | rc = -ENOMEM; |
| 3719 | goto mem_fail; |
| 3720 | } |
| 3721 | |
| 3722 | sdata = mdss_dsi_res->shared_data; |
| 3723 | |
| 3724 | rc = mdss_dsi_parse_dt_params(pdev, sdata); |
| 3725 | if (rc) { |
| 3726 | pr_err("%s: failed to parse mdss dsi DT params\n", |
| 3727 | __func__); |
| 3728 | goto mem_fail; |
| 3729 | } |
| 3730 | |
| 3731 | rc = mdss_dsi_core_clk_init(pdev, sdata); |
| 3732 | if (rc) { |
| 3733 | pr_err("%s: failed to initialize DSI core clocks\n", |
| 3734 | __func__); |
| 3735 | goto mem_fail; |
| 3736 | } |
| 3737 | |
| 3738 | /* Parse the regulator information */ |
| 3739 | for (i = DSI_CORE_PM; i < DSI_MAX_PM; i++) { |
| 3740 | rc = mdss_dsi_get_dt_vreg_data(&pdev->dev, |
| 3741 | pdev->dev.of_node, &sdata->power_data[i], i); |
| 3742 | if (rc) { |
| 3743 | pr_err("%s: '%s' get_dt_vreg_data failed.rc=%d\n", |
| 3744 | __func__, __mdss_dsi_pm_name(i), rc); |
| 3745 | i--; |
| 3746 | for (; i >= DSI_CORE_PM; i--) |
| 3747 | mdss_dsi_put_dt_vreg_data(&pdev->dev, |
| 3748 | &sdata->power_data[i]); |
| 3749 | goto mem_fail; |
| 3750 | } |
| 3751 | } |
| 3752 | rc = mdss_dsi_regulator_init(pdev, sdata); |
| 3753 | if (rc) { |
| 3754 | pr_err("%s: failed to init regulator, rc=%d\n", |
| 3755 | __func__, rc); |
| 3756 | goto mem_fail; |
| 3757 | } |
| 3758 | |
| 3759 | rc = mdss_dsi_bus_scale_init(pdev, sdata); |
| 3760 | if (rc) { |
| 3761 | pr_err("%s: failed to init bus scale settings, rc=%d\n", |
| 3762 | __func__, rc); |
| 3763 | goto mem_fail; |
| 3764 | } |
| 3765 | |
| 3766 | mutex_init(&sdata->phy_reg_lock); |
| 3767 | mutex_init(&sdata->pm_qos_lock); |
| 3768 | |
| 3769 | for (i = 0; i < DSI_CTRL_MAX; i++) { |
| 3770 | mdss_dsi_res->ctrl_pdata[i] = devm_kzalloc(&pdev->dev, |
| 3771 | sizeof(struct mdss_dsi_ctrl_pdata), |
| 3772 | GFP_KERNEL); |
| 3773 | if (!mdss_dsi_res->ctrl_pdata[i]) { |
| 3774 | pr_err("%s Unable to alloc mem for ctrl=%d\n", |
| 3775 | __func__, i); |
| 3776 | rc = -ENOMEM; |
| 3777 | goto mem_fail; |
| 3778 | } |
| 3779 | pr_debug("%s Allocated ctrl_pdata[%d]=%pK\n", |
| 3780 | __func__, i, mdss_dsi_res->ctrl_pdata[i]); |
| 3781 | mdss_dsi_res->ctrl_pdata[i]->shared_data = |
| 3782 | mdss_dsi_res->shared_data; |
| 3783 | } |
| 3784 | |
| 3785 | platform_set_drvdata(pdev, mdss_dsi_res); |
| 3786 | } |
| 3787 | |
| 3788 | mdss_dsi_res->pdev = pdev; |
| 3789 | pr_debug("%s: Setting up mdss_dsi_res=%pK\n", __func__, mdss_dsi_res); |
| 3790 | |
| 3791 | return 0; |
| 3792 | |
| 3793 | mem_fail: |
| 3794 | mdss_dsi_res_deinit(pdev); |
| 3795 | return rc; |
| 3796 | } |
| 3797 | |
| 3798 | static int mdss_dsi_parse_hw_cfg(struct platform_device *pdev, char *pan_cfg) |
| 3799 | { |
| 3800 | const char *data; |
| 3801 | struct mdss_dsi_data *dsi_res = platform_get_drvdata(pdev); |
| 3802 | struct dsi_shared_data *sdata; |
| 3803 | char dsi_cfg[20]; |
| 3804 | char *cfg_prim = NULL, *cfg_sec = NULL, *ch = NULL; |
| 3805 | int i = 0; |
| 3806 | |
| 3807 | if (!dsi_res) { |
| 3808 | pr_err("%s: DSI root device drvdata not found\n", __func__); |
| 3809 | return -EINVAL; |
| 3810 | } |
| 3811 | |
| 3812 | sdata = mdss_dsi_res->shared_data; |
| 3813 | if (!sdata) { |
| 3814 | pr_err("%s: DSI shared data not found\n", __func__); |
| 3815 | return -EINVAL; |
| 3816 | } |
| 3817 | |
| 3818 | sdata->hw_config = SINGLE_DSI; |
| 3819 | |
| 3820 | if (pan_cfg) |
| 3821 | cfg_prim = strnstr(pan_cfg, "cfg:", strlen(pan_cfg)); |
| 3822 | if (cfg_prim) { |
| 3823 | cfg_prim += 4; |
| 3824 | |
| 3825 | cfg_sec = strnchr(cfg_prim, strlen(cfg_prim), ':'); |
| 3826 | if (!cfg_sec) |
| 3827 | cfg_sec = cfg_prim + strlen(cfg_prim); |
| 3828 | |
| 3829 | for (i = 0; ((cfg_prim + i) < cfg_sec) && |
| 3830 | (*(cfg_prim+i) != '#'); i++) |
| 3831 | dsi_cfg[i] = *(cfg_prim + i); |
| 3832 | |
| 3833 | dsi_cfg[i] = '\0'; |
| 3834 | data = dsi_cfg; |
| 3835 | } else { |
| 3836 | data = of_get_property(pdev->dev.of_node, |
| 3837 | "hw-config", NULL); |
| 3838 | } |
| 3839 | |
| 3840 | if (data) { |
| 3841 | /* |
| 3842 | * To handle the override parameter (#override:sim) |
| 3843 | * passed for simulator panels |
| 3844 | */ |
| 3845 | ch = strnstr(data, "#", strlen(data)); |
| 3846 | ch ? *ch = '\0' : false; |
| 3847 | |
| 3848 | if (!strcmp(data, "dual_dsi")) |
| 3849 | sdata->hw_config = DUAL_DSI; |
| 3850 | else if (!strcmp(data, "split_dsi")) |
| 3851 | sdata->hw_config = SPLIT_DSI; |
| 3852 | else if (!strcmp(data, "single_dsi")) |
| 3853 | sdata->hw_config = SINGLE_DSI; |
| 3854 | else |
| 3855 | pr_err("%s: Incorrect string for DSI config:%s. Setting default as SINGLE_DSI\n", |
| 3856 | __func__, data); |
| 3857 | } else { |
| 3858 | pr_err("%s: Error: No DSI HW config found\n", |
| 3859 | __func__); |
| 3860 | return -EINVAL; |
| 3861 | } |
| 3862 | |
| 3863 | pr_debug("%s: DSI h/w configuration is %d\n", __func__, |
| 3864 | sdata->hw_config); |
| 3865 | |
| 3866 | return 0; |
| 3867 | } |
| 3868 | |
| 3869 | static void mdss_dsi_parse_pll_src_cfg(struct platform_device *pdev, |
| 3870 | char *pan_cfg) |
| 3871 | { |
| 3872 | const char *data; |
| 3873 | char *pll_ptr, pll_cfg[10] = {'\0'}; |
| 3874 | struct dsi_shared_data *sdata = mdss_dsi_res->shared_data; |
| 3875 | |
| 3876 | sdata->pll_src_config = PLL_SRC_DEFAULT; |
| 3877 | |
| 3878 | if (pan_cfg) { |
| 3879 | pll_ptr = strnstr(pan_cfg, ":pll0", strlen(pan_cfg)); |
| 3880 | if (!pll_ptr) { |
| 3881 | pll_ptr = strnstr(pan_cfg, ":pll1", strlen(pan_cfg)); |
| 3882 | if (pll_ptr) |
| 3883 | strlcpy(pll_cfg, "PLL1", strlen(pll_cfg)); |
| 3884 | } else { |
| 3885 | strlcpy(pll_cfg, "PLL0", strlen(pll_cfg)); |
| 3886 | } |
| 3887 | } |
| 3888 | data = pll_cfg; |
| 3889 | |
| 3890 | if (!data || !strcmp(data, "")) |
| 3891 | data = of_get_property(pdev->dev.of_node, |
| 3892 | "pll-src-config", NULL); |
| 3893 | if (data) { |
| 3894 | if (!strcmp(data, "PLL0")) |
| 3895 | sdata->pll_src_config = PLL_SRC_0; |
| 3896 | else if (!strcmp(data, "PLL1")) |
| 3897 | sdata->pll_src_config = PLL_SRC_1; |
| 3898 | else |
| 3899 | pr_err("%s: invalid pll src config %s\n", |
| 3900 | __func__, data); |
| 3901 | } else { |
| 3902 | pr_debug("%s: PLL src config not specified\n", __func__); |
| 3903 | } |
| 3904 | |
| 3905 | pr_debug("%s: pll_src_config = %d", __func__, sdata->pll_src_config); |
| 3906 | } |
| 3907 | |
| 3908 | static int mdss_dsi_validate_pll_src_config(struct dsi_shared_data *sdata) |
| 3909 | { |
| 3910 | int rc = 0; |
| 3911 | |
| 3912 | /* |
| 3913 | * DSI PLL1 can only drive DSI PHY1. As such: |
| 3914 | * - For split dsi config, only PLL0 is supported |
| 3915 | * - For dual dsi config, DSI0-PLL0 and DSI1-PLL1 is the only |
| 3916 | * possible configuration |
| 3917 | */ |
| 3918 | if (mdss_dsi_is_hw_config_split(sdata) && |
| 3919 | mdss_dsi_is_pll_src_pll1(sdata)) { |
| 3920 | pr_err("%s: unsupported PLL config: using PLL1 for split-dsi\n", |
| 3921 | __func__); |
| 3922 | rc = -EINVAL; |
| 3923 | goto error; |
| 3924 | } |
| 3925 | |
| 3926 | if (mdss_dsi_is_hw_config_dual(sdata) && |
| 3927 | !mdss_dsi_is_pll_src_default(sdata)) { |
| 3928 | pr_debug("%s: pll src config not applicable for dual-dsi\n", |
| 3929 | __func__); |
| 3930 | sdata->pll_src_config = PLL_SRC_DEFAULT; |
| 3931 | } |
| 3932 | |
| 3933 | error: |
| 3934 | return rc; |
| 3935 | } |
| 3936 | |
| 3937 | static int mdss_dsi_validate_config(struct platform_device *pdev) |
| 3938 | { |
| 3939 | struct dsi_shared_data *sdata = mdss_dsi_res->shared_data; |
| 3940 | |
| 3941 | return mdss_dsi_validate_pll_src_config(sdata); |
| 3942 | } |
| 3943 | |
| 3944 | static const struct of_device_id mdss_dsi_ctrl_dt_match[] = { |
| 3945 | {.compatible = "qcom,mdss-dsi-ctrl"}, |
| 3946 | {} |
| 3947 | }; |
| 3948 | MODULE_DEVICE_TABLE(of, mdss_dsi_ctrl_dt_match); |
| 3949 | |
| 3950 | static int mdss_dsi_probe(struct platform_device *pdev) |
| 3951 | { |
| 3952 | struct mdss_panel_cfg *pan_cfg = NULL; |
| 3953 | struct mdss_util_intf *util; |
| 3954 | char *panel_cfg; |
| 3955 | int rc = 0; |
| 3956 | |
| 3957 | util = mdss_get_util_intf(); |
| 3958 | if (util == NULL) { |
| 3959 | pr_err("%s: Failed to get mdss utility functions\n", __func__); |
| 3960 | return -ENODEV; |
| 3961 | } |
| 3962 | |
| 3963 | if (!util->mdp_probe_done) { |
| 3964 | pr_err("%s: MDP not probed yet!\n", __func__); |
| 3965 | return -EPROBE_DEFER; |
| 3966 | } |
| 3967 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 3968 | if (!pdev || !pdev->dev.of_node) { |
| 3969 | pr_err("%s: DSI driver only supports device tree probe\n", |
| 3970 | __func__); |
| 3971 | return -ENOTSUPP; |
| 3972 | } |
| 3973 | |
| 3974 | pan_cfg = util->panel_intf_type(MDSS_PANEL_INTF_HDMI); |
| 3975 | if (IS_ERR(pan_cfg)) { |
| 3976 | return PTR_ERR(pan_cfg); |
| 3977 | } else if (pan_cfg) { |
| 3978 | pr_debug("%s: HDMI is primary\n", __func__); |
| 3979 | return -ENODEV; |
| 3980 | } |
| 3981 | |
| 3982 | pan_cfg = util->panel_intf_type(MDSS_PANEL_INTF_DSI); |
| 3983 | if (IS_ERR_OR_NULL(pan_cfg)) { |
| 3984 | rc = PTR_ERR(pan_cfg); |
| 3985 | goto error; |
| 3986 | } else { |
| 3987 | panel_cfg = pan_cfg->arg_cfg; |
| 3988 | } |
| 3989 | |
| 3990 | rc = mdss_dsi_res_init(pdev); |
| 3991 | if (rc) { |
| 3992 | pr_err("%s Unable to set dsi res\n", __func__); |
| 3993 | return rc; |
| 3994 | } |
| 3995 | |
| 3996 | rc = mdss_dsi_parse_hw_cfg(pdev, panel_cfg); |
| 3997 | if (rc) { |
| 3998 | pr_err("%s Unable to parse dsi h/w config\n", __func__); |
| 3999 | mdss_dsi_res_deinit(pdev); |
| 4000 | return rc; |
| 4001 | } |
| 4002 | |
| 4003 | mdss_dsi_parse_pll_src_cfg(pdev, panel_cfg); |
| 4004 | |
| 4005 | of_platform_populate(pdev->dev.of_node, mdss_dsi_ctrl_dt_match, |
| 4006 | NULL, &pdev->dev); |
| 4007 | |
| 4008 | rc = mdss_dsi_validate_config(pdev); |
| 4009 | if (rc) { |
| 4010 | pr_err("%s: Invalid DSI hw configuration\n", __func__); |
| 4011 | goto error; |
| 4012 | } |
| 4013 | |
| 4014 | mdss_dsi_config_clk_src(pdev); |
| 4015 | |
| 4016 | error: |
| 4017 | return rc; |
| 4018 | } |
| 4019 | |
| 4020 | static int mdss_dsi_remove(struct platform_device *pdev) |
| 4021 | { |
| 4022 | mdss_dsi_res_deinit(pdev); |
| 4023 | return 0; |
| 4024 | } |
| 4025 | |
| 4026 | static int mdss_dsi_ctrl_remove(struct platform_device *pdev) |
| 4027 | { |
| 4028 | struct msm_fb_data_type *mfd; |
| 4029 | struct mdss_dsi_ctrl_pdata *ctrl_pdata = platform_get_drvdata(pdev); |
| 4030 | |
| 4031 | if (!ctrl_pdata) { |
| 4032 | pr_err("%s: no driver data\n", __func__); |
| 4033 | return -ENODEV; |
| 4034 | } |
| 4035 | |
| 4036 | mdss_dsi_pm_qos_remove_request(ctrl_pdata->shared_data); |
| 4037 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4038 | if (msm_mdss_config_vreg(&pdev->dev, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4039 | ctrl_pdata->panel_power_data.vreg_config, |
| 4040 | ctrl_pdata->panel_power_data.num_vreg, 1) < 0) |
| 4041 | pr_err("%s: failed to de-init vregs for %s\n", |
| 4042 | __func__, __mdss_dsi_pm_name(DSI_PANEL_PM)); |
| 4043 | mdss_dsi_put_dt_vreg_data(&pdev->dev, &ctrl_pdata->panel_power_data); |
| 4044 | |
| 4045 | mfd = platform_get_drvdata(pdev); |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4046 | msm_mdss_iounmap(&ctrl_pdata->mmss_misc_io); |
| 4047 | msm_mdss_iounmap(&ctrl_pdata->phy_io); |
| 4048 | msm_mdss_iounmap(&ctrl_pdata->ctrl_io); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4049 | mdss_dsi_debugfs_cleanup(ctrl_pdata); |
| 4050 | |
| 4051 | if (ctrl_pdata->workq) |
| 4052 | destroy_workqueue(ctrl_pdata->workq); |
| 4053 | |
| 4054 | return 0; |
| 4055 | } |
| 4056 | |
| 4057 | struct device dsi_dev; |
| 4058 | |
| 4059 | int mdss_dsi_retrieve_ctrl_resources(struct platform_device *pdev, int mode, |
| 4060 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 4061 | { |
| 4062 | int rc = 0; |
| 4063 | u32 index; |
| 4064 | |
| 4065 | rc = of_property_read_u32(pdev->dev.of_node, "cell-index", &index); |
| 4066 | if (rc) { |
| 4067 | dev_err(&pdev->dev, |
| 4068 | "%s: Cell-index not specified, rc=%d\n", |
| 4069 | __func__, rc); |
| 4070 | return rc; |
| 4071 | } |
| 4072 | |
| 4073 | if (index == 0) { |
| 4074 | if (mode != DISPLAY_1) { |
| 4075 | pr_err("%s:%d Panel->Ctrl mapping is wrong\n", |
| 4076 | __func__, __LINE__); |
| 4077 | return -EPERM; |
| 4078 | } |
| 4079 | } else if (index == 1) { |
| 4080 | if (mode != DISPLAY_2) { |
| 4081 | pr_err("%s:%d Panel->Ctrl mapping is wrong\n", |
| 4082 | __func__, __LINE__); |
| 4083 | return -EPERM; |
| 4084 | } |
| 4085 | } else { |
| 4086 | pr_err("%s:%d Unknown Ctrl mapped to panel\n", |
| 4087 | __func__, __LINE__); |
| 4088 | return -EPERM; |
| 4089 | } |
| 4090 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4091 | rc = msm_mdss_ioremap_byname(pdev, &ctrl->ctrl_io, "dsi_ctrl"); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4092 | if (rc) { |
| 4093 | pr_err("%s:%d unable to remap dsi ctrl resources\n", |
| 4094 | __func__, __LINE__); |
| 4095 | return rc; |
| 4096 | } |
| 4097 | |
| 4098 | ctrl->ctrl_base = ctrl->ctrl_io.base; |
| 4099 | ctrl->reg_size = ctrl->ctrl_io.len; |
| 4100 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4101 | rc = msm_mdss_ioremap_byname(pdev, &ctrl->phy_io, "dsi_phy"); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4102 | if (rc) { |
| 4103 | pr_err("%s:%d unable to remap dsi phy resources\n", |
| 4104 | __func__, __LINE__); |
| 4105 | return rc; |
| 4106 | } |
| 4107 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4108 | rc = msm_mdss_ioremap_byname(pdev, &ctrl->phy_regulator_io, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4109 | "dsi_phy_regulator"); |
| 4110 | if (rc) |
| 4111 | pr_debug("%s:%d unable to remap dsi phy regulator resources\n", |
| 4112 | __func__, __LINE__); |
| 4113 | else |
| 4114 | pr_info("%s: phy_regulator_base=%pK phy_regulator_size=%x\n", |
| 4115 | __func__, ctrl->phy_regulator_io.base, |
| 4116 | ctrl->phy_regulator_io.len); |
| 4117 | |
| 4118 | pr_info("%s: ctrl_base=%pK ctrl_size=%x phy_base=%pK phy_size=%x\n", |
| 4119 | __func__, ctrl->ctrl_base, ctrl->reg_size, ctrl->phy_io.base, |
| 4120 | ctrl->phy_io.len); |
| 4121 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4122 | rc = msm_mdss_ioremap_byname(pdev, &ctrl->mmss_misc_io, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4123 | "mmss_misc_phys"); |
| 4124 | if (rc) { |
| 4125 | pr_debug("%s:%d mmss_misc IO remap failed\n", |
| 4126 | __func__, __LINE__); |
| 4127 | } |
| 4128 | |
| 4129 | return 0; |
| 4130 | } |
| 4131 | |
| 4132 | static int mdss_dsi_irq_init(struct device *dev, int irq_no, |
| 4133 | struct mdss_dsi_ctrl_pdata *ctrl) |
| 4134 | { |
| 4135 | int ret; |
| 4136 | |
| 4137 | ret = devm_request_irq(dev, irq_no, mdss_dsi_isr, |
Sachin Bhayare | 3d3767e | 2018-01-02 21:10:57 +0530 | [diff] [blame] | 4138 | 0, "DSI", ctrl); |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4139 | if (ret) { |
| 4140 | pr_err("msm_dsi_irq_init request_irq() failed!\n"); |
| 4141 | return ret; |
| 4142 | } |
| 4143 | |
| 4144 | disable_irq(irq_no); |
| 4145 | ctrl->dsi_hw->irq_info = kcalloc(1, sizeof(struct irq_info), |
| 4146 | GFP_KERNEL); |
| 4147 | if (!ctrl->dsi_hw->irq_info) |
| 4148 | return -ENOMEM; |
| 4149 | |
| 4150 | ctrl->dsi_hw->irq_info->irq = irq_no; |
| 4151 | ctrl->dsi_hw->irq_info->irq_ena = false; |
| 4152 | |
| 4153 | return ret; |
| 4154 | } |
| 4155 | |
| 4156 | static void mdss_dsi_parse_lane_swap(struct device_node *np, char *dlane_swap) |
| 4157 | { |
| 4158 | const char *data; |
| 4159 | |
| 4160 | *dlane_swap = DSI_LANE_MAP_0123; |
| 4161 | data = of_get_property(np, "qcom,lane-map", NULL); |
| 4162 | if (data) { |
| 4163 | if (!strcmp(data, "lane_map_3012")) |
| 4164 | *dlane_swap = DSI_LANE_MAP_3012; |
| 4165 | else if (!strcmp(data, "lane_map_2301")) |
| 4166 | *dlane_swap = DSI_LANE_MAP_2301; |
| 4167 | else if (!strcmp(data, "lane_map_1230")) |
| 4168 | *dlane_swap = DSI_LANE_MAP_1230; |
| 4169 | else if (!strcmp(data, "lane_map_0321")) |
| 4170 | *dlane_swap = DSI_LANE_MAP_0321; |
| 4171 | else if (!strcmp(data, "lane_map_1032")) |
| 4172 | *dlane_swap = DSI_LANE_MAP_1032; |
| 4173 | else if (!strcmp(data, "lane_map_2103")) |
| 4174 | *dlane_swap = DSI_LANE_MAP_2103; |
| 4175 | else if (!strcmp(data, "lane_map_3210")) |
| 4176 | *dlane_swap = DSI_LANE_MAP_3210; |
| 4177 | } |
| 4178 | } |
| 4179 | |
| 4180 | static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev, |
| 4181 | struct device_node *pan_node, struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 4182 | { |
| 4183 | int i, len; |
| 4184 | struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info); |
| 4185 | const char *data; |
| 4186 | |
| 4187 | ctrl_pdata->null_insert_enabled = of_property_read_bool( |
| 4188 | ctrl_pdev->dev.of_node, "qcom,null-insertion-enabled"); |
| 4189 | |
| 4190 | data = of_get_property(ctrl_pdev->dev.of_node, |
| 4191 | "qcom,platform-strength-ctrl", &len); |
| 4192 | if (!data) { |
| 4193 | pr_err("%s:%d, Unable to read Phy Strength ctrl settings\n", |
| 4194 | __func__, __LINE__); |
Padmanabhan Komanduru | 81d8dc52 | 2018-03-22 20:00:58 +0530 | [diff] [blame] | 4195 | } else { |
| 4196 | pinfo->mipi.dsi_phy_db.strength_len = len; |
| 4197 | for (i = 0; i < len; i++) |
| 4198 | pinfo->mipi.dsi_phy_db.strength[i] = data[i]; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4199 | } |
| 4200 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4201 | pinfo->mipi.dsi_phy_db.reg_ldo_mode = of_property_read_bool( |
| 4202 | ctrl_pdev->dev.of_node, "qcom,regulator-ldo-mode"); |
| 4203 | |
| 4204 | data = of_get_property(ctrl_pdev->dev.of_node, |
| 4205 | "qcom,platform-regulator-settings", &len); |
| 4206 | if (!data) { |
| 4207 | pr_err("%s:%d, Unable to read Phy regulator settings\n", |
| 4208 | __func__, __LINE__); |
Padmanabhan Komanduru | 81d8dc52 | 2018-03-22 20:00:58 +0530 | [diff] [blame] | 4209 | } else { |
| 4210 | pinfo->mipi.dsi_phy_db.regulator_len = len; |
| 4211 | for (i = 0; i < len; i++) |
| 4212 | pinfo->mipi.dsi_phy_db.regulator[i] = data[i]; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4213 | } |
| 4214 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4215 | data = of_get_property(ctrl_pdev->dev.of_node, |
| 4216 | "qcom,platform-bist-ctrl", &len); |
| 4217 | if ((!data) || (len != 6)) |
| 4218 | pr_debug("%s:%d, Unable to read Phy Bist Ctrl settings\n", |
| 4219 | __func__, __LINE__); |
| 4220 | else |
| 4221 | for (i = 0; i < len; i++) |
| 4222 | pinfo->mipi.dsi_phy_db.bistctrl[i] = data[i]; |
| 4223 | |
| 4224 | data = of_get_property(ctrl_pdev->dev.of_node, |
| 4225 | "qcom,platform-lane-config", &len); |
| 4226 | if (!data) { |
| 4227 | pr_err("%s:%d, Unable to read Phy lane configure settings\n", |
| 4228 | __func__, __LINE__); |
Padmanabhan Komanduru | 81d8dc52 | 2018-03-22 20:00:58 +0530 | [diff] [blame] | 4229 | } else { |
| 4230 | pinfo->mipi.dsi_phy_db.lanecfg_len = len; |
| 4231 | for (i = 0; i < len; i++) |
| 4232 | pinfo->mipi.dsi_phy_db.lanecfg[i] = data[i]; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4233 | } |
| 4234 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4235 | ctrl_pdata->timing_db_mode = of_property_read_bool( |
| 4236 | ctrl_pdev->dev.of_node, "qcom,timing-db-mode"); |
| 4237 | |
| 4238 | ctrl_pdata->cmd_sync_wait_broadcast = of_property_read_bool( |
| 4239 | pan_node, "qcom,cmd-sync-wait-broadcast"); |
| 4240 | |
| 4241 | if (ctrl_pdata->cmd_sync_wait_broadcast && |
| 4242 | mdss_dsi_is_hw_config_split(ctrl_pdata->shared_data) && |
| 4243 | (pinfo->pdest == DISPLAY_2)) |
| 4244 | ctrl_pdata->cmd_sync_wait_trigger = true; |
| 4245 | |
| 4246 | pr_debug("%s: cmd_sync_wait_enable=%d trigger=%d\n", __func__, |
| 4247 | ctrl_pdata->cmd_sync_wait_broadcast, |
| 4248 | ctrl_pdata->cmd_sync_wait_trigger); |
| 4249 | |
| 4250 | mdss_dsi_parse_lane_swap(ctrl_pdev->dev.of_node, |
| 4251 | &(ctrl_pdata->dlane_swap)); |
| 4252 | |
| 4253 | pinfo->is_pluggable = of_property_read_bool(ctrl_pdev->dev.of_node, |
| 4254 | "qcom,pluggable"); |
| 4255 | |
| 4256 | data = of_get_property(ctrl_pdev->dev.of_node, |
| 4257 | "qcom,display-id", &len); |
| 4258 | if (!data || len <= 0) |
| 4259 | pr_err("%s:%d Unable to read qcom,display-id, data=%pK,len=%d\n", |
| 4260 | __func__, __LINE__, data, len); |
| 4261 | else |
| 4262 | snprintf(ctrl_pdata->panel_data.panel_info.display_id, |
| 4263 | MDSS_DISPLAY_ID_MAX_LEN, "%s", data); |
| 4264 | |
| 4265 | return 0; |
| 4266 | |
| 4267 | |
| 4268 | } |
| 4269 | |
| 4270 | static int mdss_dsi_parse_gpio_params(struct platform_device *ctrl_pdev, |
| 4271 | struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 4272 | { |
| 4273 | struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info); |
| 4274 | struct mdss_panel_data *pdata = &ctrl_pdata->panel_data; |
| 4275 | |
| 4276 | /* |
| 4277 | * If disp_en_gpio has been set previously (disp_en_gpio > 0) |
| 4278 | * while parsing the panel node, then do not override it |
| 4279 | */ |
| 4280 | if (ctrl_pdata->disp_en_gpio <= 0) { |
| 4281 | ctrl_pdata->disp_en_gpio = of_get_named_gpio( |
| 4282 | ctrl_pdev->dev.of_node, |
| 4283 | "qcom,platform-enable-gpio", 0); |
| 4284 | |
| 4285 | if (!gpio_is_valid(ctrl_pdata->disp_en_gpio)) |
| 4286 | pr_debug("%s:%d, Disp_en gpio not specified\n", |
| 4287 | __func__, __LINE__); |
Arun kumar | ec570b7 | 2018-05-09 20:23:38 +0530 | [diff] [blame] | 4288 | pdata->panel_en_gpio = ctrl_pdata->disp_en_gpio; |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4289 | } |
| 4290 | |
| 4291 | ctrl_pdata->disp_te_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node, |
| 4292 | "qcom,platform-te-gpio", 0); |
| 4293 | |
| 4294 | if (!gpio_is_valid(ctrl_pdata->disp_te_gpio)) |
| 4295 | pr_err("%s:%d, TE gpio not specified\n", |
| 4296 | __func__, __LINE__); |
| 4297 | pdata->panel_te_gpio = ctrl_pdata->disp_te_gpio; |
| 4298 | |
| 4299 | ctrl_pdata->bklt_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node, |
| 4300 | "qcom,platform-bklight-en-gpio", 0); |
| 4301 | if (!gpio_is_valid(ctrl_pdata->bklt_en_gpio)) |
| 4302 | pr_info("%s: bklt_en gpio not specified\n", __func__); |
| 4303 | |
Yahui Wang | 12a6d37 | 2016-12-12 22:43:20 +0800 | [diff] [blame] | 4304 | ctrl_pdata->bklt_en_gpio_invert = |
| 4305 | of_property_read_bool(ctrl_pdev->dev.of_node, |
| 4306 | "qcom,platform-bklight-en-gpio-invert"); |
| 4307 | |
Narender Ankam | 4fcd689 | 2018-06-11 13:09:00 +0530 | [diff] [blame] | 4308 | ctrl_pdata->vdd_ext_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node, |
| 4309 | "qcom,ext-vdd-gpio", 0); |
| 4310 | if (!gpio_is_valid(ctrl_pdata->vdd_ext_gpio)) |
| 4311 | pr_info("%s: ext vdd gpio not specified\n", __func__); |
| 4312 | |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4313 | ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node, |
| 4314 | "qcom,platform-reset-gpio", 0); |
| 4315 | if (!gpio_is_valid(ctrl_pdata->rst_gpio)) |
| 4316 | pr_err("%s:%d, reset gpio not specified\n", |
| 4317 | __func__, __LINE__); |
| 4318 | |
| 4319 | if (pinfo->mode_gpio_state != MODE_GPIO_NOT_VALID) { |
| 4320 | |
| 4321 | ctrl_pdata->mode_gpio = of_get_named_gpio( |
| 4322 | ctrl_pdev->dev.of_node, |
| 4323 | "qcom,platform-mode-gpio", 0); |
| 4324 | if (!gpio_is_valid(ctrl_pdata->mode_gpio)) |
| 4325 | pr_info("%s:%d, mode gpio not specified\n", |
| 4326 | __func__, __LINE__); |
| 4327 | } else { |
| 4328 | ctrl_pdata->mode_gpio = -EINVAL; |
| 4329 | } |
| 4330 | |
| 4331 | ctrl_pdata->intf_mux_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node, |
| 4332 | "qcom,platform-intf-mux-gpio", 0); |
| 4333 | if (!gpio_is_valid(ctrl_pdata->intf_mux_gpio)) |
| 4334 | pr_debug("%s:%d, intf mux gpio not specified\n", |
| 4335 | __func__, __LINE__); |
| 4336 | |
| 4337 | return 0; |
| 4338 | } |
| 4339 | |
| 4340 | static void mdss_dsi_set_prim_panel(struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 4341 | { |
| 4342 | struct mdss_dsi_ctrl_pdata *octrl = NULL; |
| 4343 | struct mdss_panel_info *pinfo; |
| 4344 | |
| 4345 | pinfo = &ctrl_pdata->panel_data.panel_info; |
| 4346 | |
| 4347 | /* |
| 4348 | * for Split and Single DSI case default is always primary |
| 4349 | * and for Dual dsi case below assumptions are made. |
| 4350 | * 1. DSI controller with bridge chip is always secondary |
| 4351 | * 2. When there is no brigde chip, DSI1 is secondary |
| 4352 | */ |
| 4353 | pinfo->is_prim_panel = true; |
| 4354 | if (mdss_dsi_is_hw_config_dual(ctrl_pdata->shared_data)) { |
| 4355 | if (mdss_dsi_is_right_ctrl(ctrl_pdata)) { |
| 4356 | octrl = mdss_dsi_get_other_ctrl(ctrl_pdata); |
| 4357 | if (octrl && octrl->panel_data.panel_info.is_prim_panel) |
| 4358 | pinfo->is_prim_panel = false; |
| 4359 | else |
| 4360 | pinfo->is_prim_panel = true; |
| 4361 | } |
| 4362 | } |
| 4363 | } |
| 4364 | |
| 4365 | int dsi_panel_device_register(struct platform_device *ctrl_pdev, |
| 4366 | struct device_node *pan_node, struct mdss_dsi_ctrl_pdata *ctrl_pdata) |
| 4367 | { |
| 4368 | struct mipi_panel_info *mipi; |
| 4369 | int rc; |
| 4370 | struct dsi_shared_data *sdata; |
| 4371 | struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info); |
| 4372 | struct resource *res; |
| 4373 | u64 clk_rate; |
| 4374 | |
| 4375 | mipi = &(pinfo->mipi); |
| 4376 | |
| 4377 | pinfo->type = |
| 4378 | ((mipi->mode == DSI_VIDEO_MODE) |
| 4379 | ? MIPI_VIDEO_PANEL : MIPI_CMD_PANEL); |
| 4380 | |
| 4381 | rc = mdss_dsi_clk_div_config(pinfo, mipi->frame_rate); |
| 4382 | if (rc) { |
| 4383 | pr_err("%s: unable to initialize the clk dividers\n", __func__); |
| 4384 | return rc; |
| 4385 | } |
| 4386 | ctrl_pdata->pclk_rate = mipi->dsi_pclk_rate; |
| 4387 | clk_rate = pinfo->clk_rate; |
| 4388 | do_div(clk_rate, 8U); |
| 4389 | ctrl_pdata->byte_clk_rate = (u32)clk_rate; |
| 4390 | pr_debug("%s: pclk=%d, bclk=%d\n", __func__, |
| 4391 | ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate); |
| 4392 | |
| 4393 | |
| 4394 | rc = mdss_dsi_get_dt_vreg_data(&ctrl_pdev->dev, pan_node, |
| 4395 | &ctrl_pdata->panel_power_data, DSI_PANEL_PM); |
| 4396 | if (rc) { |
| 4397 | DEV_ERR("%s: '%s' get_dt_vreg_data failed.rc=%d\n", |
| 4398 | __func__, __mdss_dsi_pm_name(DSI_PANEL_PM), rc); |
| 4399 | return rc; |
| 4400 | } |
| 4401 | |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4402 | rc = msm_mdss_config_vreg(&ctrl_pdev->dev, |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4403 | ctrl_pdata->panel_power_data.vreg_config, |
| 4404 | ctrl_pdata->panel_power_data.num_vreg, 1); |
| 4405 | if (rc) { |
| 4406 | pr_err("%s: failed to init regulator, rc=%d\n", |
| 4407 | __func__, rc); |
| 4408 | return rc; |
| 4409 | } |
| 4410 | |
| 4411 | rc = mdss_dsi_parse_ctrl_params(ctrl_pdev, pan_node, ctrl_pdata); |
| 4412 | if (rc) { |
| 4413 | pr_err("%s: failed to parse ctrl settings, rc=%d\n", |
| 4414 | __func__, rc); |
| 4415 | return rc; |
| 4416 | } |
| 4417 | |
| 4418 | pinfo->panel_max_fps = mdss_panel_get_framerate(pinfo, |
| 4419 | FPS_RESOLUTION_HZ); |
| 4420 | pinfo->panel_max_vtotal = mdss_panel_get_vtotal(pinfo); |
| 4421 | |
| 4422 | rc = mdss_dsi_parse_gpio_params(ctrl_pdev, ctrl_pdata); |
| 4423 | if (rc) { |
| 4424 | pr_err("%s: failed to parse gpio params, rc=%d\n", |
| 4425 | __func__, rc); |
| 4426 | return rc; |
| 4427 | } |
| 4428 | |
| 4429 | if (mdss_dsi_retrieve_ctrl_resources(ctrl_pdev, |
| 4430 | pinfo->pdest, |
| 4431 | ctrl_pdata)) { |
| 4432 | pr_err("%s: unable to get Dsi controller res\n", __func__); |
| 4433 | return -EPERM; |
| 4434 | } |
| 4435 | |
| 4436 | ctrl_pdata->panel_data.event_handler = mdss_dsi_event_handler; |
| 4437 | ctrl_pdata->panel_data.get_fb_node = mdss_dsi_get_fb_node_cb; |
| 4438 | |
| 4439 | if (ctrl_pdata->status_mode == ESD_REG || |
| 4440 | ctrl_pdata->status_mode == ESD_REG_NT35596) |
| 4441 | ctrl_pdata->check_status = mdss_dsi_reg_status_check; |
| 4442 | else if (ctrl_pdata->status_mode == ESD_BTA) |
| 4443 | ctrl_pdata->check_status = mdss_dsi_bta_status_check; |
| 4444 | |
| 4445 | if (ctrl_pdata->status_mode == ESD_MAX) { |
| 4446 | pr_err("%s: Using default BTA for ESD check\n", __func__); |
| 4447 | ctrl_pdata->check_status = mdss_dsi_bta_status_check; |
| 4448 | } |
| 4449 | if (ctrl_pdata->bklt_ctrl == BL_PWM) |
| 4450 | mdss_dsi_panel_pwm_cfg(ctrl_pdata); |
| 4451 | |
| 4452 | mdss_dsi_ctrl_init(&ctrl_pdev->dev, ctrl_pdata); |
| 4453 | mdss_dsi_set_prim_panel(ctrl_pdata); |
| 4454 | |
| 4455 | ctrl_pdata->dsi_irq_line = of_property_read_bool( |
| 4456 | ctrl_pdev->dev.of_node, "qcom,dsi-irq-line"); |
| 4457 | |
| 4458 | if (ctrl_pdata->dsi_irq_line) { |
| 4459 | /* DSI has it's own irq line */ |
| 4460 | res = platform_get_resource(ctrl_pdev, IORESOURCE_IRQ, 0); |
| 4461 | if (!res || res->start == 0) { |
| 4462 | pr_err("%s:%d unable to get the MDSS irq resources\n", |
| 4463 | __func__, __LINE__); |
| 4464 | return -ENODEV; |
| 4465 | } |
| 4466 | rc = mdss_dsi_irq_init(&ctrl_pdev->dev, res->start, ctrl_pdata); |
| 4467 | if (rc) { |
| 4468 | dev_err(&ctrl_pdev->dev, "%s: failed to init irq\n", |
| 4469 | __func__); |
| 4470 | return rc; |
| 4471 | } |
| 4472 | } |
| 4473 | ctrl_pdata->ctrl_state = CTRL_STATE_UNKNOWN; |
| 4474 | |
| 4475 | /* |
| 4476 | * If ULPS during suspend is enabled, add an extra vote for the |
| 4477 | * DSI CTRL power module. This keeps the regulator always enabled. |
| 4478 | * This is needed for the DSI PHY to maintain ULPS state during |
| 4479 | * suspend also. |
| 4480 | */ |
| 4481 | sdata = ctrl_pdata->shared_data; |
| 4482 | |
| 4483 | if (pinfo->ulps_suspend_enabled) { |
Sachin Bhayare | 5076e25 | 2018-01-18 14:56:45 +0530 | [diff] [blame] | 4484 | rc = msm_mdss_enable_vreg( |
Sachin Bhayare | eeb8889 | 2018-01-02 16:36:01 +0530 | [diff] [blame] | 4485 | sdata->power_data[DSI_PHY_PM].vreg_config, |
| 4486 | sdata->power_data[DSI_PHY_PM].num_vreg, 1); |
| 4487 | if (rc) { |
| 4488 | pr_err("%s: failed to enable vregs for DSI_CTRL_PM\n", |
| 4489 | __func__); |
| 4490 | return rc; |
| 4491 | } |
| 4492 | } |
| 4493 | |
| 4494 | pinfo->cont_splash_enabled = |
| 4495 | ctrl_pdata->mdss_util->panel_intf_status(pinfo->pdest, |
| 4496 | MDSS_PANEL_INTF_DSI) ? true : false; |
| 4497 | |
| 4498 | pr_info("%s: Continuous splash %s\n", __func__, |
| 4499 | pinfo->cont_splash_enabled ? "enabled" : "disabled"); |
| 4500 | |
| 4501 | rc = mdss_register_panel(ctrl_pdev, &(ctrl_pdata->panel_data)); |
| 4502 | if (rc) { |
| 4503 | pr_err("%s: unable to register MIPI DSI panel\n", __func__); |
| 4504 | return rc; |
| 4505 | } |
| 4506 | |
| 4507 | if (pinfo->pdest == DISPLAY_1) { |
| 4508 | mdss_debug_register_io("dsi0_ctrl", &ctrl_pdata->ctrl_io, NULL); |
| 4509 | mdss_debug_register_io("dsi0_phy", &ctrl_pdata->phy_io, NULL); |
| 4510 | if (ctrl_pdata->phy_regulator_io.len) |
| 4511 | mdss_debug_register_io("dsi0_phy_regulator", |
| 4512 | &ctrl_pdata->phy_regulator_io, NULL); |
| 4513 | } else { |
| 4514 | mdss_debug_register_io("dsi1_ctrl", &ctrl_pdata->ctrl_io, NULL); |
| 4515 | mdss_debug_register_io("dsi1_phy", &ctrl_pdata->phy_io, NULL); |
| 4516 | if (ctrl_pdata->phy_regulator_io.len) |
| 4517 | mdss_debug_register_io("dsi1_phy_regulator", |
| 4518 | &ctrl_pdata->phy_regulator_io, NULL); |
| 4519 | } |
| 4520 | |
| 4521 | panel_debug_register_base("panel", |
| 4522 | ctrl_pdata->ctrl_base, ctrl_pdata->reg_size); |
| 4523 | |
| 4524 | pr_debug("%s: Panel data initialized\n", __func__); |
| 4525 | return 0; |
| 4526 | } |
| 4527 | |
| 4528 | static const struct of_device_id mdss_dsi_dt_match[] = { |
| 4529 | {.compatible = "qcom,mdss-dsi"}, |
| 4530 | {} |
| 4531 | }; |
| 4532 | MODULE_DEVICE_TABLE(of, mdss_dsi_dt_match); |
| 4533 | |
| 4534 | static struct platform_driver mdss_dsi_driver = { |
| 4535 | .probe = mdss_dsi_probe, |
| 4536 | .remove = mdss_dsi_remove, |
| 4537 | .shutdown = NULL, |
| 4538 | .driver = { |
| 4539 | .name = "mdss_dsi", |
| 4540 | .of_match_table = mdss_dsi_dt_match, |
| 4541 | }, |
| 4542 | }; |
| 4543 | |
| 4544 | static struct platform_driver mdss_dsi_ctrl_driver = { |
| 4545 | .probe = mdss_dsi_ctrl_probe, |
| 4546 | .remove = mdss_dsi_ctrl_remove, |
| 4547 | .shutdown = NULL, |
| 4548 | .driver = { |
| 4549 | .name = "mdss_dsi_ctrl", |
| 4550 | .of_match_table = mdss_dsi_ctrl_dt_match, |
| 4551 | }, |
| 4552 | }; |
| 4553 | |
| 4554 | static int mdss_dsi_register_driver(void) |
| 4555 | { |
| 4556 | return platform_driver_register(&mdss_dsi_driver); |
| 4557 | } |
| 4558 | |
| 4559 | static int __init mdss_dsi_driver_init(void) |
| 4560 | { |
| 4561 | int ret; |
| 4562 | |
| 4563 | ret = mdss_dsi_register_driver(); |
| 4564 | if (ret) { |
| 4565 | pr_err("mdss_dsi_register_driver() failed!\n"); |
| 4566 | return ret; |
| 4567 | } |
| 4568 | |
| 4569 | return ret; |
| 4570 | } |
| 4571 | module_init(mdss_dsi_driver_init); |
| 4572 | |
| 4573 | |
| 4574 | static int mdss_dsi_ctrl_register_driver(void) |
| 4575 | { |
| 4576 | return platform_driver_register(&mdss_dsi_ctrl_driver); |
| 4577 | } |
| 4578 | |
| 4579 | static int __init mdss_dsi_ctrl_driver_init(void) |
| 4580 | { |
| 4581 | int ret; |
| 4582 | |
| 4583 | ret = mdss_dsi_ctrl_register_driver(); |
| 4584 | if (ret) { |
| 4585 | pr_err("mdss_dsi_ctrl_register_driver() failed!\n"); |
| 4586 | return ret; |
| 4587 | } |
| 4588 | |
| 4589 | return ret; |
| 4590 | } |
| 4591 | module_init(mdss_dsi_ctrl_driver_init); |
| 4592 | |
| 4593 | static void __exit mdss_dsi_driver_cleanup(void) |
| 4594 | { |
| 4595 | platform_driver_unregister(&mdss_dsi_ctrl_driver); |
| 4596 | } |
| 4597 | module_exit(mdss_dsi_driver_cleanup); |
| 4598 | |
| 4599 | MODULE_LICENSE("GPL v2"); |
| 4600 | MODULE_DESCRIPTION("DSI controller driver"); |