Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1 | /* |
| 2 | * DM81xx hwmod data. |
| 3 | * |
| 4 | * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ |
| 5 | * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation version 2. |
| 10 | * |
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 12 | * kind, whether express or implied; without even the implied warranty |
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | */ |
| 17 | |
| 18 | #include <linux/platform_data/gpio-omap.h> |
| 19 | #include <linux/platform_data/hsmmc-omap.h> |
| 20 | #include <linux/platform_data/spi-omap2-mcspi.h> |
| 21 | #include <plat/dmtimer.h> |
| 22 | |
| 23 | #include "omap_hwmod_common_data.h" |
| 24 | #include "cm81xx.h" |
| 25 | #include "ti81xx.h" |
| 26 | #include "wd_timer.h" |
| 27 | |
| 28 | /* |
| 29 | * DM816X hardware modules integration data |
| 30 | * |
| 31 | * Note: This is incomplete and at present, not generated from h/w database. |
| 32 | */ |
| 33 | |
| 34 | /* |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 35 | * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" |
| 36 | * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 37 | */ |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 38 | #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 |
| 39 | #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 |
| 40 | #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 |
| 41 | #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c |
| 42 | #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 |
| 43 | #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 |
| 44 | #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 |
| 45 | #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c |
| 46 | #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 |
| 47 | #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 |
| 48 | #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 |
| 49 | #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c |
| 50 | #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 |
| 51 | #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 |
| 52 | #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 |
| 53 | #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c |
| 54 | #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 |
| 55 | #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 |
| 56 | #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 |
| 57 | #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 |
| 58 | #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 |
| 59 | #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 |
| 60 | #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec |
| 61 | #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 |
| 62 | #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 |
| 63 | #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 |
| 64 | #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc |
| 65 | #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 |
| 66 | #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 |
| 67 | |
| 68 | /* Registers specific to dm814x */ |
| 69 | #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c |
| 70 | #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 |
| 71 | #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 |
| 72 | #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 |
| 73 | #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 |
| 74 | #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 |
| 75 | #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 |
| 76 | #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 |
| 77 | #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 |
| 78 | #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc |
| 79 | #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 |
| 80 | #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 |
| 81 | #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c |
| 82 | #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 |
| 83 | #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 |
| 84 | #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 |
| 85 | |
| 86 | /* Registers specific to dm816x */ |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 87 | #define DM816X_DM_ALWON_BASE 0x1400 |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 88 | #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) |
| 89 | #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) |
| 90 | #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) |
| 91 | #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) |
| 92 | #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) |
| 93 | #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) |
| 94 | #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 95 | #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) |
| 96 | #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) |
| 97 | #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 98 | #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) |
| 99 | #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 100 | #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) |
| 101 | #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) |
| 102 | |
| 103 | /* |
| 104 | * The default .clkctrl_offs field is offset from CM_DEFAULT, that's |
| 105 | * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 |
| 106 | */ |
| 107 | #define DM816X_CM_DEFAULT_OFFSET 0x500 |
| 108 | #define DM816X_CM_DEFAULT_USB_CLKCTRL (0x558 - DM816X_CM_DEFAULT_OFFSET) |
| 109 | |
| 110 | /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 111 | static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 112 | .name = "alwon_l3_slow", |
| 113 | .clkdm_name = "alwon_l3s_clkdm", |
| 114 | .class = &l3_hwmod_class, |
| 115 | .flags = HWMOD_NO_IDLEST, |
| 116 | }; |
| 117 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 118 | static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 119 | .name = "default_l3_slow", |
| 120 | .clkdm_name = "default_l3_slow_clkdm", |
| 121 | .class = &l3_hwmod_class, |
| 122 | .flags = HWMOD_NO_IDLEST, |
| 123 | }; |
| 124 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 125 | static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 126 | .name = "l3_med", |
| 127 | .clkdm_name = "alwon_l3_med_clkdm", |
| 128 | .class = &l3_hwmod_class, |
| 129 | .flags = HWMOD_NO_IDLEST, |
| 130 | }; |
| 131 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 132 | static struct omap_hwmod dm81xx_alwon_l3_fast_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 133 | .name = "l3_fast", |
| 134 | .clkdm_name = "alwon_l3_fast_clkdm", |
| 135 | .class = &l3_hwmod_class, |
| 136 | .flags = HWMOD_NO_IDLEST, |
| 137 | }; |
| 138 | |
| 139 | /* |
| 140 | * L4 standard peripherals, see TRM table 1-12 for devices using this. |
| 141 | * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. |
| 142 | */ |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 143 | static struct omap_hwmod dm81xx_l4_ls_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 144 | .name = "l4_ls", |
| 145 | .clkdm_name = "alwon_l3s_clkdm", |
| 146 | .class = &l4_hwmod_class, |
| 147 | }; |
| 148 | |
| 149 | /* |
| 150 | * L4 high-speed peripherals. For devices using this, please see the TRM |
| 151 | * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM |
| 152 | * table 1-73 for devices using 250MHz SYSCLK5 clock. |
| 153 | */ |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 154 | static struct omap_hwmod dm81xx_l4_hs_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 155 | .name = "l4_hs", |
| 156 | .clkdm_name = "alwon_l3_med_clkdm", |
| 157 | .class = &l4_hwmod_class, |
| 158 | }; |
| 159 | |
| 160 | /* L3 slow -> L4 ls peripheral interface running at 125MHz */ |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 161 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { |
| 162 | .master = &dm81xx_alwon_l3_slow_hwmod, |
| 163 | .slave = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 164 | .user = OCP_USER_MPU, |
| 165 | }; |
| 166 | |
| 167 | /* L3 med -> L4 fast peripheral interface running at 250MHz */ |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 168 | static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { |
| 169 | .master = &dm81xx_alwon_l3_med_hwmod, |
| 170 | .slave = &dm81xx_l4_hs_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 171 | .user = OCP_USER_MPU, |
| 172 | }; |
| 173 | |
| 174 | /* MPU */ |
| 175 | static struct omap_hwmod dm816x_mpu_hwmod = { |
| 176 | .name = "mpu", |
| 177 | .clkdm_name = "alwon_mpu_clkdm", |
| 178 | .class = &mpu_hwmod_class, |
| 179 | .flags = HWMOD_INIT_NO_IDLE, |
| 180 | .main_clk = "mpu_ck", |
| 181 | .prcm = { |
| 182 | .omap4 = { |
| 183 | .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, |
| 184 | .modulemode = MODULEMODE_SWCTRL, |
| 185 | }, |
| 186 | }, |
| 187 | }; |
| 188 | |
| 189 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { |
| 190 | .master = &dm816x_mpu_hwmod, |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 191 | .slave = &dm81xx_alwon_l3_slow_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 192 | .user = OCP_USER_MPU, |
| 193 | }; |
| 194 | |
| 195 | /* L3 med peripheral interface running at 250MHz */ |
| 196 | static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { |
| 197 | .master = &dm816x_mpu_hwmod, |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 198 | .slave = &dm81xx_alwon_l3_med_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 199 | .user = OCP_USER_MPU, |
| 200 | }; |
| 201 | |
| 202 | /* UART common */ |
| 203 | static struct omap_hwmod_class_sysconfig uart_sysc = { |
| 204 | .rev_offs = 0x50, |
| 205 | .sysc_offs = 0x54, |
| 206 | .syss_offs = 0x58, |
| 207 | .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 208 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 209 | SYSS_HAS_RESET_STATUS, |
| 210 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 211 | MSTANDBY_SMART_WKUP, |
| 212 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 213 | }; |
| 214 | |
| 215 | static struct omap_hwmod_class uart_class = { |
| 216 | .name = "uart", |
| 217 | .sysc = &uart_sysc, |
| 218 | }; |
| 219 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 220 | static struct omap_hwmod dm81xx_uart1_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 221 | .name = "uart1", |
| 222 | .clkdm_name = "alwon_l3s_clkdm", |
| 223 | .main_clk = "sysclk10_ck", |
| 224 | .prcm = { |
| 225 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 226 | .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 227 | .modulemode = MODULEMODE_SWCTRL, |
| 228 | }, |
| 229 | }, |
| 230 | .class = &uart_class, |
| 231 | .flags = DEBUG_TI81XXUART1_FLAGS, |
| 232 | }; |
| 233 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 234 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { |
| 235 | .master = &dm81xx_l4_ls_hwmod, |
| 236 | .slave = &dm81xx_uart1_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 237 | .clk = "sysclk6_ck", |
| 238 | .user = OCP_USER_MPU, |
| 239 | }; |
| 240 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 241 | static struct omap_hwmod dm81xx_uart2_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 242 | .name = "uart2", |
| 243 | .clkdm_name = "alwon_l3s_clkdm", |
| 244 | .main_clk = "sysclk10_ck", |
| 245 | .prcm = { |
| 246 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 247 | .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 248 | .modulemode = MODULEMODE_SWCTRL, |
| 249 | }, |
| 250 | }, |
| 251 | .class = &uart_class, |
| 252 | .flags = DEBUG_TI81XXUART2_FLAGS, |
| 253 | }; |
| 254 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 255 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { |
| 256 | .master = &dm81xx_l4_ls_hwmod, |
| 257 | .slave = &dm81xx_uart2_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 258 | .clk = "sysclk6_ck", |
| 259 | .user = OCP_USER_MPU, |
| 260 | }; |
| 261 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 262 | static struct omap_hwmod dm81xx_uart3_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 263 | .name = "uart3", |
| 264 | .clkdm_name = "alwon_l3s_clkdm", |
| 265 | .main_clk = "sysclk10_ck", |
| 266 | .prcm = { |
| 267 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 268 | .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 269 | .modulemode = MODULEMODE_SWCTRL, |
| 270 | }, |
| 271 | }, |
| 272 | .class = &uart_class, |
| 273 | .flags = DEBUG_TI81XXUART3_FLAGS, |
| 274 | }; |
| 275 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 276 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { |
| 277 | .master = &dm81xx_l4_ls_hwmod, |
| 278 | .slave = &dm81xx_uart3_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 279 | .clk = "sysclk6_ck", |
| 280 | .user = OCP_USER_MPU, |
| 281 | }; |
| 282 | |
| 283 | static struct omap_hwmod_class_sysconfig wd_timer_sysc = { |
| 284 | .rev_offs = 0x0, |
| 285 | .sysc_offs = 0x10, |
| 286 | .syss_offs = 0x14, |
| 287 | .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 288 | SYSS_HAS_RESET_STATUS, |
| 289 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 290 | }; |
| 291 | |
| 292 | static struct omap_hwmod_class wd_timer_class = { |
| 293 | .name = "wd_timer", |
| 294 | .sysc = &wd_timer_sysc, |
| 295 | .pre_shutdown = &omap2_wd_timer_disable, |
| 296 | .reset = &omap2_wd_timer_reset, |
| 297 | }; |
| 298 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 299 | static struct omap_hwmod dm81xx_wd_timer_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 300 | .name = "wd_timer", |
| 301 | .clkdm_name = "alwon_l3s_clkdm", |
| 302 | .main_clk = "sysclk18_ck", |
| 303 | .flags = HWMOD_NO_IDLEST, |
| 304 | .prcm = { |
| 305 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 306 | .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 307 | .modulemode = MODULEMODE_SWCTRL, |
| 308 | }, |
| 309 | }, |
| 310 | .class = &wd_timer_class, |
| 311 | }; |
| 312 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 313 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { |
| 314 | .master = &dm81xx_l4_ls_hwmod, |
| 315 | .slave = &dm81xx_wd_timer_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 316 | .clk = "sysclk6_ck", |
| 317 | .user = OCP_USER_MPU, |
| 318 | }; |
| 319 | |
| 320 | /* I2C common */ |
| 321 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 322 | .rev_offs = 0x0, |
| 323 | .sysc_offs = 0x10, |
| 324 | .syss_offs = 0x90, |
| 325 | .sysc_flags = SYSC_HAS_SIDLEMODE | |
| 326 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 327 | SYSC_HAS_AUTOIDLE, |
| 328 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
| 329 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 330 | }; |
| 331 | |
| 332 | static struct omap_hwmod_class i2c_class = { |
| 333 | .name = "i2c", |
| 334 | .sysc = &i2c_sysc, |
| 335 | }; |
| 336 | |
| 337 | static struct omap_hwmod dm81xx_i2c1_hwmod = { |
| 338 | .name = "i2c1", |
| 339 | .clkdm_name = "alwon_l3s_clkdm", |
| 340 | .main_clk = "sysclk10_ck", |
| 341 | .prcm = { |
| 342 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 343 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 344 | .modulemode = MODULEMODE_SWCTRL, |
| 345 | }, |
| 346 | }, |
| 347 | .class = &i2c_class, |
| 348 | }; |
| 349 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 350 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { |
| 351 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 352 | .slave = &dm81xx_i2c1_hwmod, |
| 353 | .clk = "sysclk6_ck", |
| 354 | .user = OCP_USER_MPU, |
| 355 | }; |
| 356 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 357 | static struct omap_hwmod dm81xx_i2c2_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 358 | .name = "i2c2", |
| 359 | .clkdm_name = "alwon_l3s_clkdm", |
| 360 | .main_clk = "sysclk10_ck", |
| 361 | .prcm = { |
| 362 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 363 | .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 364 | .modulemode = MODULEMODE_SWCTRL, |
| 365 | }, |
| 366 | }, |
| 367 | .class = &i2c_class, |
| 368 | }; |
| 369 | |
| 370 | static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { |
| 371 | .rev_offs = 0x0000, |
| 372 | .sysc_offs = 0x0010, |
| 373 | .syss_offs = 0x0014, |
| 374 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 375 | SYSC_HAS_SOFTRESET | |
| 376 | SYSS_HAS_RESET_STATUS, |
| 377 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
| 378 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 379 | }; |
| 380 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 381 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { |
| 382 | .master = &dm81xx_l4_ls_hwmod, |
| 383 | .slave = &dm81xx_i2c2_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 384 | .clk = "sysclk6_ck", |
| 385 | .user = OCP_USER_MPU, |
| 386 | }; |
| 387 | |
| 388 | static struct omap_hwmod_class dm81xx_elm_hwmod_class = { |
| 389 | .name = "elm", |
| 390 | .sysc = &dm81xx_elm_sysc, |
| 391 | }; |
| 392 | |
| 393 | static struct omap_hwmod dm81xx_elm_hwmod = { |
| 394 | .name = "elm", |
| 395 | .clkdm_name = "alwon_l3s_clkdm", |
| 396 | .class = &dm81xx_elm_hwmod_class, |
| 397 | .main_clk = "sysclk6_ck", |
| 398 | }; |
| 399 | |
| 400 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 401 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 402 | .slave = &dm81xx_elm_hwmod, |
| 403 | .user = OCP_USER_MPU, |
| 404 | }; |
| 405 | |
| 406 | static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { |
| 407 | .rev_offs = 0x0000, |
| 408 | .sysc_offs = 0x0010, |
| 409 | .syss_offs = 0x0114, |
| 410 | .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
| 411 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 412 | SYSS_HAS_RESET_STATUS, |
| 413 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 414 | SIDLE_SMART_WKUP, |
| 415 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 416 | }; |
| 417 | |
| 418 | static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { |
| 419 | .name = "gpio", |
| 420 | .sysc = &dm81xx_gpio_sysc, |
| 421 | .rev = 2, |
| 422 | }; |
| 423 | |
| 424 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
| 425 | .bank_width = 32, |
| 426 | .dbck_flag = true, |
| 427 | }; |
| 428 | |
| 429 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
| 430 | { .role = "dbclk", .clk = "sysclk18_ck" }, |
| 431 | }; |
| 432 | |
| 433 | static struct omap_hwmod dm81xx_gpio1_hwmod = { |
| 434 | .name = "gpio1", |
| 435 | .clkdm_name = "alwon_l3s_clkdm", |
| 436 | .class = &dm81xx_gpio_hwmod_class, |
| 437 | .main_clk = "sysclk6_ck", |
| 438 | .prcm = { |
| 439 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 440 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 441 | .modulemode = MODULEMODE_SWCTRL, |
| 442 | }, |
| 443 | }, |
| 444 | .opt_clks = gpio1_opt_clks, |
| 445 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), |
| 446 | .dev_attr = &gpio_dev_attr, |
| 447 | }; |
| 448 | |
| 449 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 450 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 451 | .slave = &dm81xx_gpio1_hwmod, |
| 452 | .user = OCP_USER_MPU, |
| 453 | }; |
| 454 | |
| 455 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
| 456 | { .role = "dbclk", .clk = "sysclk18_ck" }, |
| 457 | }; |
| 458 | |
| 459 | static struct omap_hwmod dm81xx_gpio2_hwmod = { |
| 460 | .name = "gpio2", |
| 461 | .clkdm_name = "alwon_l3s_clkdm", |
| 462 | .class = &dm81xx_gpio_hwmod_class, |
| 463 | .main_clk = "sysclk6_ck", |
| 464 | .prcm = { |
| 465 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 466 | .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 467 | .modulemode = MODULEMODE_SWCTRL, |
| 468 | }, |
| 469 | }, |
| 470 | .opt_clks = gpio2_opt_clks, |
| 471 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), |
| 472 | .dev_attr = &gpio_dev_attr, |
| 473 | }; |
| 474 | |
| 475 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 476 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 477 | .slave = &dm81xx_gpio2_hwmod, |
| 478 | .user = OCP_USER_MPU, |
| 479 | }; |
| 480 | |
| 481 | static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { |
| 482 | .rev_offs = 0x0, |
| 483 | .sysc_offs = 0x10, |
| 484 | .syss_offs = 0x14, |
| 485 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 486 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, |
| 487 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
| 488 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 489 | }; |
| 490 | |
| 491 | static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { |
| 492 | .name = "gpmc", |
| 493 | .sysc = &dm81xx_gpmc_sysc, |
| 494 | }; |
| 495 | |
| 496 | static struct omap_hwmod dm81xx_gpmc_hwmod = { |
| 497 | .name = "gpmc", |
| 498 | .clkdm_name = "alwon_l3s_clkdm", |
| 499 | .class = &dm81xx_gpmc_hwmod_class, |
| 500 | .main_clk = "sysclk6_ck", |
Tony Lindgren | 63aa945 | 2015-06-01 19:22:10 -0600 | [diff] [blame] | 501 | /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
| 502 | .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 503 | .prcm = { |
| 504 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 505 | .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 506 | .modulemode = MODULEMODE_SWCTRL, |
| 507 | }, |
| 508 | }, |
| 509 | }; |
| 510 | |
| 511 | struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 512 | .master = &dm81xx_alwon_l3_slow_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 513 | .slave = &dm81xx_gpmc_hwmod, |
| 514 | .user = OCP_USER_MPU, |
| 515 | }; |
| 516 | |
| 517 | static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { |
| 518 | .rev_offs = 0x0, |
| 519 | .sysc_offs = 0x10, |
| 520 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
| 521 | SYSC_HAS_SOFTRESET, |
| 522 | .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, |
| 523 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 524 | }; |
| 525 | |
| 526 | static struct omap_hwmod_class dm81xx_usbotg_class = { |
| 527 | .name = "usbotg", |
| 528 | .sysc = &dm81xx_usbhsotg_sysc, |
| 529 | }; |
| 530 | |
| 531 | static struct omap_hwmod dm81xx_usbss_hwmod = { |
| 532 | .name = "usb_otg_hs", |
| 533 | .clkdm_name = "default_l3_slow_clkdm", |
| 534 | .main_clk = "sysclk6_ck", |
| 535 | .prcm = { |
| 536 | .omap4 = { |
| 537 | .clkctrl_offs = DM816X_CM_DEFAULT_USB_CLKCTRL, |
| 538 | .modulemode = MODULEMODE_SWCTRL, |
| 539 | }, |
| 540 | }, |
| 541 | .class = &dm81xx_usbotg_class, |
| 542 | }; |
| 543 | |
| 544 | static struct omap_hwmod_ocp_if dm81xx_default_l3_slow__usbss = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 545 | .master = &dm81xx_default_l3_slow_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 546 | .slave = &dm81xx_usbss_hwmod, |
| 547 | .clk = "sysclk6_ck", |
| 548 | .user = OCP_USER_MPU, |
| 549 | }; |
| 550 | |
| 551 | static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { |
| 552 | .rev_offs = 0x0000, |
| 553 | .sysc_offs = 0x0010, |
| 554 | .syss_offs = 0x0014, |
| 555 | .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, |
| 556 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 557 | SIDLE_SMART_WKUP, |
| 558 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 559 | }; |
| 560 | |
| 561 | static struct omap_hwmod_class dm816x_timer_hwmod_class = { |
| 562 | .name = "timer", |
| 563 | .sysc = &dm816x_timer_sysc, |
| 564 | }; |
| 565 | |
| 566 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { |
| 567 | .timer_capability = OMAP_TIMER_ALWON, |
| 568 | }; |
| 569 | |
| 570 | static struct omap_hwmod dm816x_timer1_hwmod = { |
| 571 | .name = "timer1", |
| 572 | .clkdm_name = "alwon_l3s_clkdm", |
| 573 | .main_clk = "timer1_fck", |
| 574 | .prcm = { |
| 575 | .omap4 = { |
| 576 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, |
| 577 | .modulemode = MODULEMODE_SWCTRL, |
| 578 | }, |
| 579 | }, |
| 580 | .dev_attr = &capability_alwon_dev_attr, |
| 581 | .class = &dm816x_timer_hwmod_class, |
| 582 | }; |
| 583 | |
| 584 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 585 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 586 | .slave = &dm816x_timer1_hwmod, |
| 587 | .clk = "sysclk6_ck", |
| 588 | .user = OCP_USER_MPU, |
| 589 | }; |
| 590 | |
| 591 | static struct omap_hwmod dm816x_timer2_hwmod = { |
| 592 | .name = "timer2", |
| 593 | .clkdm_name = "alwon_l3s_clkdm", |
| 594 | .main_clk = "timer2_fck", |
| 595 | .prcm = { |
| 596 | .omap4 = { |
| 597 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, |
| 598 | .modulemode = MODULEMODE_SWCTRL, |
| 599 | }, |
| 600 | }, |
| 601 | .dev_attr = &capability_alwon_dev_attr, |
| 602 | .class = &dm816x_timer_hwmod_class, |
| 603 | }; |
| 604 | |
| 605 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 606 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 607 | .slave = &dm816x_timer2_hwmod, |
| 608 | .clk = "sysclk6_ck", |
| 609 | .user = OCP_USER_MPU, |
| 610 | }; |
| 611 | |
| 612 | static struct omap_hwmod dm816x_timer3_hwmod = { |
| 613 | .name = "timer3", |
| 614 | .clkdm_name = "alwon_l3s_clkdm", |
| 615 | .main_clk = "timer3_fck", |
| 616 | .prcm = { |
| 617 | .omap4 = { |
| 618 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, |
| 619 | .modulemode = MODULEMODE_SWCTRL, |
| 620 | }, |
| 621 | }, |
| 622 | .dev_attr = &capability_alwon_dev_attr, |
| 623 | .class = &dm816x_timer_hwmod_class, |
| 624 | }; |
| 625 | |
| 626 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 627 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 628 | .slave = &dm816x_timer3_hwmod, |
| 629 | .clk = "sysclk6_ck", |
| 630 | .user = OCP_USER_MPU, |
| 631 | }; |
| 632 | |
| 633 | static struct omap_hwmod dm816x_timer4_hwmod = { |
| 634 | .name = "timer4", |
| 635 | .clkdm_name = "alwon_l3s_clkdm", |
| 636 | .main_clk = "timer4_fck", |
| 637 | .prcm = { |
| 638 | .omap4 = { |
| 639 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, |
| 640 | .modulemode = MODULEMODE_SWCTRL, |
| 641 | }, |
| 642 | }, |
| 643 | .dev_attr = &capability_alwon_dev_attr, |
| 644 | .class = &dm816x_timer_hwmod_class, |
| 645 | }; |
| 646 | |
| 647 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 648 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 649 | .slave = &dm816x_timer4_hwmod, |
| 650 | .clk = "sysclk6_ck", |
| 651 | .user = OCP_USER_MPU, |
| 652 | }; |
| 653 | |
| 654 | static struct omap_hwmod dm816x_timer5_hwmod = { |
| 655 | .name = "timer5", |
| 656 | .clkdm_name = "alwon_l3s_clkdm", |
| 657 | .main_clk = "timer5_fck", |
| 658 | .prcm = { |
| 659 | .omap4 = { |
| 660 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, |
| 661 | .modulemode = MODULEMODE_SWCTRL, |
| 662 | }, |
| 663 | }, |
| 664 | .dev_attr = &capability_alwon_dev_attr, |
| 665 | .class = &dm816x_timer_hwmod_class, |
| 666 | }; |
| 667 | |
| 668 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 669 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 670 | .slave = &dm816x_timer5_hwmod, |
| 671 | .clk = "sysclk6_ck", |
| 672 | .user = OCP_USER_MPU, |
| 673 | }; |
| 674 | |
| 675 | static struct omap_hwmod dm816x_timer6_hwmod = { |
| 676 | .name = "timer6", |
| 677 | .clkdm_name = "alwon_l3s_clkdm", |
| 678 | .main_clk = "timer6_fck", |
| 679 | .prcm = { |
| 680 | .omap4 = { |
| 681 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, |
| 682 | .modulemode = MODULEMODE_SWCTRL, |
| 683 | }, |
| 684 | }, |
| 685 | .dev_attr = &capability_alwon_dev_attr, |
| 686 | .class = &dm816x_timer_hwmod_class, |
| 687 | }; |
| 688 | |
| 689 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 690 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 691 | .slave = &dm816x_timer6_hwmod, |
| 692 | .clk = "sysclk6_ck", |
| 693 | .user = OCP_USER_MPU, |
| 694 | }; |
| 695 | |
| 696 | static struct omap_hwmod dm816x_timer7_hwmod = { |
| 697 | .name = "timer7", |
| 698 | .clkdm_name = "alwon_l3s_clkdm", |
| 699 | .main_clk = "timer7_fck", |
| 700 | .prcm = { |
| 701 | .omap4 = { |
| 702 | .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, |
| 703 | .modulemode = MODULEMODE_SWCTRL, |
| 704 | }, |
| 705 | }, |
| 706 | .dev_attr = &capability_alwon_dev_attr, |
| 707 | .class = &dm816x_timer_hwmod_class, |
| 708 | }; |
| 709 | |
| 710 | static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 711 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 712 | .slave = &dm816x_timer7_hwmod, |
| 713 | .clk = "sysclk6_ck", |
| 714 | .user = OCP_USER_MPU, |
| 715 | }; |
| 716 | |
| 717 | /* EMAC Ethernet */ |
| 718 | static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { |
| 719 | .rev_offs = 0x0, |
| 720 | .sysc_offs = 0x4, |
| 721 | .sysc_flags = SYSC_HAS_SOFTRESET, |
| 722 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 723 | }; |
| 724 | |
| 725 | static struct omap_hwmod_class dm816x_emac_hwmod_class = { |
| 726 | .name = "emac", |
| 727 | .sysc = &dm816x_emac_sysc, |
| 728 | }; |
| 729 | |
| 730 | /* |
| 731 | * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate |
| 732 | * driver probed before EMAC0, we let MDIO do the clock idling. |
| 733 | */ |
| 734 | static struct omap_hwmod dm816x_emac0_hwmod = { |
| 735 | .name = "emac0", |
| 736 | .clkdm_name = "alwon_ethernet_clkdm", |
| 737 | .class = &dm816x_emac_hwmod_class, |
| 738 | }; |
| 739 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 740 | static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { |
| 741 | .master = &dm81xx_l4_hs_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 742 | .slave = &dm816x_emac0_hwmod, |
| 743 | .clk = "sysclk5_ck", |
| 744 | .user = OCP_USER_MPU, |
| 745 | }; |
| 746 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 747 | static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 748 | .name = "davinci_mdio", |
| 749 | .sysc = &dm816x_emac_sysc, |
| 750 | }; |
| 751 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 752 | struct omap_hwmod dm81xx_emac0_mdio_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 753 | .name = "davinci_mdio", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 754 | .class = &dm81xx_mdio_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 755 | .clkdm_name = "alwon_ethernet_clkdm", |
| 756 | .main_clk = "sysclk24_ck", |
| 757 | .flags = HWMOD_NO_IDLEST, |
| 758 | /* |
| 759 | * REVISIT: This should be moved to the emac0_hwmod |
| 760 | * once we have a better way to handle device slaves. |
| 761 | */ |
| 762 | .prcm = { |
| 763 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 764 | .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 765 | .modulemode = MODULEMODE_SWCTRL, |
| 766 | }, |
| 767 | }, |
| 768 | }; |
| 769 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 770 | struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { |
| 771 | .master = &dm81xx_l4_hs_hwmod, |
| 772 | .slave = &dm81xx_emac0_mdio_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 773 | .user = OCP_USER_MPU, |
| 774 | }; |
| 775 | |
| 776 | static struct omap_hwmod dm816x_emac1_hwmod = { |
| 777 | .name = "emac1", |
| 778 | .clkdm_name = "alwon_ethernet_clkdm", |
| 779 | .main_clk = "sysclk24_ck", |
| 780 | .flags = HWMOD_NO_IDLEST, |
| 781 | .prcm = { |
| 782 | .omap4 = { |
| 783 | .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, |
| 784 | .modulemode = MODULEMODE_SWCTRL, |
| 785 | }, |
| 786 | }, |
| 787 | .class = &dm816x_emac_hwmod_class, |
| 788 | }; |
| 789 | |
| 790 | static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 791 | .master = &dm81xx_l4_hs_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 792 | .slave = &dm816x_emac1_hwmod, |
| 793 | .clk = "sysclk5_ck", |
| 794 | .user = OCP_USER_MPU, |
| 795 | }; |
| 796 | |
| 797 | static struct omap_hwmod_class_sysconfig dm816x_mmc_sysc = { |
| 798 | .rev_offs = 0x0, |
| 799 | .sysc_offs = 0x110, |
| 800 | .syss_offs = 0x114, |
| 801 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 802 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 803 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, |
| 804 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
| 805 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 806 | }; |
| 807 | |
| 808 | static struct omap_hwmod_class dm816x_mmc_class = { |
| 809 | .name = "mmc", |
| 810 | .sysc = &dm816x_mmc_sysc, |
| 811 | }; |
| 812 | |
| 813 | static struct omap_hwmod_opt_clk dm816x_mmc1_opt_clks[] = { |
| 814 | { .role = "dbck", .clk = "sysclk18_ck", }, |
| 815 | }; |
| 816 | |
| 817 | static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
| 818 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 819 | }; |
| 820 | |
| 821 | static struct omap_hwmod dm816x_mmc1_hwmod = { |
| 822 | .name = "mmc1", |
| 823 | .clkdm_name = "alwon_l3s_clkdm", |
| 824 | .opt_clks = dm816x_mmc1_opt_clks, |
| 825 | .opt_clks_cnt = ARRAY_SIZE(dm816x_mmc1_opt_clks), |
| 826 | .main_clk = "sysclk10_ck", |
| 827 | .prcm = { |
| 828 | .omap4 = { |
| 829 | .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, |
| 830 | .modulemode = MODULEMODE_SWCTRL, |
| 831 | }, |
| 832 | }, |
| 833 | .dev_attr = &mmc1_dev_attr, |
| 834 | .class = &dm816x_mmc_class, |
| 835 | }; |
| 836 | |
| 837 | static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 838 | .master = &dm81xx_l4_ls_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 839 | .slave = &dm816x_mmc1_hwmod, |
| 840 | .clk = "sysclk6_ck", |
| 841 | .user = OCP_USER_MPU, |
| 842 | .flags = OMAP_FIREWALL_L4 |
| 843 | }; |
| 844 | |
| 845 | static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { |
| 846 | .rev_offs = 0x0, |
| 847 | .sysc_offs = 0x110, |
| 848 | .syss_offs = 0x114, |
| 849 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 850 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 851 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, |
| 852 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
| 853 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 854 | }; |
| 855 | |
| 856 | static struct omap_hwmod_class dm816x_mcspi_class = { |
| 857 | .name = "mcspi", |
| 858 | .sysc = &dm816x_mcspi_sysc, |
| 859 | .rev = OMAP3_MCSPI_REV, |
| 860 | }; |
| 861 | |
| 862 | static struct omap2_mcspi_dev_attr dm816x_mcspi1_dev_attr = { |
| 863 | .num_chipselect = 4, |
| 864 | }; |
| 865 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 866 | static struct omap_hwmod dm81xx_mcspi1_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 867 | .name = "mcspi1", |
| 868 | .clkdm_name = "alwon_l3s_clkdm", |
| 869 | .main_clk = "sysclk10_ck", |
| 870 | .prcm = { |
| 871 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 872 | .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 873 | .modulemode = MODULEMODE_SWCTRL, |
| 874 | }, |
| 875 | }, |
| 876 | .class = &dm816x_mcspi_class, |
| 877 | .dev_attr = &dm816x_mcspi1_dev_attr, |
| 878 | }; |
| 879 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 880 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { |
| 881 | .master = &dm81xx_l4_ls_hwmod, |
| 882 | .slave = &dm81xx_mcspi1_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 883 | .clk = "sysclk6_ck", |
| 884 | .user = OCP_USER_MPU, |
| 885 | }; |
| 886 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 887 | static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 888 | .rev_offs = 0x000, |
| 889 | .sysc_offs = 0x010, |
| 890 | .syss_offs = 0x014, |
| 891 | .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 892 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, |
| 893 | .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, |
| 894 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 895 | }; |
| 896 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 897 | static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 898 | .name = "mailbox", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 899 | .sysc = &dm81xx_mailbox_sysc, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 900 | }; |
| 901 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 902 | static struct omap_hwmod dm81xx_mailbox_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 903 | .name = "mailbox", |
| 904 | .clkdm_name = "alwon_l3s_clkdm", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 905 | .class = &dm81xx_mailbox_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 906 | .main_clk = "sysclk6_ck", |
| 907 | .prcm = { |
| 908 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 909 | .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 910 | .modulemode = MODULEMODE_SWCTRL, |
| 911 | }, |
| 912 | }, |
| 913 | }; |
| 914 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 915 | static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { |
| 916 | .master = &dm81xx_l4_ls_hwmod, |
| 917 | .slave = &dm81xx_mailbox_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 918 | .user = OCP_USER_MPU, |
| 919 | }; |
| 920 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 921 | static struct omap_hwmod_class dm81xx_tpcc_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 922 | .name = "tpcc", |
| 923 | }; |
| 924 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 925 | struct omap_hwmod dm81xx_tpcc_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 926 | .name = "tpcc", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 927 | .class = &dm81xx_tpcc_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 928 | .clkdm_name = "alwon_l3s_clkdm", |
| 929 | .main_clk = "sysclk4_ck", |
| 930 | .prcm = { |
| 931 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 932 | .clkctrl_offs = DM81XX_CM_ALWON_TPCC_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 933 | .modulemode = MODULEMODE_SWCTRL, |
| 934 | }, |
| 935 | }, |
| 936 | }; |
| 937 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 938 | struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tpcc = { |
| 939 | .master = &dm81xx_alwon_l3_fast_hwmod, |
| 940 | .slave = &dm81xx_tpcc_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 941 | .clk = "sysclk4_ck", |
| 942 | .user = OCP_USER_MPU, |
| 943 | }; |
| 944 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 945 | static struct omap_hwmod_addr_space dm81xx_tptc0_addr_space[] = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 946 | { |
| 947 | .pa_start = 0x49800000, |
| 948 | .pa_end = 0x49800000 + SZ_8K - 1, |
| 949 | .flags = ADDR_TYPE_RT, |
| 950 | }, |
| 951 | { }, |
| 952 | }; |
| 953 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 954 | static struct omap_hwmod_class dm81xx_tptc0_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 955 | .name = "tptc0", |
| 956 | }; |
| 957 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 958 | struct omap_hwmod dm81xx_tptc0_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 959 | .name = "tptc0", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 960 | .class = &dm81xx_tptc0_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 961 | .clkdm_name = "alwon_l3s_clkdm", |
| 962 | .main_clk = "sysclk4_ck", |
| 963 | .prcm = { |
| 964 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 965 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC0_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 966 | .modulemode = MODULEMODE_SWCTRL, |
| 967 | }, |
| 968 | }, |
| 969 | }; |
| 970 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 971 | struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc0 = { |
| 972 | .master = &dm81xx_alwon_l3_fast_hwmod, |
| 973 | .slave = &dm81xx_tptc0_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 974 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 975 | .addr = dm81xx_tptc0_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 976 | .user = OCP_USER_MPU, |
| 977 | }; |
| 978 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 979 | struct omap_hwmod_ocp_if dm81xx_tptc0__alwon_l3_fast = { |
| 980 | .master = &dm81xx_tptc0_hwmod, |
| 981 | .slave = &dm81xx_alwon_l3_fast_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 982 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 983 | .addr = dm81xx_tptc0_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 984 | .user = OCP_USER_MPU, |
| 985 | }; |
| 986 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 987 | static struct omap_hwmod_addr_space dm81xx_tptc1_addr_space[] = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 988 | { |
| 989 | .pa_start = 0x49900000, |
| 990 | .pa_end = 0x49900000 + SZ_8K - 1, |
| 991 | .flags = ADDR_TYPE_RT, |
| 992 | }, |
| 993 | { }, |
| 994 | }; |
| 995 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 996 | static struct omap_hwmod_class dm81xx_tptc1_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 997 | .name = "tptc1", |
| 998 | }; |
| 999 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1000 | struct omap_hwmod dm81xx_tptc1_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1001 | .name = "tptc1", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1002 | .class = &dm81xx_tptc1_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1003 | .clkdm_name = "alwon_l3s_clkdm", |
| 1004 | .main_clk = "sysclk4_ck", |
| 1005 | .prcm = { |
| 1006 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1007 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC1_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1008 | .modulemode = MODULEMODE_SWCTRL, |
| 1009 | }, |
| 1010 | }, |
| 1011 | }; |
| 1012 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1013 | struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc1 = { |
| 1014 | .master = &dm81xx_alwon_l3_fast_hwmod, |
| 1015 | .slave = &dm81xx_tptc1_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1016 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1017 | .addr = dm81xx_tptc1_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1018 | .user = OCP_USER_MPU, |
| 1019 | }; |
| 1020 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1021 | struct omap_hwmod_ocp_if dm81xx_tptc1__alwon_l3_fast = { |
| 1022 | .master = &dm81xx_tptc1_hwmod, |
| 1023 | .slave = &dm81xx_alwon_l3_fast_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1024 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1025 | .addr = dm81xx_tptc1_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1026 | .user = OCP_USER_MPU, |
| 1027 | }; |
| 1028 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1029 | static struct omap_hwmod_addr_space dm81xx_tptc2_addr_space[] = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1030 | { |
| 1031 | .pa_start = 0x49a00000, |
| 1032 | .pa_end = 0x49a00000 + SZ_8K - 1, |
| 1033 | .flags = ADDR_TYPE_RT, |
| 1034 | }, |
| 1035 | { }, |
| 1036 | }; |
| 1037 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1038 | static struct omap_hwmod_class dm81xx_tptc2_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1039 | .name = "tptc2", |
| 1040 | }; |
| 1041 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1042 | struct omap_hwmod dm81xx_tptc2_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1043 | .name = "tptc2", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1044 | .class = &dm81xx_tptc2_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1045 | .clkdm_name = "alwon_l3s_clkdm", |
| 1046 | .main_clk = "sysclk4_ck", |
| 1047 | .prcm = { |
| 1048 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1049 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC2_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1050 | .modulemode = MODULEMODE_SWCTRL, |
| 1051 | }, |
| 1052 | }, |
| 1053 | }; |
| 1054 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1055 | struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc2 = { |
| 1056 | .master = &dm81xx_alwon_l3_fast_hwmod, |
| 1057 | .slave = &dm81xx_tptc2_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1058 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1059 | .addr = dm81xx_tptc2_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1060 | .user = OCP_USER_MPU, |
| 1061 | }; |
| 1062 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1063 | struct omap_hwmod_ocp_if dm81xx_tptc2__alwon_l3_fast = { |
| 1064 | .master = &dm81xx_tptc2_hwmod, |
| 1065 | .slave = &dm81xx_alwon_l3_fast_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1066 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1067 | .addr = dm81xx_tptc2_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1068 | .user = OCP_USER_MPU, |
| 1069 | }; |
| 1070 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1071 | static struct omap_hwmod_addr_space dm81xx_tptc3_addr_space[] = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1072 | { |
| 1073 | .pa_start = 0x49b00000, |
| 1074 | .pa_end = 0x49b00000 + SZ_8K - 1, |
| 1075 | .flags = ADDR_TYPE_RT, |
| 1076 | }, |
| 1077 | { }, |
| 1078 | }; |
| 1079 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1080 | static struct omap_hwmod_class dm81xx_tptc3_hwmod_class = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1081 | .name = "tptc3", |
| 1082 | }; |
| 1083 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1084 | struct omap_hwmod dm81xx_tptc3_hwmod = { |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1085 | .name = "tptc3", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1086 | .class = &dm81xx_tptc3_hwmod_class, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1087 | .clkdm_name = "alwon_l3s_clkdm", |
| 1088 | .main_clk = "sysclk4_ck", |
| 1089 | .prcm = { |
| 1090 | .omap4 = { |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1091 | .clkctrl_offs = DM81XX_CM_ALWON_TPTC3_CLKCTRL, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1092 | .modulemode = MODULEMODE_SWCTRL, |
| 1093 | }, |
| 1094 | }, |
| 1095 | }; |
| 1096 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1097 | struct omap_hwmod_ocp_if dm81xx_alwon_l3_fast__tptc3 = { |
| 1098 | .master = &dm81xx_alwon_l3_fast_hwmod, |
| 1099 | .slave = &dm81xx_tptc3_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1100 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1101 | .addr = dm81xx_tptc3_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1102 | .user = OCP_USER_MPU, |
| 1103 | }; |
| 1104 | |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1105 | struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = { |
| 1106 | .master = &dm81xx_tptc3_hwmod, |
| 1107 | .slave = &dm81xx_alwon_l3_fast_hwmod, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1108 | .clk = "sysclk4_ck", |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1109 | .addr = dm81xx_tptc3_addr_space, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1110 | .user = OCP_USER_MPU, |
| 1111 | }; |
| 1112 | |
| 1113 | static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { |
| 1114 | &dm816x_mpu__alwon_l3_slow, |
| 1115 | &dm816x_mpu__alwon_l3_med, |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1116 | &dm81xx_alwon_l3_slow__l4_ls, |
| 1117 | &dm81xx_alwon_l3_slow__l4_hs, |
| 1118 | &dm81xx_l4_ls__uart1, |
| 1119 | &dm81xx_l4_ls__uart2, |
| 1120 | &dm81xx_l4_ls__uart3, |
| 1121 | &dm81xx_l4_ls__wd_timer1, |
| 1122 | &dm81xx_l4_ls__i2c1, |
| 1123 | &dm81xx_l4_ls__i2c2, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1124 | &dm81xx_l4_ls__gpio1, |
| 1125 | &dm81xx_l4_ls__gpio2, |
| 1126 | &dm81xx_l4_ls__elm, |
| 1127 | &dm816x_l4_ls__mmc1, |
| 1128 | &dm816x_l4_ls__timer1, |
| 1129 | &dm816x_l4_ls__timer2, |
| 1130 | &dm816x_l4_ls__timer3, |
| 1131 | &dm816x_l4_ls__timer4, |
| 1132 | &dm816x_l4_ls__timer5, |
| 1133 | &dm816x_l4_ls__timer6, |
| 1134 | &dm816x_l4_ls__timer7, |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1135 | &dm81xx_l4_ls__mcspi1, |
| 1136 | &dm81xx_l4_ls__mailbox, |
| 1137 | &dm81xx_l4_hs__emac0, |
| 1138 | &dm81xx_emac0__mdio, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1139 | &dm816x_l4_hs__emac1, |
Tony Lindgren | 7e1b11d | 2015-07-16 01:55:58 -0700 | [diff] [blame^] | 1140 | &dm81xx_alwon_l3_fast__tpcc, |
| 1141 | &dm81xx_alwon_l3_fast__tptc0, |
| 1142 | &dm81xx_alwon_l3_fast__tptc1, |
| 1143 | &dm81xx_alwon_l3_fast__tptc2, |
| 1144 | &dm81xx_alwon_l3_fast__tptc3, |
| 1145 | &dm81xx_tptc0__alwon_l3_fast, |
| 1146 | &dm81xx_tptc1__alwon_l3_fast, |
| 1147 | &dm81xx_tptc2__alwon_l3_fast, |
| 1148 | &dm81xx_tptc3__alwon_l3_fast, |
Tony Lindgren | 4d38bd1 | 2015-01-26 09:26:32 -0800 | [diff] [blame] | 1149 | &dm81xx_alwon_l3_slow__gpmc, |
| 1150 | &dm81xx_default_l3_slow__usbss, |
| 1151 | NULL, |
| 1152 | }; |
| 1153 | |
| 1154 | int __init ti81xx_hwmod_init(void) |
| 1155 | { |
| 1156 | omap_hwmod_init(); |
| 1157 | return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); |
| 1158 | } |