Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | &soc { |
| 14 | |
| 15 | replicator_qdss: replicator@6046000 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 16 | compatible = "arm,primecell"; |
| 17 | arm,primecell-periphid = <0x0003b909>; |
| 18 | |
| 19 | reg = <0x6046000 0x1000>; |
| 20 | reg-names = "replicator-base"; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 21 | |
| 22 | coresight-name = "coresight-replicator"; |
| 23 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 24 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 25 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 26 | clock-names = "apb_pclk", "core_a_clk"; |
| 27 | |
| 28 | ports { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; |
| 31 | |
| 32 | port@0 { |
| 33 | reg = <0>; |
| 34 | replicator_out_tmc_etr: endpoint { |
| 35 | remote-endpoint= |
| 36 | <&tmc_etr_in_replicator>; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | port@1 { |
| 41 | reg = <0>; |
| 42 | replicator_in_tmc_etf: endpoint { |
| 43 | slave-mode; |
| 44 | remote-endpoint= |
| 45 | <&tmc_etf_out_replicator>; |
| 46 | }; |
| 47 | }; |
| 48 | }; |
| 49 | }; |
| 50 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 51 | replicator_swao: replicator@6b0a000 { |
| 52 | compatible = "arm,primecell"; |
| 53 | arm,primecell-periphid = <0x0003b909>; |
| 54 | |
| 55 | reg = <0x6b0a000 0x1000>; |
| 56 | reg-names = "replicator-base"; |
| 57 | |
| 58 | coresight-name = "coresight-replicator-swao"; |
| 59 | |
| 60 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 61 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 62 | clock-names = "apb_pclk", "core_a_clk"; |
| 63 | |
| 64 | ports { |
| 65 | #address-cells = <1>; |
| 66 | #size-cells = <0>; |
| 67 | |
| 68 | port@0 { |
| 69 | reg = <0>; |
| 70 | replicator_swao_in_tmc_etf_swao: endpoint { |
| 71 | slave-mode; |
| 72 | remote-endpoint = |
| 73 | <&tmc_etf_swao_out_replicator>; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | /* Always have EUD before funnel leading to ETR. If both |
| 78 | * sink are active we need to give preference to EUD |
| 79 | * over ETR |
| 80 | */ |
| 81 | port@1 { |
| 82 | reg = <1>; |
| 83 | replicator_swao_out_eud: endpoint { |
| 84 | remote-endpoint = |
| 85 | <&eud_in_replicator_swao>; |
| 86 | }; |
| 87 | }; |
| 88 | |
| 89 | port@2 { |
| 90 | reg = <0>; |
| 91 | replicator_swao_out_funnel_in2: endpoint { |
| 92 | remote-endpoint = |
| 93 | <&funnel_in2_in_replicator_swao>; |
| 94 | }; |
| 95 | }; |
| 96 | |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | tmc_etf_swao: tmc@6b09000 { |
| 101 | compatible = "arm,primecell"; |
| 102 | arm,primecell-periphid = <0x0003b961>; |
| 103 | |
| 104 | reg = <0x6b09000 0x1000>; |
| 105 | reg-names = "tmc-base"; |
| 106 | |
| 107 | coresight-name = "coresight-tmc-etf-swao"; |
| 108 | |
| 109 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 110 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 111 | clock-names = "apb_pclk", "core_a_clk"; |
| 112 | |
| 113 | ports { |
| 114 | #address-cells = <1>; |
| 115 | #size-cells = <0>; |
| 116 | |
| 117 | port@0 { |
| 118 | reg = <0>; |
| 119 | tmc_etf_swao_out_replicator: endpoint { |
| 120 | remote-endpoint= |
| 121 | <&replicator_swao_in_tmc_etf_swao>; |
| 122 | }; |
| 123 | }; |
| 124 | |
| 125 | port@1 { |
| 126 | reg = <0>; |
| 127 | tmc_etf_swao_in_funnel_swao: endpoint { |
| 128 | slave-mode; |
| 129 | remote-endpoint= |
| 130 | <&funnel_swao_out_tmc_etf_swao>; |
| 131 | }; |
| 132 | }; |
| 133 | }; |
| 134 | |
| 135 | }; |
| 136 | |
| 137 | funnel_swao:funnel@0x6b08000 { |
| 138 | compatible = "arm,primecell"; |
| 139 | arm,primecell-periphid = <0x0003b908>; |
| 140 | |
| 141 | reg = <0x6b08000 0x1000>; |
| 142 | reg-names = "funnel-base"; |
| 143 | |
| 144 | coresight-name = "coresight-funnel-swao"; |
| 145 | |
| 146 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 147 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 148 | clock-names = "apb_pclk", "core_a_clk"; |
| 149 | |
| 150 | ports { |
| 151 | #address-cells = <1>; |
| 152 | #size-cells = <0>; |
| 153 | |
| 154 | port@0 { |
| 155 | reg = <0>; |
| 156 | funnel_swao_out_tmc_etf_swao: endpoint { |
| 157 | remote-endpoint = |
| 158 | <&tmc_etf_swao_in_funnel_swao>; |
| 159 | }; |
| 160 | }; |
| 161 | |
| 162 | port@1 { |
| 163 | reg = <7>; |
| 164 | funnel_swao_in_tpda_swao: endpoint { |
| 165 | slave-mode; |
| 166 | remote-endpoint= |
| 167 | <&tpda_swao_out_funnel_swao>; |
| 168 | }; |
| 169 | }; |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | tpda_swao: tpda@6b01000 { |
| 174 | compatible = "qcom,coresight-tpda"; |
| 175 | reg = <0x6b01000 0x1000>; |
| 176 | reg-names = "tpda-base"; |
| 177 | |
| 178 | coresight-name = "coresight-tpda-swao"; |
| 179 | |
| 180 | qcom,tpda-atid = <71>; |
| 181 | qcom,dsb-elem-size = <1 32>; |
| 182 | qcom,cmb-elem-size = <0 64>; |
| 183 | |
| 184 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 185 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 186 | clock-names = "core_clk", "core_a_clk"; |
| 187 | |
| 188 | ports { |
| 189 | #address-cells = <1>; |
| 190 | #size-cells = <0>; |
| 191 | |
| 192 | port@0 { |
| 193 | reg = <0>; |
| 194 | tpda_swao_out_funnel_swao: endpoint { |
| 195 | remote-endpoint = |
| 196 | <&funnel_swao_in_tpda_swao>; |
| 197 | }; |
| 198 | |
| 199 | }; |
| 200 | |
| 201 | port@1 { |
| 202 | reg = <0>; |
| 203 | tpda_swao_in_tpdm_swao0: endpoint { |
| 204 | slave-mode; |
| 205 | remote-endpoint = |
| 206 | <&tpdm_swao0_out_tpda_swao>; |
| 207 | }; |
| 208 | }; |
| 209 | |
| 210 | port@2 { |
| 211 | reg = <1>; |
| 212 | tpda_swao_in_tpdm_swao1: endpoint { |
| 213 | slave-mode; |
| 214 | remote-endpoint = |
| 215 | <&tpdm_swao1_out_tpda_swao>; |
| 216 | }; |
| 217 | |
| 218 | }; |
| 219 | }; |
| 220 | }; |
| 221 | |
| 222 | tpdm_swao0: tpdm@6b02000 { |
| 223 | compatible = "qcom,coresight-tpdm"; |
| 224 | |
| 225 | reg = <0x6b02000 0x1000>; |
| 226 | reg-names = "tpdm-base"; |
| 227 | |
| 228 | coresight-name = "coresight-tpdm-swao-0"; |
| 229 | |
| 230 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 231 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 232 | clock-names = "core_clk", "core_a_clk"; |
| 233 | |
| 234 | port { |
| 235 | tpdm_swao0_out_tpda_swao: endpoint { |
| 236 | remote-endpoint = <&tpda_swao_in_tpdm_swao0>; |
| 237 | }; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | tpdm_swao1: tpdm@6b03000 { |
| 242 | compatible = "qcom,coresight-tpdm"; |
| 243 | reg = <0x6b03000 0x1000>; |
| 244 | reg-names = "tpdm-base"; |
| 245 | |
| 246 | coresight-name="coresight-tpdm-swao-1"; |
| 247 | |
| 248 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 249 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 250 | clock-names = "core_clk", "core_a_clk"; |
| 251 | |
| 252 | port { |
| 253 | tpdm_swao1_out_tpda_swao: endpoint { |
| 254 | remote-endpoint = <&tpda_swao_in_tpdm_swao1>; |
| 255 | }; |
| 256 | }; |
| 257 | }; |
| 258 | |
| 259 | tmc_etr: tmc@6048000 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 260 | compatible = "arm,primecell"; |
| 261 | arm,primecell-periphid = <0x0003b961>; |
| 262 | |
| 263 | reg = <0x6048000 0x1000>, |
| 264 | <0x6064000 0x15000>; |
| 265 | reg-names = "tmc-base", "bam-base"; |
| 266 | |
| 267 | arm,buffer-size = <0x400000>; |
| 268 | |
| 269 | coresight-name = "coresight-tmc-etr"; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 270 | coresight-ctis = <&cti0 &cti8>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 271 | |
| 272 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 273 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 274 | clock-names = "apb_pclk", "core_a_clk"; |
| 275 | |
| 276 | port { |
| 277 | tmc_etr_in_replicator: endpoint { |
| 278 | slave-mode; |
| 279 | remote-endpoint = <&replicator_out_tmc_etr>; |
| 280 | }; |
| 281 | }; |
| 282 | }; |
| 283 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 284 | tmc_etf: tmc@6047000 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 285 | compatible = "arm,primecell"; |
| 286 | arm,primecell-periphid = <0x0003b961>; |
| 287 | |
| 288 | reg = <0x6047000 0x1000>; |
| 289 | reg-names = "tmc-base"; |
| 290 | |
| 291 | coresight-name = "coresight-tmc-etf"; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 292 | coresight-ctis = <&cti0 &cti8>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 293 | arm,default-sink; |
| 294 | |
| 295 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 296 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 297 | clock-names = "apb_pclk", "core_a_clk"; |
| 298 | |
| 299 | ports { |
| 300 | #address-cells = <1>; |
| 301 | #size-cells = <0>; |
| 302 | |
| 303 | port@0 { |
| 304 | reg = <0>; |
| 305 | tmc_etf_out_replicator: endpoint { |
| 306 | remote-endpoint = |
| 307 | <&replicator_in_tmc_etf>; |
| 308 | }; |
| 309 | }; |
| 310 | |
| 311 | port@1 { |
| 312 | reg = <1>; |
| 313 | tmc_etf_in_funnel_merg: endpoint { |
| 314 | slave-mode; |
| 315 | remote-endpoint = |
| 316 | <&funnel_merg_out_tmc_etf>; |
| 317 | }; |
| 318 | }; |
| 319 | }; |
| 320 | |
| 321 | }; |
| 322 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 323 | funnel_merg: funnel@6045000 { |
| 324 | compatible = "arm,primecell"; |
| 325 | arm,primecell-periphid = <0x0003b908>; |
| 326 | |
| 327 | reg = <0x6045000 0x1000>; |
| 328 | reg-names = "funnel-base"; |
| 329 | |
| 330 | coresight-name = "coresight-funnel-merg"; |
| 331 | |
| 332 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 333 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 334 | clock-names = "apb_pclk", "core_a_clk"; |
| 335 | |
| 336 | ports { |
| 337 | #address-cells = <1>; |
| 338 | #size-cells = <0>; |
| 339 | |
| 340 | port@0 { |
| 341 | reg = <0>; |
| 342 | funnel_merg_out_tmc_etf: endpoint { |
| 343 | remote-endpoint = |
| 344 | <&tmc_etf_in_funnel_merg>; |
| 345 | }; |
| 346 | }; |
| 347 | |
| 348 | port@1 { |
| 349 | reg = <0>; |
| 350 | funnel_merg_in_funnel_in0: endpoint { |
| 351 | slave-mode; |
| 352 | remote-endpoint = |
| 353 | <&funnel_in0_out_funnel_merg>; |
| 354 | }; |
| 355 | }; |
| 356 | |
| 357 | port@2 { |
| 358 | reg = <2>; |
| 359 | funnel_merg_in_funnel_in2: endpoint { |
| 360 | slave-mode; |
| 361 | remote-endpoint = |
| 362 | <&funnel_in2_out_funnel_merg>; |
| 363 | }; |
| 364 | }; |
| 365 | }; |
| 366 | }; |
| 367 | |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 368 | stm: stm@6002000 { |
| 369 | compatible = "arm,primecell"; |
| 370 | arm,primecell-periphid = <0x0003b962>; |
| 371 | |
| 372 | reg = <0x6002000 0x1000>, |
| 373 | <0x16280000 0x180000>; |
| 374 | reg-names = "stm-base", "stm-stimulus-base"; |
| 375 | |
| 376 | coresight-name = "coresight-stm"; |
| 377 | |
| 378 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 379 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 380 | clock-names = "apb_pclk", "core_a_clk"; |
| 381 | |
| 382 | port { |
| 383 | stm_out_funnel_in0: endpoint { |
| 384 | remote-endpoint = <&funnel_in0_in_stm>; |
| 385 | }; |
| 386 | }; |
| 387 | |
| 388 | }; |
| 389 | |
| 390 | funnel_in0: funnel@0x6041000 { |
| 391 | compatible = "arm,primecell"; |
| 392 | arm,primecell-periphid = <0x0003b908>; |
| 393 | |
| 394 | reg = <0x6041000 0x1000>; |
| 395 | reg-names = "funnel-base"; |
| 396 | |
| 397 | coresight-name = "coresight-funnel-in0"; |
| 398 | |
| 399 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 400 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 401 | clock-names = "apb_pclk", "core_a_clk"; |
| 402 | |
| 403 | ports { |
| 404 | #address-cells = <1>; |
| 405 | #size-cells = <0>; |
| 406 | |
| 407 | port@0 { |
| 408 | reg = <0>; |
| 409 | funnel_in0_out_funnel_merg: endpoint { |
| 410 | remote-endpoint = |
| 411 | <&funnel_merg_in_funnel_in0>; |
| 412 | }; |
| 413 | }; |
| 414 | |
| 415 | port@1 { |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 416 | reg = <3>; |
| 417 | funnel_in0_in_funnel_spss: endpoint { |
| 418 | slave-mode; |
| 419 | remote-endpoint = |
| 420 | <&funnel_spss_out_funnel_in0>; |
| 421 | }; |
| 422 | }; |
| 423 | |
| 424 | port@2 { |
| 425 | reg = <6>; |
| 426 | funnel_in0_in_funnel_qatb: endpoint { |
| 427 | slave-mode; |
| 428 | remote-endpoint = |
| 429 | <&funnel_qatb_out_funnel_in0>; |
| 430 | }; |
| 431 | }; |
| 432 | |
| 433 | port@3 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 434 | reg = <7>; |
| 435 | funnel_in0_in_stm: endpoint { |
| 436 | slave-mode; |
| 437 | remote-endpoint = <&stm_out_funnel_in0>; |
| 438 | }; |
| 439 | }; |
| 440 | }; |
| 441 | }; |
| 442 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 443 | funnel_in2: funnel@0x6043000 { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 444 | compatible = "arm,primecell"; |
| 445 | arm,primecell-periphid = <0x0003b908>; |
| 446 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 447 | reg = <0x6043000 0x1000>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 448 | reg-names = "funnel-base"; |
| 449 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 450 | coresight-name = "coresight-funnel-in2"; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 451 | |
| 452 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 453 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 454 | clock-names = "apb_pclk", "core_a_clk"; |
| 455 | |
| 456 | ports { |
| 457 | #address-cells = <1>; |
| 458 | #size-cells = <0>; |
| 459 | |
| 460 | port@0 { |
| 461 | reg = <0>; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 462 | funnel_in2_out_funnel_merg: endpoint { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 463 | remote-endpoint = |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 464 | <&funnel_merg_in_funnel_in2>; |
| 465 | }; |
| 466 | }; |
| 467 | |
| 468 | port@1 { |
| 469 | reg = <1>; |
| 470 | funnel_in2_in_replicator_swao: endpoint { |
| 471 | slave-mode; |
| 472 | remote-endpoint = |
| 473 | <&replicator_swao_out_funnel_in2>; |
| 474 | }; |
| 475 | |
| 476 | }; |
| 477 | |
| 478 | port@2 { |
| 479 | reg = <5>; |
| 480 | funnel_in2_in_funnel_apss_merg: endpoint { |
| 481 | slave-mode; |
| 482 | remote-endpoint = |
| 483 | <&funnel_apss_merg_out_funnel_in2>; |
| 484 | }; |
| 485 | }; |
| 486 | |
| 487 | }; |
| 488 | }; |
| 489 | |
| 490 | tpda: tpda@6004000 { |
| 491 | compatible = "qcom,coresight-tpda"; |
| 492 | reg = <0x6004000 0x1000>; |
| 493 | reg-names = "tpda-base"; |
| 494 | |
| 495 | coresight-name = "coresight-tpda"; |
| 496 | |
| 497 | qcom,tpda-atid = <65>; |
| 498 | qcom,bc-elem-size = <13 32>; |
| 499 | qcom,tc-elem-size = <7 32>, |
| 500 | <13 32>; |
| 501 | qcom,dsb-elem-size = <13 32>; |
| 502 | qcom,cmb-elem-size = <7 32>, |
| 503 | <8 32>, |
| 504 | <13 64>; |
| 505 | |
| 506 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 507 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 508 | clock-names = "core_clk", "core_a_clk"; |
| 509 | |
| 510 | ports { |
| 511 | #address-cells = <1>; |
| 512 | #size-cells = <0>; |
| 513 | port@0 { |
| 514 | reg = <0>; |
| 515 | tpda_out_funnel_qatb: endpoint { |
| 516 | remote-endpoint = |
| 517 | <&funnel_qatb_in_tpda>; |
| 518 | }; |
| 519 | |
| 520 | }; |
| 521 | |
| 522 | port@1 { |
| 523 | reg = <7>; |
| 524 | tpda_in_tpdm_vsense: endpoint { |
| 525 | slave-mode; |
| 526 | remote-endpoint = |
| 527 | <&tpdm_vsense_out_tpda>; |
| 528 | }; |
| 529 | }; |
| 530 | |
| 531 | port@2 { |
| 532 | reg = <8>; |
| 533 | tpda_in_tpdm_dcc: endpoint { |
| 534 | slave-mode; |
| 535 | remote-endpoint = |
| 536 | <&tpdm_dcc_out_tpda>; |
| 537 | }; |
| 538 | }; |
| 539 | |
| 540 | port@3 { |
| 541 | reg = <13>; |
| 542 | tpda_in_tpdm_pimem: endpoint { |
| 543 | slave-mode; |
| 544 | remote-endpoint = |
| 545 | <&tpdm_pimem_out_tpda>; |
| 546 | }; |
| 547 | }; |
| 548 | }; |
| 549 | }; |
| 550 | |
| 551 | tpdm_pimem: tpdm@6850000 { |
| 552 | compatible = "qcom,coresight-tpdm"; |
| 553 | reg = <0x6850000 0x1000>; |
| 554 | reg-names = "tpdm-base"; |
| 555 | |
| 556 | coresight-name = "coresight-tpdm-pimem"; |
| 557 | |
| 558 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 559 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 560 | clock-names = "core_clk", "core_a_clk"; |
| 561 | |
| 562 | port { |
| 563 | tpdm_pimem_out_tpda: endpoint { |
| 564 | remote-endpoint = <&tpda_in_tpdm_pimem>; |
| 565 | }; |
| 566 | }; |
| 567 | }; |
| 568 | |
| 569 | |
| 570 | tpdm_dcc: tpdm@6870000 { |
| 571 | compatible = "qcom,coresight-tpdm"; |
| 572 | reg = <0x6870000 0x1000>; |
| 573 | reg-names = "tpdm-base"; |
| 574 | |
| 575 | coresight-name = "coresight-tpdm-dcc"; |
| 576 | |
| 577 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 578 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 579 | clock-names = "core_clk", "core_a_clk"; |
| 580 | |
| 581 | port { |
| 582 | tpdm_dcc_out_tpda: endpoint { |
| 583 | remote-endpoint = <&tpda_in_tpdm_dcc>; |
| 584 | }; |
| 585 | }; |
| 586 | }; |
| 587 | |
| 588 | tpdm_vsense: tpdm@6840000 { |
| 589 | compatible = "qcom,coresight-tpdm"; |
| 590 | reg = <0x6840000 0x1000>; |
| 591 | reg-names = "tpdm-base"; |
| 592 | |
| 593 | coresight-name = "coresight-tpdm-vsense"; |
| 594 | |
| 595 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 596 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 597 | clock-names = "core_clk", "core_a_clk"; |
| 598 | |
| 599 | port{ |
| 600 | tpdm_vsense_out_tpda: endpoint { |
| 601 | remote-endpoint = <&tpda_in_tpdm_vsense>; |
| 602 | }; |
| 603 | }; |
| 604 | }; |
| 605 | |
| 606 | tpda_olc: tpda@7832000 { |
| 607 | compatible = "qcom,coresight-tpda"; |
| 608 | reg = <0x7832000 0x1000>; |
| 609 | reg-names = "tpda-base"; |
| 610 | |
| 611 | coresight-name = "coresight-tpda-olc"; |
| 612 | |
| 613 | qcom,tpda-atid = <69>; |
| 614 | qcom,cmb-elem-size = <0 64>; |
| 615 | |
| 616 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 617 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 618 | clock-names = "core_clk", "core_a_clk"; |
| 619 | |
| 620 | ports { |
| 621 | #address-cells = <1>; |
| 622 | #size-cells = <0>; |
| 623 | port@0 { |
| 624 | reg = <0>; |
| 625 | tpda_olc_out_funnel_apss_merg: endpoint { |
| 626 | remote-endpoint = |
| 627 | <&funnel_apss_merg_in_tpda_olc>; |
| 628 | }; |
| 629 | }; |
| 630 | port@1 { |
| 631 | reg = <0>; |
| 632 | tpda_olc_in_tpdm_olc: endpoint { |
| 633 | slave-mode; |
| 634 | remote-endpoint = |
| 635 | <&tpdm_olc_out_tpda_olc>; |
| 636 | }; |
| 637 | }; |
| 638 | }; |
| 639 | }; |
| 640 | |
| 641 | tpdm_olc: tpdm@7830000 { |
| 642 | compatible = "qcom,coresight-tpdm"; |
| 643 | reg = <0x7830000 0x1000>; |
| 644 | reg-names = "tpdm-base"; |
| 645 | |
| 646 | coresight-name = "coresight-tpdm-olc"; |
| 647 | |
| 648 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 649 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 650 | clock-names = "core_clk", "core_a_clk"; |
| 651 | |
| 652 | port{ |
| 653 | tpdm_olc_out_tpda_olc: endpoint { |
| 654 | remote-endpoint = <&tpda_olc_in_tpdm_olc>; |
| 655 | }; |
| 656 | }; |
| 657 | }; |
| 658 | |
| 659 | tpda_spss: tpda@6882000 { |
| 660 | compatible = "qcom,coresight-tpda"; |
| 661 | reg = <0x6882000 0x1000>; |
| 662 | reg-names = "tpda-base"; |
| 663 | |
| 664 | coresight-name = "coresight-tpda-spss"; |
| 665 | |
| 666 | qcom,tpda-atid = <70>; |
| 667 | qcom,dsb-elem-size = <0 32>; |
| 668 | |
| 669 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 670 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 671 | clock-names = "core_clk", "core_a_clk"; |
| 672 | |
| 673 | ports { |
| 674 | #address-cells = <1>; |
| 675 | #size-cells = <0>; |
| 676 | port@0 { |
| 677 | reg = <0>; |
| 678 | tpda_spss_out_funnel_spss: endpoint { |
| 679 | remote-endpoint = |
| 680 | <&funnel_spss_in_tpda_spss>; |
| 681 | }; |
| 682 | }; |
| 683 | port@1 { |
| 684 | reg = <0>; |
| 685 | tpda_spss_in_tpdm_spss: endpoint { |
| 686 | slave-mode; |
| 687 | remote-endpoint = |
| 688 | <&tpdm_spss_out_tpda_spss>; |
| 689 | }; |
| 690 | }; |
| 691 | }; |
| 692 | }; |
| 693 | |
| 694 | tpdm_spss: tpdm@6880000 { |
| 695 | compatible = "qcom,coresight-tpdm"; |
| 696 | reg = <0x6880000 0x1000>; |
| 697 | reg-names = "tpdm-base"; |
| 698 | |
| 699 | coresight-name = "coresight-tpdm-spss"; |
| 700 | |
| 701 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 702 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 703 | clock-names = "core_clk", "core_a_clk"; |
| 704 | |
| 705 | qcom,msr-fix-req; |
| 706 | |
| 707 | port{ |
| 708 | tpdm_spss_out_tpda_spss: endpoint { |
| 709 | remote-endpoint = <&tpda_spss_in_tpdm_spss>; |
| 710 | }; |
| 711 | }; |
| 712 | }; |
| 713 | |
| 714 | funnel_spss: funnel@6883000 { |
| 715 | compatible = "arm,primecell"; |
| 716 | arm,primecell-periphid = <0x0003b908>; |
| 717 | |
| 718 | reg = <0x6883000 0x1000>; |
| 719 | reg-names = "funnel-base"; |
| 720 | |
| 721 | coresight-name = "coresight-funnel-spss"; |
| 722 | |
| 723 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 724 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 725 | clock-names = "apb_pclk", "core_a_clk"; |
| 726 | |
| 727 | ports { |
| 728 | #address-cells = <1>; |
| 729 | #size-cells = <0>; |
| 730 | |
| 731 | port@0 { |
| 732 | reg = <0>; |
| 733 | funnel_spss_out_funnel_in0: endpoint { |
| 734 | remote-endpoint = |
| 735 | <&funnel_in0_in_funnel_spss>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 736 | }; |
| 737 | }; |
| 738 | |
| 739 | port@1 { |
| 740 | reg = <0>; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 741 | funnel_spss_in_tpda_spss: endpoint { |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 742 | slave-mode; |
| 743 | remote-endpoint = |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 744 | <&tpda_spss_out_funnel_spss>; |
| 745 | }; |
| 746 | }; |
| 747 | }; |
| 748 | }; |
| 749 | |
| 750 | funnel_qatb: funnel@6005000 { |
| 751 | compatible = "arm,primecell"; |
| 752 | arm,primecell-periphid = <0x0003b908>; |
| 753 | |
| 754 | reg = <0x6005000 0x1000>; |
| 755 | reg-names = "funnel-base"; |
| 756 | |
| 757 | coresight-name = "coresight-funnel-qatb"; |
| 758 | |
| 759 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 760 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 761 | clock-names = "apb_pclk", "core_a_clk"; |
| 762 | |
| 763 | ports { |
| 764 | #address-cells = <1>; |
| 765 | #size-cells = <0>; |
| 766 | |
| 767 | port@0 { |
| 768 | reg = <0>; |
| 769 | funnel_qatb_out_funnel_in0: endpoint { |
| 770 | remote-endpoint = |
| 771 | <&funnel_in0_in_funnel_qatb>; |
| 772 | }; |
| 773 | }; |
| 774 | |
| 775 | port@1 { |
| 776 | reg = <0>; |
| 777 | funnel_qatb_in_tpda: endpoint { |
| 778 | slave-mode; |
| 779 | remote-endpoint = |
| 780 | <&tpda_out_funnel_qatb>; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 781 | }; |
| 782 | }; |
| 783 | }; |
| 784 | }; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 785 | |
| 786 | cti0: cti@6010000 { |
| 787 | compatible = "arm,coresight-cti"; |
| 788 | reg = <0x6010000 0x1000>; |
| 789 | reg-names = "cti-base"; |
| 790 | |
| 791 | coresight-name = "coresight-cti0"; |
| 792 | |
| 793 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 794 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 795 | clock-names = "core_clk", "core_a_clk"; |
| 796 | }; |
| 797 | |
| 798 | cti1: cti@6011000 { |
| 799 | compatible = "arm,coresight-cti"; |
| 800 | reg = <0x6011000 0x1000>; |
| 801 | reg-names = "cti-base"; |
| 802 | |
| 803 | coresight-name = "coresight-cti1"; |
| 804 | |
| 805 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 806 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 807 | clock-names = "core_clk", "core_a_clk"; |
| 808 | }; |
| 809 | |
| 810 | cti2: cti@6012000 { |
| 811 | compatible = "arm,coresight-cti"; |
| 812 | reg = <0x6012000 0x1000>; |
| 813 | reg-names = "cti-base"; |
| 814 | |
| 815 | coresight-name = "coresight-cti2"; |
| 816 | |
| 817 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 818 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 819 | clock-names = "core_clk", "core_a_clk"; |
| 820 | }; |
| 821 | |
| 822 | cti3: cti@6013000 { |
| 823 | compatible = "arm,coresight-cti"; |
| 824 | reg = <0x6013000 0x1000>; |
| 825 | reg-names = "cti-base"; |
| 826 | |
| 827 | coresight-name = "coresight-cti3"; |
| 828 | |
| 829 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 830 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 831 | clock-names = "core_clk", "core_a_clk"; |
| 832 | }; |
| 833 | |
| 834 | cti4: cti@6014000 { |
| 835 | compatible = "arm,coresight-cti"; |
| 836 | reg = <0x6014000 0x1000>; |
| 837 | reg-names = "cti-base"; |
| 838 | |
| 839 | coresight-name = "coresight-cti4"; |
| 840 | |
| 841 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 842 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 843 | clock-names = "core_clk", "core_a_clk"; |
| 844 | }; |
| 845 | |
| 846 | cti5: cti@6015000 { |
| 847 | compatible = "arm,coresight-cti"; |
| 848 | reg = <0x6015000 0x1000>; |
| 849 | reg-names = "cti-base"; |
| 850 | |
| 851 | coresight-name = "coresight-cti5"; |
| 852 | |
| 853 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 854 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 855 | clock-names = "core_clk", "core_a_clk"; |
| 856 | }; |
| 857 | |
| 858 | cti6: cti@6016000 { |
| 859 | compatible = "arm,coresight-cti"; |
| 860 | reg = <0x6016000 0x1000>; |
| 861 | reg-names = "cti-base"; |
| 862 | |
| 863 | coresight-name = "coresight-cti6"; |
| 864 | |
| 865 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 866 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 867 | clock-names = "core_clk", "core_a_clk"; |
| 868 | }; |
| 869 | |
| 870 | cti7: cti@6017000 { |
| 871 | compatible = "arm,coresight-cti"; |
| 872 | reg = <0x6017000 0x1000>; |
| 873 | reg-names = "cti-base"; |
| 874 | |
| 875 | coresight-name = "coresight-cti7"; |
| 876 | |
| 877 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 878 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 879 | clock-names = "core_clk", "core_a_clk"; |
| 880 | }; |
| 881 | |
| 882 | cti8: cti@6018000 { |
| 883 | compatible = "arm,coresight-cti"; |
| 884 | reg = <0x6018000 0x1000>; |
| 885 | reg-names = "cti-base"; |
| 886 | |
| 887 | coresight-name = "coresight-cti8"; |
| 888 | |
| 889 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 890 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 891 | clock-names = "core_clk", "core_a_clk"; |
| 892 | }; |
| 893 | |
| 894 | cti9: cti@6019000 { |
| 895 | compatible = "arm,coresight-cti"; |
| 896 | reg = <0x6019000 0x1000>; |
| 897 | reg-names = "cti-base"; |
| 898 | |
| 899 | coresight-name = "coresight-cti9"; |
| 900 | |
| 901 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 902 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 903 | clock-names = "core_clk", "core_a_clk"; |
| 904 | }; |
| 905 | |
| 906 | cti10: cti@601a000 { |
| 907 | compatible = "arm,coresight-cti"; |
| 908 | reg = <0x601a000 0x1000>; |
| 909 | reg-names = "cti-base"; |
| 910 | |
| 911 | coresight-name = "coresight-cti10"; |
| 912 | |
| 913 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 914 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 915 | clock-names = "core_clk", "core_a_clk"; |
| 916 | }; |
| 917 | |
| 918 | cti11: cti@601b000 { |
| 919 | compatible = "arm,coresight-cti"; |
| 920 | reg = <0x601b000 0x1000>; |
| 921 | reg-names = "cti-base"; |
| 922 | |
| 923 | coresight-name = "coresight-cti11"; |
| 924 | |
| 925 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 926 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 927 | clock-names = "core_clk", "core_a_clk"; |
| 928 | }; |
| 929 | |
| 930 | cti12: cti@601c000 { |
| 931 | compatible = "arm,coresight-cti"; |
| 932 | reg = <0x601c000 0x1000>; |
| 933 | reg-names = "cti-base"; |
| 934 | |
| 935 | coresight-name = "coresight-cti12"; |
| 936 | |
| 937 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 938 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 939 | clock-names = "core_clk", "core_a_clk"; |
| 940 | }; |
| 941 | |
| 942 | cti13: cti@601d000 { |
| 943 | compatible = "arm,coresight-cti"; |
| 944 | reg = <0x601d000 0x1000>; |
| 945 | reg-names = "cti-base"; |
| 946 | |
| 947 | coresight-name = "coresight-cti13"; |
| 948 | |
| 949 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 950 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 951 | clock-names = "core_clk", "core_a_clk"; |
| 952 | }; |
| 953 | |
| 954 | cti14: cti@601e000 { |
| 955 | compatible = "arm,coresight-cti"; |
| 956 | reg = <0x601e000 0x1000>; |
| 957 | reg-names = "cti-base"; |
| 958 | |
| 959 | coresight-name = "coresight-cti14"; |
| 960 | |
| 961 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 962 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 963 | clock-names = "core_clk", "core_a_clk"; |
| 964 | }; |
| 965 | |
| 966 | cti15: cti@601f000 { |
| 967 | compatible = "arm,coresight-cti"; |
| 968 | reg = <0x601f000 0x1000>; |
| 969 | reg-names = "cti-base"; |
| 970 | |
| 971 | coresight-name = "coresight-cti15"; |
| 972 | |
| 973 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 974 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 975 | clock-names = "core_clk", "core_a_clk"; |
| 976 | }; |
| 977 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 978 | cti_cpu0: cti@7020000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 979 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 980 | reg = <0x7020000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 981 | reg-names = "cti-base"; |
| 982 | |
| 983 | coresight-name = "coresight-cti-cpu0"; |
| 984 | cpu = <&CPU0>; |
| 985 | |
| 986 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 987 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 988 | clock-names = "core_clk", "core_a_clk"; |
| 989 | }; |
| 990 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 991 | cti_cpu1: cti@7120000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 992 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 993 | reg = <0x7120000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 994 | reg-names = "cti-base"; |
| 995 | |
| 996 | coresight-name = "coresight-cti-cpu1"; |
| 997 | cpu = <&CPU1>; |
| 998 | |
| 999 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1000 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1001 | clock-names = "core_clk", "core_a_clk"; |
| 1002 | }; |
| 1003 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1004 | cti_cpu2: cti@7220000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1005 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1006 | reg = <0x7220000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1007 | reg-names = "cti-base"; |
| 1008 | |
| 1009 | coresight-name = "coresight-cti-cpu2"; |
| 1010 | cpu = <&CPU2>; |
| 1011 | |
| 1012 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1013 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1014 | clock-names = "core_clk", "core_a_clk"; |
| 1015 | }; |
| 1016 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1017 | cti_cpu3: cti@7320000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1018 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1019 | reg = <0x7320000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1020 | reg-names = "cti-base"; |
| 1021 | |
| 1022 | coresight-name = "coresight-cti-cpu3"; |
| 1023 | cpu = <&CPU3>; |
| 1024 | |
| 1025 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1026 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1027 | clock-names = "core_clk", "core_a_clk"; |
| 1028 | }; |
| 1029 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1030 | cti_cpu4: cti@7420000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1031 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1032 | reg = <0x7420000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1033 | reg-names = "cti-base"; |
| 1034 | |
| 1035 | coresight-name = "coresight-cti-cpu4"; |
| 1036 | cpu = <&CPU4>; |
| 1037 | |
| 1038 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1039 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1040 | clock-names = "core_clk", "core_a_clk"; |
| 1041 | }; |
| 1042 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1043 | cti_cpu5: cti@7520000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1044 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1045 | reg = <0x7520000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1046 | reg-names = "cti-base"; |
| 1047 | |
| 1048 | coresight-name = "coresight-cti-cpu5"; |
| 1049 | cpu = <&CPU5>; |
| 1050 | |
| 1051 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1052 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1053 | clock-names = "core_clk", "core_a_clk"; |
| 1054 | }; |
| 1055 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1056 | cti_cpu6: cti@7620000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1057 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1058 | reg = <0x7620000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1059 | reg-names = "cti-base"; |
| 1060 | |
| 1061 | coresight-name = "coresight-cti-cpu6"; |
| 1062 | cpu = <&CPU6>; |
| 1063 | |
| 1064 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1065 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1066 | clock-names = "core_clk", "core_a_clk"; |
| 1067 | }; |
| 1068 | |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1069 | cti_cpu7: cti@7720000 { |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1070 | compatible = "arm,coresight-cti"; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1071 | reg = <0x7720000 0x1000>; |
Satyajit Desai | b303981 | 2017-01-30 11:34:03 -0800 | [diff] [blame] | 1072 | reg-names = "cti-base"; |
| 1073 | |
| 1074 | coresight-name = "coresight-cti-cpu7"; |
| 1075 | cpu = <&CPU7>; |
| 1076 | |
| 1077 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1078 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1079 | clock-names = "core_clk", "core_a_clk"; |
| 1080 | }; |
Satyajit Desai | 7e2f032 | 2017-02-07 13:54:23 -0800 | [diff] [blame^] | 1081 | |
| 1082 | dummy_eud: dummy_sink { |
| 1083 | compatible = "qcom,coresight-dummy"; |
| 1084 | |
| 1085 | coresight-name = "coresight-eud"; |
| 1086 | |
| 1087 | qcom,dummy-sink; |
| 1088 | port { |
| 1089 | eud_in_replicator_swao: endpoint { |
| 1090 | slave-mode; |
| 1091 | remote-endpoint = |
| 1092 | <&replicator_swao_out_eud>; |
| 1093 | }; |
| 1094 | }; |
| 1095 | }; |
| 1096 | |
| 1097 | funnel_apss_merg: funnel@7810000 { |
| 1098 | compatible = "arm,primecell"; |
| 1099 | arm,primecell-periphid = <0x0003b908>; |
| 1100 | |
| 1101 | reg = <0x7810000 0x1000>; |
| 1102 | reg-names = "funnel-base"; |
| 1103 | |
| 1104 | coresight-name = "coresight-funnel-apss-merg"; |
| 1105 | |
| 1106 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1107 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1108 | clock-names = "apb_pclk", "core_a_clk"; |
| 1109 | |
| 1110 | ports { |
| 1111 | #address-cells = <1>; |
| 1112 | #size-cells = <0>; |
| 1113 | |
| 1114 | port@0 { |
| 1115 | reg = <0>; |
| 1116 | funnel_apss_merg_out_funnel_in2: endpoint { |
| 1117 | remote-endpoint = |
| 1118 | <&funnel_in2_in_funnel_apss_merg>; |
| 1119 | }; |
| 1120 | }; |
| 1121 | |
| 1122 | port@1 { |
| 1123 | reg = <0>; |
| 1124 | funnel_apss_merg_in_funnel_apss: endpoint { |
| 1125 | slave-mode; |
| 1126 | remote-endpoint = |
| 1127 | <&funnel_apss_out_funnel_apss_merg>; |
| 1128 | }; |
| 1129 | }; |
| 1130 | |
| 1131 | port@2 { |
| 1132 | reg = <1>; |
| 1133 | funnel_apss_merg_in_tpda_olc: endpoint { |
| 1134 | slave-mode; |
| 1135 | remote-endpoint = |
| 1136 | <&tpda_olc_out_funnel_apss_merg>; |
| 1137 | }; |
| 1138 | }; |
| 1139 | }; |
| 1140 | }; |
| 1141 | |
| 1142 | funnel_apss: funnel@7800000 { |
| 1143 | compatible = "arm,primecell"; |
| 1144 | arm,primecell-periphid = <0x0003b908>; |
| 1145 | |
| 1146 | reg = <0x7800000 0x1000>; |
| 1147 | reg-names = "funnel-base"; |
| 1148 | |
| 1149 | coresight-name = "coresight-funnel-apss"; |
| 1150 | |
| 1151 | clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| 1152 | <&clock_gcc RPMH_QDSS_A_CLK>; |
| 1153 | clock-names = "apb_pclk", "core_a_clk"; |
| 1154 | |
| 1155 | ports { |
| 1156 | #address-cells = <1>; |
| 1157 | #size-cells = <0>; |
| 1158 | |
| 1159 | port@0 { |
| 1160 | reg = <0>; |
| 1161 | funnel_apss_out_funnel_apss_merg: endpoint { |
| 1162 | remote-endpoint = |
| 1163 | <&funnel_apss_merg_in_funnel_apss>; |
| 1164 | }; |
| 1165 | }; |
| 1166 | }; |
| 1167 | }; |
Satyajit Desai | 84bde12 | 2016-09-13 14:36:11 -0700 | [diff] [blame] | 1168 | }; |