blob: 61502bc7bf1d4bcf06a74fc2452371eb0da21aa8 [file] [log] [blame]
Akira Iguchia619f981b2007-01-26 16:28:18 +09001/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/device.h>
42#include <scsi/scsi_host.h>
43#include <linux/libata.h>
44
45#define DRV_NAME "pata_scc"
Jeff Garzik8bc3fc42007-05-21 20:26:38 -040046#define DRV_VERSION "0.2"
Akira Iguchia619f981b2007-01-26 16:28:18 +090047
48#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50/* PCI BARs */
51#define SCC_CTRL_BAR 0
52#define SCC_BMID_BAR 1
53
54/* offset of CTRL registers */
55#define SCC_CTL_PIOSHT 0x000
56#define SCC_CTL_PIOCT 0x004
57#define SCC_CTL_MDMACT 0x008
58#define SCC_CTL_MCRCST 0x00C
59#define SCC_CTL_SDMACT 0x010
60#define SCC_CTL_SCRCST 0x014
61#define SCC_CTL_UDENVT 0x018
62#define SCC_CTL_TDVHSEL 0x020
63#define SCC_CTL_MODEREG 0x024
64#define SCC_CTL_ECMODE 0xF00
65#define SCC_CTL_MAEA0 0xF50
66#define SCC_CTL_MAEC0 0xF54
67#define SCC_CTL_CCKCTRL 0xFF0
68
69/* offset of BMID registers */
70#define SCC_DMA_CMD 0x000
71#define SCC_DMA_STATUS 0x004
72#define SCC_DMA_TABLE_OFS 0x008
73#define SCC_DMA_INTMASK 0x010
74#define SCC_DMA_INTST 0x014
75#define SCC_DMA_PTERADD 0x018
76#define SCC_REG_CMD_ADDR 0x020
77#define SCC_REG_DATA 0x000
78#define SCC_REG_ERR 0x004
79#define SCC_REG_FEATURE 0x004
80#define SCC_REG_NSECT 0x008
81#define SCC_REG_LBAL 0x00C
82#define SCC_REG_LBAM 0x010
83#define SCC_REG_LBAH 0x014
84#define SCC_REG_DEVICE 0x018
85#define SCC_REG_STATUS 0x01C
86#define SCC_REG_CMD 0x01C
87#define SCC_REG_ALTSTATUS 0x020
88
89/* register value */
90#define TDVHSEL_MASTER 0x00000001
91#define TDVHSEL_SLAVE 0x00000004
92
93#define MODE_JCUSFEN 0x00000080
94
95#define ECMODE_VALUE 0x01
96
97#define CCKCTRL_ATARESET 0x00040000
98#define CCKCTRL_BUFCNT 0x00020000
99#define CCKCTRL_CRST 0x00010000
100#define CCKCTRL_OCLKEN 0x00000100
101#define CCKCTRL_ATACLKOEN 0x00000002
102#define CCKCTRL_LCLKEN 0x00000001
103
104#define QCHCD_IOS_SS 0x00000001
105
106#define QCHSD_STPDIAG 0x00020000
107
108#define INTMASK_MSK 0xD1000012
109#define INTSTS_SERROR 0x80000000
110#define INTSTS_PRERR 0x40000000
111#define INTSTS_RERR 0x10000000
112#define INTSTS_ICERR 0x01000000
113#define INTSTS_BMSINT 0x00000010
114#define INTSTS_BMHE 0x00000008
115#define INTSTS_IOIRQS 0x00000004
116#define INTSTS_INTRQ 0x00000002
117#define INTSTS_ACTEINT 0x00000001
118
119
120/* PIO transfer mode table */
121/* JCHST */
122static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125};
126
127/* JCHHT */
128static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131};
132
133/* JCHCT */
134static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137};
138
139/* DMA transfer mode table */
140/* JCHDCTM/JCHDCTS */
141static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144};
145
146/* JCSTWTM/JCSTWTS */
147static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150};
151
152/* JCTSS */
153static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156};
157
158/* JCENVT */
159static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162};
163
164/* JCACTSELS/JCACTSELM */
165static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168};
169
170static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
174};
175
176/**
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: um
180 *
181 * Set PIO mode for device.
182 *
183 * LOCKING:
184 * None (inherited from caller).
185 */
186
187static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
188{
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
194 unsigned long reg;
195 int offset;
196
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
200 else
201 offset = 0; /* 100MHz */
202
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
207}
208
209/**
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
212 * @adev: um
213 * @udma: udma mode, 0 - 6
214 *
215 * Set UDMA mode for device.
216 *
217 * LOCKING:
218 * None (inherited from caller).
219 */
220
221static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
222{
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
225 u8 speed = udma;
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
234 int offset, idx;
235
Jeff Garzika84471f2007-02-26 05:51:33 -0500236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900237 offset = 1; /* 133MHz */
238 else
239 offset = 0; /* 100MHz */
240
241 if (speed >= XFER_UDMA_0)
242 idx = speed - XFER_UDMA_0;
243 else
244 return;
245
246 if (is_slave) {
247 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
248 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
249 out_be32(tdvhsel_port,
250 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
251 } else {
252 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
254 out_be32(tdvhsel_port,
255 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
256 }
257 out_be32(udenvt_port,
258 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
259}
260
261/**
262 * scc_tf_load - send taskfile registers to host controller
263 * @ap: Port to which output is sent
264 * @tf: ATA taskfile register set
265 *
266 * Note: Original code is ata_tf_load().
267 */
268
269static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
270{
271 struct ata_ioports *ioaddr = &ap->ioaddr;
272 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
273
274 if (tf->ctl != ap->last_ctl) {
275 out_be32(ioaddr->ctl_addr, tf->ctl);
276 ap->last_ctl = tf->ctl;
277 ata_wait_idle(ap);
278 }
279
280 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
281 out_be32(ioaddr->feature_addr, tf->hob_feature);
282 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
283 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
284 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
285 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
286 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
287 tf->hob_feature,
288 tf->hob_nsect,
289 tf->hob_lbal,
290 tf->hob_lbam,
291 tf->hob_lbah);
292 }
293
294 if (is_addr) {
295 out_be32(ioaddr->feature_addr, tf->feature);
296 out_be32(ioaddr->nsect_addr, tf->nsect);
297 out_be32(ioaddr->lbal_addr, tf->lbal);
298 out_be32(ioaddr->lbam_addr, tf->lbam);
299 out_be32(ioaddr->lbah_addr, tf->lbah);
300 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
301 tf->feature,
302 tf->nsect,
303 tf->lbal,
304 tf->lbam,
305 tf->lbah);
306 }
307
308 if (tf->flags & ATA_TFLAG_DEVICE) {
309 out_be32(ioaddr->device_addr, tf->device);
310 VPRINTK("device 0x%X\n", tf->device);
311 }
312
313 ata_wait_idle(ap);
314}
315
316/**
317 * scc_check_status - Read device status reg & clear interrupt
318 * @ap: port where the device is
319 *
320 * Note: Original code is ata_check_status().
321 */
322
323static u8 scc_check_status (struct ata_port *ap)
324{
325 return in_be32(ap->ioaddr.status_addr);
326}
327
328/**
329 * scc_tf_read - input device's ATA taskfile shadow registers
330 * @ap: Port from which input is read
331 * @tf: ATA taskfile register set for storing input
332 *
333 * Note: Original code is ata_tf_read().
334 */
335
336static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
337{
338 struct ata_ioports *ioaddr = &ap->ioaddr;
339
340 tf->command = scc_check_status(ap);
341 tf->feature = in_be32(ioaddr->error_addr);
342 tf->nsect = in_be32(ioaddr->nsect_addr);
343 tf->lbal = in_be32(ioaddr->lbal_addr);
344 tf->lbam = in_be32(ioaddr->lbam_addr);
345 tf->lbah = in_be32(ioaddr->lbah_addr);
346 tf->device = in_be32(ioaddr->device_addr);
347
348 if (tf->flags & ATA_TFLAG_LBA48) {
349 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
350 tf->hob_feature = in_be32(ioaddr->error_addr);
351 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
352 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
353 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
354 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
355 }
356}
357
358/**
359 * scc_exec_command - issue ATA command to host controller
360 * @ap: port to which command is being issued
361 * @tf: ATA taskfile register set
362 *
363 * Note: Original code is ata_exec_command().
364 */
365
366static void scc_exec_command (struct ata_port *ap,
367 const struct ata_taskfile *tf)
368{
Tejun Heo878d4fe2007-02-21 16:36:33 +0900369 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900370
371 out_be32(ap->ioaddr.command_addr, tf->command);
372 ata_pause(ap);
373}
374
375/**
376 * scc_check_altstatus - Read device alternate status reg
377 * @ap: port where the device is
378 */
379
380static u8 scc_check_altstatus (struct ata_port *ap)
381{
382 return in_be32(ap->ioaddr.altstatus_addr);
383}
384
385/**
386 * scc_std_dev_select - Select device 0/1 on ATA bus
387 * @ap: ATA channel to manipulate
388 * @device: ATA device (numbered from zero) to select
389 *
390 * Note: Original code is ata_std_dev_select().
391 */
392
393static void scc_std_dev_select (struct ata_port *ap, unsigned int device)
394{
395 u8 tmp;
396
397 if (device == 0)
398 tmp = ATA_DEVICE_OBS;
399 else
400 tmp = ATA_DEVICE_OBS | ATA_DEV1;
401
402 out_be32(ap->ioaddr.device_addr, tmp);
403 ata_pause(ap);
404}
405
406/**
407 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
408 * @qc: Info associated with this ATA transaction.
409 *
410 * Note: Original code is ata_bmdma_setup().
411 */
412
413static void scc_bmdma_setup (struct ata_queued_cmd *qc)
414{
415 struct ata_port *ap = qc->ap;
416 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
417 u8 dmactl;
418 void __iomem *mmio = ap->ioaddr.bmdma_addr;
419
420 /* load PRD table addr */
421 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
422
423 /* specify data direction, triple-check start bit is clear */
424 dmactl = in_be32(mmio + SCC_DMA_CMD);
425 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
426 if (!rw)
427 dmactl |= ATA_DMA_WR;
428 out_be32(mmio + SCC_DMA_CMD, dmactl);
429
430 /* issue r/w command */
431 ap->ops->exec_command(ap, &qc->tf);
432}
433
434/**
435 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
436 * @qc: Info associated with this ATA transaction.
437 *
438 * Note: Original code is ata_bmdma_start().
439 */
440
441static void scc_bmdma_start (struct ata_queued_cmd *qc)
442{
443 struct ata_port *ap = qc->ap;
444 u8 dmactl;
445 void __iomem *mmio = ap->ioaddr.bmdma_addr;
446
447 /* start host DMA transaction */
448 dmactl = in_be32(mmio + SCC_DMA_CMD);
449 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
450}
451
452/**
453 * scc_devchk - PATA device presence detection
454 * @ap: ATA channel to examine
455 * @device: Device to examine (starting at zero)
456 *
457 * Note: Original code is ata_devchk().
458 */
459
460static unsigned int scc_devchk (struct ata_port *ap,
461 unsigned int device)
462{
463 struct ata_ioports *ioaddr = &ap->ioaddr;
464 u8 nsect, lbal;
465
466 ap->ops->dev_select(ap, device);
467
468 out_be32(ioaddr->nsect_addr, 0x55);
469 out_be32(ioaddr->lbal_addr, 0xaa);
470
471 out_be32(ioaddr->nsect_addr, 0xaa);
472 out_be32(ioaddr->lbal_addr, 0x55);
473
474 out_be32(ioaddr->nsect_addr, 0x55);
475 out_be32(ioaddr->lbal_addr, 0xaa);
476
477 nsect = in_be32(ioaddr->nsect_addr);
478 lbal = in_be32(ioaddr->lbal_addr);
479
480 if ((nsect == 0x55) && (lbal == 0xaa))
481 return 1; /* we found a device */
482
483 return 0; /* nothing found */
484}
485
486/**
487 * scc_bus_post_reset - PATA device post reset
488 *
489 * Note: Original code is ata_bus_post_reset().
490 */
491
Tony Breeds7e068372007-05-23 14:26:43 -0700492static int scc_bus_post_reset(struct ata_port *ap, unsigned int devmask,
493 unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900494{
495 struct ata_ioports *ioaddr = &ap->ioaddr;
496 unsigned int dev0 = devmask & (1 << 0);
497 unsigned int dev1 = devmask & (1 << 1);
Tony Breeds7e068372007-05-23 14:26:43 -0700498 int rc;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900499
500 /* if device 0 was found in ata_devchk, wait for its
501 * BSY bit to clear
502 */
Tony Breeds7e068372007-05-23 14:26:43 -0700503 if (dev0) {
504 rc = ata_wait_ready(ap, deadline);
505 if (rc && rc != -ENODEV)
506 return rc;
507 }
Akira Iguchia619f981b2007-01-26 16:28:18 +0900508
509 /* if device 1 was found in ata_devchk, wait for
510 * register access, then wait for BSY to clear
511 */
Akira Iguchia619f981b2007-01-26 16:28:18 +0900512 while (dev1) {
513 u8 nsect, lbal;
514
515 ap->ops->dev_select(ap, 1);
516 nsect = in_be32(ioaddr->nsect_addr);
517 lbal = in_be32(ioaddr->lbal_addr);
518 if ((nsect == 1) && (lbal == 1))
519 break;
Tony Breeds7e068372007-05-23 14:26:43 -0700520 if (time_after(jiffies, deadline))
521 return -EBUSY;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900522 msleep(50); /* give drive a breather */
523 }
Tony Breeds7e068372007-05-23 14:26:43 -0700524 if (dev1) {
525 rc = ata_wait_ready(ap, deadline);
526 if (rc && rc != -ENODEV)
527 return rc;
528 }
Akira Iguchia619f981b2007-01-26 16:28:18 +0900529
530 /* is all this really necessary? */
531 ap->ops->dev_select(ap, 0);
532 if (dev1)
533 ap->ops->dev_select(ap, 1);
534 if (dev0)
535 ap->ops->dev_select(ap, 0);
Tony Breeds7e068372007-05-23 14:26:43 -0700536
537 return 0;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900538}
539
540/**
541 * scc_bus_softreset - PATA device software reset
542 *
543 * Note: Original code is ata_bus_softreset().
544 */
545
Tony Breeds7e068372007-05-23 14:26:43 -0700546static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
547 unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900548{
549 struct ata_ioports *ioaddr = &ap->ioaddr;
550
Tejun Heo878d4fe2007-02-21 16:36:33 +0900551 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900552
553 /* software reset. causes dev0 to be selected */
554 out_be32(ioaddr->ctl_addr, ap->ctl);
555 udelay(20);
556 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
557 udelay(20);
558 out_be32(ioaddr->ctl_addr, ap->ctl);
559
560 /* spec mandates ">= 2ms" before checking status.
561 * We wait 150ms, because that was the magic delay used for
562 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
563 * between when the ATA command register is written, and then
564 * status is checked. Because waiting for "a while" before
565 * checking status is fine, post SRST, we perform this magic
566 * delay here as well.
567 *
568 * Old drivers/ide uses the 2mS rule and then waits for ready
569 */
570 msleep(150);
571
572 /* Before we perform post reset processing we want to see if
573 * the bus shows 0xFF because the odd clown forgets the D7
574 * pulldown resistor.
575 */
576 if (scc_check_status(ap) == 0xFF)
577 return 0;
578
Tony Breeds7e068372007-05-23 14:26:43 -0700579 scc_bus_post_reset(ap, devmask, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900580
581 return 0;
582}
583
584/**
585 * scc_std_softreset - reset host port via ATA SRST
586 * @ap: port to reset
587 * @classes: resulting classes of attached devices
Tony Breeds7e068372007-05-23 14:26:43 -0700588 * @deadline: deadline jiffies for the operation
Akira Iguchia619f981b2007-01-26 16:28:18 +0900589 *
590 * Note: Original code is ata_std_softreset().
591 */
592
Tony Breeds7e068372007-05-23 14:26:43 -0700593static int scc_std_softreset (struct ata_port *ap, unsigned int *classes,
594 unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900595{
596 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
597 unsigned int devmask = 0, err_mask;
598 u8 err;
599
600 DPRINTK("ENTER\n");
601
602 if (ata_port_offline(ap)) {
603 classes[0] = ATA_DEV_NONE;
604 goto out;
605 }
606
607 /* determine if device 0/1 are present */
608 if (scc_devchk(ap, 0))
609 devmask |= (1 << 0);
610 if (slave_possible && scc_devchk(ap, 1))
611 devmask |= (1 << 1);
612
613 /* select device 0 again */
614 ap->ops->dev_select(ap, 0);
615
616 /* issue bus reset */
617 DPRINTK("about to softreset, devmask=%x\n", devmask);
Tony Breeds7e068372007-05-23 14:26:43 -0700618 err_mask = scc_bus_softreset(ap, devmask, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900619 if (err_mask) {
620 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
621 err_mask);
622 return -EIO;
623 }
624
625 /* determine by signature whether we have ATA or ATAPI devices */
626 classes[0] = ata_dev_try_classify(ap, 0, &err);
627 if (slave_possible && err != 0x81)
628 classes[1] = ata_dev_try_classify(ap, 1, &err);
629
630 out:
631 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
632 return 0;
633}
634
635/**
636 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
637 * @qc: Command we are ending DMA for
638 */
639
640static void scc_bmdma_stop (struct ata_queued_cmd *qc)
641{
642 struct ata_port *ap = qc->ap;
643 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
644 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
645 u32 reg;
646
647 while (1) {
648 reg = in_be32(bmid_base + SCC_DMA_INTST);
649
650 if (reg & INTSTS_SERROR) {
651 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
652 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
653 out_be32(bmid_base + SCC_DMA_CMD,
654 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
655 continue;
656 }
657
658 if (reg & INTSTS_PRERR) {
659 u32 maea0, maec0;
660 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
661 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
662 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
663 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
664 out_be32(bmid_base + SCC_DMA_CMD,
665 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
666 continue;
667 }
668
669 if (reg & INTSTS_RERR) {
670 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
671 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
672 out_be32(bmid_base + SCC_DMA_CMD,
673 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
674 continue;
675 }
676
677 if (reg & INTSTS_ICERR) {
678 out_be32(bmid_base + SCC_DMA_CMD,
679 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
680 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
681 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
682 continue;
683 }
684
685 if (reg & INTSTS_BMSINT) {
686 unsigned int classes;
Tony Breeds7e068372007-05-23 14:26:43 -0700687 unsigned long deadline = jiffies + ATA_TMOUT_BOOT;
Akira Iguchia619f981b2007-01-26 16:28:18 +0900688 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
689 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
690 /* TBD: SW reset */
Tony Breeds7e068372007-05-23 14:26:43 -0700691 scc_std_softreset(ap, &classes, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900692 continue;
693 }
694
695 if (reg & INTSTS_BMHE) {
696 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
697 continue;
698 }
699
700 if (reg & INTSTS_ACTEINT) {
701 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
702 continue;
703 }
704
705 if (reg & INTSTS_IOIRQS) {
706 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
707 continue;
708 }
709 break;
710 }
711
712 /* clear start/stop bit */
713 out_be32(bmid_base + SCC_DMA_CMD,
714 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
715
716 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
717 ata_altstatus(ap); /* dummy read */
718}
719
720/**
721 * scc_bmdma_status - Read PCI IDE BMDMA status
722 * @ap: Port associated with this ATA transaction.
723 */
724
725static u8 scc_bmdma_status (struct ata_port *ap)
726{
727 u8 host_stat;
728 void __iomem *mmio = ap->ioaddr.bmdma_addr;
729
730 host_stat = in_be32(mmio + SCC_DMA_STATUS);
731
Jeff Garzika84471f2007-02-26 05:51:33 -0500732 /* Workaround for PTERADD: emulate DMA_INTR when
Akira Iguchia619f981b2007-01-26 16:28:18 +0900733 * - IDE_STATUS[ERR] = 1
734 * - INT_STATUS[INTRQ] = 1
735 * - DMA_STATUS[IORACTA] = 1
736 */
737 if (!(host_stat & ATA_DMA_INTR)) {
738 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
739 if (ata_altstatus(ap) & ATA_ERR &&
740 int_status & INTSTS_INTRQ &&
741 host_stat & ATA_DMA_ACTIVE)
742 host_stat |= ATA_DMA_INTR;
743 }
744
745 return host_stat;
746}
747
748/**
749 * scc_data_xfer - Transfer data by PIO
750 * @adev: device for this I/O
751 * @buf: data buffer
752 * @buflen: buffer length
753 * @write_data: read/write
754 *
755 * Note: Original code is ata_data_xfer().
756 */
757
758static void scc_data_xfer (struct ata_device *adev, unsigned char *buf,
759 unsigned int buflen, int write_data)
760{
761 struct ata_port *ap = adev->ap;
762 unsigned int words = buflen >> 1;
763 unsigned int i;
764 u16 *buf16 = (u16 *) buf;
765 void __iomem *mmio = ap->ioaddr.data_addr;
766
767 /* Transfer multiple of 2 bytes */
768 if (write_data) {
769 for (i = 0; i < words; i++)
770 out_be32(mmio, cpu_to_le16(buf16[i]));
771 } else {
772 for (i = 0; i < words; i++)
773 buf16[i] = le16_to_cpu(in_be32(mmio));
774 }
775
776 /* Transfer trailing 1 byte, if any. */
777 if (unlikely(buflen & 0x01)) {
778 u16 align_buf[1] = { 0 };
779 unsigned char *trailing_buf = buf + buflen - 1;
780
781 if (write_data) {
782 memcpy(align_buf, trailing_buf, 1);
783 out_be32(mmio, cpu_to_le16(align_buf[0]));
784 } else {
785 align_buf[0] = le16_to_cpu(in_be32(mmio));
786 memcpy(trailing_buf, align_buf, 1);
787 }
788 }
789}
790
791/**
792 * scc_irq_on - Enable interrupts on a port.
793 * @ap: Port on which interrupts are enabled.
794 *
795 * Note: Original code is ata_irq_on().
796 */
797
798static u8 scc_irq_on (struct ata_port *ap)
799{
800 struct ata_ioports *ioaddr = &ap->ioaddr;
801 u8 tmp;
802
803 ap->ctl &= ~ATA_NIEN;
804 ap->last_ctl = ap->ctl;
805
806 out_be32(ioaddr->ctl_addr, ap->ctl);
807 tmp = ata_wait_idle(ap);
808
809 ap->ops->irq_clear(ap);
810
811 return tmp;
812}
813
814/**
815 * scc_irq_ack - Acknowledge a device interrupt.
816 * @ap: Port on which interrupts are enabled.
817 *
818 * Note: Original code is ata_irq_ack().
819 */
820
821static u8 scc_irq_ack (struct ata_port *ap, unsigned int chk_drq)
822{
823 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
824 u8 host_stat, post_stat, status;
825
826 status = ata_busy_wait(ap, bits, 1000);
827 if (status & bits)
828 if (ata_msg_err(ap))
829 printk(KERN_ERR "abnormal status 0x%X\n", status);
830
831 /* get controller status; clear intr, err bits */
832 host_stat = in_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS);
833 out_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS,
834 host_stat | ATA_DMA_INTR | ATA_DMA_ERR);
835
836 post_stat = in_be32(ap->ioaddr.bmdma_addr + SCC_DMA_STATUS);
837
838 if (ata_msg_intr(ap))
839 printk(KERN_INFO "%s: irq ack: host_stat 0x%X, new host_stat 0x%X, drv_stat 0x%X\n",
840 __FUNCTION__,
841 host_stat, post_stat, status);
842
843 return status;
844}
845
846/**
847 * scc_bmdma_freeze - Freeze BMDMA controller port
848 * @ap: port to freeze
849 *
850 * Note: Original code is ata_bmdma_freeze().
851 */
852
853static void scc_bmdma_freeze (struct ata_port *ap)
854{
855 struct ata_ioports *ioaddr = &ap->ioaddr;
856
857 ap->ctl |= ATA_NIEN;
858 ap->last_ctl = ap->ctl;
859
860 out_be32(ioaddr->ctl_addr, ap->ctl);
861
862 /* Under certain circumstances, some controllers raise IRQ on
863 * ATA_NIEN manipulation. Also, many controllers fail to mask
864 * previously pending IRQ on ATA_NIEN assertion. Clear it.
865 */
866 ata_chk_status(ap);
867
868 ap->ops->irq_clear(ap);
869}
870
871/**
872 * scc_pata_prereset - prepare for reset
873 * @ap: ATA port to be reset
Tony Breeds7e068372007-05-23 14:26:43 -0700874 * @deadline: deadline jiffies for the operation
Akira Iguchia619f981b2007-01-26 16:28:18 +0900875 */
876
Tony Breeds7e068372007-05-23 14:26:43 -0700877static int scc_pata_prereset(struct ata_port *ap, unsigned long deadline)
Akira Iguchia619f981b2007-01-26 16:28:18 +0900878{
879 ap->cbl = ATA_CBL_PATA80;
Al Virod1c68fa2007-05-15 08:21:17 +0100880 return ata_std_prereset(ap, deadline);
Akira Iguchia619f981b2007-01-26 16:28:18 +0900881}
882
883/**
884 * scc_std_postreset - standard postreset callback
885 * @ap: the target ata_port
886 * @classes: classes of attached devices
887 *
888 * Note: Original code is ata_std_postreset().
889 */
890
891static void scc_std_postreset (struct ata_port *ap, unsigned int *classes)
892{
893 DPRINTK("ENTER\n");
894
895 /* re-enable interrupts */
896 if (!ap->ops->error_handler)
897 ap->ops->irq_on(ap);
898
899 /* is double-select really necessary? */
900 if (classes[0] != ATA_DEV_NONE)
901 ap->ops->dev_select(ap, 1);
902 if (classes[1] != ATA_DEV_NONE)
903 ap->ops->dev_select(ap, 0);
904
905 /* bail out if no device is present */
906 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
907 DPRINTK("EXIT, no device\n");
908 return;
909 }
910
911 /* set up device control */
912 if (ap->ioaddr.ctl_addr)
913 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
914
915 DPRINTK("EXIT\n");
916}
917
918/**
919 * scc_error_handler - Stock error handler for BMDMA controller
920 * @ap: port to handle error for
921 */
922
923static void scc_error_handler (struct ata_port *ap)
924{
925 ata_bmdma_drive_eh(ap, scc_pata_prereset, scc_std_softreset, NULL,
926 scc_std_postreset);
927}
928
929/**
930 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
931 * @ap: Port associated with this ATA transaction.
932 *
933 * Note: Original code is ata_bmdma_irq_clear().
934 */
935
936static void scc_bmdma_irq_clear (struct ata_port *ap)
937{
938 void __iomem *mmio = ap->ioaddr.bmdma_addr;
939
940 if (!mmio)
941 return;
942
943 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
944}
945
946/**
947 * scc_port_start - Set port up for dma.
948 * @ap: Port to initialize
949 *
950 * Allocate space for PRD table using ata_port_start().
951 * Set PRD table address for PTERADD. (PRD Transfer End Read)
952 */
953
954static int scc_port_start (struct ata_port *ap)
955{
956 void __iomem *mmio = ap->ioaddr.bmdma_addr;
957 int rc;
958
959 rc = ata_port_start(ap);
960 if (rc)
961 return rc;
962
963 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
964 return 0;
965}
966
967/**
968 * scc_port_stop - Undo scc_port_start()
969 * @ap: Port to shut down
970 *
971 * Reset PTERADD.
972 */
973
974static void scc_port_stop (struct ata_port *ap)
975{
976 void __iomem *mmio = ap->ioaddr.bmdma_addr;
977
978 out_be32(mmio + SCC_DMA_PTERADD, 0);
979}
980
981static struct scsi_host_template scc_sht = {
982 .module = THIS_MODULE,
983 .name = DRV_NAME,
984 .ioctl = ata_scsi_ioctl,
985 .queuecommand = ata_scsi_queuecmd,
986 .can_queue = ATA_DEF_QUEUE,
987 .this_id = ATA_SHT_THIS_ID,
988 .sg_tablesize = LIBATA_MAX_PRD,
989 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
990 .emulated = ATA_SHT_EMULATED,
991 .use_clustering = ATA_SHT_USE_CLUSTERING,
992 .proc_name = DRV_NAME,
993 .dma_boundary = ATA_DMA_BOUNDARY,
994 .slave_configure = ata_scsi_slave_config,
995 .slave_destroy = ata_scsi_slave_destroy,
996 .bios_param = ata_std_bios_param,
Akira Iguchia619f981b2007-01-26 16:28:18 +0900997};
998
999static const struct ata_port_operations scc_pata_ops = {
1000 .port_disable = ata_port_disable,
1001 .set_piomode = scc_set_piomode,
1002 .set_dmamode = scc_set_dmamode,
1003 .mode_filter = ata_pci_default_filter,
1004
1005 .tf_load = scc_tf_load,
1006 .tf_read = scc_tf_read,
1007 .exec_command = scc_exec_command,
1008 .check_status = scc_check_status,
1009 .check_altstatus = scc_check_altstatus,
1010 .dev_select = scc_std_dev_select,
1011
1012 .bmdma_setup = scc_bmdma_setup,
1013 .bmdma_start = scc_bmdma_start,
1014 .bmdma_stop = scc_bmdma_stop,
1015 .bmdma_status = scc_bmdma_status,
1016 .data_xfer = scc_data_xfer,
1017
1018 .qc_prep = ata_qc_prep,
1019 .qc_issue = ata_qc_issue_prot,
1020
1021 .freeze = scc_bmdma_freeze,
1022 .error_handler = scc_error_handler,
1023 .post_internal_cmd = scc_bmdma_stop,
1024
Akira Iguchia619f981b2007-01-26 16:28:18 +09001025 .irq_clear = scc_bmdma_irq_clear,
1026 .irq_on = scc_irq_on,
1027 .irq_ack = scc_irq_ack,
1028
1029 .port_start = scc_port_start,
1030 .port_stop = scc_port_stop,
1031};
1032
1033static struct ata_port_info scc_port_info[] = {
1034 {
Akira Iguchia619f981b2007-01-26 16:28:18 +09001035 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1036 .pio_mask = 0x1f, /* pio0-4 */
1037 .mwdma_mask = 0x00,
1038 .udma_mask = ATA_UDMA6,
1039 .port_ops = &scc_pata_ops,
1040 },
1041};
1042
1043/**
1044 * scc_reset_controller - initialize SCC PATA controller.
1045 */
1046
Tejun Heo5d728822007-04-17 23:44:08 +09001047static int scc_reset_controller(struct ata_host *host)
Akira Iguchia619f981b2007-01-26 16:28:18 +09001048{
Tejun Heo5d728822007-04-17 23:44:08 +09001049 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1050 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
Akira Iguchia619f981b2007-01-26 16:28:18 +09001051 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1052 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1053 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1054 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1055 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1056 u32 reg = 0;
1057
1058 out_be32(cckctrl_port, reg);
1059 reg |= CCKCTRL_ATACLKOEN;
1060 out_be32(cckctrl_port, reg);
1061 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1062 out_be32(cckctrl_port, reg);
1063 reg |= CCKCTRL_CRST;
1064 out_be32(cckctrl_port, reg);
1065
1066 for (;;) {
1067 reg = in_be32(cckctrl_port);
1068 if (reg & CCKCTRL_CRST)
1069 break;
1070 udelay(5000);
1071 }
1072
1073 reg |= CCKCTRL_ATARESET;
1074 out_be32(cckctrl_port, reg);
1075 out_be32(ecmode_port, ECMODE_VALUE);
1076 out_be32(mode_port, MODE_JCUSFEN);
1077 out_be32(intmask_port, INTMASK_MSK);
1078
1079 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1080 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1081 return -EIO;
1082 }
1083
1084 return 0;
1085}
1086
1087/**
1088 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1089 * @ioaddr: IO address structure to be initialized
1090 * @base: base address of BMID region
1091 */
1092
1093static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1094{
1095 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1096 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1097 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1098 ioaddr->bmdma_addr = base;
1099 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1100 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1101 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1102 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1103 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1104 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1105 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1106 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1107 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1108 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1109}
1110
Tejun Heo5d728822007-04-17 23:44:08 +09001111static int scc_host_init(struct ata_host *host)
Akira Iguchia619f981b2007-01-26 16:28:18 +09001112{
Tejun Heo5d728822007-04-17 23:44:08 +09001113 struct pci_dev *pdev = to_pci_dev(host->dev);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001114 int rc;
1115
Tejun Heo5d728822007-04-17 23:44:08 +09001116 rc = scc_reset_controller(host);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001117 if (rc)
1118 return rc;
1119
Akira Iguchia619f981b2007-01-26 16:28:18 +09001120 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1121 if (rc)
1122 return rc;
1123 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1124 if (rc)
1125 return rc;
1126
Tejun Heo5d728822007-04-17 23:44:08 +09001127 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001128
1129 pci_set_master(pdev);
1130
1131 return 0;
1132}
1133
1134/**
1135 * scc_init_one - Register SCC PATA device with kernel services
1136 * @pdev: PCI device to register
1137 * @ent: Entry in scc_pci_tbl matching with @pdev
1138 *
1139 * LOCKING:
1140 * Inherited from PCI layer (may sleep).
1141 *
1142 * RETURNS:
1143 * Zero on success, or -ERRNO value.
1144 */
1145
1146static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1147{
1148 static int printed_version;
1149 unsigned int board_idx = (unsigned int) ent->driver_data;
Tejun Heo5d728822007-04-17 23:44:08 +09001150 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
Alexey Dobriyan0397bad2007-05-03 23:44:59 +04001151 struct ata_host *host;
Akira Iguchia619f981b2007-01-26 16:28:18 +09001152 int rc;
1153
1154 if (!printed_version++)
1155 dev_printk(KERN_DEBUG, &pdev->dev,
1156 "version " DRV_VERSION "\n");
1157
Alexey Dobriyan0397bad2007-05-03 23:44:59 +04001158 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
Tejun Heo5d728822007-04-17 23:44:08 +09001159 if (!host)
1160 return -ENOMEM;
1161
Akira Iguchia619f981b2007-01-26 16:28:18 +09001162 rc = pcim_enable_device(pdev);
1163 if (rc)
1164 return rc;
1165
1166 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1167 if (rc == -EBUSY)
1168 pcim_pin_device(pdev);
1169 if (rc)
1170 return rc;
Tejun Heo5d728822007-04-17 23:44:08 +09001171 host->iomap = pcim_iomap_table(pdev);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001172
Tejun Heo5d728822007-04-17 23:44:08 +09001173 rc = scc_host_init(host);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001174 if (rc)
1175 return rc;
1176
Tejun Heo5d728822007-04-17 23:44:08 +09001177 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
1178 &scc_sht);
Akira Iguchia619f981b2007-01-26 16:28:18 +09001179}
1180
1181static struct pci_driver scc_pci_driver = {
1182 .name = DRV_NAME,
1183 .id_table = scc_pci_tbl,
1184 .probe = scc_init_one,
1185 .remove = ata_pci_remove_one,
1186#ifdef CONFIG_PM
1187 .suspend = ata_pci_device_suspend,
1188 .resume = ata_pci_device_resume,
1189#endif
1190};
1191
1192static int __init scc_init (void)
1193{
1194 int rc;
1195
1196 DPRINTK("pci_register_driver\n");
1197 rc = pci_register_driver(&scc_pci_driver);
1198 if (rc)
1199 return rc;
1200
1201 DPRINTK("done\n");
1202 return 0;
1203}
1204
1205static void __exit scc_exit (void)
1206{
1207 pci_unregister_driver(&scc_pci_driver);
1208}
1209
1210module_init(scc_init);
1211module_exit(scc_exit);
1212
1213MODULE_AUTHOR("Toshiba corp");
1214MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1215MODULE_LICENSE("GPL");
1216MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1217MODULE_VERSION(DRV_VERSION);