Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for OMAP3 SoC |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 11 | #include <dt-bindings/gpio/gpio.h> |
Florian Vaussard | 71fdc6e | 2013-06-11 16:49:46 +0200 | [diff] [blame] | 12 | #include <dt-bindings/interrupt-controller/irq.h> |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 13 | #include <dt-bindings/pinctrl/omap.h> |
Florian Vaussard | 6d624ea | 2013-05-31 14:32:56 +0200 | [diff] [blame] | 14 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 15 | #include "skeleton.dtsi" |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 16 | |
| 17 | / { |
| 18 | compatible = "ti,omap3430", "ti,omap3"; |
Benoit Cousson | 4c94ac2 | 2012-10-24 10:47:52 +0200 | [diff] [blame] | 19 | interrupt-parent = <&intc>; |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 20 | |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 21 | aliases { |
Nishanth Menon | 20b8094 | 2013-10-16 15:21:03 -0500 | [diff] [blame] | 22 | i2c0 = &i2c1; |
| 23 | i2c1 = &i2c2; |
| 24 | i2c2 = &i2c3; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 25 | serial0 = &uart1; |
| 26 | serial1 = &uart2; |
| 27 | serial2 = &uart3; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 28 | }; |
| 29 | |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 30 | cpus { |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 31 | #address-cells = <1>; |
| 32 | #size-cells = <0>; |
| 33 | |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 34 | cpu@0 { |
| 35 | compatible = "arm,cortex-a8"; |
Lorenzo Pieralisi | eeb25fd | 2013-04-18 18:35:59 +0100 | [diff] [blame] | 36 | device_type = "cpu"; |
| 37 | reg = <0x0>; |
Nishanth Menon | 8d766fa | 2014-01-29 12:19:17 -0600 | [diff] [blame] | 38 | |
| 39 | clocks = <&dpll1_ck>; |
| 40 | clock-names = "cpu"; |
| 41 | |
| 42 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 43 | }; |
| 44 | }; |
| 45 | |
Jon Hunter | 9b07b47 | 2012-10-18 09:28:52 -0500 | [diff] [blame] | 46 | pmu { |
| 47 | compatible = "arm,cortex-a8-pmu"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 48 | reg = <0x54000000 0x800000>; |
Jon Hunter | 9b07b47 | 2012-10-18 09:28:52 -0500 | [diff] [blame] | 49 | interrupts = <3>; |
| 50 | ti,hwmods = "debugss"; |
| 51 | }; |
| 52 | |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 53 | /* |
Christoph Fritz | 161e89a | 2013-03-29 17:32:05 +0100 | [diff] [blame] | 54 | * The soc node represents the soc top level view. It is used for IPs |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 55 | * that are not memory mapped in the MPU view or for the MPU itself. |
| 56 | */ |
| 57 | soc { |
| 58 | compatible = "ti,omap-infra"; |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 59 | mpu { |
| 60 | compatible = "ti,omap3-mpu"; |
| 61 | ti,hwmods = "mpu"; |
| 62 | }; |
| 63 | |
Suman Anna | 4c05160 | 2014-04-22 17:23:37 -0500 | [diff] [blame] | 64 | iva: iva { |
Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 65 | compatible = "ti,iva2.2"; |
| 66 | ti,hwmods = "iva"; |
| 67 | |
| 68 | dsp { |
| 69 | compatible = "ti,omap3-c64"; |
| 70 | }; |
| 71 | }; |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | /* |
| 75 | * XXX: Use a flat representation of the OMAP3 interconnect. |
| 76 | * The real OMAP interconnect network is quite complex. |
Geert Uytterhoeven | b7ab524 | 2014-03-28 11:11:39 +0100 | [diff] [blame] | 77 | * Since it will not bring real advantage to represent that in DT for |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 78 | * the moment, just use a fake OCP bus entry to represent the whole bus |
| 79 | * hierarchy. |
| 80 | */ |
| 81 | ocp { |
Tony Lindgren | aa25729c | 2014-11-05 09:21:23 -0800 | [diff] [blame] | 82 | compatible = "ti,omap3-l3-smx", "simple-bus"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 83 | reg = <0x68000000 0x10000>; |
| 84 | interrupts = <9 10>; |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 85 | #address-cells = <1>; |
| 86 | #size-cells = <1>; |
| 87 | ranges; |
| 88 | ti,hwmods = "l3_main"; |
| 89 | |
Tero Kristo | b884507 | 2015-02-24 16:22:45 +0200 | [diff] [blame] | 90 | l4_core: l4@48000000 { |
| 91 | compatible = "ti,omap3-l4-core", "simple-bus"; |
| 92 | #address-cells = <1>; |
| 93 | #size-cells = <1>; |
| 94 | ranges = <0 0x48000000 0x1000000>; |
| 95 | |
| 96 | scm: scm@2000 { |
| 97 | compatible = "ti,omap3-scm", "simple-bus"; |
| 98 | reg = <0x2000 0x2000>; |
| 99 | #address-cells = <1>; |
| 100 | #size-cells = <1>; |
| 101 | ranges = <0 0x2000 0x2000>; |
| 102 | |
| 103 | omap3_pmx_core: pinmux@30 { |
| 104 | compatible = "ti,omap3-padconf", |
| 105 | "pinctrl-single"; |
| 106 | reg = <0x30 0x238>; |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | #interrupt-cells = <1>; |
| 110 | interrupt-controller; |
| 111 | pinctrl-single,register-width = <16>; |
| 112 | pinctrl-single,function-mask = <0xff1f>; |
| 113 | }; |
| 114 | |
| 115 | scm_conf: scm_conf@270 { |
| 116 | compatible = "syscon"; |
| 117 | reg = <0x270 0x330>; |
| 118 | #address-cells = <1>; |
| 119 | #size-cells = <1>; |
| 120 | |
| 121 | scm_clocks: clocks { |
| 122 | #address-cells = <1>; |
| 123 | #size-cells = <0>; |
| 124 | }; |
| 125 | }; |
| 126 | |
| 127 | scm_clockdomains: clockdomains { |
| 128 | }; |
| 129 | |
| 130 | omap3_pmx_wkup: pinmux@a00 { |
| 131 | compatible = "ti,omap3-padconf", |
| 132 | "pinctrl-single"; |
| 133 | reg = <0xa00 0x5c>; |
| 134 | #address-cells = <1>; |
| 135 | #size-cells = <0>; |
| 136 | #interrupt-cells = <1>; |
| 137 | interrupt-controller; |
| 138 | pinctrl-single,register-width = <16>; |
| 139 | pinctrl-single,function-mask = <0xff1f>; |
| 140 | }; |
| 141 | }; |
| 142 | }; |
| 143 | |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 144 | aes: aes@480c5000 { |
| 145 | compatible = "ti,omap3-aes"; |
| 146 | ti,hwmods = "aes"; |
| 147 | reg = <0x480c5000 0x50>; |
| 148 | interrupts = <0>; |
Pali Rohár | d6e5b7c | 2015-02-26 14:49:56 +0100 | [diff] [blame] | 149 | dmas = <&sdma 65 &sdma 66>; |
| 150 | dma-names = "tx", "rx"; |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 151 | }; |
| 152 | |
Tero Kristo | 657fc11 | 2013-07-22 12:29:29 +0300 | [diff] [blame] | 153 | prm: prm@48306000 { |
| 154 | compatible = "ti,omap3-prm"; |
| 155 | reg = <0x48306000 0x4000>; |
Nishanth Menon | 5081ce6 | 2014-08-22 09:03:50 -0500 | [diff] [blame] | 156 | interrupts = <11>; |
Tero Kristo | 657fc11 | 2013-07-22 12:29:29 +0300 | [diff] [blame] | 157 | |
| 158 | prm_clocks: clocks { |
| 159 | #address-cells = <1>; |
| 160 | #size-cells = <0>; |
| 161 | }; |
| 162 | |
| 163 | prm_clockdomains: clockdomains { |
| 164 | }; |
| 165 | }; |
| 166 | |
| 167 | cm: cm@48004000 { |
| 168 | compatible = "ti,omap3-cm"; |
| 169 | reg = <0x48004000 0x4000>; |
| 170 | |
| 171 | cm_clocks: clocks { |
| 172 | #address-cells = <1>; |
| 173 | #size-cells = <0>; |
| 174 | }; |
| 175 | |
| 176 | cm_clockdomains: clockdomains { |
| 177 | }; |
| 178 | }; |
| 179 | |
Jon Hunter | 510c0ff | 2012-10-25 14:24:14 -0500 | [diff] [blame] | 180 | counter32k: counter@48320000 { |
| 181 | compatible = "ti,omap-counter32k"; |
| 182 | reg = <0x48320000 0x20>; |
| 183 | ti,hwmods = "counter_32k"; |
| 184 | }; |
| 185 | |
Benoit Cousson | d65c542 | 2011-11-30 19:26:42 +0100 | [diff] [blame] | 186 | intc: interrupt-controller@48200000 { |
Felipe Balbi | cab82b7 | 2014-09-08 17:54:48 -0700 | [diff] [blame] | 187 | compatible = "ti,omap3-intc"; |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 188 | interrupt-controller; |
| 189 | #interrupt-cells = <1>; |
Benoit Cousson | d65c542 | 2011-11-30 19:26:42 +0100 | [diff] [blame] | 190 | reg = <0x48200000 0x1000>; |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 191 | }; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 192 | |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 193 | sdma: dma-controller@48056000 { |
| 194 | compatible = "ti,omap3630-sdma", "ti,omap3430-sdma"; |
| 195 | reg = <0x48056000 0x1000>; |
| 196 | interrupts = <12>, |
| 197 | <13>, |
| 198 | <14>, |
| 199 | <15>; |
| 200 | #dma-cells = <1>; |
Peter Ujfalusi | 7e8d25d | 2015-02-20 15:42:03 +0200 | [diff] [blame] | 201 | dma-channels = <32>; |
| 202 | dma-requests = <96>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 203 | }; |
| 204 | |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 205 | pbias_regulator: pbias_regulator { |
| 206 | compatible = "ti,pbias-omap"; |
| 207 | reg = <0x2b0 0x4>; |
Tero Kristo | b884507 | 2015-02-24 16:22:45 +0200 | [diff] [blame] | 208 | syscon = <&scm_conf>; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 209 | pbias_mmc_reg: pbias_mmc_omap2430 { |
| 210 | regulator-name = "pbias_mmc_omap2430"; |
| 211 | regulator-min-microvolt = <1800000>; |
| 212 | regulator-max-microvolt = <3000000>; |
| 213 | }; |
| 214 | }; |
| 215 | |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 216 | gpio1: gpio@48310000 { |
| 217 | compatible = "ti,omap3-gpio"; |
Jon Hunter | e299185 | 2013-03-07 16:02:31 -0600 | [diff] [blame] | 218 | reg = <0x48310000 0x200>; |
| 219 | interrupts = <29>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 220 | ti,hwmods = "gpio1"; |
Jon Hunter | e4b9b9f | 2013-04-04 15:16:16 -0500 | [diff] [blame] | 221 | ti,gpio-always-on; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 222 | gpio-controller; |
| 223 | #gpio-cells = <2>; |
| 224 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 225 | #interrupt-cells = <2>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | gpio2: gpio@49050000 { |
| 229 | compatible = "ti,omap3-gpio"; |
Jon Hunter | e299185 | 2013-03-07 16:02:31 -0600 | [diff] [blame] | 230 | reg = <0x49050000 0x200>; |
| 231 | interrupts = <30>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 232 | ti,hwmods = "gpio2"; |
| 233 | gpio-controller; |
| 234 | #gpio-cells = <2>; |
| 235 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 236 | #interrupt-cells = <2>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 237 | }; |
| 238 | |
| 239 | gpio3: gpio@49052000 { |
| 240 | compatible = "ti,omap3-gpio"; |
Jon Hunter | e299185 | 2013-03-07 16:02:31 -0600 | [diff] [blame] | 241 | reg = <0x49052000 0x200>; |
| 242 | interrupts = <31>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 243 | ti,hwmods = "gpio3"; |
| 244 | gpio-controller; |
| 245 | #gpio-cells = <2>; |
| 246 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 247 | #interrupt-cells = <2>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | gpio4: gpio@49054000 { |
| 251 | compatible = "ti,omap3-gpio"; |
Jon Hunter | e299185 | 2013-03-07 16:02:31 -0600 | [diff] [blame] | 252 | reg = <0x49054000 0x200>; |
| 253 | interrupts = <32>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 254 | ti,hwmods = "gpio4"; |
| 255 | gpio-controller; |
| 256 | #gpio-cells = <2>; |
| 257 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 258 | #interrupt-cells = <2>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | gpio5: gpio@49056000 { |
| 262 | compatible = "ti,omap3-gpio"; |
Jon Hunter | e299185 | 2013-03-07 16:02:31 -0600 | [diff] [blame] | 263 | reg = <0x49056000 0x200>; |
| 264 | interrupts = <33>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 265 | ti,hwmods = "gpio5"; |
| 266 | gpio-controller; |
| 267 | #gpio-cells = <2>; |
| 268 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 269 | #interrupt-cells = <2>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 270 | }; |
| 271 | |
| 272 | gpio6: gpio@49058000 { |
| 273 | compatible = "ti,omap3-gpio"; |
Jon Hunter | e299185 | 2013-03-07 16:02:31 -0600 | [diff] [blame] | 274 | reg = <0x49058000 0x200>; |
| 275 | interrupts = <34>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 276 | ti,hwmods = "gpio6"; |
| 277 | gpio-controller; |
| 278 | #gpio-cells = <2>; |
| 279 | interrupt-controller; |
Jon Hunter | ff5c905 | 2013-03-07 15:44:39 -0600 | [diff] [blame] | 280 | #interrupt-cells = <2>; |
Benoit Cousson | 385a64b | 2011-08-16 11:51:54 +0200 | [diff] [blame] | 281 | }; |
| 282 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 283 | uart1: serial@4806a000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 284 | compatible = "ti,omap3-uart"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 285 | reg = <0x4806a000 0x2000>; |
Tony Lindgren | 31f0820 | 2014-05-05 17:27:39 -0700 | [diff] [blame] | 286 | interrupts-extended = <&intc 72>; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 287 | dmas = <&sdma 49 &sdma 50>; |
| 288 | dma-names = "tx", "rx"; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 289 | ti,hwmods = "uart1"; |
| 290 | clock-frequency = <48000000>; |
| 291 | }; |
| 292 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 293 | uart2: serial@4806c000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 294 | compatible = "ti,omap3-uart"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 295 | reg = <0x4806c000 0x400>; |
Tony Lindgren | 31f0820 | 2014-05-05 17:27:39 -0700 | [diff] [blame] | 296 | interrupts-extended = <&intc 73>; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 297 | dmas = <&sdma 51 &sdma 52>; |
| 298 | dma-names = "tx", "rx"; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 299 | ti,hwmods = "uart2"; |
| 300 | clock-frequency = <48000000>; |
| 301 | }; |
| 302 | |
Benoit Cousson | 19bfb76 | 2012-02-16 11:55:27 +0100 | [diff] [blame] | 303 | uart3: serial@49020000 { |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 304 | compatible = "ti,omap3-uart"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 305 | reg = <0x49020000 0x400>; |
Tony Lindgren | 31f0820 | 2014-05-05 17:27:39 -0700 | [diff] [blame] | 306 | interrupts-extended = <&intc 74>; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 307 | dmas = <&sdma 53 &sdma 54>; |
| 308 | dma-names = "tx", "rx"; |
Rajendra Nayak | cf3c79d | 2011-12-14 17:25:46 +0530 | [diff] [blame] | 309 | ti,hwmods = "uart3"; |
| 310 | clock-frequency = <48000000>; |
| 311 | }; |
| 312 | |
Benoit Cousson | ca59a5c | 2011-08-30 16:50:24 +0200 | [diff] [blame] | 313 | i2c1: i2c@48070000 { |
| 314 | compatible = "ti,omap3-i2c"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 315 | reg = <0x48070000 0x80>; |
| 316 | interrupts = <56>; |
| 317 | dmas = <&sdma 27 &sdma 28>; |
| 318 | dma-names = "tx", "rx"; |
Benoit Cousson | ca59a5c | 2011-08-30 16:50:24 +0200 | [diff] [blame] | 319 | #address-cells = <1>; |
| 320 | #size-cells = <0>; |
| 321 | ti,hwmods = "i2c1"; |
| 322 | }; |
| 323 | |
| 324 | i2c2: i2c@48072000 { |
| 325 | compatible = "ti,omap3-i2c"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 326 | reg = <0x48072000 0x80>; |
| 327 | interrupts = <57>; |
| 328 | dmas = <&sdma 29 &sdma 30>; |
| 329 | dma-names = "tx", "rx"; |
Benoit Cousson | ca59a5c | 2011-08-30 16:50:24 +0200 | [diff] [blame] | 330 | #address-cells = <1>; |
| 331 | #size-cells = <0>; |
| 332 | ti,hwmods = "i2c2"; |
| 333 | }; |
| 334 | |
| 335 | i2c3: i2c@48060000 { |
| 336 | compatible = "ti,omap3-i2c"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 337 | reg = <0x48060000 0x80>; |
| 338 | interrupts = <61>; |
| 339 | dmas = <&sdma 25 &sdma 26>; |
| 340 | dma-names = "tx", "rx"; |
Benoit Cousson | ca59a5c | 2011-08-30 16:50:24 +0200 | [diff] [blame] | 341 | #address-cells = <1>; |
| 342 | #size-cells = <0>; |
| 343 | ti,hwmods = "i2c3"; |
| 344 | }; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 345 | |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 346 | mailbox: mailbox@48094000 { |
| 347 | compatible = "ti,omap3-mailbox"; |
| 348 | ti,hwmods = "mailbox"; |
| 349 | reg = <0x48094000 0x200>; |
| 350 | interrupts = <26>; |
Suman Anna | 24df045 | 2014-11-03 17:07:35 -0600 | [diff] [blame] | 351 | #mbox-cells = <1>; |
Suman Anna | 41ffada | 2014-07-11 16:44:34 -0500 | [diff] [blame] | 352 | ti,mbox-num-users = <2>; |
| 353 | ti,mbox-num-fifos = <2>; |
Suman Anna | d27704d | 2014-09-10 14:27:23 -0500 | [diff] [blame] | 354 | mbox_dsp: dsp { |
| 355 | ti,mbox-tx = <0 0 0>; |
| 356 | ti,mbox-rx = <1 0 0>; |
| 357 | }; |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 358 | }; |
| 359 | |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 360 | mcspi1: spi@48098000 { |
| 361 | compatible = "ti,omap2-mcspi"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 362 | reg = <0x48098000 0x100>; |
| 363 | interrupts = <65>; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 364 | #address-cells = <1>; |
| 365 | #size-cells = <0>; |
| 366 | ti,hwmods = "mcspi1"; |
| 367 | ti,spi-num-cs = <4>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 368 | dmas = <&sdma 35>, |
| 369 | <&sdma 36>, |
| 370 | <&sdma 37>, |
| 371 | <&sdma 38>, |
| 372 | <&sdma 39>, |
| 373 | <&sdma 40>, |
| 374 | <&sdma 41>, |
| 375 | <&sdma 42>; |
| 376 | dma-names = "tx0", "rx0", "tx1", "rx1", |
| 377 | "tx2", "rx2", "tx3", "rx3"; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 378 | }; |
| 379 | |
| 380 | mcspi2: spi@4809a000 { |
| 381 | compatible = "ti,omap2-mcspi"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 382 | reg = <0x4809a000 0x100>; |
| 383 | interrupts = <66>; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 384 | #address-cells = <1>; |
| 385 | #size-cells = <0>; |
| 386 | ti,hwmods = "mcspi2"; |
| 387 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 388 | dmas = <&sdma 43>, |
| 389 | <&sdma 44>, |
| 390 | <&sdma 45>, |
| 391 | <&sdma 46>; |
| 392 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 393 | }; |
| 394 | |
| 395 | mcspi3: spi@480b8000 { |
| 396 | compatible = "ti,omap2-mcspi"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 397 | reg = <0x480b8000 0x100>; |
| 398 | interrupts = <91>; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 399 | #address-cells = <1>; |
| 400 | #size-cells = <0>; |
| 401 | ti,hwmods = "mcspi3"; |
| 402 | ti,spi-num-cs = <2>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 403 | dmas = <&sdma 15>, |
| 404 | <&sdma 16>, |
| 405 | <&sdma 23>, |
| 406 | <&sdma 24>; |
| 407 | dma-names = "tx0", "rx0", "tx1", "rx1"; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 408 | }; |
| 409 | |
| 410 | mcspi4: spi@480ba000 { |
| 411 | compatible = "ti,omap2-mcspi"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 412 | reg = <0x480ba000 0x100>; |
| 413 | interrupts = <48>; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 414 | #address-cells = <1>; |
| 415 | #size-cells = <0>; |
| 416 | ti,hwmods = "mcspi4"; |
| 417 | ti,spi-num-cs = <1>; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 418 | dmas = <&sdma 70>, <&sdma 71>; |
| 419 | dma-names = "tx0", "rx0"; |
Benoit Cousson | fc72d24 | 2012-01-20 14:15:58 +0100 | [diff] [blame] | 420 | }; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 421 | |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 422 | hdqw1w: 1w@480b2000 { |
| 423 | compatible = "ti,omap3-1w"; |
| 424 | reg = <0x480b2000 0x1000>; |
| 425 | interrupts = <58>; |
| 426 | ti,hwmods = "hdq1w"; |
| 427 | }; |
| 428 | |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 429 | mmc1: mmc@4809c000 { |
| 430 | compatible = "ti,omap3-hsmmc"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 431 | reg = <0x4809c000 0x200>; |
| 432 | interrupts = <83>; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 433 | ti,hwmods = "mmc1"; |
| 434 | ti,dual-volt; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 435 | dmas = <&sdma 61>, <&sdma 62>; |
| 436 | dma-names = "tx", "rx"; |
Balaji T K | cd042fe | 2014-02-19 20:26:40 +0530 | [diff] [blame] | 437 | pbias-supply = <&pbias_mmc_reg>; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | mmc2: mmc@480b4000 { |
| 441 | compatible = "ti,omap3-hsmmc"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 442 | reg = <0x480b4000 0x200>; |
| 443 | interrupts = <86>; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 444 | ti,hwmods = "mmc2"; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 445 | dmas = <&sdma 47>, <&sdma 48>; |
| 446 | dma-names = "tx", "rx"; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 447 | }; |
| 448 | |
| 449 | mmc3: mmc@480ad000 { |
| 450 | compatible = "ti,omap3-hsmmc"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 451 | reg = <0x480ad000 0x200>; |
| 452 | interrupts = <94>; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 453 | ti,hwmods = "mmc3"; |
Jon Hunter | 2c2dc54 | 2012-04-26 13:47:59 -0500 | [diff] [blame] | 454 | dmas = <&sdma 77>, <&sdma 78>; |
| 455 | dma-names = "tx", "rx"; |
Rajendra Nayak | b3431f5 | 2012-02-22 17:42:27 +0530 | [diff] [blame] | 456 | }; |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 457 | |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 458 | mmu_isp: mmu@480bd400 { |
Florian Vaussard | b7cd959 | 2014-03-05 18:24:16 -0600 | [diff] [blame] | 459 | compatible = "ti,omap2-iommu"; |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 460 | reg = <0x480bd400 0x80>; |
Florian Vaussard | b7cd959 | 2014-03-05 18:24:16 -0600 | [diff] [blame] | 461 | interrupts = <24>; |
| 462 | ti,hwmods = "mmu_isp"; |
| 463 | ti,#tlb-entries = <8>; |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 464 | }; |
| 465 | |
Florian Vaussard | 40ac051 | 2014-03-05 18:24:17 -0600 | [diff] [blame] | 466 | mmu_iva: mmu@5d000000 { |
| 467 | compatible = "ti,omap2-iommu"; |
| 468 | reg = <0x5d000000 0x80>; |
| 469 | interrupts = <28>; |
| 470 | ti,hwmods = "mmu_iva"; |
| 471 | status = "disabled"; |
| 472 | }; |
| 473 | |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 474 | wdt2: wdt@48314000 { |
| 475 | compatible = "ti,omap3-wdt"; |
Tony Lindgren | d7c8f25 | 2013-10-17 15:15:22 -0700 | [diff] [blame] | 476 | reg = <0x48314000 0x80>; |
Xiao Jiang | 94c3073 | 2012-06-01 12:44:14 +0800 | [diff] [blame] | 477 | ti,hwmods = "wd_timer2"; |
| 478 | }; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 479 | |
| 480 | mcbsp1: mcbsp@48074000 { |
| 481 | compatible = "ti,omap3-mcbsp"; |
| 482 | reg = <0x48074000 0xff>; |
| 483 | reg-names = "mpu"; |
| 484 | interrupts = <16>, /* OCP compliant interrupt */ |
| 485 | <59>, /* TX interrupt */ |
| 486 | <60>; /* RX interrupt */ |
| 487 | interrupt-names = "common", "tx", "rx"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 488 | ti,buffer-size = <128>; |
| 489 | ti,hwmods = "mcbsp1"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 490 | dmas = <&sdma 31>, |
| 491 | <&sdma 32>; |
| 492 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 726322c | 2014-01-24 10:19:05 +0200 | [diff] [blame] | 493 | status = "disabled"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 494 | }; |
| 495 | |
| 496 | mcbsp2: mcbsp@49022000 { |
| 497 | compatible = "ti,omap3-mcbsp"; |
| 498 | reg = <0x49022000 0xff>, |
| 499 | <0x49028000 0xff>; |
| 500 | reg-names = "mpu", "sidetone"; |
| 501 | interrupts = <17>, /* OCP compliant interrupt */ |
| 502 | <62>, /* TX interrupt */ |
| 503 | <63>, /* RX interrupt */ |
| 504 | <4>; /* Sidetone */ |
| 505 | interrupt-names = "common", "tx", "rx", "sidetone"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 506 | ti,buffer-size = <1280>; |
Peter Ujfalusi | eef6fca | 2012-10-18 11:25:07 +0200 | [diff] [blame] | 507 | ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 508 | dmas = <&sdma 33>, |
| 509 | <&sdma 34>; |
| 510 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 726322c | 2014-01-24 10:19:05 +0200 | [diff] [blame] | 511 | status = "disabled"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 512 | }; |
| 513 | |
| 514 | mcbsp3: mcbsp@49024000 { |
| 515 | compatible = "ti,omap3-mcbsp"; |
| 516 | reg = <0x49024000 0xff>, |
| 517 | <0x4902a000 0xff>; |
| 518 | reg-names = "mpu", "sidetone"; |
| 519 | interrupts = <22>, /* OCP compliant interrupt */ |
| 520 | <89>, /* TX interrupt */ |
| 521 | <90>, /* RX interrupt */ |
| 522 | <5>; /* Sidetone */ |
| 523 | interrupt-names = "common", "tx", "rx", "sidetone"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 524 | ti,buffer-size = <128>; |
Peter Ujfalusi | eef6fca | 2012-10-18 11:25:07 +0200 | [diff] [blame] | 525 | ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 526 | dmas = <&sdma 17>, |
| 527 | <&sdma 18>; |
| 528 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 726322c | 2014-01-24 10:19:05 +0200 | [diff] [blame] | 529 | status = "disabled"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 530 | }; |
| 531 | |
| 532 | mcbsp4: mcbsp@49026000 { |
| 533 | compatible = "ti,omap3-mcbsp"; |
| 534 | reg = <0x49026000 0xff>; |
| 535 | reg-names = "mpu"; |
| 536 | interrupts = <23>, /* OCP compliant interrupt */ |
| 537 | <54>, /* TX interrupt */ |
| 538 | <55>; /* RX interrupt */ |
| 539 | interrupt-names = "common", "tx", "rx"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 540 | ti,buffer-size = <128>; |
| 541 | ti,hwmods = "mcbsp4"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 542 | dmas = <&sdma 19>, |
| 543 | <&sdma 20>; |
| 544 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 726322c | 2014-01-24 10:19:05 +0200 | [diff] [blame] | 545 | status = "disabled"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 546 | }; |
| 547 | |
| 548 | mcbsp5: mcbsp@48096000 { |
| 549 | compatible = "ti,omap3-mcbsp"; |
| 550 | reg = <0x48096000 0xff>; |
| 551 | reg-names = "mpu"; |
| 552 | interrupts = <27>, /* OCP compliant interrupt */ |
| 553 | <81>, /* TX interrupt */ |
| 554 | <82>; /* RX interrupt */ |
| 555 | interrupt-names = "common", "tx", "rx"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 556 | ti,buffer-size = <128>; |
| 557 | ti,hwmods = "mcbsp5"; |
Sebastien Guiriec | 4e4ead7 | 2013-03-11 08:50:21 +0100 | [diff] [blame] | 558 | dmas = <&sdma 21>, |
| 559 | <&sdma 22>; |
| 560 | dma-names = "tx", "rx"; |
Peter Ujfalusi | 726322c | 2014-01-24 10:19:05 +0200 | [diff] [blame] | 561 | status = "disabled"; |
Peter Ujfalusi | 0be484b | 2012-09-05 14:21:22 +0300 | [diff] [blame] | 562 | }; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 563 | |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 564 | sham: sham@480c3000 { |
| 565 | compatible = "ti,omap3-sham"; |
| 566 | ti,hwmods = "sham"; |
| 567 | reg = <0x480c3000 0x64>; |
| 568 | interrupts = <49>; |
Pali Rohár | d6e5b7c | 2015-02-26 14:49:56 +0100 | [diff] [blame] | 569 | dmas = <&sdma 69>; |
| 570 | dma-names = "rx"; |
Tony Lindgren | 7ce93f3 | 2013-11-25 14:23:45 -0800 | [diff] [blame] | 571 | }; |
| 572 | |
| 573 | smartreflex_core: smartreflex@480cb000 { |
| 574 | compatible = "ti,omap3-smartreflex-core"; |
| 575 | ti,hwmods = "smartreflex_core"; |
| 576 | reg = <0x480cb000 0x400>; |
| 577 | interrupts = <19>; |
| 578 | }; |
| 579 | |
| 580 | smartreflex_mpu_iva: smartreflex@480c9000 { |
| 581 | compatible = "ti,omap3-smartreflex-iva"; |
| 582 | ti,hwmods = "smartreflex_mpu_iva"; |
| 583 | reg = <0x480c9000 0x400>; |
| 584 | interrupts = <18>; |
| 585 | }; |
| 586 | |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 587 | timer1: timer@48318000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 588 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 589 | reg = <0x48318000 0x400>; |
| 590 | interrupts = <37>; |
| 591 | ti,hwmods = "timer1"; |
| 592 | ti,timer-alwon; |
| 593 | }; |
| 594 | |
| 595 | timer2: timer@49032000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 596 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 597 | reg = <0x49032000 0x400>; |
| 598 | interrupts = <38>; |
| 599 | ti,hwmods = "timer2"; |
| 600 | }; |
| 601 | |
| 602 | timer3: timer@49034000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 603 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 604 | reg = <0x49034000 0x400>; |
| 605 | interrupts = <39>; |
| 606 | ti,hwmods = "timer3"; |
| 607 | }; |
| 608 | |
| 609 | timer4: timer@49036000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 610 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 611 | reg = <0x49036000 0x400>; |
| 612 | interrupts = <40>; |
| 613 | ti,hwmods = "timer4"; |
| 614 | }; |
| 615 | |
| 616 | timer5: timer@49038000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 617 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 618 | reg = <0x49038000 0x400>; |
| 619 | interrupts = <41>; |
| 620 | ti,hwmods = "timer5"; |
| 621 | ti,timer-dsp; |
| 622 | }; |
| 623 | |
| 624 | timer6: timer@4903a000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 625 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 626 | reg = <0x4903a000 0x400>; |
| 627 | interrupts = <42>; |
| 628 | ti,hwmods = "timer6"; |
| 629 | ti,timer-dsp; |
| 630 | }; |
| 631 | |
| 632 | timer7: timer@4903c000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 633 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 634 | reg = <0x4903c000 0x400>; |
| 635 | interrupts = <43>; |
| 636 | ti,hwmods = "timer7"; |
| 637 | ti,timer-dsp; |
| 638 | }; |
| 639 | |
| 640 | timer8: timer@4903e000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 641 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 642 | reg = <0x4903e000 0x400>; |
| 643 | interrupts = <44>; |
| 644 | ti,hwmods = "timer8"; |
| 645 | ti,timer-pwm; |
| 646 | ti,timer-dsp; |
| 647 | }; |
| 648 | |
| 649 | timer9: timer@49040000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 650 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 651 | reg = <0x49040000 0x400>; |
| 652 | interrupts = <45>; |
| 653 | ti,hwmods = "timer9"; |
| 654 | ti,timer-pwm; |
| 655 | }; |
| 656 | |
| 657 | timer10: timer@48086000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 658 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 659 | reg = <0x48086000 0x400>; |
| 660 | interrupts = <46>; |
| 661 | ti,hwmods = "timer10"; |
| 662 | ti,timer-pwm; |
| 663 | }; |
| 664 | |
| 665 | timer11: timer@48088000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 666 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 667 | reg = <0x48088000 0x400>; |
| 668 | interrupts = <47>; |
| 669 | ti,hwmods = "timer11"; |
| 670 | ti,timer-pwm; |
| 671 | }; |
| 672 | |
| 673 | timer12: timer@48304000 { |
Jon Hunter | 002e1ec | 2013-03-19 12:38:18 -0500 | [diff] [blame] | 674 | compatible = "ti,omap3430-timer"; |
Jon Hunter | fab8ad0 | 2012-10-19 09:59:00 -0500 | [diff] [blame] | 675 | reg = <0x48304000 0x400>; |
| 676 | interrupts = <95>; |
| 677 | ti,hwmods = "timer12"; |
| 678 | ti,timer-alwon; |
| 679 | ti,timer-secure; |
| 680 | }; |
Roger Quadros | af3eb36 | 2013-03-20 17:44:59 +0200 | [diff] [blame] | 681 | |
| 682 | usbhstll: usbhstll@48062000 { |
| 683 | compatible = "ti,usbhs-tll"; |
| 684 | reg = <0x48062000 0x1000>; |
| 685 | interrupts = <78>; |
| 686 | ti,hwmods = "usb_tll_hs"; |
| 687 | }; |
| 688 | |
| 689 | usbhshost: usbhshost@48064000 { |
| 690 | compatible = "ti,usbhs-host"; |
| 691 | reg = <0x48064000 0x400>; |
| 692 | ti,hwmods = "usb_host_hs"; |
| 693 | #address-cells = <1>; |
| 694 | #size-cells = <1>; |
| 695 | ranges; |
| 696 | |
| 697 | usbhsohci: ohci@48064400 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 698 | compatible = "ti,ohci-omap3"; |
Roger Quadros | af3eb36 | 2013-03-20 17:44:59 +0200 | [diff] [blame] | 699 | reg = <0x48064400 0x400>; |
| 700 | interrupt-parent = <&intc>; |
| 701 | interrupts = <76>; |
| 702 | }; |
| 703 | |
| 704 | usbhsehci: ehci@48064800 { |
Roger Quadros | a2525e5 | 2014-02-27 16:18:30 +0200 | [diff] [blame] | 705 | compatible = "ti,ehci-omap"; |
Roger Quadros | af3eb36 | 2013-03-20 17:44:59 +0200 | [diff] [blame] | 706 | reg = <0x48064800 0x400>; |
| 707 | interrupt-parent = <&intc>; |
| 708 | interrupts = <77>; |
| 709 | }; |
| 710 | }; |
| 711 | |
Florian Vaussard | 6e8489d | 2013-01-28 18:54:07 +0100 | [diff] [blame] | 712 | gpmc: gpmc@6e000000 { |
| 713 | compatible = "ti,omap3430-gpmc"; |
| 714 | ti,hwmods = "gpmc"; |
Javier Martinez Canillas | 41644e7 | 2013-02-27 02:30:51 +0100 | [diff] [blame] | 715 | reg = <0x6e000000 0x02d0>; |
Florian Vaussard | 6e8489d | 2013-01-28 18:54:07 +0100 | [diff] [blame] | 716 | interrupts = <20>; |
| 717 | gpmc,num-cs = <8>; |
| 718 | gpmc,num-waitpins = <4>; |
| 719 | #address-cells = <2>; |
| 720 | #size-cells = <1>; |
| 721 | }; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 722 | |
| 723 | usb_otg_hs: usb_otg_hs@480ab000 { |
| 724 | compatible = "ti,omap3-musb"; |
| 725 | reg = <0x480ab000 0x1000>; |
Tony Lindgren | 304e71e | 2013-05-14 20:28:15 -0700 | [diff] [blame] | 726 | interrupts = <92>, <93>; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 727 | interrupt-names = "mc", "dma"; |
| 728 | ti,hwmods = "usb_otg_hs"; |
Kishon Vijay Abraham I | ad871c1 | 2013-03-07 19:05:16 +0530 | [diff] [blame] | 729 | multipoint = <1>; |
| 730 | num-eps = <16>; |
| 731 | ram-bits = <12>; |
| 732 | }; |
Tomi Valkeinen | b8a7e42 | 2013-03-19 11:38:13 +0200 | [diff] [blame] | 733 | |
| 734 | dss: dss@48050000 { |
| 735 | compatible = "ti,omap3-dss"; |
| 736 | reg = <0x48050000 0x200>; |
| 737 | status = "disabled"; |
| 738 | ti,hwmods = "dss_core"; |
| 739 | clocks = <&dss1_alwon_fck>; |
| 740 | clock-names = "fck"; |
| 741 | #address-cells = <1>; |
| 742 | #size-cells = <1>; |
| 743 | ranges; |
| 744 | |
| 745 | dispc@48050400 { |
| 746 | compatible = "ti,omap3-dispc"; |
| 747 | reg = <0x48050400 0x400>; |
| 748 | interrupts = <25>; |
| 749 | ti,hwmods = "dss_dispc"; |
| 750 | clocks = <&dss1_alwon_fck>; |
| 751 | clock-names = "fck"; |
| 752 | }; |
| 753 | |
| 754 | dsi: encoder@4804fc00 { |
| 755 | compatible = "ti,omap3-dsi"; |
| 756 | reg = <0x4804fc00 0x200>, |
| 757 | <0x4804fe00 0x40>, |
| 758 | <0x4804ff00 0x20>; |
| 759 | reg-names = "proto", "phy", "pll"; |
| 760 | interrupts = <25>; |
| 761 | status = "disabled"; |
| 762 | ti,hwmods = "dss_dsi1"; |
| 763 | clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; |
| 764 | clock-names = "fck", "sys_clk"; |
| 765 | }; |
| 766 | |
| 767 | rfbi: encoder@48050800 { |
| 768 | compatible = "ti,omap3-rfbi"; |
| 769 | reg = <0x48050800 0x100>; |
| 770 | status = "disabled"; |
| 771 | ti,hwmods = "dss_rfbi"; |
| 772 | clocks = <&dss1_alwon_fck>, <&dss_ick>; |
| 773 | clock-names = "fck", "ick"; |
| 774 | }; |
| 775 | |
| 776 | venc: encoder@48050c00 { |
| 777 | compatible = "ti,omap3-venc"; |
| 778 | reg = <0x48050c00 0x100>; |
| 779 | status = "disabled"; |
| 780 | ti,hwmods = "dss_venc"; |
| 781 | clocks = <&dss_tv_fck>; |
| 782 | clock-names = "fck"; |
| 783 | }; |
| 784 | }; |
Sebastian Reichel | 782e25a | 2014-05-10 18:37:49 +0200 | [diff] [blame] | 785 | |
| 786 | ssi: ssi-controller@48058000 { |
| 787 | compatible = "ti,omap3-ssi"; |
| 788 | ti,hwmods = "ssi"; |
| 789 | |
| 790 | status = "disabled"; |
| 791 | |
| 792 | reg = <0x48058000 0x1000>, |
| 793 | <0x48059000 0x1000>; |
| 794 | reg-names = "sys", |
| 795 | "gdd"; |
| 796 | |
| 797 | interrupts = <71>; |
| 798 | interrupt-names = "gdd_mpu"; |
| 799 | |
| 800 | #address-cells = <1>; |
| 801 | #size-cells = <1>; |
| 802 | ranges; |
| 803 | |
| 804 | ssi_port1: ssi-port@4805a000 { |
| 805 | compatible = "ti,omap3-ssi-port"; |
| 806 | |
| 807 | reg = <0x4805a000 0x800>, |
| 808 | <0x4805a800 0x800>; |
| 809 | reg-names = "tx", |
| 810 | "rx"; |
| 811 | |
| 812 | interrupt-parent = <&intc>; |
| 813 | interrupts = <67>, |
| 814 | <68>; |
| 815 | }; |
| 816 | |
| 817 | ssi_port2: ssi-port@4805b000 { |
| 818 | compatible = "ti,omap3-ssi-port"; |
| 819 | |
| 820 | reg = <0x4805b000 0x800>, |
| 821 | <0x4805b800 0x800>; |
| 822 | reg-names = "tx", |
| 823 | "rx"; |
| 824 | |
| 825 | interrupt-parent = <&intc>; |
| 826 | interrupts = <69>, |
| 827 | <70>; |
| 828 | }; |
| 829 | }; |
Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 830 | }; |
| 831 | }; |
Tero Kristo | 657fc11 | 2013-07-22 12:29:29 +0300 | [diff] [blame] | 832 | |
| 833 | /include/ "omap3xxx-clocks.dtsi" |