Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * xHCI host controller driver |
| 3 | * |
| 4 | * Copyright (C) 2008 Intel Corp. |
| 5 | * |
| 6 | * Author: Sarah Sharp |
| 7 | * Some code borrowed from the Linux EHCI driver. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| 15 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 16 | * for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software Foundation, |
| 20 | * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | */ |
| 22 | |
| 23 | #include "xhci.h" |
| 24 | |
| 25 | #define XHCI_INIT_VALUE 0x0 |
| 26 | |
| 27 | /* Add verbose debugging later, just print everything for now */ |
| 28 | |
| 29 | void xhci_dbg_regs(struct xhci_hcd *xhci) |
| 30 | { |
| 31 | u32 temp; |
| 32 | |
| 33 | xhci_dbg(xhci, "// xHCI capability registers at 0x%x:\n", |
| 34 | (unsigned int) xhci->cap_regs); |
| 35 | temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); |
| 36 | xhci_dbg(xhci, "// @%x = 0x%x (CAPLENGTH AND HCIVERSION)\n", |
| 37 | (unsigned int) &xhci->cap_regs->hc_capbase, |
| 38 | (unsigned int) temp); |
| 39 | xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n", |
| 40 | (unsigned int) HC_LENGTH(temp)); |
| 41 | #if 0 |
| 42 | xhci_dbg(xhci, "// HCIVERSION: 0x%x\n", |
| 43 | (unsigned int) HC_VERSION(temp)); |
| 44 | #endif |
| 45 | |
| 46 | xhci_dbg(xhci, "// xHCI operational registers at 0x%x:\n", |
| 47 | (unsigned int) xhci->op_regs); |
| 48 | |
| 49 | temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off); |
| 50 | xhci_dbg(xhci, "// @%x = 0x%x RTSOFF\n", |
| 51 | (unsigned int) &xhci->cap_regs->run_regs_off, |
| 52 | (unsigned int) temp & RTSOFF_MASK); |
| 53 | xhci_dbg(xhci, "// xHCI runtime registers at 0x%x:\n", |
| 54 | (unsigned int) xhci->run_regs); |
| 55 | |
| 56 | temp = xhci_readl(xhci, &xhci->cap_regs->db_off); |
| 57 | xhci_dbg(xhci, "// @%x = 0x%x DBOFF\n", |
| 58 | (unsigned int) &xhci->cap_regs->db_off, temp); |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 59 | xhci_dbg(xhci, "// Doorbell array at 0x%x:\n", |
| 60 | (unsigned int) xhci->dba); |
Sarah Sharp | 74c6874 | 2009-04-27 19:52:22 -0700 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | void xhci_print_cap_regs(struct xhci_hcd *xhci) |
| 64 | { |
| 65 | u32 temp; |
| 66 | |
| 67 | xhci_dbg(xhci, "xHCI capability registers at 0x%x:\n", |
| 68 | (unsigned int) xhci->cap_regs); |
| 69 | |
| 70 | temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase); |
| 71 | xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n", |
| 72 | (unsigned int) temp); |
| 73 | xhci_dbg(xhci, "CAPLENGTH: 0x%x\n", |
| 74 | (unsigned int) HC_LENGTH(temp)); |
| 75 | xhci_dbg(xhci, "HCIVERSION: 0x%x\n", |
| 76 | (unsigned int) HC_VERSION(temp)); |
| 77 | |
| 78 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1); |
| 79 | xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n", |
| 80 | (unsigned int) temp); |
| 81 | xhci_dbg(xhci, " Max device slots: %u\n", |
| 82 | (unsigned int) HCS_MAX_SLOTS(temp)); |
| 83 | xhci_dbg(xhci, " Max interrupters: %u\n", |
| 84 | (unsigned int) HCS_MAX_INTRS(temp)); |
| 85 | xhci_dbg(xhci, " Max ports: %u\n", |
| 86 | (unsigned int) HCS_MAX_PORTS(temp)); |
| 87 | |
| 88 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2); |
| 89 | xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n", |
| 90 | (unsigned int) temp); |
| 91 | xhci_dbg(xhci, " Isoc scheduling threshold: %u\n", |
| 92 | (unsigned int) HCS_IST(temp)); |
| 93 | xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n", |
| 94 | (unsigned int) HCS_ERST_MAX(temp)); |
| 95 | |
| 96 | temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3); |
| 97 | xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n", |
| 98 | (unsigned int) temp); |
| 99 | xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n", |
| 100 | (unsigned int) HCS_U1_LATENCY(temp)); |
| 101 | xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n", |
| 102 | (unsigned int) HCS_U2_LATENCY(temp)); |
| 103 | |
| 104 | temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params); |
| 105 | xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp); |
| 106 | xhci_dbg(xhci, " HC generates %s bit addresses\n", |
| 107 | HCC_64BIT_ADDR(temp) ? "64" : "32"); |
| 108 | /* FIXME */ |
| 109 | xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n"); |
| 110 | |
| 111 | temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off); |
| 112 | xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK); |
| 113 | } |
| 114 | |
| 115 | void xhci_print_command_reg(struct xhci_hcd *xhci) |
| 116 | { |
| 117 | u32 temp; |
| 118 | |
| 119 | temp = xhci_readl(xhci, &xhci->op_regs->command); |
| 120 | xhci_dbg(xhci, "USBCMD 0x%x:\n", temp); |
| 121 | xhci_dbg(xhci, " HC is %s\n", |
| 122 | (temp & CMD_RUN) ? "running" : "being stopped"); |
| 123 | xhci_dbg(xhci, " HC has %sfinished hard reset\n", |
| 124 | (temp & CMD_RESET) ? "not " : ""); |
| 125 | xhci_dbg(xhci, " Event Interrupts %s\n", |
| 126 | (temp & CMD_EIE) ? "enabled " : "disabled"); |
| 127 | xhci_dbg(xhci, " Host System Error Interrupts %s\n", |
| 128 | (temp & CMD_EIE) ? "enabled " : "disabled"); |
| 129 | xhci_dbg(xhci, " HC has %sfinished light reset\n", |
| 130 | (temp & CMD_LRESET) ? "not " : ""); |
| 131 | } |
| 132 | |
| 133 | void xhci_print_status(struct xhci_hcd *xhci) |
| 134 | { |
| 135 | u32 temp; |
| 136 | |
| 137 | temp = xhci_readl(xhci, &xhci->op_regs->status); |
| 138 | xhci_dbg(xhci, "USBSTS 0x%x:\n", temp); |
| 139 | xhci_dbg(xhci, " Event ring is %sempty\n", |
| 140 | (temp & STS_EINT) ? "not " : ""); |
| 141 | xhci_dbg(xhci, " %sHost System Error\n", |
| 142 | (temp & STS_FATAL) ? "WARNING: " : "No "); |
| 143 | xhci_dbg(xhci, " HC is %s\n", |
| 144 | (temp & STS_HALT) ? "halted" : "running"); |
| 145 | } |
| 146 | |
| 147 | void xhci_print_op_regs(struct xhci_hcd *xhci) |
| 148 | { |
| 149 | xhci_dbg(xhci, "xHCI operational registers at 0x%x:\n", |
| 150 | (unsigned int) xhci->op_regs); |
| 151 | xhci_print_command_reg(xhci); |
| 152 | xhci_print_status(xhci); |
| 153 | } |
| 154 | |
| 155 | void xhci_print_ir_set(struct xhci_hcd *xhci, struct intr_reg *ir_set, int set_num) |
| 156 | { |
| 157 | void *addr; |
| 158 | u32 temp; |
| 159 | |
| 160 | addr = &ir_set->irq_pending; |
| 161 | temp = xhci_readl(xhci, addr); |
| 162 | if (temp == XHCI_INIT_VALUE) |
| 163 | return; |
| 164 | |
| 165 | xhci_dbg(xhci, " 0x%x: ir_set[%i]\n", (unsigned int) ir_set, set_num); |
| 166 | |
| 167 | xhci_dbg(xhci, " 0x%x: ir_set.pending = 0x%x\n", |
| 168 | (unsigned int) addr, (unsigned int) temp); |
| 169 | |
| 170 | addr = &ir_set->irq_control; |
| 171 | temp = xhci_readl(xhci, addr); |
| 172 | xhci_dbg(xhci, " 0x%x: ir_set.control = 0x%x\n", |
| 173 | (unsigned int) addr, (unsigned int) temp); |
| 174 | |
| 175 | addr = &ir_set->erst_size; |
| 176 | temp = xhci_readl(xhci, addr); |
| 177 | xhci_dbg(xhci, " 0x%x: ir_set.erst_size = 0x%x\n", |
| 178 | (unsigned int) addr, (unsigned int) temp); |
| 179 | |
| 180 | addr = &ir_set->rsvd; |
| 181 | temp = xhci_readl(xhci, addr); |
| 182 | if (temp != XHCI_INIT_VALUE) |
| 183 | xhci_dbg(xhci, " WARN: 0x%x: ir_set.rsvd = 0x%x\n", |
| 184 | (unsigned int) addr, (unsigned int) temp); |
| 185 | |
| 186 | addr = &ir_set->erst_base[0]; |
| 187 | temp = xhci_readl(xhci, addr); |
| 188 | xhci_dbg(xhci, " 0x%x: ir_set.erst_base[0] = 0x%x\n", |
| 189 | (unsigned int) addr, (unsigned int) temp); |
| 190 | |
| 191 | addr = &ir_set->erst_base[1]; |
| 192 | temp = xhci_readl(xhci, addr); |
| 193 | xhci_dbg(xhci, " 0x%x: ir_set.erst_base[1] = 0x%x\n", |
| 194 | (unsigned int) addr, (unsigned int) temp); |
| 195 | |
| 196 | addr = &ir_set->erst_dequeue[0]; |
| 197 | temp = xhci_readl(xhci, addr); |
| 198 | xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[0] = 0x%x\n", |
| 199 | (unsigned int) addr, (unsigned int) temp); |
| 200 | |
| 201 | addr = &ir_set->erst_dequeue[1]; |
| 202 | temp = xhci_readl(xhci, addr); |
| 203 | xhci_dbg(xhci, " 0x%x: ir_set.erst_dequeue[1] = 0x%x\n", |
| 204 | (unsigned int) addr, (unsigned int) temp); |
| 205 | } |
| 206 | |
| 207 | void xhci_print_run_regs(struct xhci_hcd *xhci) |
| 208 | { |
| 209 | u32 temp; |
| 210 | int i; |
| 211 | |
| 212 | xhci_dbg(xhci, "xHCI runtime registers at 0x%x:\n", |
| 213 | (unsigned int) xhci->run_regs); |
| 214 | temp = xhci_readl(xhci, &xhci->run_regs->microframe_index); |
| 215 | xhci_dbg(xhci, " 0x%x: Microframe index = 0x%x\n", |
| 216 | (unsigned int) &xhci->run_regs->microframe_index, |
| 217 | (unsigned int) temp); |
| 218 | for (i = 0; i < 7; ++i) { |
| 219 | temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]); |
| 220 | if (temp != XHCI_INIT_VALUE) |
| 221 | xhci_dbg(xhci, " WARN: 0x%x: Rsvd[%i] = 0x%x\n", |
| 222 | (unsigned int) &xhci->run_regs->rsvd[i], |
| 223 | i, (unsigned int) temp); |
| 224 | } |
| 225 | } |
| 226 | |
| 227 | void xhci_print_registers(struct xhci_hcd *xhci) |
| 228 | { |
| 229 | xhci_print_cap_regs(xhci); |
| 230 | xhci_print_op_regs(xhci); |
| 231 | } |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 232 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame^] | 233 | void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb) |
| 234 | { |
| 235 | int i; |
| 236 | for (i = 0; i < 4; ++i) |
| 237 | xhci_dbg(xhci, "Offset 0x%x = 0x%x\n", |
| 238 | i*4, trb->generic.field[i]); |
| 239 | } |
| 240 | |
| 241 | /** |
| 242 | * Debug a transfer request block (TRB). |
| 243 | */ |
| 244 | void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb) |
| 245 | { |
| 246 | u64 address; |
| 247 | u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK; |
| 248 | |
| 249 | switch (type) { |
| 250 | case TRB_TYPE(TRB_LINK): |
| 251 | xhci_dbg(xhci, "Link TRB:\n"); |
| 252 | xhci_print_trb_offsets(xhci, trb); |
| 253 | |
| 254 | address = trb->link.segment_ptr[0] + |
| 255 | (((u64) trb->link.segment_ptr[1]) << 32); |
| 256 | xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address); |
| 257 | |
| 258 | xhci_dbg(xhci, "Interrupter target = 0x%x\n", |
| 259 | GET_INTR_TARGET(trb->link.intr_target)); |
| 260 | xhci_dbg(xhci, "Cycle bit = %u\n", |
| 261 | (unsigned int) (trb->link.control & TRB_CYCLE)); |
| 262 | xhci_dbg(xhci, "Toggle cycle bit = %u\n", |
| 263 | (unsigned int) (trb->link.control & LINK_TOGGLE)); |
| 264 | xhci_dbg(xhci, "No Snoop bit = %u\n", |
| 265 | (unsigned int) (trb->link.control & TRB_NO_SNOOP)); |
| 266 | break; |
| 267 | case TRB_TYPE(TRB_TRANSFER): |
| 268 | address = trb->trans_event.buffer[0] + |
| 269 | (((u64) trb->trans_event.buffer[1]) << 32); |
| 270 | /* |
| 271 | * FIXME: look at flags to figure out if it's an address or if |
| 272 | * the data is directly in the buffer field. |
| 273 | */ |
| 274 | xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address); |
| 275 | break; |
| 276 | case TRB_TYPE(TRB_COMPLETION): |
| 277 | address = trb->event_cmd.cmd_trb[0] + |
| 278 | (((u64) trb->event_cmd.cmd_trb[1]) << 32); |
| 279 | xhci_dbg(xhci, "Command TRB pointer = %llu\n", address); |
| 280 | xhci_dbg(xhci, "Completion status = %u\n", |
| 281 | (unsigned int) GET_COMP_CODE(trb->event_cmd.status)); |
| 282 | xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags); |
| 283 | break; |
| 284 | default: |
| 285 | xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n", |
| 286 | (unsigned int) type>>10); |
| 287 | xhci_print_trb_offsets(xhci, trb); |
| 288 | break; |
| 289 | } |
| 290 | } |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 291 | |
| 292 | /** |
| 293 | * Debug a segment with an xHCI ring. |
| 294 | * |
| 295 | * @return The Link TRB of the segment, or NULL if there is no Link TRB |
| 296 | * (which is a bug, since all segments must have a Link TRB). |
| 297 | * |
| 298 | * Prints out all TRBs in the segment, even those after the Link TRB. |
| 299 | * |
| 300 | * XXX: should we print out TRBs that the HC owns? As long as we don't |
| 301 | * write, that should be fine... We shouldn't expect that the memory pointed to |
| 302 | * by the TRB is valid at all. Do we care about ones the HC owns? Probably, |
| 303 | * for HC debugging. |
| 304 | */ |
| 305 | void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg) |
| 306 | { |
| 307 | int i; |
| 308 | u32 addr = (u32) seg->dma; |
| 309 | union xhci_trb *trb = seg->trbs; |
| 310 | |
| 311 | for (i = 0; i < TRBS_PER_SEGMENT; ++i) { |
| 312 | trb = &seg->trbs[i]; |
| 313 | xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr, |
| 314 | (unsigned int) trb->link.segment_ptr[0], |
| 315 | (unsigned int) trb->link.segment_ptr[1], |
| 316 | (unsigned int) trb->link.intr_target, |
| 317 | (unsigned int) trb->link.control); |
| 318 | addr += sizeof(*trb); |
| 319 | } |
| 320 | } |
| 321 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame^] | 322 | void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring) |
| 323 | { |
| 324 | xhci_dbg(xhci, "Ring deq = 0x%x (virt), 0x%x (dma)\n", |
| 325 | (unsigned int) ring->dequeue, |
| 326 | trb_virt_to_dma(ring->deq_seg, ring->dequeue)); |
| 327 | xhci_dbg(xhci, "Ring deq updated %u times\n", |
| 328 | ring->deq_updates); |
| 329 | xhci_dbg(xhci, "Ring enq = 0x%x (virt), 0x%x (dma)\n", |
| 330 | (unsigned int) ring->enqueue, |
| 331 | trb_virt_to_dma(ring->enq_seg, ring->enqueue)); |
| 332 | xhci_dbg(xhci, "Ring enq updated %u times\n", |
| 333 | ring->enq_updates); |
| 334 | } |
| 335 | |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 336 | /** |
| 337 | * Debugging for an xHCI ring, which is a queue broken into multiple segments. |
| 338 | * |
| 339 | * Print out each segment in the ring. Check that the DMA address in |
| 340 | * each link segment actually matches the segment's stored DMA address. |
| 341 | * Check that the link end bit is only set at the end of the ring. |
| 342 | * Check that the dequeue and enqueue pointers point to real data in this ring |
| 343 | * (not some other ring). |
| 344 | */ |
| 345 | void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring) |
| 346 | { |
| 347 | /* FIXME: Throw an error if any segment doesn't have a Link TRB */ |
| 348 | struct xhci_segment *seg; |
| 349 | struct xhci_segment *first_seg = ring->first_seg; |
| 350 | xhci_debug_segment(xhci, first_seg); |
| 351 | |
Sarah Sharp | 7f84eef | 2009-04-27 19:53:56 -0700 | [diff] [blame^] | 352 | if (!ring->enq_updates && !ring->deq_updates) { |
| 353 | xhci_dbg(xhci, " Ring has not been updated\n"); |
| 354 | return; |
| 355 | } |
Sarah Sharp | 0ebbab3 | 2009-04-27 19:52:34 -0700 | [diff] [blame] | 356 | for (seg = first_seg->next; seg != first_seg; seg = seg->next) |
| 357 | xhci_debug_segment(xhci, seg); |
| 358 | } |
| 359 | |
| 360 | void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst) |
| 361 | { |
| 362 | u32 addr = (u32) erst->erst_dma_addr; |
| 363 | int i; |
| 364 | struct xhci_erst_entry *entry; |
| 365 | |
| 366 | for (i = 0; i < erst->num_entries; ++i) { |
| 367 | entry = &erst->entries[i]; |
| 368 | xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", |
| 369 | (unsigned int) addr, |
| 370 | (unsigned int) entry->seg_addr[0], |
| 371 | (unsigned int) entry->seg_addr[1], |
| 372 | (unsigned int) entry->seg_size, |
| 373 | (unsigned int) entry->rsvd); |
| 374 | addr += sizeof(*entry); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci) |
| 379 | { |
| 380 | u32 val; |
| 381 | |
| 382 | val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]); |
| 383 | xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = 0x%x\n", val); |
| 384 | val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[1]); |
| 385 | xhci_dbg(xhci, "// xHC command ring deq ptr high bits = 0x%x\n", val); |
| 386 | } |