blob: 65b6e71512c0389637f99ba2f02a9f94ca351d12 [file] [log] [blame]
Thierry Reding4de6a2d2013-09-02 09:48:53 +02001/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/clk.h>
24#include <linux/delay.h>
Thierry Redingaef03d32013-11-08 13:28:34 +010025#include <linux/host1x.h>
Thierry Reding4de6a2d2013-09-02 09:48:53 +020026#include <linux/io.h>
27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30
Thierry Redingaef03d32013-11-08 13:28:34 +010031#include "dev.h"
32
Thierry Reding4de6a2d2013-09-02 09:48:53 +020033#define MIPI_CAL_CTRL 0x00
Thierry Reding83a3c222015-04-08 17:03:49 +020034#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26)
35#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24)
36#define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4)
Thierry Reding4de6a2d2013-09-02 09:48:53 +020037#define MIPI_CAL_CTRL_START (1 << 0)
38
39#define MIPI_CAL_AUTOCAL_CTRL 0x01
40
41#define MIPI_CAL_STATUS 0x02
42#define MIPI_CAL_STATUS_DONE (1 << 16)
43#define MIPI_CAL_STATUS_ACTIVE (1 << 0)
44
45#define MIPI_CAL_CONFIG_CSIA 0x05
46#define MIPI_CAL_CONFIG_CSIB 0x06
47#define MIPI_CAL_CONFIG_CSIC 0x07
48#define MIPI_CAL_CONFIG_CSID 0x08
49#define MIPI_CAL_CONFIG_CSIE 0x09
50#define MIPI_CAL_CONFIG_DSIA 0x0e
51#define MIPI_CAL_CONFIG_DSIB 0x0f
52#define MIPI_CAL_CONFIG_DSIC 0x10
53#define MIPI_CAL_CONFIG_DSID 0x11
54
Thierry Reding8ed5c062015-04-08 17:06:08 +020055#define MIPI_CAL_CONFIG_DSIA_CLK 0x19
56#define MIPI_CAL_CONFIG_DSIB_CLK 0x1a
Sean Paul08a15cc2014-09-10 10:52:04 -040057#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b
58#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c
59#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d
60
61/* for data and clock lanes */
Thierry Reding4de6a2d2013-09-02 09:48:53 +020062#define MIPI_CAL_CONFIG_SELECT (1 << 21)
Sean Paul08a15cc2014-09-10 10:52:04 -040063
64/* for data lanes */
Thierry Reding4de6a2d2013-09-02 09:48:53 +020065#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
66#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
67#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
68
Sean Paul08a15cc2014-09-10 10:52:04 -040069/* for clock lanes */
70#define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8)
71#define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0)
72
Thierry Reding4de6a2d2013-09-02 09:48:53 +020073#define MIPI_CAL_BIAS_PAD_CFG0 0x16
74#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
75#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
76
77#define MIPI_CAL_BIAS_PAD_CFG1 0x17
Sean Paulb298e982014-09-10 10:52:05 -040078#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16)
Thierry Reding83a3c222015-04-08 17:03:49 +020079#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8)
Thierry Reding4de6a2d2013-09-02 09:48:53 +020080
81#define MIPI_CAL_BIAS_PAD_CFG2 0x18
Thierry Reding83a3c222015-04-08 17:03:49 +020082#define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16)
83#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4)
Thierry Reding4de6a2d2013-09-02 09:48:53 +020084#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
85
Sean Paul08a15cc2014-09-10 10:52:04 -040086struct tegra_mipi_pad {
87 unsigned long data;
88 unsigned long clk;
89};
90
91struct tegra_mipi_soc {
92 bool has_clk_lane;
93 const struct tegra_mipi_pad *pads;
94 unsigned int num_pads;
Thierry Reding83a3c222015-04-08 17:03:49 +020095
96 bool clock_enable_override;
97 bool needs_vclamp_ref;
98
99 /* bias pad configuration settings */
100 u8 pad_drive_down_ref;
101 u8 pad_drive_up_ref;
102
103 u8 pad_vclamp_level;
104 u8 pad_vauxp_level;
105
106 /* calibration settings for data lanes */
107 u8 hspdos;
108 u8 hspuos;
109 u8 termos;
110
111 /* calibration settings for clock lanes */
112 u8 hsclkpdos;
113 u8 hsclkpuos;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200114};
115
116struct tegra_mipi {
Sean Paul08a15cc2014-09-10 10:52:04 -0400117 const struct tegra_mipi_soc *soc;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200118 void __iomem *regs;
119 struct mutex lock;
120 struct clk *clk;
121};
122
123struct tegra_mipi_device {
124 struct platform_device *pdev;
125 struct tegra_mipi *mipi;
126 struct device *device;
127 unsigned long pads;
128};
129
Thierry Reding57b17ae2014-10-02 14:33:31 +0200130static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi,
131 unsigned long offset)
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200132{
Thierry Reding57b17ae2014-10-02 14:33:31 +0200133 return readl(mipi->regs + (offset << 2));
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200134}
135
Thierry Reding57b17ae2014-10-02 14:33:31 +0200136static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value,
137 unsigned long offset)
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200138{
Thierry Reding57b17ae2014-10-02 14:33:31 +0200139 writel(value, mipi->regs + (offset << 2));
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200140}
141
142struct tegra_mipi_device *tegra_mipi_request(struct device *device)
143{
144 struct device_node *np = device->of_node;
145 struct tegra_mipi_device *dev;
146 struct of_phandle_args args;
147 int err;
148
149 err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
150 "#nvidia,mipi-calibrate-cells", 0,
151 &args);
152 if (err < 0)
153 return ERR_PTR(err);
154
155 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
156 if (!dev) {
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200157 err = -ENOMEM;
158 goto out;
159 }
160
161 dev->pdev = of_find_device_by_node(args.np);
162 if (!dev->pdev) {
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200163 err = -ENODEV;
164 goto free;
165 }
166
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200167 dev->mipi = platform_get_drvdata(dev->pdev);
168 if (!dev->mipi) {
169 err = -EPROBE_DEFER;
Sean Paul08a15cc2014-09-10 10:52:04 -0400170 goto put;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200171 }
172
Sean Paul08a15cc2014-09-10 10:52:04 -0400173 of_node_put(args.np);
174
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200175 dev->pads = args.args[0];
176 dev->device = device;
177
178 return dev;
179
Sean Paul08a15cc2014-09-10 10:52:04 -0400180put:
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200181 platform_device_put(dev->pdev);
182free:
183 kfree(dev);
184out:
Sean Paul08a15cc2014-09-10 10:52:04 -0400185 of_node_put(args.np);
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200186 return ERR_PTR(err);
187}
188EXPORT_SYMBOL(tegra_mipi_request);
189
190void tegra_mipi_free(struct tegra_mipi_device *device)
191{
192 platform_device_put(device->pdev);
193 kfree(device);
194}
195EXPORT_SYMBOL(tegra_mipi_free);
196
197static int tegra_mipi_wait(struct tegra_mipi *mipi)
198{
199 unsigned long timeout = jiffies + msecs_to_jiffies(250);
Thierry Reding57b17ae2014-10-02 14:33:31 +0200200 u32 value;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200201
202 while (time_before(jiffies, timeout)) {
203 value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
204 if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
205 (value & MIPI_CAL_STATUS_DONE) != 0)
206 return 0;
207
208 usleep_range(10, 50);
209 }
210
211 return -ETIMEDOUT;
212}
213
214int tegra_mipi_calibrate(struct tegra_mipi_device *device)
215{
Sean Paul08a15cc2014-09-10 10:52:04 -0400216 const struct tegra_mipi_soc *soc = device->mipi->soc;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200217 unsigned int i;
Thierry Reding57b17ae2014-10-02 14:33:31 +0200218 u32 value;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200219 int err;
220
221 err = clk_enable(device->mipi->clk);
222 if (err < 0)
223 return err;
224
225 mutex_lock(&device->mipi->lock);
226
227 value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
228 value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
Thierry Reding83a3c222015-04-08 17:03:49 +0200229
230 if (soc->needs_vclamp_ref)
231 value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
232
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200233 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
234
Thierry Reding83a3c222015-04-08 17:03:49 +0200235 value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
236 MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
237 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG1);
Sean Paulb298e982014-09-10 10:52:05 -0400238
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200239 value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
240 value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
241 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
242
Thierry Reding83a3c222015-04-08 17:03:49 +0200243 value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
244 value &= ~MIPI_CAL_BIAS_PAD_VCLAMP(0x7);
245 value &= ~MIPI_CAL_BIAS_PAD_VAUXP(0x7);
246 value |= MIPI_CAL_BIAS_PAD_VCLAMP(soc->pad_vclamp_level);
247 value |= MIPI_CAL_BIAS_PAD_VAUXP(soc->pad_vauxp_level);
248 tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
249
Sean Paul08a15cc2014-09-10 10:52:04 -0400250 for (i = 0; i < soc->num_pads; i++) {
251 u32 clk = 0, data = 0;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200252
Sean Paul08a15cc2014-09-10 10:52:04 -0400253 if (device->pads & BIT(i)) {
254 data = MIPI_CAL_CONFIG_SELECT |
Thierry Reding83a3c222015-04-08 17:03:49 +0200255 MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
256 MIPI_CAL_CONFIG_HSPUOS(soc->hspuos) |
257 MIPI_CAL_CONFIG_TERMOS(soc->termos);
Sean Paul08a15cc2014-09-10 10:52:04 -0400258 clk = MIPI_CAL_CONFIG_SELECT |
Thierry Reding83a3c222015-04-08 17:03:49 +0200259 MIPI_CAL_CONFIG_HSCLKPDOSD(soc->hsclkpdos) |
260 MIPI_CAL_CONFIG_HSCLKPUOSD(soc->hsclkpuos);
Sean Paul08a15cc2014-09-10 10:52:04 -0400261 }
262
263 tegra_mipi_writel(device->mipi, data, soc->pads[i].data);
264
265 if (soc->has_clk_lane)
266 tegra_mipi_writel(device->mipi, clk, soc->pads[i].clk);
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200267 }
268
Sean Paul26f7a922014-09-10 10:52:03 -0400269 value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
Thierry Reding83a3c222015-04-08 17:03:49 +0200270 value &= ~MIPI_CAL_CTRL_NOISE_FILTER(0xf);
271 value &= ~MIPI_CAL_CTRL_PRESCALE(0x3);
272 value |= MIPI_CAL_CTRL_NOISE_FILTER(0xa);
273 value |= MIPI_CAL_CTRL_PRESCALE(0x2);
274
275 if (!soc->clock_enable_override)
276 value &= ~MIPI_CAL_CTRL_CLKEN_OVR;
277 else
278 value |= MIPI_CAL_CTRL_CLKEN_OVR;
279
280 tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
281
Thierry Reding2ed264b2015-04-08 17:17:44 +0200282 /* clear any pending status bits */
283 value = tegra_mipi_readl(device->mipi, MIPI_CAL_STATUS);
284 tegra_mipi_writel(device->mipi, value, MIPI_CAL_STATUS);
285
Thierry Reding83a3c222015-04-08 17:03:49 +0200286 value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL);
Sean Paul26f7a922014-09-10 10:52:03 -0400287 value |= MIPI_CAL_CTRL_START;
288 tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200289
290 err = tegra_mipi_wait(device->mipi);
291
292 mutex_unlock(&device->mipi->lock);
293 clk_disable(device->mipi->clk);
294
295 return err;
296}
297EXPORT_SYMBOL(tegra_mipi_calibrate);
298
Sean Paul08a15cc2014-09-10 10:52:04 -0400299static const struct tegra_mipi_pad tegra114_mipi_pads[] = {
300 { .data = MIPI_CAL_CONFIG_CSIA },
301 { .data = MIPI_CAL_CONFIG_CSIB },
302 { .data = MIPI_CAL_CONFIG_CSIC },
303 { .data = MIPI_CAL_CONFIG_CSID },
304 { .data = MIPI_CAL_CONFIG_CSIE },
305 { .data = MIPI_CAL_CONFIG_DSIA },
306 { .data = MIPI_CAL_CONFIG_DSIB },
307 { .data = MIPI_CAL_CONFIG_DSIC },
308 { .data = MIPI_CAL_CONFIG_DSID },
309};
310
311static const struct tegra_mipi_soc tegra114_mipi_soc = {
312 .has_clk_lane = false,
313 .pads = tegra114_mipi_pads,
314 .num_pads = ARRAY_SIZE(tegra114_mipi_pads),
Thierry Reding83a3c222015-04-08 17:03:49 +0200315 .clock_enable_override = true,
316 .needs_vclamp_ref = true,
317 .pad_drive_down_ref = 0x2,
318 .pad_drive_up_ref = 0x0,
319 .pad_vclamp_level = 0x0,
320 .pad_vauxp_level = 0x0,
321 .hspdos = 0x0,
322 .hspuos = 0x4,
323 .termos = 0x5,
324 .hsclkpdos = 0x0,
325 .hsclkpuos = 0x4,
Sean Paul08a15cc2014-09-10 10:52:04 -0400326};
327
328static const struct tegra_mipi_pad tegra124_mipi_pads[] = {
329 { .data = MIPI_CAL_CONFIG_CSIA, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
330 { .data = MIPI_CAL_CONFIG_CSIB, .clk = MIPI_CAL_CONFIG_CSIAB_CLK },
331 { .data = MIPI_CAL_CONFIG_CSIC, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
332 { .data = MIPI_CAL_CONFIG_CSID, .clk = MIPI_CAL_CONFIG_CSICD_CLK },
Thierry Reding8ed5c062015-04-08 17:06:08 +0200333 { .data = MIPI_CAL_CONFIG_CSIE, .clk = MIPI_CAL_CONFIG_CSIE_CLK },
334 { .data = MIPI_CAL_CONFIG_DSIA, .clk = MIPI_CAL_CONFIG_DSIA_CLK },
335 { .data = MIPI_CAL_CONFIG_DSIB, .clk = MIPI_CAL_CONFIG_DSIB_CLK },
Sean Paul08a15cc2014-09-10 10:52:04 -0400336};
337
338static const struct tegra_mipi_soc tegra124_mipi_soc = {
339 .has_clk_lane = true,
340 .pads = tegra124_mipi_pads,
341 .num_pads = ARRAY_SIZE(tegra124_mipi_pads),
Thierry Reding83a3c222015-04-08 17:03:49 +0200342 .clock_enable_override = true,
343 .needs_vclamp_ref = true,
344 .pad_drive_down_ref = 0x2,
345 .pad_drive_up_ref = 0x0,
346 .pad_vclamp_level = 0x0,
347 .pad_vauxp_level = 0x0,
348 .hspdos = 0x0,
349 .hspuos = 0x0,
350 .termos = 0x0,
351 .hsclkpdos = 0x1,
352 .hsclkpuos = 0x2,
Sean Paul08a15cc2014-09-10 10:52:04 -0400353};
354
Thierry Redingc22fb792015-04-08 17:19:19 +0200355static const struct of_device_id tegra_mipi_of_match[] = {
Sean Paul08a15cc2014-09-10 10:52:04 -0400356 { .compatible = "nvidia,tegra114-mipi", .data = &tegra114_mipi_soc },
357 { .compatible = "nvidia,tegra124-mipi", .data = &tegra124_mipi_soc },
358 { },
359};
360
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200361static int tegra_mipi_probe(struct platform_device *pdev)
362{
Sean Paul08a15cc2014-09-10 10:52:04 -0400363 const struct of_device_id *match;
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200364 struct tegra_mipi *mipi;
365 struct resource *res;
366 int err;
367
Sean Paul08a15cc2014-09-10 10:52:04 -0400368 match = of_match_node(tegra_mipi_of_match, pdev->dev.of_node);
369 if (!match)
370 return -ENODEV;
371
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200372 mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
373 if (!mipi)
374 return -ENOMEM;
375
Sean Paul08a15cc2014-09-10 10:52:04 -0400376 mipi->soc = match->data;
377
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200378 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
379 mipi->regs = devm_ioremap_resource(&pdev->dev, res);
380 if (IS_ERR(mipi->regs))
381 return PTR_ERR(mipi->regs);
382
383 mutex_init(&mipi->lock);
384
385 mipi->clk = devm_clk_get(&pdev->dev, NULL);
386 if (IS_ERR(mipi->clk)) {
387 dev_err(&pdev->dev, "failed to get clock\n");
388 return PTR_ERR(mipi->clk);
389 }
390
391 err = clk_prepare(mipi->clk);
392 if (err < 0)
393 return err;
394
395 platform_set_drvdata(pdev, mipi);
396
397 return 0;
398}
399
400static int tegra_mipi_remove(struct platform_device *pdev)
401{
402 struct tegra_mipi *mipi = platform_get_drvdata(pdev);
403
404 clk_unprepare(mipi->clk);
405
406 return 0;
407}
408
Thierry Reding4de6a2d2013-09-02 09:48:53 +0200409struct platform_driver tegra_mipi_driver = {
410 .driver = {
411 .name = "tegra-mipi",
412 .of_match_table = tegra_mipi_of_match,
413 },
414 .probe = tegra_mipi_probe,
415 .remove = tegra_mipi_remove,
416};