Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 1 | #include <linux/bitops.h> |
| 2 | #include <linux/types.h> |
| 3 | #include <linux/slab.h> |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 4 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 5 | #include <asm/kaiser.h> |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 6 | #include <asm/perf_event.h> |
Stephane Eranian | 3e702ff | 2012-02-09 23:20:58 +0100 | [diff] [blame] | 7 | #include <asm/insn.h> |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 8 | |
Borislav Petkov | 27f6d22 | 2016-02-10 10:55:23 +0100 | [diff] [blame] | 9 | #include "../perf_event.h" |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 10 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 11 | static |
| 12 | DEFINE_PER_CPU_SHARED_ALIGNED_USER_MAPPED(struct debug_store, cpu_debug_store); |
| 13 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 14 | /* The size of a BTS record in bytes: */ |
| 15 | #define BTS_RECORD_SIZE 24 |
| 16 | |
| 17 | #define BTS_BUFFER_SIZE (PAGE_SIZE << 4) |
Yan, Zheng | 1561749 | 2015-05-06 15:33:52 -0400 | [diff] [blame] | 18 | #define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 19 | #define PEBS_FIXUP_SIZE PAGE_SIZE |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 20 | |
| 21 | /* |
| 22 | * pebs_record_32 for p4 and core not supported |
| 23 | |
| 24 | struct pebs_record_32 { |
| 25 | u32 flags, ip; |
| 26 | u32 ax, bc, cx, dx; |
| 27 | u32 si, di, bp, sp; |
| 28 | }; |
| 29 | |
| 30 | */ |
| 31 | |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 32 | union intel_x86_pebs_dse { |
| 33 | u64 val; |
| 34 | struct { |
| 35 | unsigned int ld_dse:4; |
| 36 | unsigned int ld_stlb_miss:1; |
| 37 | unsigned int ld_locked:1; |
| 38 | unsigned int ld_reserved:26; |
| 39 | }; |
| 40 | struct { |
| 41 | unsigned int st_l1d_hit:1; |
| 42 | unsigned int st_reserved1:3; |
| 43 | unsigned int st_stlb_miss:1; |
| 44 | unsigned int st_locked:1; |
| 45 | unsigned int st_reserved2:26; |
| 46 | }; |
| 47 | }; |
| 48 | |
| 49 | |
| 50 | /* |
| 51 | * Map PEBS Load Latency Data Source encodings to generic |
| 52 | * memory data source information |
| 53 | */ |
| 54 | #define P(a, b) PERF_MEM_S(a, b) |
| 55 | #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) |
| 56 | #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) |
| 57 | |
Andi Kleen | e17dc65 | 2016-03-01 14:25:24 -0800 | [diff] [blame] | 58 | /* Version for Sandy Bridge and later */ |
| 59 | static u64 pebs_data_source[] = { |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 60 | P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ |
| 61 | OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */ |
| 62 | OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ |
| 63 | OP_LH | P(LVL, L2) | P(SNOOP, NONE), /* 0x03: L2 hit */ |
| 64 | OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */ |
| 65 | OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */ |
| 66 | OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */ |
| 67 | OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */ |
| 68 | OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */ |
| 69 | OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/ |
| 70 | OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */ |
| 71 | OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */ |
| 72 | OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,/* 0x0c: L3 miss, excl */ |
| 73 | OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,/* 0x0d: L3 miss, excl */ |
| 74 | OP_LH | P(LVL, IO) | P(SNOOP, NONE), /* 0x0e: I/O */ |
| 75 | OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */ |
| 76 | }; |
| 77 | |
Andi Kleen | e17dc65 | 2016-03-01 14:25:24 -0800 | [diff] [blame] | 78 | /* Patch up minor differences in the bits */ |
| 79 | void __init intel_pmu_pebs_data_source_nhm(void) |
| 80 | { |
| 81 | pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT); |
| 82 | pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); |
| 83 | pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); |
| 84 | } |
| 85 | |
Stephane Eranian | 9ad64c0 | 2013-01-24 16:10:34 +0100 | [diff] [blame] | 86 | static u64 precise_store_data(u64 status) |
| 87 | { |
| 88 | union intel_x86_pebs_dse dse; |
| 89 | u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); |
| 90 | |
| 91 | dse.val = status; |
| 92 | |
| 93 | /* |
| 94 | * bit 4: TLB access |
| 95 | * 1 = stored missed 2nd level TLB |
| 96 | * |
| 97 | * so it either hit the walker or the OS |
| 98 | * otherwise hit 2nd level TLB |
| 99 | */ |
| 100 | if (dse.st_stlb_miss) |
| 101 | val |= P(TLB, MISS); |
| 102 | else |
| 103 | val |= P(TLB, HIT); |
| 104 | |
| 105 | /* |
| 106 | * bit 0: hit L1 data cache |
| 107 | * if not set, then all we know is that |
| 108 | * it missed L1D |
| 109 | */ |
| 110 | if (dse.st_l1d_hit) |
| 111 | val |= P(LVL, HIT); |
| 112 | else |
| 113 | val |= P(LVL, MISS); |
| 114 | |
| 115 | /* |
| 116 | * bit 5: Locked prefix |
| 117 | */ |
| 118 | if (dse.st_locked) |
| 119 | val |= P(LOCK, LOCKED); |
| 120 | |
| 121 | return val; |
| 122 | } |
| 123 | |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 124 | static u64 precise_datala_hsw(struct perf_event *event, u64 status) |
Andi Kleen | f9134f3 | 2013-06-17 17:36:52 -0700 | [diff] [blame] | 125 | { |
| 126 | union perf_mem_data_src dse; |
| 127 | |
Stephane Eranian | 770eee1 | 2014-08-11 21:27:12 +0200 | [diff] [blame] | 128 | dse.val = PERF_MEM_NA; |
| 129 | |
| 130 | if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) |
| 131 | dse.mem_op = PERF_MEM_OP_STORE; |
| 132 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) |
| 133 | dse.mem_op = PERF_MEM_OP_LOAD; |
Stephane Eranian | 722e76e | 2014-05-15 17:56:44 +0200 | [diff] [blame] | 134 | |
| 135 | /* |
| 136 | * L1 info only valid for following events: |
| 137 | * |
| 138 | * MEM_UOPS_RETIRED.STLB_MISS_STORES |
| 139 | * MEM_UOPS_RETIRED.LOCK_STORES |
| 140 | * MEM_UOPS_RETIRED.SPLIT_STORES |
| 141 | * MEM_UOPS_RETIRED.ALL_STORES |
| 142 | */ |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 143 | if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { |
| 144 | if (status & 1) |
| 145 | dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT; |
| 146 | else |
| 147 | dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS; |
| 148 | } |
Andi Kleen | f9134f3 | 2013-06-17 17:36:52 -0700 | [diff] [blame] | 149 | return dse.val; |
| 150 | } |
| 151 | |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 152 | static u64 load_latency_data(u64 status) |
| 153 | { |
| 154 | union intel_x86_pebs_dse dse; |
| 155 | u64 val; |
| 156 | int model = boot_cpu_data.x86_model; |
| 157 | int fam = boot_cpu_data.x86; |
| 158 | |
| 159 | dse.val = status; |
| 160 | |
| 161 | /* |
| 162 | * use the mapping table for bit 0-3 |
| 163 | */ |
| 164 | val = pebs_data_source[dse.ld_dse]; |
| 165 | |
| 166 | /* |
| 167 | * Nehalem models do not support TLB, Lock infos |
| 168 | */ |
| 169 | if (fam == 0x6 && (model == 26 || model == 30 |
| 170 | || model == 31 || model == 46)) { |
| 171 | val |= P(TLB, NA) | P(LOCK, NA); |
| 172 | return val; |
| 173 | } |
| 174 | /* |
| 175 | * bit 4: TLB access |
| 176 | * 0 = did not miss 2nd level TLB |
| 177 | * 1 = missed 2nd level TLB |
| 178 | */ |
| 179 | if (dse.ld_stlb_miss) |
| 180 | val |= P(TLB, MISS) | P(TLB, L2); |
| 181 | else |
| 182 | val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); |
| 183 | |
| 184 | /* |
| 185 | * bit 5: locked prefix |
| 186 | */ |
| 187 | if (dse.ld_locked) |
| 188 | val |= P(LOCK, LOCKED); |
| 189 | |
| 190 | return val; |
| 191 | } |
| 192 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 193 | struct pebs_record_core { |
| 194 | u64 flags, ip; |
| 195 | u64 ax, bx, cx, dx; |
| 196 | u64 si, di, bp, sp; |
| 197 | u64 r8, r9, r10, r11; |
| 198 | u64 r12, r13, r14, r15; |
| 199 | }; |
| 200 | |
| 201 | struct pebs_record_nhm { |
| 202 | u64 flags, ip; |
| 203 | u64 ax, bx, cx, dx; |
| 204 | u64 si, di, bp, sp; |
| 205 | u64 r8, r9, r10, r11; |
| 206 | u64 r12, r13, r14, r15; |
| 207 | u64 status, dla, dse, lat; |
| 208 | }; |
| 209 | |
Andi Kleen | 130768b | 2013-06-17 17:36:47 -0700 | [diff] [blame] | 210 | /* |
| 211 | * Same as pebs_record_nhm, with two additional fields. |
| 212 | */ |
| 213 | struct pebs_record_hsw { |
Andi Kleen | 748e86a | 2013-09-05 20:37:39 -0700 | [diff] [blame] | 214 | u64 flags, ip; |
| 215 | u64 ax, bx, cx, dx; |
| 216 | u64 si, di, bp, sp; |
| 217 | u64 r8, r9, r10, r11; |
| 218 | u64 r12, r13, r14, r15; |
| 219 | u64 status, dla, dse, lat; |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 220 | u64 real_ip, tsx_tuning; |
Andi Kleen | 748e86a | 2013-09-05 20:37:39 -0700 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | union hsw_tsx_tuning { |
| 224 | struct { |
| 225 | u32 cycles_last_block : 32, |
| 226 | hle_abort : 1, |
| 227 | rtm_abort : 1, |
| 228 | instruction_abort : 1, |
| 229 | non_instruction_abort : 1, |
| 230 | retry : 1, |
| 231 | data_conflict : 1, |
| 232 | capacity_writes : 1, |
| 233 | capacity_reads : 1; |
| 234 | }; |
| 235 | u64 value; |
Andi Kleen | 130768b | 2013-06-17 17:36:47 -0700 | [diff] [blame] | 236 | }; |
| 237 | |
Andi Kleen | a405bad | 2013-09-20 07:40:40 -0700 | [diff] [blame] | 238 | #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL |
| 239 | |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 240 | /* Same as HSW, plus TSC */ |
| 241 | |
| 242 | struct pebs_record_skl { |
| 243 | u64 flags, ip; |
| 244 | u64 ax, bx, cx, dx; |
| 245 | u64 si, di, bp, sp; |
| 246 | u64 r8, r9, r10, r11; |
| 247 | u64 r12, r13, r14, r15; |
| 248 | u64 status, dla, dse, lat; |
| 249 | u64 real_ip, tsx_tuning; |
| 250 | u64 tsc; |
| 251 | }; |
| 252 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 253 | void init_debug_store_on_cpu(int cpu) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 254 | { |
| 255 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
| 256 | |
| 257 | if (!ds) |
| 258 | return; |
| 259 | |
| 260 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, |
| 261 | (u32)((u64)(unsigned long)ds), |
| 262 | (u32)((u64)(unsigned long)ds >> 32)); |
| 263 | } |
| 264 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 265 | void fini_debug_store_on_cpu(int cpu) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 266 | { |
| 267 | if (!per_cpu(cpu_hw_events, cpu).ds) |
| 268 | return; |
| 269 | |
| 270 | wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0); |
| 271 | } |
| 272 | |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 273 | static DEFINE_PER_CPU(void *, insn_buffer); |
| 274 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 275 | static void *dsalloc(size_t size, gfp_t flags, int node) |
| 276 | { |
Kees Cook | e71fac0 | 2018-01-03 10:17:35 -0800 | [diff] [blame] | 277 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 278 | unsigned int order = get_order(size); |
| 279 | struct page *page; |
| 280 | unsigned long addr; |
| 281 | |
| 282 | page = __alloc_pages_node(node, flags | __GFP_ZERO, order); |
| 283 | if (!page) |
| 284 | return NULL; |
| 285 | addr = (unsigned long)page_address(page); |
| 286 | if (kaiser_add_mapping(addr, size, __PAGE_KERNEL) < 0) { |
| 287 | __free_pages(page, order); |
| 288 | addr = 0; |
| 289 | } |
| 290 | return (void *)addr; |
| 291 | #else |
| 292 | return kmalloc_node(size, flags | __GFP_ZERO, node); |
| 293 | #endif |
| 294 | } |
| 295 | |
| 296 | static void dsfree(const void *buffer, size_t size) |
| 297 | { |
Kees Cook | e71fac0 | 2018-01-03 10:17:35 -0800 | [diff] [blame] | 298 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 299 | if (!buffer) |
| 300 | return; |
| 301 | kaiser_remove_mapping((unsigned long)buffer, size); |
| 302 | free_pages((unsigned long)buffer, get_order(size)); |
| 303 | #else |
| 304 | kfree(buffer); |
| 305 | #endif |
| 306 | } |
| 307 | |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 308 | static int alloc_pebs_buffer(int cpu) |
| 309 | { |
| 310 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
Peter Zijlstra | 96681fc | 2010-10-19 14:55:33 +0200 | [diff] [blame] | 311 | int node = cpu_to_node(cpu); |
Yan, Zheng | 3569c0d | 2015-05-06 15:33:50 -0400 | [diff] [blame] | 312 | int max; |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 313 | void *buffer, *ibuffer; |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 314 | |
| 315 | if (!x86_pmu.pebs) |
| 316 | return 0; |
| 317 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 318 | buffer = dsalloc(x86_pmu.pebs_buffer_size, GFP_KERNEL, node); |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 319 | if (unlikely(!buffer)) |
| 320 | return -ENOMEM; |
| 321 | |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 322 | /* |
| 323 | * HSW+ already provides us the eventing ip; no need to allocate this |
| 324 | * buffer then. |
| 325 | */ |
| 326 | if (x86_pmu.intel_cap.pebs_format < 2) { |
| 327 | ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node); |
| 328 | if (!ibuffer) { |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 329 | dsfree(buffer, x86_pmu.pebs_buffer_size); |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 330 | return -ENOMEM; |
| 331 | } |
| 332 | per_cpu(insn_buffer, cpu) = ibuffer; |
| 333 | } |
| 334 | |
Jiri Olsa | e72daf3 | 2016-03-01 20:03:52 +0100 | [diff] [blame] | 335 | max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size; |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 336 | |
| 337 | ds->pebs_buffer_base = (u64)(unsigned long)buffer; |
| 338 | ds->pebs_index = ds->pebs_buffer_base; |
| 339 | ds->pebs_absolute_maximum = ds->pebs_buffer_base + |
| 340 | max * x86_pmu.pebs_record_size; |
| 341 | |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 342 | return 0; |
| 343 | } |
| 344 | |
Peter Zijlstra | b39f88a | 2010-10-19 14:08:29 +0200 | [diff] [blame] | 345 | static void release_pebs_buffer(int cpu) |
| 346 | { |
| 347 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
| 348 | |
| 349 | if (!ds || !x86_pmu.pebs) |
| 350 | return; |
| 351 | |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 352 | kfree(per_cpu(insn_buffer, cpu)); |
| 353 | per_cpu(insn_buffer, cpu) = NULL; |
| 354 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 355 | dsfree((void *)(unsigned long)ds->pebs_buffer_base, |
| 356 | x86_pmu.pebs_buffer_size); |
Peter Zijlstra | b39f88a | 2010-10-19 14:08:29 +0200 | [diff] [blame] | 357 | ds->pebs_buffer_base = 0; |
| 358 | } |
| 359 | |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 360 | static int alloc_bts_buffer(int cpu) |
| 361 | { |
| 362 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
Peter Zijlstra | 96681fc | 2010-10-19 14:55:33 +0200 | [diff] [blame] | 363 | int node = cpu_to_node(cpu); |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 364 | int max, thresh; |
| 365 | void *buffer; |
| 366 | |
| 367 | if (!x86_pmu.bts) |
| 368 | return 0; |
| 369 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 370 | buffer = dsalloc(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node); |
David Rientjes | 4485154 | 2014-06-30 16:04:08 -0700 | [diff] [blame] | 371 | if (unlikely(!buffer)) { |
| 372 | WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__); |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 373 | return -ENOMEM; |
David Rientjes | 4485154 | 2014-06-30 16:04:08 -0700 | [diff] [blame] | 374 | } |
Peter Zijlstra | 5ee25c8 | 2010-10-19 14:15:04 +0200 | [diff] [blame] | 375 | |
| 376 | max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE; |
| 377 | thresh = max / 16; |
| 378 | |
| 379 | ds->bts_buffer_base = (u64)(unsigned long)buffer; |
| 380 | ds->bts_index = ds->bts_buffer_base; |
| 381 | ds->bts_absolute_maximum = ds->bts_buffer_base + |
| 382 | max * BTS_RECORD_SIZE; |
| 383 | ds->bts_interrupt_threshold = ds->bts_absolute_maximum - |
| 384 | thresh * BTS_RECORD_SIZE; |
| 385 | |
| 386 | return 0; |
| 387 | } |
| 388 | |
Peter Zijlstra | b39f88a | 2010-10-19 14:08:29 +0200 | [diff] [blame] | 389 | static void release_bts_buffer(int cpu) |
| 390 | { |
| 391 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
| 392 | |
| 393 | if (!ds || !x86_pmu.bts) |
| 394 | return; |
| 395 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 396 | dsfree((void *)(unsigned long)ds->bts_buffer_base, BTS_BUFFER_SIZE); |
Peter Zijlstra | b39f88a | 2010-10-19 14:08:29 +0200 | [diff] [blame] | 397 | ds->bts_buffer_base = 0; |
| 398 | } |
| 399 | |
Peter Zijlstra | 65af94b | 2010-10-19 14:37:23 +0200 | [diff] [blame] | 400 | static int alloc_ds_buffer(int cpu) |
| 401 | { |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 402 | struct debug_store *ds = per_cpu_ptr(&cpu_debug_store, cpu); |
Peter Zijlstra | 65af94b | 2010-10-19 14:37:23 +0200 | [diff] [blame] | 403 | |
Hugh Dickins | f881e62 | 2017-08-23 14:21:14 -0700 | [diff] [blame] | 404 | memset(ds, 0, sizeof(*ds)); |
Peter Zijlstra | 65af94b | 2010-10-19 14:37:23 +0200 | [diff] [blame] | 405 | per_cpu(cpu_hw_events, cpu).ds = ds; |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | static void release_ds_buffer(int cpu) |
| 411 | { |
| 412 | struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds; |
| 413 | |
| 414 | if (!ds) |
| 415 | return; |
| 416 | |
| 417 | per_cpu(cpu_hw_events, cpu).ds = NULL; |
Peter Zijlstra | 65af94b | 2010-10-19 14:37:23 +0200 | [diff] [blame] | 418 | } |
| 419 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 420 | void release_ds_buffers(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 421 | { |
| 422 | int cpu; |
| 423 | |
| 424 | if (!x86_pmu.bts && !x86_pmu.pebs) |
| 425 | return; |
| 426 | |
| 427 | get_online_cpus(); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 428 | for_each_online_cpu(cpu) |
| 429 | fini_debug_store_on_cpu(cpu); |
| 430 | |
| 431 | for_each_possible_cpu(cpu) { |
Peter Zijlstra | b39f88a | 2010-10-19 14:08:29 +0200 | [diff] [blame] | 432 | release_pebs_buffer(cpu); |
| 433 | release_bts_buffer(cpu); |
Peter Zijlstra | 65af94b | 2010-10-19 14:37:23 +0200 | [diff] [blame] | 434 | release_ds_buffer(cpu); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 435 | } |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 436 | put_online_cpus(); |
| 437 | } |
| 438 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 439 | void reserve_ds_buffers(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 440 | { |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 441 | int bts_err = 0, pebs_err = 0; |
| 442 | int cpu; |
| 443 | |
| 444 | x86_pmu.bts_active = 0; |
| 445 | x86_pmu.pebs_active = 0; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 446 | |
| 447 | if (!x86_pmu.bts && !x86_pmu.pebs) |
Peter Zijlstra | f80c9e3 | 2010-10-19 14:50:02 +0200 | [diff] [blame] | 448 | return; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 449 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 450 | if (!x86_pmu.bts) |
| 451 | bts_err = 1; |
| 452 | |
| 453 | if (!x86_pmu.pebs) |
| 454 | pebs_err = 1; |
| 455 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 456 | get_online_cpus(); |
| 457 | |
| 458 | for_each_possible_cpu(cpu) { |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 459 | if (alloc_ds_buffer(cpu)) { |
| 460 | bts_err = 1; |
| 461 | pebs_err = 1; |
| 462 | } |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 463 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 464 | if (!bts_err && alloc_bts_buffer(cpu)) |
| 465 | bts_err = 1; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 466 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 467 | if (!pebs_err && alloc_pebs_buffer(cpu)) |
| 468 | pebs_err = 1; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 469 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 470 | if (bts_err && pebs_err) |
| 471 | break; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 472 | } |
| 473 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 474 | if (bts_err) { |
| 475 | for_each_possible_cpu(cpu) |
| 476 | release_bts_buffer(cpu); |
| 477 | } |
| 478 | |
| 479 | if (pebs_err) { |
| 480 | for_each_possible_cpu(cpu) |
| 481 | release_pebs_buffer(cpu); |
| 482 | } |
| 483 | |
| 484 | if (bts_err && pebs_err) { |
| 485 | for_each_possible_cpu(cpu) |
| 486 | release_ds_buffer(cpu); |
| 487 | } else { |
| 488 | if (x86_pmu.bts && !bts_err) |
| 489 | x86_pmu.bts_active = 1; |
| 490 | |
| 491 | if (x86_pmu.pebs && !pebs_err) |
| 492 | x86_pmu.pebs_active = 1; |
| 493 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 494 | for_each_online_cpu(cpu) |
| 495 | init_debug_store_on_cpu(cpu); |
| 496 | } |
| 497 | |
| 498 | put_online_cpus(); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | /* |
| 502 | * BTS |
| 503 | */ |
| 504 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 505 | struct event_constraint bts_constraint = |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 506 | EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 507 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 508 | void intel_pmu_enable_bts(u64 config) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 509 | { |
| 510 | unsigned long debugctlmsr; |
| 511 | |
| 512 | debugctlmsr = get_debugctlmsr(); |
| 513 | |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 514 | debugctlmsr |= DEBUGCTLMSR_TR; |
| 515 | debugctlmsr |= DEBUGCTLMSR_BTS; |
Alexander Shishkin | 8062382 | 2015-01-30 12:40:35 +0200 | [diff] [blame] | 516 | if (config & ARCH_PERFMON_EVENTSEL_INT) |
| 517 | debugctlmsr |= DEBUGCTLMSR_BTINT; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 518 | |
| 519 | if (!(config & ARCH_PERFMON_EVENTSEL_OS)) |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 520 | debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 521 | |
| 522 | if (!(config & ARCH_PERFMON_EVENTSEL_USR)) |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 523 | debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 524 | |
| 525 | update_debugctlmsr(debugctlmsr); |
| 526 | } |
| 527 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 528 | void intel_pmu_disable_bts(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 529 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 530 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 531 | unsigned long debugctlmsr; |
| 532 | |
| 533 | if (!cpuc->ds) |
| 534 | return; |
| 535 | |
| 536 | debugctlmsr = get_debugctlmsr(); |
| 537 | |
| 538 | debugctlmsr &= |
Peter Zijlstra | 7c5ecaf | 2010-03-25 14:51:49 +0100 | [diff] [blame] | 539 | ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT | |
| 540 | DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 541 | |
| 542 | update_debugctlmsr(debugctlmsr); |
| 543 | } |
| 544 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 545 | int intel_pmu_drain_bts_buffer(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 546 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 547 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 548 | struct debug_store *ds = cpuc->ds; |
| 549 | struct bts_record { |
| 550 | u64 from; |
| 551 | u64 to; |
| 552 | u64 flags; |
| 553 | }; |
Robert Richter | 15c7ad5 | 2012-06-20 20:46:33 +0200 | [diff] [blame] | 554 | struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 555 | struct bts_record *at, *base, *top; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 556 | struct perf_output_handle handle; |
| 557 | struct perf_event_header header; |
| 558 | struct perf_sample_data data; |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 559 | unsigned long skip = 0; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 560 | struct pt_regs regs; |
| 561 | |
| 562 | if (!event) |
Stephane Eranian | b0b2072 | 2010-09-10 13:28:01 +0200 | [diff] [blame] | 563 | return 0; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 564 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 565 | if (!x86_pmu.bts_active) |
Stephane Eranian | b0b2072 | 2010-09-10 13:28:01 +0200 | [diff] [blame] | 566 | return 0; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 567 | |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 568 | base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; |
| 569 | top = (struct bts_record *)(unsigned long)ds->bts_index; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 570 | |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 571 | if (top <= base) |
Stephane Eranian | b0b2072 | 2010-09-10 13:28:01 +0200 | [diff] [blame] | 572 | return 0; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 573 | |
Stephane Eranian | 0e48026 | 2013-03-19 16:10:38 +0100 | [diff] [blame] | 574 | memset(®s, 0, sizeof(regs)); |
| 575 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 576 | ds->bts_index = ds->bts_buffer_base; |
| 577 | |
Robert Richter | fd0d000 | 2012-04-02 20:19:08 +0200 | [diff] [blame] | 578 | perf_sample_data_init(&data, 0, event->hw.last_period); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 579 | |
| 580 | /* |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 581 | * BTS leaks kernel addresses in branches across the cpl boundary, |
| 582 | * such as traps or system calls, so unless the user is asking for |
| 583 | * kernel tracing (and right now it's not possible), we'd need to |
| 584 | * filter them out. But first we need to count how many of those we |
| 585 | * have in the current batch. This is an extra O(n) pass, however, |
| 586 | * it's much faster than the other one especially considering that |
| 587 | * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the |
| 588 | * alloc_bts_buffer()). |
| 589 | */ |
| 590 | for (at = base; at < top; at++) { |
| 591 | /* |
| 592 | * Note that right now *this* BTS code only works if |
| 593 | * attr::exclude_kernel is set, but let's keep this extra |
| 594 | * check here in case that changes. |
| 595 | */ |
| 596 | if (event->attr.exclude_kernel && |
| 597 | (kernel_ip(at->from) || kernel_ip(at->to))) |
| 598 | skip++; |
| 599 | } |
| 600 | |
| 601 | /* |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 602 | * Prepare a generic sample, i.e. fill in the invariant fields. |
| 603 | * We will overwrite the from and to address before we output |
| 604 | * the sample. |
| 605 | */ |
Peter Zijlstra | e8d8a90 | 2016-03-18 17:31:27 +0100 | [diff] [blame] | 606 | rcu_read_lock(); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 607 | perf_prepare_sample(&header, &data, event, ®s); |
| 608 | |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 609 | if (perf_output_begin(&handle, event, header.size * |
| 610 | (top - base - skip))) |
Peter Zijlstra | e8d8a90 | 2016-03-18 17:31:27 +0100 | [diff] [blame] | 611 | goto unlock; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 612 | |
Alexander Shishkin | a09d31f4 | 2015-08-31 17:09:27 +0300 | [diff] [blame] | 613 | for (at = base; at < top; at++) { |
| 614 | /* Filter out any records that contain kernel addresses. */ |
| 615 | if (event->attr.exclude_kernel && |
| 616 | (kernel_ip(at->from) || kernel_ip(at->to))) |
| 617 | continue; |
| 618 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 619 | data.ip = at->from; |
| 620 | data.addr = at->to; |
| 621 | |
| 622 | perf_output_sample(&handle, &header, &data, event); |
| 623 | } |
| 624 | |
| 625 | perf_output_end(&handle); |
| 626 | |
| 627 | /* There's new data available. */ |
| 628 | event->hw.interrupts++; |
| 629 | event->pending_kill = POLL_IN; |
Peter Zijlstra | e8d8a90 | 2016-03-18 17:31:27 +0100 | [diff] [blame] | 630 | unlock: |
| 631 | rcu_read_unlock(); |
Stephane Eranian | b0b2072 | 2010-09-10 13:28:01 +0200 | [diff] [blame] | 632 | return 1; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 633 | } |
| 634 | |
Yan, Zheng | 9c964ef | 2015-05-06 15:33:51 -0400 | [diff] [blame] | 635 | static inline void intel_pmu_drain_pebs_buffer(void) |
| 636 | { |
| 637 | struct pt_regs regs; |
| 638 | |
| 639 | x86_pmu.drain_pebs(®s); |
| 640 | } |
| 641 | |
| 642 | void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in) |
| 643 | { |
| 644 | if (!sched_in) |
| 645 | intel_pmu_drain_pebs_buffer(); |
| 646 | } |
| 647 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 648 | /* |
| 649 | * PEBS |
| 650 | */ |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 651 | struct event_constraint intel_core2_pebs_event_constraints[] = { |
Andi Kleen | af4bdcf | 2014-09-24 07:34:48 -0700 | [diff] [blame] | 652 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ |
| 653 | INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */ |
| 654 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */ |
| 655 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */ |
| 656 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ |
Peter Zijlstra | 517e634 | 2015-04-11 12:16:22 +0200 | [diff] [blame] | 657 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
| 658 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 659 | EVENT_CONSTRAINT_END |
| 660 | }; |
| 661 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 662 | struct event_constraint intel_atom_pebs_event_constraints[] = { |
Andi Kleen | af4bdcf | 2014-09-24 07:34:48 -0700 | [diff] [blame] | 663 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */ |
| 664 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */ |
| 665 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */ |
Peter Zijlstra | 517e634 | 2015-04-11 12:16:22 +0200 | [diff] [blame] | 666 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
| 667 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01), |
Stephane Eranian | 673d188 | 2015-12-03 21:03:10 +0100 | [diff] [blame] | 668 | /* Allow all events as PEBS with no flags */ |
| 669 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), |
Stephane Eranian | 17e3162 | 2011-03-02 17:05:01 +0200 | [diff] [blame] | 670 | EVENT_CONSTRAINT_END |
| 671 | }; |
| 672 | |
Yan, Zheng | 1fa64180 | 2013-07-18 17:02:24 +0800 | [diff] [blame] | 673 | struct event_constraint intel_slm_pebs_event_constraints[] = { |
Kan Liang | 3363673 | 2015-01-12 17:42:21 +0000 | [diff] [blame] | 674 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
| 675 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1), |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 676 | /* Allow all events as PEBS with no flags */ |
| 677 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), |
Yan, Zheng | 1fa64180 | 2013-07-18 17:02:24 +0800 | [diff] [blame] | 678 | EVENT_CONSTRAINT_END |
| 679 | }; |
| 680 | |
Kan Liang | 8b92c3a | 2016-04-15 00:42:47 -0700 | [diff] [blame] | 681 | struct event_constraint intel_glm_pebs_event_constraints[] = { |
| 682 | /* Allow all events as PEBS with no flags */ |
| 683 | INTEL_ALL_EVENT_CONSTRAINT(0, 0x1), |
| 684 | EVENT_CONSTRAINT_END |
| 685 | }; |
| 686 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 687 | struct event_constraint intel_nehalem_pebs_event_constraints[] = { |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 688 | INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ |
Andi Kleen | af4bdcf | 2014-09-24 07:34:48 -0700 | [diff] [blame] | 689 | INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ |
| 690 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ |
| 691 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */ |
Lin Ming | 7d5d02d | 2011-03-09 23:21:29 +0800 | [diff] [blame] | 692 | INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ |
Andi Kleen | af4bdcf | 2014-09-24 07:34:48 -0700 | [diff] [blame] | 693 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ |
| 694 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */ |
| 695 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ |
| 696 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ |
| 697 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ |
| 698 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ |
Peter Zijlstra | 517e634 | 2015-04-11 12:16:22 +0200 | [diff] [blame] | 699 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
| 700 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), |
Stephane Eranian | 17e3162 | 2011-03-02 17:05:01 +0200 | [diff] [blame] | 701 | EVENT_CONSTRAINT_END |
| 702 | }; |
| 703 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 704 | struct event_constraint intel_westmere_pebs_event_constraints[] = { |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 705 | INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */ |
Andi Kleen | af4bdcf | 2014-09-24 07:34:48 -0700 | [diff] [blame] | 706 | INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */ |
| 707 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */ |
| 708 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */ |
Lin Ming | 7d5d02d | 2011-03-09 23:21:29 +0800 | [diff] [blame] | 709 | INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */ |
Andi Kleen | af4bdcf | 2014-09-24 07:34:48 -0700 | [diff] [blame] | 710 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */ |
| 711 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */ |
| 712 | INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */ |
| 713 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */ |
| 714 | INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */ |
| 715 | INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */ |
Peter Zijlstra | 517e634 | 2015-04-11 12:16:22 +0200 | [diff] [blame] | 716 | /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */ |
| 717 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 718 | EVENT_CONSTRAINT_END |
| 719 | }; |
| 720 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 721 | struct event_constraint intel_snb_pebs_event_constraints[] = { |
Andi Kleen | 0dbc947 | 2014-09-24 07:34:47 -0700 | [diff] [blame] | 722 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 723 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
Stephane Eranian | 9ad64c0 | 2013-01-24 16:10:34 +0100 | [diff] [blame] | 724 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 725 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
| 726 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), |
Maria Dimakopoulou | b63b4b4 | 2014-11-17 20:07:00 +0100 | [diff] [blame] | 727 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ |
| 728 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ |
| 729 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ |
| 730 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 731 | /* Allow all events as PEBS with no flags */ |
| 732 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), |
Lin Ming | b06b3d4 | 2011-03-02 21:27:04 +0800 | [diff] [blame] | 733 | EVENT_CONSTRAINT_END |
| 734 | }; |
| 735 | |
Stephane Eranian | 20a36e3 | 2012-09-11 01:07:01 +0200 | [diff] [blame] | 736 | struct event_constraint intel_ivb_pebs_event_constraints[] = { |
Andi Kleen | 0dbc947 | 2014-09-24 07:34:47 -0700 | [diff] [blame] | 737 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 738 | INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ |
Stephane Eranian | 9ad64c0 | 2013-01-24 16:10:34 +0100 | [diff] [blame] | 739 | INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 740 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
| 741 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), |
Andi Kleen | 7246976 | 2015-12-04 03:50:52 -0800 | [diff] [blame] | 742 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
| 743 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), |
Maria Dimakopoulou | b63b4b4 | 2014-11-17 20:07:00 +0100 | [diff] [blame] | 744 | INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ |
| 745 | INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ |
| 746 | INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ |
| 747 | INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 748 | /* Allow all events as PEBS with no flags */ |
| 749 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), |
Stephane Eranian | 20a36e3 | 2012-09-11 01:07:01 +0200 | [diff] [blame] | 750 | EVENT_CONSTRAINT_END |
| 751 | }; |
| 752 | |
Andi Kleen | 3044318 | 2013-06-17 17:36:49 -0700 | [diff] [blame] | 753 | struct event_constraint intel_hsw_pebs_event_constraints[] = { |
Andi Kleen | 0dbc947 | 2014-09-24 07:34:47 -0700 | [diff] [blame] | 754 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 755 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
| 756 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
| 757 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), |
Andi Kleen | 7246976 | 2015-12-04 03:50:52 -0800 | [diff] [blame] | 758 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
| 759 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 760 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ |
Maria Dimakopoulou | b63b4b4 | 2014-11-17 20:07:00 +0100 | [diff] [blame] | 761 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ |
| 762 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ |
| 763 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ |
| 764 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ |
| 765 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ |
| 766 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ |
| 767 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ |
| 768 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ |
| 769 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ |
| 770 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ |
Andi Kleen | 86a0446 | 2014-08-11 21:27:10 +0200 | [diff] [blame] | 771 | /* Allow all events as PEBS with no flags */ |
| 772 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), |
Andi Kleen | 3044318 | 2013-06-17 17:36:49 -0700 | [diff] [blame] | 773 | EVENT_CONSTRAINT_END |
| 774 | }; |
| 775 | |
Stephane Eranian | b3e6246 | 2016-03-03 20:50:42 +0100 | [diff] [blame] | 776 | struct event_constraint intel_bdw_pebs_event_constraints[] = { |
| 777 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ |
| 778 | INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
| 779 | /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */ |
| 780 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf), |
| 781 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
| 782 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), |
| 783 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ |
| 784 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */ |
| 785 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */ |
| 786 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */ |
| 787 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ |
| 788 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */ |
| 789 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */ |
| 790 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ |
| 791 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ |
| 792 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */ |
| 793 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */ |
| 794 | /* Allow all events as PEBS with no flags */ |
| 795 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), |
| 796 | EVENT_CONSTRAINT_END |
| 797 | }; |
| 798 | |
| 799 | |
Andi Kleen | 9a92e16 | 2015-05-10 12:22:44 -0700 | [diff] [blame] | 800 | struct event_constraint intel_skl_pebs_event_constraints[] = { |
| 801 | INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
Andi Kleen | 7246976 | 2015-12-04 03:50:52 -0800 | [diff] [blame] | 802 | /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */ |
| 803 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2), |
Andi Kleen | 442f5c7 | 2015-12-04 03:50:32 -0800 | [diff] [blame] | 804 | /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */ |
| 805 | INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f), |
Andi Kleen | 9a92e16 | 2015-05-10 12:22:44 -0700 | [diff] [blame] | 806 | INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */ |
| 807 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */ |
| 808 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */ |
| 809 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */ |
| 810 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */ |
| 811 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */ |
| 812 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */ |
| 813 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */ |
| 814 | INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */ |
| 815 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ |
| 816 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ |
| 817 | INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */ |
| 818 | /* Allow all events as PEBS with no flags */ |
| 819 | INTEL_ALL_EVENT_CONSTRAINT(0, 0xf), |
| 820 | EVENT_CONSTRAINT_END |
| 821 | }; |
| 822 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 823 | struct event_constraint *intel_pebs_constraints(struct perf_event *event) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 824 | { |
| 825 | struct event_constraint *c; |
| 826 | |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 827 | if (!event->attr.precise_ip) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 828 | return NULL; |
| 829 | |
| 830 | if (x86_pmu.pebs_constraints) { |
| 831 | for_each_event_constraint(c, x86_pmu.pebs_constraints) { |
Stephane Eranian | 9fac2cf | 2013-01-24 16:10:27 +0100 | [diff] [blame] | 832 | if ((event->hw.config & c->cmask) == c->code) { |
| 833 | event->hw.flags |= c->flags; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 834 | return c; |
Stephane Eranian | 9fac2cf | 2013-01-24 16:10:27 +0100 | [diff] [blame] | 835 | } |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 836 | } |
| 837 | } |
| 838 | |
| 839 | return &emptyconstraint; |
| 840 | } |
| 841 | |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 842 | /* |
| 843 | * We need the sched_task callback even for per-cpu events when we use |
| 844 | * the large interrupt threshold, such that we can provide PID and TID |
| 845 | * to PEBS samples. |
| 846 | */ |
| 847 | static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc) |
Yan, Zheng | 3569c0d | 2015-05-06 15:33:50 -0400 | [diff] [blame] | 848 | { |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 849 | return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); |
| 850 | } |
| 851 | |
| 852 | static inline void pebs_update_threshold(struct cpu_hw_events *cpuc) |
| 853 | { |
| 854 | struct debug_store *ds = cpuc->ds; |
| 855 | u64 threshold; |
| 856 | |
| 857 | if (cpuc->n_pebs == cpuc->n_large_pebs) { |
| 858 | threshold = ds->pebs_absolute_maximum - |
| 859 | x86_pmu.max_pebs_events * x86_pmu.pebs_record_size; |
| 860 | } else { |
| 861 | threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size; |
| 862 | } |
| 863 | |
| 864 | ds->pebs_interrupt_threshold = threshold; |
| 865 | } |
| 866 | |
| 867 | static void |
| 868 | pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc, struct pmu *pmu) |
| 869 | { |
Jiri Olsa | b6a32f0 | 2016-08-18 11:09:52 +0200 | [diff] [blame] | 870 | /* |
| 871 | * Make sure we get updated with the first PEBS |
| 872 | * event. It will trigger also during removal, but |
| 873 | * that does not hurt: |
| 874 | */ |
| 875 | bool update = cpuc->n_pebs == 1; |
| 876 | |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 877 | if (needed_cb != pebs_needs_sched_cb(cpuc)) { |
| 878 | if (!needed_cb) |
| 879 | perf_sched_cb_inc(pmu); |
| 880 | else |
| 881 | perf_sched_cb_dec(pmu); |
| 882 | |
Jiri Olsa | b6a32f0 | 2016-08-18 11:09:52 +0200 | [diff] [blame] | 883 | update = true; |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 884 | } |
Jiri Olsa | b6a32f0 | 2016-08-18 11:09:52 +0200 | [diff] [blame] | 885 | |
| 886 | if (update) |
| 887 | pebs_update_threshold(cpuc); |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 888 | } |
| 889 | |
Peter Zijlstra | 68f7082 | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 890 | void intel_pmu_pebs_add(struct perf_event *event) |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 891 | { |
| 892 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| 893 | struct hw_perf_event *hwc = &event->hw; |
| 894 | bool needed_cb = pebs_needs_sched_cb(cpuc); |
| 895 | |
| 896 | cpuc->n_pebs++; |
| 897 | if (hwc->flags & PERF_X86_EVENT_FREERUNNING) |
| 898 | cpuc->n_large_pebs++; |
| 899 | |
| 900 | pebs_update_state(needed_cb, cpuc, event->ctx->pmu); |
Yan, Zheng | 3569c0d | 2015-05-06 15:33:50 -0400 | [diff] [blame] | 901 | } |
| 902 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 903 | void intel_pmu_pebs_enable(struct perf_event *event) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 904 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 905 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 906 | struct hw_perf_event *hwc = &event->hw; |
Yan, Zheng | 851559e | 2015-05-06 15:33:47 -0400 | [diff] [blame] | 907 | struct debug_store *ds = cpuc->ds; |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 908 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 909 | hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; |
| 910 | |
Peter Zijlstra | ad0e6cf | 2010-03-06 19:49:06 +0100 | [diff] [blame] | 911 | cpuc->pebs_enabled |= 1ULL << hwc->idx; |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 912 | |
| 913 | if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) |
| 914 | cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); |
Stephane Eranian | 9ad64c0 | 2013-01-24 16:10:34 +0100 | [diff] [blame] | 915 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) |
| 916 | cpuc->pebs_enabled |= 1ULL << 63; |
Yan, Zheng | 851559e | 2015-05-06 15:33:47 -0400 | [diff] [blame] | 917 | |
Yan, Zheng | 3569c0d | 2015-05-06 15:33:50 -0400 | [diff] [blame] | 918 | /* |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 919 | * Use auto-reload if possible to save a MSR write in the PMI. |
| 920 | * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD. |
Yan, Zheng | 3569c0d | 2015-05-06 15:33:50 -0400 | [diff] [blame] | 921 | */ |
Yan, Zheng | 851559e | 2015-05-06 15:33:47 -0400 | [diff] [blame] | 922 | if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { |
| 923 | ds->pebs_event_reset[hwc->idx] = |
| 924 | (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; |
| 925 | } |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 926 | } |
Yan, Zheng | 3569c0d | 2015-05-06 15:33:50 -0400 | [diff] [blame] | 927 | |
Peter Zijlstra | 68f7082 | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 928 | void intel_pmu_pebs_del(struct perf_event *event) |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 929 | { |
| 930 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| 931 | struct hw_perf_event *hwc = &event->hw; |
| 932 | bool needed_cb = pebs_needs_sched_cb(cpuc); |
| 933 | |
| 934 | cpuc->n_pebs--; |
| 935 | if (hwc->flags & PERF_X86_EVENT_FREERUNNING) |
| 936 | cpuc->n_large_pebs--; |
| 937 | |
| 938 | pebs_update_state(needed_cb, cpuc, event->ctx->pmu); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 939 | } |
| 940 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 941 | void intel_pmu_pebs_disable(struct perf_event *event) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 942 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 943 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 944 | struct hw_perf_event *hwc = &event->hw; |
Liang, Kan | 2a853e1 | 2015-07-03 20:08:27 +0000 | [diff] [blame] | 945 | |
Peter Zijlstra | 09e61b4f | 2016-07-06 18:02:43 +0200 | [diff] [blame] | 946 | if (cpuc->n_pebs == cpuc->n_large_pebs) |
Liang, Kan | 2a853e1 | 2015-07-03 20:08:27 +0000 | [diff] [blame] | 947 | intel_pmu_drain_pebs_buffer(); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 948 | |
Peter Zijlstra | ad0e6cf | 2010-03-06 19:49:06 +0100 | [diff] [blame] | 949 | cpuc->pebs_enabled &= ~(1ULL << hwc->idx); |
Stephane Eranian | 983433b | 2013-06-21 16:20:41 +0200 | [diff] [blame] | 950 | |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 951 | if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) |
Stephane Eranian | 983433b | 2013-06-21 16:20:41 +0200 | [diff] [blame] | 952 | cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); |
Peter Zijlstra | b371b59 | 2015-05-21 10:57:13 +0200 | [diff] [blame] | 953 | else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) |
Stephane Eranian | 983433b | 2013-06-21 16:20:41 +0200 | [diff] [blame] | 954 | cpuc->pebs_enabled &= ~(1ULL << 63); |
| 955 | |
Peter Zijlstra | 4807e3d | 2010-03-06 13:47:07 +0100 | [diff] [blame] | 956 | if (cpuc->enabled) |
Peter Zijlstra | ad0e6cf | 2010-03-06 19:49:06 +0100 | [diff] [blame] | 957 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 958 | |
| 959 | hwc->config |= ARCH_PERFMON_EVENTSEL_INT; |
| 960 | } |
| 961 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 962 | void intel_pmu_pebs_enable_all(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 963 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 964 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 965 | |
| 966 | if (cpuc->pebs_enabled) |
| 967 | wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); |
| 968 | } |
| 969 | |
Kevin Winchester | de0428a | 2011-08-30 20:41:05 -0300 | [diff] [blame] | 970 | void intel_pmu_pebs_disable_all(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 971 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 972 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 973 | |
| 974 | if (cpuc->pebs_enabled) |
| 975 | wrmsrl(MSR_IA32_PEBS_ENABLE, 0); |
| 976 | } |
| 977 | |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 978 | static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs) |
| 979 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 980 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 981 | unsigned long from = cpuc->lbr_entries[0].from; |
| 982 | unsigned long old_to, to = cpuc->lbr_entries[0].to; |
| 983 | unsigned long ip = regs->ip; |
Peter Zijlstra | 57d1c0c | 2011-10-07 13:36:40 +0200 | [diff] [blame] | 984 | int is_64bit = 0; |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 985 | void *kaddr; |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 986 | int size; |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 987 | |
Peter Zijlstra | 8db909a | 2010-03-03 17:07:40 +0100 | [diff] [blame] | 988 | /* |
| 989 | * We don't need to fixup if the PEBS assist is fault like |
| 990 | */ |
| 991 | if (!x86_pmu.intel_cap.pebs_trap) |
| 992 | return 1; |
| 993 | |
Peter Zijlstra | a562b18 | 2010-03-05 16:29:14 +0100 | [diff] [blame] | 994 | /* |
| 995 | * No LBR entry, no basic block, no rewinding |
| 996 | */ |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 997 | if (!cpuc->lbr_stack.nr || !from || !to) |
| 998 | return 0; |
| 999 | |
Peter Zijlstra | a562b18 | 2010-03-05 16:29:14 +0100 | [diff] [blame] | 1000 | /* |
| 1001 | * Basic blocks should never cross user/kernel boundaries |
| 1002 | */ |
| 1003 | if (kernel_ip(ip) != kernel_ip(to)) |
| 1004 | return 0; |
| 1005 | |
| 1006 | /* |
| 1007 | * unsigned math, either ip is before the start (impossible) or |
| 1008 | * the basic block is larger than 1 page (sanity) |
| 1009 | */ |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1010 | if ((ip - to) > PEBS_FIXUP_SIZE) |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1011 | return 0; |
| 1012 | |
| 1013 | /* |
| 1014 | * We sampled a branch insn, rewind using the LBR stack |
| 1015 | */ |
| 1016 | if (ip == to) { |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 1017 | set_linear_ip(regs, from); |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1018 | return 1; |
| 1019 | } |
| 1020 | |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 1021 | size = ip - to; |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1022 | if (!kernel_ip(ip)) { |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 1023 | int bytes; |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1024 | u8 *buf = this_cpu_read(insn_buffer); |
| 1025 | |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 1026 | /* 'size' must fit our buffer, see above */ |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1027 | bytes = copy_from_user_nmi(buf, (void __user *)to, size); |
Peter Zijlstra | 0a19684 | 2013-10-30 21:16:22 +0100 | [diff] [blame] | 1028 | if (bytes != 0) |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1029 | return 0; |
| 1030 | |
| 1031 | kaddr = buf; |
| 1032 | } else { |
| 1033 | kaddr = (void *)to; |
| 1034 | } |
| 1035 | |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1036 | do { |
| 1037 | struct insn insn; |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1038 | |
| 1039 | old_to = to; |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1040 | |
Peter Zijlstra | 57d1c0c | 2011-10-07 13:36:40 +0200 | [diff] [blame] | 1041 | #ifdef CONFIG_X86_64 |
| 1042 | is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32); |
| 1043 | #endif |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 1044 | insn_init(&insn, kaddr, size, is_64bit); |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1045 | insn_get_length(&insn); |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 1046 | /* |
| 1047 | * Make sure there was not a problem decoding the |
| 1048 | * instruction and getting the length. This is |
| 1049 | * doubly important because we have an infinite |
| 1050 | * loop if insn.length=0. |
| 1051 | */ |
| 1052 | if (!insn.length) |
| 1053 | break; |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1054 | |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1055 | to += insn.length; |
Peter Zijlstra | 9536c8d | 2013-10-15 12:14:04 +0200 | [diff] [blame] | 1056 | kaddr += insn.length; |
Dave Hansen | 6ba48ff | 2014-11-14 07:39:57 -0800 | [diff] [blame] | 1057 | size -= insn.length; |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1058 | } while (to < ip); |
| 1059 | |
| 1060 | if (to == ip) { |
Peter Zijlstra | d07bdfd | 2012-07-10 09:42:15 +0200 | [diff] [blame] | 1061 | set_linear_ip(regs, old_to); |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1062 | return 1; |
| 1063 | } |
| 1064 | |
Peter Zijlstra | a562b18 | 2010-03-05 16:29:14 +0100 | [diff] [blame] | 1065 | /* |
| 1066 | * Even though we decoded the basic block, the instruction stream |
| 1067 | * never matched the given IP, either the TO or the IP got corrupted. |
| 1068 | */ |
Peter Zijlstra | ef21f68 | 2010-03-03 13:12:23 +0100 | [diff] [blame] | 1069 | return 0; |
| 1070 | } |
| 1071 | |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 1072 | static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs) |
Andi Kleen | 748e86a | 2013-09-05 20:37:39 -0700 | [diff] [blame] | 1073 | { |
| 1074 | if (pebs->tsx_tuning) { |
| 1075 | union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning }; |
| 1076 | return tsx.cycles_last_block; |
| 1077 | } |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 1081 | static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs) |
Andi Kleen | a405bad | 2013-09-20 07:40:40 -0700 | [diff] [blame] | 1082 | { |
| 1083 | u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32; |
| 1084 | |
| 1085 | /* For RTM XABORTs also log the abort code from AX */ |
| 1086 | if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1)) |
| 1087 | txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT; |
| 1088 | return txn; |
| 1089 | } |
| 1090 | |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1091 | static void setup_pebs_sample_data(struct perf_event *event, |
| 1092 | struct pt_regs *iregs, void *__pebs, |
| 1093 | struct perf_sample_data *data, |
| 1094 | struct pt_regs *regs) |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1095 | { |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1096 | #define PERF_X86_EVENT_PEBS_HSW_PREC \ |
| 1097 | (PERF_X86_EVENT_PEBS_ST_HSW | \ |
| 1098 | PERF_X86_EVENT_PEBS_LD_HSW | \ |
| 1099 | PERF_X86_EVENT_PEBS_NA_HSW) |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1100 | /* |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1101 | * We cast to the biggest pebs_record but are careful not to |
| 1102 | * unconditionally access the 'extra' entries. |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1103 | */ |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1104 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 1105 | struct pebs_record_skl *pebs = __pebs; |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1106 | u64 sample_type; |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1107 | int fll, fst, dsrc; |
| 1108 | int fl = event->hw.flags; |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1109 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1110 | if (pebs == NULL) |
| 1111 | return; |
| 1112 | |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1113 | sample_type = event->attr.sample_type; |
| 1114 | dsrc = sample_type & PERF_SAMPLE_DATA_SRC; |
| 1115 | |
| 1116 | fll = fl & PERF_X86_EVENT_PEBS_LDLAT; |
| 1117 | fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1118 | |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1119 | perf_sample_data_init(data, 0, event->hw.last_period); |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1120 | |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1121 | data->period = event->hw.last_period; |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1122 | |
| 1123 | /* |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1124 | * Use latency for weight (only avail with PEBS-LL) |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1125 | */ |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1126 | if (fll && (sample_type & PERF_SAMPLE_WEIGHT)) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1127 | data->weight = pebs->lat; |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1128 | |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1129 | /* |
| 1130 | * data.data_src encodes the data source |
| 1131 | */ |
| 1132 | if (dsrc) { |
| 1133 | u64 val = PERF_MEM_NA; |
| 1134 | if (fll) |
| 1135 | val = load_latency_data(pebs->dse); |
| 1136 | else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) |
| 1137 | val = precise_datala_hsw(event, pebs->dse); |
| 1138 | else if (fst) |
| 1139 | val = precise_store_data(pebs->dse); |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1140 | data->data_src.val = val; |
Stephane Eranian | f20093e | 2013-01-24 16:10:32 +0100 | [diff] [blame] | 1141 | } |
| 1142 | |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1143 | /* |
Peter Zijlstra | b800058 | 2016-11-17 18:17:31 +0100 | [diff] [blame] | 1144 | * We use the interrupt regs as a base because the PEBS record does not |
| 1145 | * contain a full regs set, specifically it seems to lack segment |
| 1146 | * descriptors, which get used by things like user_mode(). |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1147 | * |
Peter Zijlstra | b800058 | 2016-11-17 18:17:31 +0100 | [diff] [blame] | 1148 | * In the simple case fix up only the IP for PERF_SAMPLE_IP. |
| 1149 | * |
| 1150 | * We must however always use BP,SP from iregs for the unwinder to stay |
| 1151 | * sane; the record BP,SP can point into thin air when the record is |
| 1152 | * from a previous PMI context or an (I)RET happend between the record |
| 1153 | * and PMI. |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1154 | */ |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1155 | *regs = *iregs; |
| 1156 | regs->flags = pebs->flags; |
| 1157 | set_linear_ip(regs, pebs->ip); |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1158 | |
Stephane Eranian | aea4855 | 2014-09-24 13:48:38 +0200 | [diff] [blame] | 1159 | if (sample_type & PERF_SAMPLE_REGS_INTR) { |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1160 | regs->ax = pebs->ax; |
| 1161 | regs->bx = pebs->bx; |
| 1162 | regs->cx = pebs->cx; |
| 1163 | regs->dx = pebs->dx; |
| 1164 | regs->si = pebs->si; |
| 1165 | regs->di = pebs->di; |
Stephane Eranian | aea4855 | 2014-09-24 13:48:38 +0200 | [diff] [blame] | 1166 | |
Peter Zijlstra | b800058 | 2016-11-17 18:17:31 +0100 | [diff] [blame] | 1167 | /* |
| 1168 | * Per the above; only set BP,SP if we don't need callchains. |
| 1169 | * |
| 1170 | * XXX: does this make sense? |
| 1171 | */ |
| 1172 | if (!(sample_type & PERF_SAMPLE_CALLCHAIN)) { |
| 1173 | regs->bp = pebs->bp; |
| 1174 | regs->sp = pebs->sp; |
| 1175 | } |
| 1176 | |
| 1177 | /* |
| 1178 | * Preserve PERF_EFLAGS_VM from set_linear_ip(). |
| 1179 | */ |
| 1180 | regs->flags = pebs->flags | (regs->flags & PERF_EFLAGS_VM); |
Stephane Eranian | aea4855 | 2014-09-24 13:48:38 +0200 | [diff] [blame] | 1181 | #ifndef CONFIG_X86_32 |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1182 | regs->r8 = pebs->r8; |
| 1183 | regs->r9 = pebs->r9; |
| 1184 | regs->r10 = pebs->r10; |
| 1185 | regs->r11 = pebs->r11; |
| 1186 | regs->r12 = pebs->r12; |
| 1187 | regs->r13 = pebs->r13; |
| 1188 | regs->r14 = pebs->r14; |
| 1189 | regs->r15 = pebs->r15; |
Stephane Eranian | aea4855 | 2014-09-24 13:48:38 +0200 | [diff] [blame] | 1190 | #endif |
| 1191 | } |
| 1192 | |
Andi Kleen | 130768b | 2013-06-17 17:36:47 -0700 | [diff] [blame] | 1193 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) { |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1194 | regs->ip = pebs->real_ip; |
| 1195 | regs->flags |= PERF_EFLAGS_EXACT; |
| 1196 | } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs)) |
| 1197 | regs->flags |= PERF_EFLAGS_EXACT; |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1198 | else |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1199 | regs->flags &= ~PERF_EFLAGS_EXACT; |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1200 | |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1201 | if ((sample_type & PERF_SAMPLE_ADDR) && |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1202 | x86_pmu.intel_cap.pebs_format >= 1) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1203 | data->addr = pebs->dla; |
Andi Kleen | f9134f3 | 2013-06-17 17:36:52 -0700 | [diff] [blame] | 1204 | |
Andi Kleen | a405bad | 2013-09-20 07:40:40 -0700 | [diff] [blame] | 1205 | if (x86_pmu.intel_cap.pebs_format >= 2) { |
| 1206 | /* Only set the TSX weight when no memory weight. */ |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1207 | if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1208 | data->weight = intel_hsw_weight(pebs); |
Andi Kleen | a405bad | 2013-09-20 07:40:40 -0700 | [diff] [blame] | 1209 | |
Stephane Eranian | c8aab2e | 2014-08-11 21:27:13 +0200 | [diff] [blame] | 1210 | if (sample_type & PERF_SAMPLE_TRANSACTION) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1211 | data->txn = intel_hsw_transaction(pebs); |
Andi Kleen | a405bad | 2013-09-20 07:40:40 -0700 | [diff] [blame] | 1212 | } |
Andi Kleen | 748e86a | 2013-09-05 20:37:39 -0700 | [diff] [blame] | 1213 | |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 1214 | /* |
| 1215 | * v3 supplies an accurate time stamp, so we use that |
| 1216 | * for the time stamp. |
| 1217 | * |
| 1218 | * We can only do this for the default trace clock. |
| 1219 | */ |
| 1220 | if (x86_pmu.intel_cap.pebs_format >= 3 && |
| 1221 | event->attr.use_clockid == 0) |
| 1222 | data->time = native_sched_clock_from_tsc(pebs->tsc); |
| 1223 | |
Stephane Eranian | 60ce0fb | 2012-02-09 23:20:57 +0100 | [diff] [blame] | 1224 | if (has_branch_stack(event)) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1225 | data->br_stack = &cpuc->lbr_stack; |
| 1226 | } |
| 1227 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1228 | static inline void * |
| 1229 | get_next_pebs_record_by_bit(void *base, void *top, int bit) |
| 1230 | { |
| 1231 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
| 1232 | void *at; |
| 1233 | u64 pebs_status; |
| 1234 | |
Stephane Eranian | 1424a09 | 2015-12-03 23:33:18 +0100 | [diff] [blame] | 1235 | /* |
| 1236 | * fmt0 does not have a status bitfield (does not use |
| 1237 | * perf_record_nhm format) |
| 1238 | */ |
| 1239 | if (x86_pmu.intel_cap.pebs_format < 1) |
| 1240 | return base; |
| 1241 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1242 | if (base == NULL) |
| 1243 | return NULL; |
| 1244 | |
| 1245 | for (at = base; at < top; at += x86_pmu.pebs_record_size) { |
| 1246 | struct pebs_record_nhm *p = at; |
| 1247 | |
| 1248 | if (test_bit(bit, (unsigned long *)&p->status)) { |
Peter Zijlstra | a3d8654 | 2015-05-12 15:18:18 +0200 | [diff] [blame] | 1249 | /* PEBS v3 has accurate status bits */ |
| 1250 | if (x86_pmu.intel_cap.pebs_format >= 3) |
| 1251 | return at; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1252 | |
| 1253 | if (p->status == (1 << bit)) |
| 1254 | return at; |
| 1255 | |
| 1256 | /* clear non-PEBS bit and re-check */ |
| 1257 | pebs_status = p->status & cpuc->pebs_enabled; |
| 1258 | pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1; |
| 1259 | if (pebs_status == (1 << bit)) |
| 1260 | return at; |
| 1261 | } |
| 1262 | } |
| 1263 | return NULL; |
| 1264 | } |
| 1265 | |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1266 | static void __intel_pmu_pebs_event(struct perf_event *event, |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1267 | struct pt_regs *iregs, |
| 1268 | void *base, void *top, |
| 1269 | int bit, int count) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1270 | { |
| 1271 | struct perf_sample_data data; |
| 1272 | struct pt_regs regs; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1273 | void *at = get_next_pebs_record_by_bit(base, top, bit); |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1274 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1275 | if (!intel_pmu_save_and_restart(event) && |
| 1276 | !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)) |
Yan, Zheng | 43cf763 | 2015-05-06 15:33:48 -0400 | [diff] [blame] | 1277 | return; |
| 1278 | |
Peter Zijlstra | a3d8654 | 2015-05-12 15:18:18 +0200 | [diff] [blame] | 1279 | while (count > 1) { |
| 1280 | setup_pebs_sample_data(event, iregs, at, &data, ®s); |
| 1281 | perf_event_output(event, &data, ®s); |
| 1282 | at += x86_pmu.pebs_record_size; |
| 1283 | at = get_next_pebs_record_by_bit(at, top, bit); |
| 1284 | count--; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1285 | } |
Stephane Eranian | 60ce0fb | 2012-02-09 23:20:57 +0100 | [diff] [blame] | 1286 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1287 | setup_pebs_sample_data(event, iregs, at, &data, ®s); |
| 1288 | |
| 1289 | /* |
| 1290 | * All but the last records are processed. |
| 1291 | * The last one is left to be able to call the overflow handler. |
| 1292 | */ |
| 1293 | if (perf_event_overflow(event, &data, ®s)) { |
Peter Zijlstra | a4eaf7f | 2010-06-16 14:37:10 +0200 | [diff] [blame] | 1294 | x86_pmu_stop(event, 0); |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1295 | return; |
| 1296 | } |
| 1297 | |
Peter Zijlstra | 2b0b5c6 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1298 | } |
| 1299 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1300 | static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) |
| 1301 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1302 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1303 | struct debug_store *ds = cpuc->ds; |
| 1304 | struct perf_event *event = cpuc->events[0]; /* PMC0 only */ |
| 1305 | struct pebs_record_core *at, *top; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1306 | int n; |
| 1307 | |
Peter Zijlstra | 6809b6e | 2010-10-19 14:22:50 +0200 | [diff] [blame] | 1308 | if (!x86_pmu.pebs_active) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1309 | return; |
| 1310 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1311 | at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; |
| 1312 | top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; |
| 1313 | |
Peter Zijlstra | d80c750 | 2010-03-09 11:41:02 +0100 | [diff] [blame] | 1314 | /* |
| 1315 | * Whatever else happens, drain the thing |
| 1316 | */ |
| 1317 | ds->pebs_index = ds->pebs_buffer_base; |
| 1318 | |
| 1319 | if (!test_bit(0, cpuc->active_mask)) |
Peter Zijlstra | 8f4aebd | 2010-03-06 13:26:11 +0100 | [diff] [blame] | 1320 | return; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1321 | |
Peter Zijlstra | d80c750 | 2010-03-09 11:41:02 +0100 | [diff] [blame] | 1322 | WARN_ON_ONCE(!event); |
| 1323 | |
Peter Zijlstra | ab60834 | 2010-04-08 23:03:20 +0200 | [diff] [blame] | 1324 | if (!event->attr.precise_ip) |
Peter Zijlstra | d80c750 | 2010-03-09 11:41:02 +0100 | [diff] [blame] | 1325 | return; |
| 1326 | |
Stephane Eranian | 1424a09 | 2015-12-03 23:33:18 +0100 | [diff] [blame] | 1327 | n = top - at; |
Peter Zijlstra | d80c750 | 2010-03-09 11:41:02 +0100 | [diff] [blame] | 1328 | if (n <= 0) |
| 1329 | return; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1330 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1331 | __intel_pmu_pebs_event(event, iregs, at, top, 0, n); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1332 | } |
| 1333 | |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1334 | static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1335 | { |
Christoph Lameter | 89cbc76 | 2014-08-17 12:30:40 -0500 | [diff] [blame] | 1336 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1337 | struct debug_store *ds = cpuc->ds; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1338 | struct perf_event *event; |
| 1339 | void *base, *at, *top; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1340 | short counts[MAX_PEBS_EVENTS] = {}; |
Kan Liang | f38b0db | 2015-05-10 15:13:14 -0400 | [diff] [blame] | 1341 | short error[MAX_PEBS_EVENTS] = {}; |
Peter Zijlstra | a3d8654 | 2015-05-12 15:18:18 +0200 | [diff] [blame] | 1342 | int bit, i; |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1343 | |
| 1344 | if (!x86_pmu.pebs_active) |
| 1345 | return; |
| 1346 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1347 | base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1348 | top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1349 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1350 | ds->pebs_index = ds->pebs_buffer_base; |
| 1351 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1352 | if (unlikely(base >= top)) |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1353 | return; |
| 1354 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1355 | for (at = base; at < top; at += x86_pmu.pebs_record_size) { |
Andi Kleen | 130768b | 2013-06-17 17:36:47 -0700 | [diff] [blame] | 1356 | struct pebs_record_nhm *p = at; |
Peter Zijlstra | 75f8085 | 2015-07-15 14:35:46 +0200 | [diff] [blame] | 1357 | u64 pebs_status; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1358 | |
Peter Zijlstra | 8ef9b84 | 2016-09-07 14:42:55 +0200 | [diff] [blame] | 1359 | pebs_status = p->status & cpuc->pebs_enabled; |
| 1360 | pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1; |
| 1361 | |
| 1362 | /* PEBS v3 has more accurate status bits */ |
Peter Zijlstra | a3d8654 | 2015-05-12 15:18:18 +0200 | [diff] [blame] | 1363 | if (x86_pmu.intel_cap.pebs_format >= 3) { |
Peter Zijlstra | 8ef9b84 | 2016-09-07 14:42:55 +0200 | [diff] [blame] | 1364 | for_each_set_bit(bit, (unsigned long *)&pebs_status, |
| 1365 | x86_pmu.max_pebs_events) |
Peter Zijlstra | a3d8654 | 2015-05-12 15:18:18 +0200 | [diff] [blame] | 1366 | counts[bit]++; |
| 1367 | |
| 1368 | continue; |
| 1369 | } |
| 1370 | |
Andi Kleen | 01330d7 | 2015-12-03 13:22:20 -0800 | [diff] [blame] | 1371 | /* |
| 1372 | * On some CPUs the PEBS status can be zero when PEBS is |
| 1373 | * racing with clearing of GLOBAL_STATUS. |
| 1374 | * |
| 1375 | * Normally we would drop that record, but in the |
| 1376 | * case when there is only a single active PEBS event |
| 1377 | * we can assume it's for that event. |
| 1378 | */ |
| 1379 | if (!pebs_status && cpuc->pebs_enabled && |
| 1380 | !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) |
| 1381 | pebs_status = cpuc->pebs_enabled; |
| 1382 | |
Peter Zijlstra | 75f8085 | 2015-07-15 14:35:46 +0200 | [diff] [blame] | 1383 | bit = find_first_bit((unsigned long *)&pebs_status, |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1384 | x86_pmu.max_pebs_events); |
Andi Kleen | 957ea1f | 2015-12-03 13:22:19 -0800 | [diff] [blame] | 1385 | if (bit >= x86_pmu.max_pebs_events) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1386 | continue; |
Peter Zijlstra | 75f8085 | 2015-07-15 14:35:46 +0200 | [diff] [blame] | 1387 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1388 | /* |
| 1389 | * The PEBS hardware does not deal well with the situation |
| 1390 | * when events happen near to each other and multiple bits |
| 1391 | * are set. But it should happen rarely. |
| 1392 | * |
| 1393 | * If these events include one PEBS and multiple non-PEBS |
| 1394 | * events, it doesn't impact PEBS record. The record will |
| 1395 | * be handled normally. (slow path) |
| 1396 | * |
| 1397 | * If these events include two or more PEBS events, the |
| 1398 | * records for the events can be collapsed into a single |
| 1399 | * one, and it's not possible to reconstruct all events |
| 1400 | * that caused the PEBS record. It's called collision. |
| 1401 | * If collision happened, the record will be dropped. |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1402 | */ |
Peter Zijlstra | 75f8085 | 2015-07-15 14:35:46 +0200 | [diff] [blame] | 1403 | if (p->status != (1ULL << bit)) { |
| 1404 | for_each_set_bit(i, (unsigned long *)&pebs_status, |
| 1405 | x86_pmu.max_pebs_events) |
| 1406 | error[i]++; |
| 1407 | continue; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1408 | } |
Peter Zijlstra | 75f8085 | 2015-07-15 14:35:46 +0200 | [diff] [blame] | 1409 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1410 | counts[bit]++; |
| 1411 | } |
| 1412 | |
| 1413 | for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) { |
Kan Liang | f38b0db | 2015-05-10 15:13:14 -0400 | [diff] [blame] | 1414 | if ((counts[bit] == 0) && (error[bit] == 0)) |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1415 | continue; |
Peter Zijlstra | 75f8085 | 2015-07-15 14:35:46 +0200 | [diff] [blame] | 1416 | |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1417 | event = cpuc->events[bit]; |
Peter Zijlstra | 8ef9b84 | 2016-09-07 14:42:55 +0200 | [diff] [blame] | 1418 | if (WARN_ON_ONCE(!event)) |
| 1419 | continue; |
| 1420 | |
| 1421 | if (WARN_ON_ONCE(!event->attr.precise_ip)) |
| 1422 | continue; |
Yan, Zheng | 2150908 | 2015-05-06 15:33:49 -0400 | [diff] [blame] | 1423 | |
Kan Liang | f38b0db | 2015-05-10 15:13:14 -0400 | [diff] [blame] | 1424 | /* log dropped samples number */ |
Jiri Olsa | a88ff23 | 2016-12-28 14:31:03 +0100 | [diff] [blame] | 1425 | if (error[bit]) { |
Kan Liang | f38b0db | 2015-05-10 15:13:14 -0400 | [diff] [blame] | 1426 | perf_log_lost_samples(event, error[bit]); |
| 1427 | |
Jiri Olsa | a88ff23 | 2016-12-28 14:31:03 +0100 | [diff] [blame] | 1428 | if (perf_event_account_interrupt(event)) |
| 1429 | x86_pmu_stop(event, 0); |
| 1430 | } |
| 1431 | |
Kan Liang | f38b0db | 2015-05-10 15:13:14 -0400 | [diff] [blame] | 1432 | if (counts[bit]) { |
| 1433 | __intel_pmu_pebs_event(event, iregs, base, |
| 1434 | top, bit, counts[bit]); |
| 1435 | } |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1436 | } |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1437 | } |
| 1438 | |
| 1439 | /* |
| 1440 | * BTS, PEBS probe and setup |
| 1441 | */ |
| 1442 | |
Mathias Krause | 066ce64 | 2014-08-26 18:49:45 +0200 | [diff] [blame] | 1443 | void __init intel_ds_init(void) |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1444 | { |
| 1445 | /* |
| 1446 | * No support for 32bit formats |
| 1447 | */ |
| 1448 | if (!boot_cpu_has(X86_FEATURE_DTES64)) |
| 1449 | return; |
| 1450 | |
| 1451 | x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); |
| 1452 | x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); |
Jiri Olsa | e72daf3 | 2016-03-01 20:03:52 +0100 | [diff] [blame] | 1453 | x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1454 | if (x86_pmu.pebs) { |
Peter Zijlstra | 8db909a | 2010-03-03 17:07:40 +0100 | [diff] [blame] | 1455 | char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; |
| 1456 | int format = x86_pmu.intel_cap.pebs_format; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1457 | |
| 1458 | switch (format) { |
| 1459 | case 0: |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 1460 | pr_cont("PEBS fmt0%c, ", pebs_type); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1461 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); |
Jiri Olsa | e72daf3 | 2016-03-01 20:03:52 +0100 | [diff] [blame] | 1462 | /* |
| 1463 | * Using >PAGE_SIZE buffers makes the WRMSR to |
| 1464 | * PERF_GLOBAL_CTRL in intel_pmu_enable_all() |
| 1465 | * mysteriously hang on Core2. |
| 1466 | * |
| 1467 | * As a workaround, we don't do this. |
| 1468 | */ |
| 1469 | x86_pmu.pebs_buffer_size = PAGE_SIZE; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1470 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1471 | break; |
| 1472 | |
| 1473 | case 1: |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 1474 | pr_cont("PEBS fmt1%c, ", pebs_type); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1475 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); |
| 1476 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1477 | break; |
| 1478 | |
Andi Kleen | 130768b | 2013-06-17 17:36:47 -0700 | [diff] [blame] | 1479 | case 2: |
| 1480 | pr_cont("PEBS fmt2%c, ", pebs_type); |
| 1481 | x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); |
Peter Zijlstra | d2beea4 | 2013-09-12 13:00:47 +0200 | [diff] [blame] | 1482 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; |
Andi Kleen | 130768b | 2013-06-17 17:36:47 -0700 | [diff] [blame] | 1483 | break; |
| 1484 | |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 1485 | case 3: |
| 1486 | pr_cont("PEBS fmt3%c, ", pebs_type); |
| 1487 | x86_pmu.pebs_record_size = |
| 1488 | sizeof(struct pebs_record_skl); |
| 1489 | x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; |
Andi Kleen | a7b58d2 | 2015-05-27 21:13:14 -0700 | [diff] [blame] | 1490 | x86_pmu.free_running_flags |= PERF_SAMPLE_TIME; |
Andi Kleen | 2f7ebf2 | 2015-05-10 12:22:40 -0700 | [diff] [blame] | 1491 | break; |
| 1492 | |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1493 | default: |
Chen Yucong | 1b74dde | 2016-02-02 11:45:02 +0800 | [diff] [blame] | 1494 | pr_cont("no PEBS fmt%d%c, ", format, pebs_type); |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1495 | x86_pmu.pebs = 0; |
Peter Zijlstra | ca03770 | 2010-03-02 19:52:12 +0100 | [diff] [blame] | 1496 | } |
| 1497 | } |
| 1498 | } |
Stephane Eranian | 1d9d863 | 2013-03-15 14:26:07 +0100 | [diff] [blame] | 1499 | |
| 1500 | void perf_restore_debug_store(void) |
| 1501 | { |
Linus Torvalds | 2a6e06b | 2013-03-17 15:44:43 -0700 | [diff] [blame] | 1502 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
| 1503 | |
Stephane Eranian | 1d9d863 | 2013-03-15 14:26:07 +0100 | [diff] [blame] | 1504 | if (!x86_pmu.bts && !x86_pmu.pebs) |
| 1505 | return; |
| 1506 | |
Linus Torvalds | 2a6e06b | 2013-03-17 15:44:43 -0700 | [diff] [blame] | 1507 | wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds); |
Stephane Eranian | 1d9d863 | 2013-03-15 14:26:07 +0100 | [diff] [blame] | 1508 | } |