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gerrit-public.fairphone.software / kernel / msm-4.9 / 7fe845d11ad1b4aac098d40c55275569e143c483 / . / drivers / net / sk_mca.h
blob: 7e7c995827460831f4200c139d98ffaff9bd4f31 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1#include <linux/version.h>
2
3#ifndef _SK_MCA_INCLUDE_
4#define _SK_MCA_INCLUDE_
5
6#ifdef _SK_MCA_DRIVER_
7
8/* Adapter ID's */
9#define SKNET_MCA_ID 0x6afd
10#define SKNET_JUNIOR_MCA_ID 0x6be9
11
12/* media enumeration - defined in a way that it fits onto the MC2+'s
13 POS registers... */
14
15typedef enum { Media_10Base2, Media_10BaseT,
16 Media_10Base5, Media_Unknown, Media_Count
17} skmca_medium;
18
19/* private structure */
20typedef struct {
21 unsigned int slot; /* MCA-Slot-# */
22 void __iomem *base;
23 void __iomem *macbase; /* base address of MAC address PROM */
24 void __iomem *ioregaddr;/* address of I/O-register (Lo) */
25 void __iomem *ctrladdr; /* address of control/stat register */
26 void __iomem *cmdaddr; /* address of I/O-command register */
27 int nextrx; /* index of next RX descriptor to
28 be read */
29 int nexttxput; /* index of next free TX descriptor */
30 int nexttxdone; /* index of next TX descriptor to
31 be finished */
32 int txbusy; /* # of busy TX descriptors */
33 struct net_device_stats stat; /* packet statistics */
34 int realirq; /* memorizes actual IRQ, even when
35 currently not allocated */
36 skmca_medium medium; /* physical cannector */
37 spinlock_t lock;
38} skmca_priv;
39
40/* card registers: control/status register bits */
41
42#define CTRL_ADR_DATA 0 /* Bit 0 = 0 ->access data register */
43#define CTRL_ADR_RAP 1 /* Bit 0 = 1 ->access RAP register */
44#define CTRL_RW_WRITE 0 /* Bit 1 = 0 ->write register */
45#define CTRL_RW_READ 2 /* Bit 1 = 1 ->read register */
46#define CTRL_RESET_ON 0 /* Bit 3 = 0 ->reset board */
47#define CTRL_RESET_OFF 8 /* Bit 3 = 1 ->no reset of board */
48
49#define STAT_ADR_DATA 0 /* Bit 0 of ctrl register read back */
50#define STAT_ADR_RAP 1
51#define STAT_RW_WRITE 0 /* Bit 1 of ctrl register read back */
52#define STAT_RW_READ 2
53#define STAT_RESET_ON 0 /* Bit 3 of ctrl register read back */
54#define STAT_RESET_OFF 8
55#define STAT_IRQ_ACT 0 /* interrupt pending */
56#define STAT_IRQ_NOACT 16 /* no interrupt pending */
57#define STAT_IO_NOBUSY 0 /* no transfer busy */
58#define STAT_IO_BUSY 32 /* transfer busy */
59
60/* I/O command register bits */
61
62#define IOCMD_GO 128 /* Bit 7 = 1 -> start register xfer */
63
64/* LANCE registers */
65
66#define LANCE_CSR0 0 /* Status/Control */
67
68#define CSR0_ERR 0x8000 /* general error flag */
69#define CSR0_BABL 0x4000 /* transmitter timeout */
70#define CSR0_CERR 0x2000 /* collision error */
71#define CSR0_MISS 0x1000 /* lost Rx block */
72#define CSR0_MERR 0x0800 /* memory access error */
73#define CSR0_RINT 0x0400 /* receiver interrupt */
74#define CSR0_TINT 0x0200 /* transmitter interrupt */
75#define CSR0_IDON 0x0100 /* initialization done */
76#define CSR0_INTR 0x0080 /* general interrupt flag */
77#define CSR0_INEA 0x0040 /* interrupt enable */
78#define CSR0_RXON 0x0020 /* receiver enabled */
79#define CSR0_TXON 0x0010 /* transmitter enabled */
80#define CSR0_TDMD 0x0008 /* force transmission now */
81#define CSR0_STOP 0x0004 /* stop LANCE */
82#define CSR0_STRT 0x0002 /* start LANCE */
83#define CSR0_INIT 0x0001 /* read initialization block */
84
85#define LANCE_CSR1 1 /* addr bit 0..15 of initialization */
86#define LANCE_CSR2 2 /* 16..23 block */
87
88#define LANCE_CSR3 3 /* Bus control */
89#define CSR3_BCON_HOLD 0 /* Bit 0 = 0 -> BM1,BM0,HOLD */
90#define CSR3_BCON_BUSRQ 1 /* Bit 0 = 1 -> BUSAK0,BYTE,BUSRQ */
91#define CSR3_ALE_HIGH 0 /* Bit 1 = 0 -> ALE asserted high */
92#define CSR3_ALE_LOW 2 /* Bit 1 = 1 -> ALE asserted low */
93#define CSR3_BSWAP_OFF 0 /* Bit 2 = 0 -> no byte swap */
94#define CSR3_BSWAP_ON 4 /* Bit 2 = 1 -> byte swap */
95
96/* LANCE structures */
97
98typedef struct { /* LANCE initialization block */
99 u16 Mode; /* mode flags */
100 u8 PAdr[6]; /* MAC address */
101 u8 LAdrF[8]; /* Multicast filter */
102 u32 RdrP; /* Receive descriptor */
103 u32 TdrP; /* Transmit descriptor */
104} LANCE_InitBlock;
105
106/* Mode flags init block */
107
108#define LANCE_INIT_PROM 0x8000 /* enable promiscous mode */
109#define LANCE_INIT_INTL 0x0040 /* internal loopback */
110#define LANCE_INIT_DRTY 0x0020 /* disable retry */
111#define LANCE_INIT_COLL 0x0010 /* force collision */
112#define LANCE_INIT_DTCR 0x0008 /* disable transmit CRC */
113#define LANCE_INIT_LOOP 0x0004 /* loopback */
114#define LANCE_INIT_DTX 0x0002 /* disable transmitter */
115#define LANCE_INIT_DRX 0x0001 /* disable receiver */
116
117typedef struct { /* LANCE Tx descriptor */
118 u16 LowAddr; /* bit 0..15 of address */
119 u16 Flags; /* bit 16..23 of address + Flags */
120 u16 Len; /* 2s complement of packet length */
121 u16 Status; /* Result of transmission */
122} LANCE_TxDescr;
123
124#define TXDSCR_FLAGS_OWN 0x8000 /* LANCE owns descriptor */
125#define TXDSCR_FLAGS_ERR 0x4000 /* summary error flag */
126#define TXDSCR_FLAGS_MORE 0x1000 /* more than one retry needed? */
127#define TXDSCR_FLAGS_ONE 0x0800 /* one retry? */
128#define TXDSCR_FLAGS_DEF 0x0400 /* transmission deferred? */
129#define TXDSCR_FLAGS_STP 0x0200 /* first packet in chain? */
130#define TXDSCR_FLAGS_ENP 0x0100 /* last packet in chain? */
131
132#define TXDSCR_STATUS_BUFF 0x8000 /* buffer error? */
133#define TXDSCR_STATUS_UFLO 0x4000 /* silo underflow during transmit? */
134#define TXDSCR_STATUS_LCOL 0x1000 /* late collision? */
135#define TXDSCR_STATUS_LCAR 0x0800 /* loss of carrier? */
136#define TXDSCR_STATUS_RTRY 0x0400 /* retry error? */
137
138typedef struct { /* LANCE Rx descriptor */
139 u16 LowAddr; /* bit 0..15 of address */
140 u16 Flags; /* bit 16..23 of address + Flags */
141 u16 MaxLen; /* 2s complement of buffer length */
142 u16 Len; /* packet length */
143} LANCE_RxDescr;
144
145#define RXDSCR_FLAGS_OWN 0x8000 /* LANCE owns descriptor */
146#define RXDSCR_FLAGS_ERR 0x4000 /* summary error flag */
147#define RXDSCR_FLAGS_FRAM 0x2000 /* framing error flag */
148#define RXDSCR_FLAGS_OFLO 0x1000 /* FIFO overflow? */
149#define RXDSCR_FLAGS_CRC 0x0800 /* CRC error? */
150#define RXDSCR_FLAGS_BUFF 0x0400 /* buffer error? */
151#define RXDSCR_FLAGS_STP 0x0200 /* first packet in chain? */
152#define RXDCSR_FLAGS_ENP 0x0100 /* last packet in chain? */
153
154/* RAM layout */
155
156#define TXCOUNT 4 /* length of TX descriptor queue */
157#define LTXCOUNT 2 /* log2 of it */
158#define RXCOUNT 4 /* length of RX descriptor queue */
159#define LRXCOUNT 2 /* log2 of it */
160
161#define RAM_INITBASE 0 /* LANCE init block */
162#define RAM_TXBASE 24 /* Start of TX descriptor queue */
163#define RAM_RXBASE \
164(RAM_TXBASE + (TXCOUNT * 8)) /* Start of RX descriptor queue */
165#define RAM_DATABASE \
166(RAM_RXBASE + (RXCOUNT * 8)) /* Start of data area for frames */
167#define RAM_BUFSIZE 1580 /* max. frame size - should never be
168 reached */
169
170#endif /* _SK_MCA_DRIVER_ */
171
172#endif /* _SK_MCA_INCLUDE_ */