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gerrit-public.fairphone.software / kernel / msm-4.9 / 804f1594cc3deb161e531a43d90c501f0db2635a / . / include / asm-parisc / cache.h
blob: ae50f8e12eed8e54abe736ab6b7876087f611e19 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * include/asm-parisc/cache.h
3 */
4
5#ifndef __ARCH_PARISC_CACHE_H
6#define __ARCH_PARISC_CACHE_H
7
8#include <linux/config.h>
9
10/*
11 * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
12 * 32-byte cachelines. The default configuration is not for SMP anyway,
13 * so if you're building for SMP, you should select the appropriate
14 * processor type. There is a potential livelock danger when running
15 * a machine with this value set too small, but it's more probable you'll
16 * just ruin performance.
17 */
18#ifdef CONFIG_PA20
19#define L1_CACHE_BYTES 64
20#define L1_CACHE_SHIFT 6
21#else
22#define L1_CACHE_BYTES 32
23#define L1_CACHE_SHIFT 5
24#endif
25
26#ifndef __ASSEMBLY__
27
28#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
29
30#define SMP_CACHE_BYTES L1_CACHE_BYTES
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]31
Kyle McMartin804f1592006-03-23 03:00:16 -0800[diff] [blame^]32#define __read_mostly __attribute__((__section__(".data.read_mostly")))
33
Matthew Wilcox1b2425e2006-01-10 20:47:49 -0500[diff] [blame]34extern void flush_data_cache_local(void *); /* flushes local data-cache only */
35extern void flush_instruction_cache_local(void *); /* flushes local code-cache only */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]36#ifdef CONFIG_SMP
37extern void flush_data_cache(void); /* flushes data-cache only (all processors) */
38extern void flush_instruction_cache(void); /* flushes i-cache only (all processors) */
39#else
Matthew Wilcox1b2425e2006-01-10 20:47:49 -0500[diff] [blame]40#define flush_data_cache() flush_data_cache_local(NULL)
41#define flush_instruction_cache() flush_instruction_cache_local(NULL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]42#endif
43
44extern void parisc_cache_init(void); /* initializes cache-flushing */
45extern void flush_all_caches(void); /* flush everything (tlb & cache) */
46extern int get_cache_info(char *);
47extern void flush_user_icache_range_asm(unsigned long, unsigned long);
48extern void flush_kernel_icache_range_asm(unsigned long, unsigned long);
49extern void flush_user_dcache_range_asm(unsigned long, unsigned long);
50extern void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
51extern void flush_kernel_dcache_page(void *);
52extern void flush_kernel_icache_page(void *);
53extern void disable_sr_hashing(void); /* turns off space register hashing */
54extern void disable_sr_hashing_asm(int); /* low level support for above */
55extern void free_sid(unsigned long);
56unsigned long alloc_sid(void);
57extern void flush_user_dcache_page(unsigned long);
58extern void flush_user_icache_page(unsigned long);
59
60struct seq_file;
61extern void show_cache_info(struct seq_file *m);
62
63extern int split_tlb;
64extern int dcache_stride;
65extern int icache_stride;
66extern struct pdc_cache_info cache_info;
67
68#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
69#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
70#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
71
72#endif /* ! __ASSEMBLY__ */
73
74/* Classes of processor wrt: disabling space register hashing */
75
76#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
77#define SRHASH_PCXL 1 /* pcxl */
78#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
79
80#endif