| Joseph Lo | 59b0f68 | 2012-08-16 17:31:51 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012, NVIDIA Corporation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/linkage.h> |
| 18 | |
| 19 | #include <asm/assembler.h> |
| 20 | |
| 21 | #include <mach/iomap.h> |
| 22 | |
| 23 | #include "sleep.h" |
| 24 | #include "flowctrl.h" |
| 25 | |
| 26 | #define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ |
| 27 | |
| 28 | #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) |
| 29 | /* |
| 30 | * tegra30_hotplug_shutdown(void) |
| 31 | * |
| 32 | * Powergates the current CPU. |
| 33 | * Should never return. |
| 34 | */ |
| 35 | ENTRY(tegra30_hotplug_shutdown) |
| 36 | /* Turn off SMP coherency */ |
| 37 | exit_smp r4, r5 |
| 38 | |
| 39 | /* Powergate this CPU */ |
| 40 | mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN |
| 41 | bl tegra30_cpu_shutdown |
| 42 | mov pc, lr @ should never get here |
| 43 | ENDPROC(tegra30_hotplug_shutdown) |
| 44 | |
| 45 | /* |
| 46 | * tegra30_cpu_shutdown(unsigned long flags) |
| 47 | * |
| 48 | * Puts the current CPU in wait-for-event mode on the flow controller |
| 49 | * and powergates it -- flags (in R0) indicate the request type. |
| 50 | * Must never be called for CPU 0. |
| 51 | * |
| 52 | * corrupts r0-r4, r12 |
| 53 | */ |
| 54 | ENTRY(tegra30_cpu_shutdown) |
| 55 | cpu_id r3 |
| 56 | cmp r3, #0 |
| 57 | moveq pc, lr @ Must never be called for CPU 0 |
| 58 | |
| 59 | ldr r12, =TEGRA_FLOW_CTRL_VIRT |
| 60 | cpu_to_csr_reg r1, r3 |
| 61 | add r1, r1, r12 @ virtual CSR address for this CPU |
| 62 | cpu_to_halt_reg r2, r3 |
| 63 | add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU |
| 64 | |
| 65 | /* |
| 66 | * Clear this CPU's "event" and "interrupt" flags and power gate |
| 67 | * it when halting but not before it is in the "WFE" state. |
| 68 | */ |
| 69 | movw r12, \ |
| 70 | FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \ |
| 71 | FLOW_CTRL_CSR_ENABLE |
| 72 | mov r4, #(1 << 4) |
| 73 | orr r12, r12, r4, lsl r3 |
| 74 | str r12, [r1] |
| 75 | |
| 76 | /* Halt this CPU. */ |
| 77 | mov r3, #0x400 |
| 78 | delay_1: |
| 79 | subs r3, r3, #1 @ delay as a part of wfe war. |
| 80 | bge delay_1; |
| 81 | cpsid a @ disable imprecise aborts. |
| 82 | ldr r3, [r1] @ read CSR |
| 83 | str r3, [r1] @ clear CSR |
| 84 | tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN |
| 85 | movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug |
| 86 | str r3, [r2] |
| 87 | ldr r0, [r2] |
| 88 | b wfe_war |
| 89 | |
| 90 | __cpu_reset_again: |
| 91 | dsb |
| 92 | .align 5 |
| 93 | wfe @ CPU should be power gated here |
| 94 | wfe_war: |
| 95 | b __cpu_reset_again |
| 96 | |
| 97 | /* |
| 98 | * 38 nop's, which fills reset of wfe cache line and |
| 99 | * 4 more cachelines with nop |
| 100 | */ |
| 101 | .rept 38 |
| 102 | nop |
| 103 | .endr |
| 104 | b . @ should never get here |
| 105 | |
| 106 | ENDPROC(tegra30_cpu_shutdown) |
| 107 | #endif |