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Linus Walleij2744e8a2011-05-02 20:50:54 +02001PINCTRL (PIN CONTROL) subsystem
2This document outlines the pin control subsystem in Linux
3
4This subsystem deals with:
5
6- Enumerating and naming controllable pins
7
8- Multiplexing of pins, pads, fingers (etc) see below for details
9
Linus Walleijae6b4d82011-10-19 18:14:33 +020010- Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
12 load capacitance etc.
Linus Walleij2744e8a2011-05-02 20:50:54 +020013
14Top-level interface
15===================
16
17Definition of PIN CONTROLLER:
18
19- A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
21 set drive strength etc for individual pins or groups of pins.
22
23Definition of PIN:
24
25- PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
30 pin exists.
31
Linus Walleij336cdba02011-11-10 09:27:41 +010032When a PIN CONTROLLER is instantiated, it will register a descriptor to the
Linus Walleij2744e8a2011-05-02 20:50:54 +020033pin control framework, and this descriptor contains an array of pin descriptors
34describing the pins handled by this specific pin controller.
35
36Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
37
38 A B C D E F G H
39
40 8 o o o o o o o o
41
42 7 o o o o o o o o
43
44 6 o o o o o o o o
45
46 5 o o o o o o o o
47
48 4 o o o o o o o o
49
50 3 o o o o o o o o
51
52 2 o o o o o o o o
53
54 1 o o o o o o o o
55
56To register a pin controller and name all the pins on this package we can do
57this in our driver:
58
59#include <linux/pinctrl/pinctrl.h>
60
Linus Walleij336cdba02011-11-10 09:27:41 +010061const struct pinctrl_pin_desc foo_pins[] = {
62 PINCTRL_PIN(0, "A8"),
63 PINCTRL_PIN(1, "B8"),
64 PINCTRL_PIN(2, "C8"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020065 ...
Linus Walleij336cdba02011-11-10 09:27:41 +010066 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
Linus Walleij2744e8a2011-05-02 20:50:54 +020069};
70
71static struct pinctrl_desc foo_desc = {
72 .name = "foo",
73 .pins = foo_pins,
74 .npins = ARRAY_SIZE(foo_pins),
75 .maxpin = 63,
76 .owner = THIS_MODULE,
77};
78
79int __init foo_probe(void)
80{
81 struct pinctrl_dev *pctl;
82
83 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
84 if (IS_ERR(pctl))
85 pr_err("could not register foo pin driver\n");
86}
87
Linus Walleijae6b4d82011-10-19 18:14:33 +020088To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89selected drivers, you need to select them from your machine's Kconfig entry,
90since these are so tightly integrated with the machines they are used on.
91See for example arch/arm/mach-u300/Kconfig for an example.
92
Linus Walleij2744e8a2011-05-02 20:50:54 +020093Pins usually have fancier names than this. You can find these in the dataheet
94for your chip. Notice that the core pinctrl.h file provides a fancy macro
95called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
Linus Walleij336cdba02011-11-10 09:27:41 +010096the pins from 0 in the upper left corner to 63 in the lower right corner.
97This enumeration was arbitrarily chosen, in practice you need to think
Linus Walleij2744e8a2011-05-02 20:50:54 +020098through your numbering system so that it matches the layout of registers
99and such things in your driver, or the code may become complicated. You must
100also consider matching of offsets to the GPIO ranges that may be handled by
101the pin controller.
102
103For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104like this, walking around the edge of the chip, which seems to be industry
105standard too (all these pads had names, too):
106
107
108 0 ..... 104
109 466 105
110 . .
111 . .
112 358 224
113 357 .... 225
114
115
116Pin groups
117==========
118
119Many controllers need to deal with groups of pins, so the pin controller
120subsystem has a mechanism for enumerating groups of pins and retrieving the
121actual enumerated pins that are part of a certain group.
122
123For example, say that we have a group of pins dealing with an SPI interface
124on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
125on { 24, 25 }.
126
127These two groups are presented to the pin control subsystem by implementing
128some generic pinctrl_ops like this:
129
130#include <linux/pinctrl/pinctrl.h>
131
132struct foo_group {
133 const char *name;
134 const unsigned int *pins;
135 const unsigned num_pins;
136};
137
Linus Walleij336cdba02011-11-10 09:27:41 +0100138static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139static const unsigned int i2c0_pins[] = { 24, 25 };
Linus Walleij2744e8a2011-05-02 20:50:54 +0200140
141static const struct foo_group foo_groups[] = {
142 {
143 .name = "spi0_grp",
144 .pins = spi0_pins,
145 .num_pins = ARRAY_SIZE(spi0_pins),
146 },
147 {
148 .name = "i2c0_grp",
149 .pins = i2c0_pins,
150 .num_pins = ARRAY_SIZE(i2c0_pins),
151 },
152};
153
154
155static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
156{
157 if (selector >= ARRAY_SIZE(foo_groups))
158 return -EINVAL;
159 return 0;
160}
161
162static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
163 unsigned selector)
164{
165 return foo_groups[selector].name;
166}
167
168static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
169 unsigned ** const pins,
170 unsigned * const num_pins)
171{
172 *pins = (unsigned *) foo_groups[selector].pins;
173 *num_pins = foo_groups[selector].num_pins;
174 return 0;
175}
176
177static struct pinctrl_ops foo_pctrl_ops = {
178 .list_groups = foo_list_groups,
179 .get_group_name = foo_get_group_name,
180 .get_group_pins = foo_get_group_pins,
181};
182
183
184static struct pinctrl_desc foo_desc = {
185 ...
186 .pctlops = &foo_pctrl_ops,
187};
188
189The pin control subsystem will call the .list_groups() function repeatedly
190beginning on 0 until it returns non-zero to determine legal selectors, then
191it will call the other functions to retrieve the name and pins of the group.
192Maintaining the data structure of the groups is up to the driver, this is
193just a simple example - in practice you may need more entries in your group
194structure, for example specific register ranges associated with each group
195and so on.
196
197
Linus Walleijae6b4d82011-10-19 18:14:33 +0200198Pin configuration
199=================
200
201Pins can sometimes be software-configured in an various ways, mostly related
202to their electronic properties when used as inputs or outputs. For example you
203may be able to make an output pin high impedance, or "tristate" meaning it is
204effectively disconnected. You may be able to connect an input pin to VDD or GND
205using a certain resistor value - pull up and pull down - so that the pin has a
206stable value when nothing is driving the rail it is connected to, or when it's
207unconnected.
208
209For example, a platform may do this:
210
Linus Walleij28a8d142012-02-09 01:52:22 +0100211#include <linux/pinctrl/consumer.h>
212
Stephen Warren43699de2011-12-15 16:57:17 -0700213ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
Linus Walleijae6b4d82011-10-19 18:14:33 +0200214
215To pull up a pin to VDD. The pin configuration driver implements callbacks for
216changing pin configuration in the pin controller ops like this:
217
218#include <linux/pinctrl/pinctrl.h>
219#include <linux/pinctrl/pinconf.h>
220#include "platform_x_pindefs.h"
221
Dong Aishenge6337c32011-12-20 17:51:59 +0800222static int foo_pin_config_get(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200223 unsigned offset,
224 unsigned long *config)
225{
226 struct my_conftype conf;
227
228 ... Find setting for pin @ offset ...
229
230 *config = (unsigned long) conf;
231}
232
Dong Aishenge6337c32011-12-20 17:51:59 +0800233static int foo_pin_config_set(struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200234 unsigned offset,
235 unsigned long config)
236{
237 struct my_conftype *conf = (struct my_conftype *) config;
238
239 switch (conf) {
240 case PLATFORM_X_PULL_UP:
241 ...
242 }
243 }
244}
245
Dong Aishenge6337c32011-12-20 17:51:59 +0800246static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200247 unsigned selector,
248 unsigned long *config)
249{
250 ...
251}
252
Dong Aishenge6337c32011-12-20 17:51:59 +0800253static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
Linus Walleijae6b4d82011-10-19 18:14:33 +0200254 unsigned selector,
255 unsigned long config)
256{
257 ...
258}
259
260static struct pinconf_ops foo_pconf_ops = {
261 .pin_config_get = foo_pin_config_get,
262 .pin_config_set = foo_pin_config_set,
263 .pin_config_group_get = foo_pin_config_group_get,
264 .pin_config_group_set = foo_pin_config_group_set,
265};
266
267/* Pin config operations are handled by some pin controller */
268static struct pinctrl_desc foo_desc = {
269 ...
270 .confops = &foo_pconf_ops,
271};
272
273Since some controllers have special logic for handling entire groups of pins
274they can exploit the special whole-group pin control function. The
275pin_config_group_set() callback is allowed to return the error code -EAGAIN,
276for groups it does not want to handle, or if it just wants to do some
277group-level handling and then fall through to iterate over all pins, in which
278case each individual pin will be treated by separate pin_config_set() calls as
279well.
280
281
Linus Walleij2744e8a2011-05-02 20:50:54 +0200282Interaction with the GPIO subsystem
283===================================
284
285The GPIO drivers may want to perform operations of various types on the same
286physical pins that are also registered as pin controller pins.
287
288Since the pin controller subsystem have its pinspace local to the pin
289controller we need a mapping so that the pin control subsystem can figure out
290which pin controller handles control of a certain GPIO pin. Since a single
291pin controller may be muxing several GPIO ranges (typically SoCs that have
292one set of pins but internally several GPIO silicon blocks, each modeled as
293a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
294instance like this:
295
296struct gpio_chip chip_a;
297struct gpio_chip chip_b;
298
299static struct pinctrl_gpio_range gpio_range_a = {
300 .name = "chip a",
301 .id = 0,
302 .base = 32,
Chanho Park3c739ad2011-11-11 18:47:58 +0900303 .pin_base = 32,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200304 .npins = 16,
305 .gc = &chip_a;
306};
307
Chanho Park3c739ad2011-11-11 18:47:58 +0900308static struct pinctrl_gpio_range gpio_range_b = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200309 .name = "chip b",
310 .id = 0,
311 .base = 48,
Chanho Park3c739ad2011-11-11 18:47:58 +0900312 .pin_base = 64,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200313 .npins = 8,
314 .gc = &chip_b;
315};
316
Linus Walleij2744e8a2011-05-02 20:50:54 +0200317{
318 struct pinctrl_dev *pctl;
319 ...
320 pinctrl_add_gpio_range(pctl, &gpio_range_a);
321 pinctrl_add_gpio_range(pctl, &gpio_range_b);
322}
323
324So this complex system has one pin controller handling two different
Chanho Park3c739ad2011-11-11 18:47:58 +0900325GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
326"chip b" have different .pin_base, which means a start pin number of the
327GPIO range.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200328
Chanho Park3c739ad2011-11-11 18:47:58 +0900329The GPIO range of "chip a" starts from the GPIO base of 32 and actual
330pin range also starts from 32. However "chip b" has different starting
331offset for the GPIO range and pin range. The GPIO range of "chip b" starts
332from GPIO number 48, while the pin range of "chip b" starts from 64.
333
334We can convert a gpio number to actual pin number using this "pin_base".
335They are mapped in the global GPIO pin space at:
336
337chip a:
338 - GPIO range : [32 .. 47]
339 - pin range : [32 .. 47]
340chip b:
341 - GPIO range : [48 .. 55]
342 - pin range : [64 .. 71]
Linus Walleij2744e8a2011-05-02 20:50:54 +0200343
344When GPIO-specific functions in the pin control subsystem are called, these
Linus Walleij336cdba02011-11-10 09:27:41 +0100345ranges will be used to look up the appropriate pin controller by inspecting
Linus Walleij2744e8a2011-05-02 20:50:54 +0200346and matching the pin to the pin ranges across all controllers. When a
347pin controller handling the matching range is found, GPIO-specific functions
348will be called on that specific pin controller.
349
350For all functionalities dealing with pin biasing, pin muxing etc, the pin
351controller subsystem will subtract the range's .base offset from the passed
Chanho Park3c739ad2011-11-11 18:47:58 +0900352in gpio number, and add the ranges's .pin_base offset to retrive a pin number.
353After that, the subsystem passes it on to the pin control driver, so the driver
354will get an pin number into its handled number range. Further it is also passed
Linus Walleij2744e8a2011-05-02 20:50:54 +0200355the range ID value, so that the pin controller knows which range it should
356deal with.
357
Linus Walleij2744e8a2011-05-02 20:50:54 +0200358PINMUX interfaces
359=================
360
361These calls use the pinmux_* naming prefix. No other calls should use that
362prefix.
363
364
365What is pinmuxing?
366==================
367
368PINMUX, also known as padmux, ballmux, alternate functions or mission modes
369is a way for chip vendors producing some kind of electrical packages to use
370a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
371functions, depending on the application. By "application" in this context
372we usually mean a way of soldering or wiring the package into an electronic
373system, even though the framework makes it possible to also change the function
374at runtime.
375
376Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
377
378 A B C D E F G H
379 +---+
380 8 | o | o o o o o o o
381 | |
382 7 | o | o o o o o o o
383 | |
384 6 | o | o o o o o o o
385 +---+---+
386 5 | o | o | o o o o o o
387 +---+---+ +---+
388 4 o o o o o o | o | o
389 | |
390 3 o o o o o o | o | o
391 | |
392 2 o o o o o o | o | o
393 +-------+-------+-------+---+---+
394 1 | o o | o o | o o | o | o |
395 +-------+-------+-------+---+---+
396
397This is not tetris. The game to think of is chess. Not all PGA/BGA packages
398are chessboard-like, big ones have "holes" in some arrangement according to
399different design patterns, but we're using this as a simple example. Of the
400pins you see some will be taken by things like a few VCC and GND to feed power
401to the chip, and quite a few will be taken by large ports like an external
402memory interface. The remaining pins will often be subject to pin multiplexing.
403
404The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
405its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
406pinctrl_register_pins() and a suitable data set as shown earlier.
407
408In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
409(these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
410some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
411be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
412we cannot use the SPI port and I2C port at the same time. However in the inside
413of the package the silicon performing the SPI logic can alternatively be routed
414out on pins { G4, G3, G2, G1 }.
415
416On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
417special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
418consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
419{ A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
420port on pins { G4, G3, G2, G1 } of course.
421
422This way the silicon blocks present inside the chip can be multiplexed "muxed"
423out on different pin ranges. Often contemporary SoC (systems on chip) will
424contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
425different pins by pinmux settings.
426
427Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
428common to be able to use almost any pin as a GPIO pin if it is not currently
429in use by some other I/O port.
430
431
432Pinmux conventions
433==================
434
435The purpose of the pinmux functionality in the pin controller subsystem is to
436abstract and provide pinmux settings to the devices you choose to instantiate
437in your machine configuration. It is inspired by the clk, GPIO and regulator
438subsystems, so devices will request their mux setting, but it's also possible
439to request a single pin for e.g. GPIO.
440
441Definitions:
442
443- FUNCTIONS can be switched in and out by a driver residing with the pin
444 control subsystem in the drivers/pinctrl/* directory of the kernel. The
445 pin control driver knows the possible functions. In the example above you can
446 identify three pinmux functions, one for spi, one for i2c and one for mmc.
447
448- FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
449 In this case the array could be something like: { spi0, i2c0, mmc0 }
450 for the three available functions.
451
452- FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
453 function is *always* associated with a certain set of pin groups, could
454 be just a single one, but could also be many. In the example above the
455 function i2c is associated with the pins { A5, B5 }, enumerated as
456 { 24, 25 } in the controller pin space.
457
458 The Function spi is associated with pin groups { A8, A7, A6, A5 }
459 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
460 { 38, 46, 54, 62 } respectively.
461
462 Group names must be unique per pin controller, no two groups on the same
463 controller may have the same name.
464
465- The combination of a FUNCTION and a PIN GROUP determine a certain function
466 for a certain set of pins. The knowledge of the functions and pin groups
467 and their machine-specific particulars are kept inside the pinmux driver,
468 from the outside only the enumerators are known, and the driver core can:
469
470 - Request the name of a function with a certain selector (>= 0)
471 - A list of groups associated with a certain function
472 - Request that a certain group in that list to be activated for a certain
473 function
474
475 As already described above, pin groups are in turn self-descriptive, so
476 the core will retrieve the actual pin range in a certain group from the
477 driver.
478
479- FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
480 device by the board file, device tree or similar machine setup configuration
481 mechanism, similar to how regulators are connected to devices, usually by
482 name. Defining a pin controller, function and group thus uniquely identify
483 the set of pins to be used by a certain device. (If only one possible group
484 of pins is available for the function, no group name need to be supplied -
485 the core will simply select the first and only group available.)
486
487 In the example case we can define that this particular machine shall
488 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
489 fi2c0 group gi2c0, on the primary pin controller, we get mappings
490 like these:
491
492 {
493 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
494 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
495 }
496
Stephen Warren1681f5a2012-02-22 14:25:58 -0700497 Every map must be assigned a state name, pin controller, device and
498 function. The group is not compulsory - if it is omitted the first group
499 presented by the driver as applicable for the function will be selected,
500 which is useful for simple cases.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200501
502 It is possible to map several groups to the same combination of device,
503 pin controller and function. This is for cases where a certain function on
504 a certain pin controller may use different sets of pins in different
505 configurations.
506
507- PINS for a certain FUNCTION using a certain PIN GROUP on a certain
508 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
509 other device mux setting or GPIO pin request has already taken your physical
510 pin, you will be denied the use of it. To get (activate) a new setting, the
511 old one has to be put (deactivated) first.
512
513Sometimes the documentation and hardware registers will be oriented around
514pads (or "fingers") rather than pins - these are the soldering surfaces on the
515silicon inside the package, and may or may not match the actual number of
516pins/balls underneath the capsule. Pick some enumeration that makes sense to
517you. Define enumerators only for the pins you can control if that makes sense.
518
519Assumptions:
520
Linus Walleij336cdba02011-11-10 09:27:41 +0100521We assume that the number of possible function maps to pin groups is limited by
Linus Walleij2744e8a2011-05-02 20:50:54 +0200522the hardware. I.e. we assume that there is no system where any function can be
523mapped to any pin, like in a phone exchange. So the available pins groups for
524a certain function will be limited to a few choices (say up to eight or so),
525not hundreds or any amount of choices. This is the characteristic we have found
526by inspecting available pinmux hardware, and a necessary assumption since we
527expect pinmux drivers to present *all* possible function vs pin group mappings
528to the subsystem.
529
530
531Pinmux drivers
532==============
533
534The pinmux core takes care of preventing conflicts on pins and calling
535the pin controller driver to execute different settings.
536
537It is the responsibility of the pinmux driver to impose further restrictions
538(say for example infer electronic limitations due to load etc) to determine
539whether or not the requested function can actually be allowed, and in case it
540is possible to perform the requested mux setting, poke the hardware so that
541this happens.
542
543Pinmux drivers are required to supply a few callback functions, some are
544optional. Usually the enable() and disable() functions are implemented,
545writing values into some certain registers to activate a certain mux setting
546for a certain pin.
547
548A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
549into some register named MUX to select a certain function with a certain
550group of pins would work something like this:
551
552#include <linux/pinctrl/pinctrl.h>
553#include <linux/pinctrl/pinmux.h>
554
555struct foo_group {
556 const char *name;
557 const unsigned int *pins;
558 const unsigned num_pins;
559};
560
561static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
562static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
563static const unsigned i2c0_pins[] = { 24, 25 };
564static const unsigned mmc0_1_pins[] = { 56, 57 };
565static const unsigned mmc0_2_pins[] = { 58, 59 };
566static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
567
568static const struct foo_group foo_groups[] = {
569 {
570 .name = "spi0_0_grp",
571 .pins = spi0_0_pins,
572 .num_pins = ARRAY_SIZE(spi0_0_pins),
573 },
574 {
575 .name = "spi0_1_grp",
576 .pins = spi0_1_pins,
577 .num_pins = ARRAY_SIZE(spi0_1_pins),
578 },
579 {
580 .name = "i2c0_grp",
581 .pins = i2c0_pins,
582 .num_pins = ARRAY_SIZE(i2c0_pins),
583 },
584 {
585 .name = "mmc0_1_grp",
586 .pins = mmc0_1_pins,
587 .num_pins = ARRAY_SIZE(mmc0_1_pins),
588 },
589 {
590 .name = "mmc0_2_grp",
591 .pins = mmc0_2_pins,
592 .num_pins = ARRAY_SIZE(mmc0_2_pins),
593 },
594 {
595 .name = "mmc0_3_grp",
596 .pins = mmc0_3_pins,
597 .num_pins = ARRAY_SIZE(mmc0_3_pins),
598 },
599};
600
601
602static int foo_list_groups(struct pinctrl_dev *pctldev, unsigned selector)
603{
604 if (selector >= ARRAY_SIZE(foo_groups))
605 return -EINVAL;
606 return 0;
607}
608
609static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
610 unsigned selector)
611{
612 return foo_groups[selector].name;
613}
614
615static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
616 unsigned ** const pins,
617 unsigned * const num_pins)
618{
619 *pins = (unsigned *) foo_groups[selector].pins;
620 *num_pins = foo_groups[selector].num_pins;
621 return 0;
622}
623
624static struct pinctrl_ops foo_pctrl_ops = {
625 .list_groups = foo_list_groups,
626 .get_group_name = foo_get_group_name,
627 .get_group_pins = foo_get_group_pins,
628};
629
630struct foo_pmx_func {
631 const char *name;
632 const char * const *groups;
633 const unsigned num_groups;
634};
635
636static const char * const spi0_groups[] = { "spi0_1_grp" };
637static const char * const i2c0_groups[] = { "i2c0_grp" };
638static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
639 "mmc0_3_grp" };
640
641static const struct foo_pmx_func foo_functions[] = {
642 {
643 .name = "spi0",
644 .groups = spi0_groups,
645 .num_groups = ARRAY_SIZE(spi0_groups),
646 },
647 {
648 .name = "i2c0",
649 .groups = i2c0_groups,
650 .num_groups = ARRAY_SIZE(i2c0_groups),
651 },
652 {
653 .name = "mmc0",
654 .groups = mmc0_groups,
655 .num_groups = ARRAY_SIZE(mmc0_groups),
656 },
657};
658
659int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
660{
661 if (selector >= ARRAY_SIZE(foo_functions))
662 return -EINVAL;
663 return 0;
664}
665
666const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
667{
Linus Walleij336cdba02011-11-10 09:27:41 +0100668 return foo_functions[selector].name;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200669}
670
671static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
672 const char * const **groups,
673 unsigned * const num_groups)
674{
675 *groups = foo_functions[selector].groups;
676 *num_groups = foo_functions[selector].num_groups;
677 return 0;
678}
679
680int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
681 unsigned group)
682{
Linus Walleij336cdba02011-11-10 09:27:41 +0100683 u8 regbit = (1 << selector + group);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200684
685 writeb((readb(MUX)|regbit), MUX)
686 return 0;
687}
688
Linus Walleij336cdba02011-11-10 09:27:41 +0100689void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200690 unsigned group)
691{
Linus Walleij336cdba02011-11-10 09:27:41 +0100692 u8 regbit = (1 << selector + group);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200693
694 writeb((readb(MUX) & ~(regbit)), MUX)
695 return 0;
696}
697
698struct pinmux_ops foo_pmxops = {
699 .list_functions = foo_list_funcs,
700 .get_function_name = foo_get_fname,
701 .get_function_groups = foo_get_groups,
702 .enable = foo_enable,
703 .disable = foo_disable,
704};
705
706/* Pinmux operations are handled by some pin controller */
707static struct pinctrl_desc foo_desc = {
708 ...
709 .pctlops = &foo_pctrl_ops,
710 .pmxops = &foo_pmxops,
711};
712
713In the example activating muxing 0 and 1 at the same time setting bits
7140 and 1, uses one pin in common so they would collide.
715
716The beauty of the pinmux subsystem is that since it keeps track of all
717pins and who is using them, it will already have denied an impossible
718request like that, so the driver does not need to worry about such
719things - when it gets a selector passed in, the pinmux subsystem makes
720sure no other device or GPIO assignment is already using the selected
721pins. Thus bits 0 and 1 in the control register will never be set at the
722same time.
723
724All the above functions are mandatory to implement for a pinmux driver.
725
726
Linus Walleije93bcee2012-02-09 07:23:28 +0100727Pin control interaction with the GPIO subsystem
728===============================================
Linus Walleij2744e8a2011-05-02 20:50:54 +0200729
Linus Walleije93bcee2012-02-09 07:23:28 +0100730The public pinmux API contains two functions named pinctrl_request_gpio()
731and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
Linus Walleij542e7042011-11-14 10:06:22 +0100732gpiolib-based drivers as part of their gpio_request() and
Linus Walleije93bcee2012-02-09 07:23:28 +0100733gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
Linus Walleij542e7042011-11-14 10:06:22 +0100734shall only be called from within respective gpio_direction_[input|output]
735gpiolib implementation.
736
737NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
Linus Walleije93bcee2012-02-09 07:23:28 +0100738controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
739that driver request proper muxing and other control for its pins.
Linus Walleij542e7042011-11-14 10:06:22 +0100740
Linus Walleij2744e8a2011-05-02 20:50:54 +0200741The function list could become long, especially if you can convert every
742individual pin into a GPIO pin independent of any other pins, and then try
743the approach to define every pin as a function.
744
745In this case, the function array would become 64 entries for each GPIO
746setting and then the device functions.
747
Linus Walleije93bcee2012-02-09 07:23:28 +0100748For this reason there are two functions a pin control driver can implement
Linus Walleij542e7042011-11-14 10:06:22 +0100749to enable only GPIO on an individual pin: .gpio_request_enable() and
750.gpio_disable_free().
Linus Walleij2744e8a2011-05-02 20:50:54 +0200751
752This function will pass in the affected GPIO range identified by the pin
753controller core, so you know which GPIO pins are being affected by the request
754operation.
755
Linus Walleij542e7042011-11-14 10:06:22 +0100756If your driver needs to have an indication from the framework of whether the
757GPIO pin shall be used for input or output you can implement the
758.gpio_set_direction() function. As described this shall be called from the
759gpiolib driver and the affected GPIO range, pin offset and desired direction
760will be passed along to this function.
761
762Alternatively to using these special functions, it is fully allowed to use
Linus Walleije93bcee2012-02-09 07:23:28 +0100763named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
Linus Walleij542e7042011-11-14 10:06:22 +0100764obtain the function "gpioN" where "N" is the global GPIO pin number if no
765special GPIO-handler is registered.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200766
767
768Pinmux board/machine configuration
769==================================
770
771Boards and machines define how a certain complete running system is put
772together, including how GPIOs and devices are muxed, how regulators are
773constrained and how the clock tree looks. Of course pinmux settings are also
774part of this.
775
776A pinmux config for a machine looks pretty much like a simple regulator
777configuration, so for the example array above we want to enable i2c and
778spi on the second function mapping:
779
780#include <linux/pinctrl/machine.h>
781
Linus Walleije93bcee2012-02-09 07:23:28 +0100782static const struct pinctrl_map __initdata mapping[] = {
Linus Walleij2744e8a2011-05-02 20:50:54 +0200783 {
Stephen Warren806d3142012-02-23 17:04:39 -0700784 .dev_name = "foo-spi.0",
Stephen Warren51cd24e2011-12-09 16:59:05 -0700785 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200786 .function = "spi0",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200787 },
788 {
Stephen Warren806d3142012-02-23 17:04:39 -0700789 .dev_name = "foo-i2c.0",
Stephen Warren51cd24e2011-12-09 16:59:05 -0700790 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200791 .function = "i2c0",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200792 },
793 {
Stephen Warren806d3142012-02-23 17:04:39 -0700794 .dev_name = "foo-mmc.0",
Stephen Warren51cd24e2011-12-09 16:59:05 -0700795 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200796 .function = "mmc0",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200797 },
798};
799
800The dev_name here matches to the unique device name that can be used to look
801up the device struct (just like with clockdev or regulators). The function name
802must match a function provided by the pinmux driver handling this pin range.
803
804As you can see we may have several pin controllers on the system and thus
805we need to specify which one of them that contain the functions we wish
Linus Walleij9dfac4f2012-02-01 18:02:47 +0100806to map.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200807
808You register this pinmux mapping to the pinmux subsystem by simply:
809
Linus Walleije93bcee2012-02-09 07:23:28 +0100810 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
Linus Walleij2744e8a2011-05-02 20:50:54 +0200811
812Since the above construct is pretty common there is a helper macro to make
Stephen Warren51cd24e2011-12-09 16:59:05 -0700813it even more compact which assumes you want to use pinctrl-foo and position
Linus Walleij2744e8a2011-05-02 20:50:54 +02008140 for mapping, for example:
815
Linus Walleije93bcee2012-02-09 07:23:28 +0100816static struct pinctrl_map __initdata mapping[] = {
817 PIN_MAP("I2CMAP", "pinctrl-foo", "i2c0", "foo-i2c.0"),
Linus Walleij2744e8a2011-05-02 20:50:54 +0200818};
819
820
821Complex mappings
822================
823
824As it is possible to map a function to different groups of pins an optional
825.group can be specified like this:
826
827...
828{
Stephen Warren806d3142012-02-23 17:04:39 -0700829 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200830 .name = "spi0-pos-A",
Stephen Warren51cd24e2011-12-09 16:59:05 -0700831 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200832 .function = "spi0",
833 .group = "spi0_0_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200834},
835{
Stephen Warren806d3142012-02-23 17:04:39 -0700836 .dev_name = "foo-spi.0",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200837 .name = "spi0-pos-B",
Stephen Warren51cd24e2011-12-09 16:59:05 -0700838 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200839 .function = "spi0",
840 .group = "spi0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200841},
842...
843
844This example mapping is used to switch between two positions for spi0 at
845runtime, as described further below under the heading "Runtime pinmuxing".
846
847Further it is possible to match several groups of pins to the same function
848for a single device, say for example in the mmc0 example above, where you can
849additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
850three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
851case), we define a mapping like this:
852
853...
854{
Stephen Warren806d3142012-02-23 17:04:39 -0700855 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100856 .name = "2bit"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700857 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200858 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +0100859 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200860},
861{
Stephen Warren806d3142012-02-23 17:04:39 -0700862 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100863 .name = "4bit"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700864 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200865 .function = "mmc0",
866 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200867},
868{
Stephen Warren806d3142012-02-23 17:04:39 -0700869 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100870 .name = "4bit"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700871 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200872 .function = "mmc0",
Linus Walleij336cdba02011-11-10 09:27:41 +0100873 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200874},
875{
Stephen Warren806d3142012-02-23 17:04:39 -0700876 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100877 .name = "8bit"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700878 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200879 .group = "mmc0_1_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200880},
881{
Stephen Warren806d3142012-02-23 17:04:39 -0700882 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100883 .name = "8bit"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700884 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200885 .function = "mmc0",
886 .group = "mmc0_2_grp",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200887},
Linus Walleij336cdba02011-11-10 09:27:41 +0100888{
Stephen Warren806d3142012-02-23 17:04:39 -0700889 .dev_name = "foo-mmc.0",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100890 .name = "8bit"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700891 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij336cdba02011-11-10 09:27:41 +0100892 .function = "mmc0",
893 .group = "mmc0_3_grp",
Linus Walleij336cdba02011-11-10 09:27:41 +0100894},
Linus Walleij2744e8a2011-05-02 20:50:54 +0200895...
896
897The result of grabbing this mapping from the device with something like
898this (see next paragraph):
899
Linus Walleije93bcee2012-02-09 07:23:28 +0100900 p = pinctrl_get(&device, "8bit");
Linus Walleij2744e8a2011-05-02 20:50:54 +0200901
902Will be that you activate all the three bottom records in the mapping at
903once. Since they share the same name, pin controller device, funcion and
904device, and since we allow multiple groups to match to a single device, they
905all get selected, and they all get enabled and disable simultaneously by the
906pinmux core.
907
908
909Pinmux requests from drivers
910============================
911
Linus Walleije93bcee2012-02-09 07:23:28 +0100912Generally it is discouraged to let individual drivers get and enable pin
913control. So if possible, handle the pin control in platform code or some other
914place where you have access to all the affected struct device * pointers. In
915some cases where a driver needs to e.g. switch between different mux mappings
916at runtime this is not possible.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200917
Linus Walleije93bcee2012-02-09 07:23:28 +0100918A driver may request a certain control state to be activated, usually just the
919default state like this:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200920
Linus Walleij28a8d142012-02-09 01:52:22 +0100921#include <linux/pinctrl/consumer.h>
Linus Walleij2744e8a2011-05-02 20:50:54 +0200922
923struct foo_state {
Linus Walleije93bcee2012-02-09 07:23:28 +0100924 struct pinctrl *p;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200925 ...
926};
927
928foo_probe()
929{
930 /* Allocate a state holder named "state" etc */
Linus Walleije93bcee2012-02-09 07:23:28 +0100931 struct pinctrl p;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200932
Linus Walleije93bcee2012-02-09 07:23:28 +0100933 p = pinctrl_get(&device, NULL);
934 if IS_ERR(p)
935 return PTR_ERR(p);
936 pinctrl_enable(p);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200937
Linus Walleije93bcee2012-02-09 07:23:28 +0100938 state->p = p;
Linus Walleij2744e8a2011-05-02 20:50:54 +0200939}
940
941foo_remove()
942{
Linus Walleije93bcee2012-02-09 07:23:28 +0100943 pinctrl_disable(state->p);
944 pinctrl_put(state->p);
Linus Walleij2744e8a2011-05-02 20:50:54 +0200945}
946
Linus Walleije93bcee2012-02-09 07:23:28 +0100947If you want to grab a specific control mapping and not just the first one
948found for this device you can specify a specific mapping name, for example in
949the above example the second i2c0 setting: pinctrl_get(&device, "spi0-pos-B");
Linus Walleij2744e8a2011-05-02 20:50:54 +0200950
951This get/enable/disable/put sequence can just as well be handled by bus drivers
952if you don't want each and every driver to handle it and you know the
953arrangement on your bus.
954
955The semantics of the get/enable respective disable/put is as follows:
956
Linus Walleije93bcee2012-02-09 07:23:28 +0100957- pinctrl_get() is called in process context to reserve the pins affected with
Linus Walleij2744e8a2011-05-02 20:50:54 +0200958 a certain mapping and set up the pinmux core and the driver. It will allocate
959 a struct from the kernel memory to hold the pinmux state.
960
Linus Walleije93bcee2012-02-09 07:23:28 +0100961- pinctrl_enable()/pinctrl_disable() is quick and can be called from fastpath
Linus Walleij2744e8a2011-05-02 20:50:54 +0200962 (irq context) when you quickly want to set up/tear down the hardware muxing
963 when running a device driver. Usually it will just poke some values into a
964 register.
965
Linus Walleije93bcee2012-02-09 07:23:28 +0100966- pinctrl_disable() is called in process context to tear down the pin requests
967 and release the state holder struct for the mux setting etc.
Linus Walleij2744e8a2011-05-02 20:50:54 +0200968
Linus Walleije93bcee2012-02-09 07:23:28 +0100969Usually the pin control core handled the get/put pair and call out to the
970device drivers bookkeeping operations, like checking available functions and
971the associated pins, whereas the enable/disable pass on to the pin controller
Linus Walleij2744e8a2011-05-02 20:50:54 +0200972driver which takes care of activating and/or deactivating the mux setting by
973quickly poking some registers.
974
Linus Walleije93bcee2012-02-09 07:23:28 +0100975The pins are allocated for your device when you issue the pinctrl_get() call,
Linus Walleij2744e8a2011-05-02 20:50:54 +0200976after this you should be able to see this in the debugfs listing of all pins.
977
978
Linus Walleije93bcee2012-02-09 07:23:28 +0100979System pin control hogging
980==========================
Linus Walleij2744e8a2011-05-02 20:50:54 +0200981
Stephen Warren1681f5a2012-02-22 14:25:58 -0700982Pin control map entries can be hogged by the core when the pin controller
Linus Walleije93bcee2012-02-09 07:23:28 +0100983is registered. This means that the core will attempt to call pinctrl_get() and
984pinctrl_enable() on it immediately after the pin control device has been
Linus Walleij2744e8a2011-05-02 20:50:54 +0200985registered.
986
Linus Walleij77a59882012-02-10 01:34:12 +0100987This is enabled by simply setting the .dev_name field in the map to the name
988of the pin controller itself, like this:
Linus Walleij2744e8a2011-05-02 20:50:54 +0200989
990{
Stephen Warren806d3142012-02-23 17:04:39 -0700991 .dev_name = "pinctrl-foo",
Uwe Kleine-Königf54367f2012-01-19 22:35:05 +0100992 .name = "POWERMAP"
Stephen Warren51cd24e2011-12-09 16:59:05 -0700993 .ctrl_dev_name = "pinctrl-foo",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200994 .function = "power_func",
Linus Walleij2744e8a2011-05-02 20:50:54 +0200995},
996
997Since it may be common to request the core to hog a few always-applicable
998mux settings on the primary pin controller, there is a convenience macro for
999this:
1000
Linus Walleij77a59882012-02-10 01:34:12 +01001001PIN_MAP_PRIMARY_SYS_HOG("POWERMAP", "pinctrl-foo", "power_func")
Linus Walleij2744e8a2011-05-02 20:50:54 +02001002
1003This gives the exact same result as the above construction.
1004
1005
1006Runtime pinmuxing
1007=================
1008
1009It is possible to mux a certain function in and out at runtime, say to move
1010an SPI port from one set of pins to another set of pins. Say for example for
1011spi0 in the example above, we expose two different groups of pins for the same
1012function, but with different named in the mapping as described under
1013"Advanced mapping" above. So we have two mappings named "spi0-pos-A" and
1014"spi0-pos-B".
1015
1016This snippet first muxes the function in the pins defined by group A, enables
1017it, disables and releases it, and muxes it in on the pins defined by group B:
1018
Linus Walleij28a8d142012-02-09 01:52:22 +01001019#include <linux/pinctrl/consumer.h>
1020
Linus Walleij2744e8a2011-05-02 20:50:54 +02001021foo_switch()
1022{
Linus Walleije93bcee2012-02-09 07:23:28 +01001023 struct pinctrl *p;
Linus Walleij2744e8a2011-05-02 20:50:54 +02001024
1025 /* Enable on position A */
Linus Walleije93bcee2012-02-09 07:23:28 +01001026 p = pinctrl_get(&device, "spi0-pos-A");
1027 if IS_ERR(p)
1028 return PTR_ERR(p);
1029 pinctrl_enable(p);
Linus Walleij2744e8a2011-05-02 20:50:54 +02001030
1031 /* This releases the pins again */
Linus Walleije93bcee2012-02-09 07:23:28 +01001032 pinctrl_disable(p);
1033 pinctrl_put(p);
Linus Walleij2744e8a2011-05-02 20:50:54 +02001034
1035 /* Enable on position B */
Linus Walleije93bcee2012-02-09 07:23:28 +01001036 p = pinctrl_get(&device, "spi0-pos-B");
1037 if IS_ERR(p)
1038 return PTR_ERR(p);
1039 pinctrl_enable(p);
Linus Walleij2744e8a2011-05-02 20:50:54 +02001040 ...
1041}
1042
1043The above has to be done from process context.