blob: 204d3d4d73882ea6b00ee5d953d56af7f08c8ea0 [file] [log] [blame]
Erik Gillingc5f80062010-01-21 16:53:02 -08001if ARCH_TEGRA
2
3comment "NVIDIA Tegra options"
4
Erik Gillingc5f80062010-01-21 16:53:02 -08005config ARCH_TEGRA_2x_SOC
Peter De Schrijver44107d82011-12-14 17:03:25 +02006 bool "Enable support for Tegra20 family"
Erik Gillingc5f80062010-01-21 16:53:02 -08007 select CPU_V7
8 select ARM_GIC
Erik Gilling3c92db92010-03-15 19:40:06 -07009 select ARCH_REQUIRE_GPIOLIB
Stephen Warrenf1f1ffa2012-02-01 14:04:48 -070010 select PINCTRL
11 select PINCTRL_TEGRA20
Benoit Goby91525d02011-03-09 16:28:55 -080012 select USB_ARCH_HAS_EHCI if USB_SUPPORT
Arnd Bergmann279b6582012-03-02 17:26:00 -050013 select USB_ULPI if USB
Benoit Goby91525d02011-03-09 16:28:55 -080014 select USB_ULPI_VIEWPORT if USB_SUPPORT
Stephen Warrenf35b4312012-02-14 13:39:39 -070015 select ARM_ERRATA_720789
16 select ARM_ERRATA_742230
17 select ARM_ERRATA_751472
18 select ARM_ERRATA_754327
19 select ARM_ERRATA_764369
20 select PL310_ERRATA_727915 if CACHE_L2X0
21 select PL310_ERRATA_769419 if CACHE_L2X0
Arnd Bergmann013df382012-03-02 15:58:28 -050022 select CPU_FREQ_TABLE if CPU_FREQ
Erik Gillingc5f80062010-01-21 16:53:02 -080023 help
24 Support for NVIDIA Tegra AP20 and T20 processors, based on the
25 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
26
Peter De Schrijver44107d82011-12-14 17:03:25 +020027config ARCH_TEGRA_3x_SOC
28 bool "Enable support for Tegra30 family"
29 select CPU_V7
30 select ARM_GIC
31 select ARCH_REQUIRE_GPIOLIB
Stephen Warrenf1f1ffa2012-02-01 14:04:48 -070032 select PINCTRL
33 select PINCTRL_TEGRA30
Peter De Schrijver44107d82011-12-14 17:03:25 +020034 select USB_ARCH_HAS_EHCI if USB_SUPPORT
Arnd Bergmann279b6582012-03-02 17:26:00 -050035 select USB_ULPI if USB
Peter De Schrijver44107d82011-12-14 17:03:25 +020036 select USB_ULPI_VIEWPORT if USB_SUPPORT
37 select USE_OF
Stephen Warrenf35b4312012-02-14 13:39:39 -070038 select ARM_ERRATA_743622
39 select ARM_ERRATA_751472
40 select ARM_ERRATA_754322
41 select ARM_ERRATA_764369
42 select PL310_ERRATA_769419 if CACHE_L2X0
Arnd Bergmann013df382012-03-02 15:58:28 -050043 select CPU_FREQ_TABLE if CPU_FREQ
Peter De Schrijver44107d82011-12-14 17:03:25 +020044 help
45 Support for NVIDIA Tegra T30 processor family, based on the
46 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
Erik Gillingc5f80062010-01-21 16:53:02 -080047
Mike Rapoport77ffc142010-09-27 11:26:33 +020048config TEGRA_PCI
49 bool "PCI Express support"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020050 depends on ARCH_TEGRA_2x_SOC
Mike Rapoport77ffc142010-09-27 11:26:33 +020051 select PCI
52
Erik Gillingc5f80062010-01-21 16:53:02 -080053comment "Tegra board type"
54
55config MACH_HARMONY
56 bool "Harmony board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020057 depends on ARCH_TEGRA_2x_SOC
Uwe Kleine-König885f24e2011-07-26 10:15:59 +020058 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
Erik Gillingc5f80062010-01-21 16:53:02 -080059 help
60 Support for nVidia Harmony development platform
61
Olof Johanssond9a51fe2011-02-19 17:25:32 -080062config MACH_KAEN
63 bool "Kaen board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020064 depends on ARCH_TEGRA_2x_SOC
Olof Johanssond9a51fe2011-02-19 17:25:32 -080065 select MACH_SEABOARD
Uwe Kleine-König885f24e2011-07-26 10:15:59 +020066 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
Olof Johanssond9a51fe2011-02-19 17:25:32 -080067 help
68 Support for the Kaen version of Seaboard
69
Marc Dietrich65b935a2011-03-07 21:01:31 +010070config MACH_PAZ00
71 bool "Paz00 board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020072 depends on ARCH_TEGRA_2x_SOC
Marc Dietrich65b935a2011-03-07 21:01:31 +010073 help
74 Support for the Toshiba AC100/Dynabook AZ netbook
75
Olof Johanssond9a51fe2011-02-19 17:25:32 -080076config MACH_SEABOARD
77 bool "Seaboard board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020078 depends on ARCH_TEGRA_2x_SOC
Uwe Kleine-König885f24e2011-07-26 10:15:59 +020079 select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
Olof Johanssond9a51fe2011-02-19 17:25:32 -080080 help
81 Support for nVidia Seaboard development platform. It will
82 also be included for some of the derivative boards that
83 have large similarities with the seaboard design.
84
Grant Likely8e267f32011-07-19 17:26:54 -060085config MACH_TEGRA_DT
Peter De Schrijvera2385dc2011-12-14 17:03:18 +020086 bool "Generic Tegra20 board (FDT support)"
Stephen Warren24692c02011-12-19 12:24:04 -070087 depends on ARCH_TEGRA_2x_SOC
Grant Likely8e267f32011-07-19 17:26:54 -060088 select USE_OF
89 help
Peter De Schrijvera2385dc2011-12-14 17:03:18 +020090 Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
Grant Likely8e267f32011-07-19 17:26:54 -060091
Mike Rapoportcca414b2011-02-07 10:10:53 +020092config MACH_TRIMSLICE
93 bool "TrimSlice board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +020094 depends on ARCH_TEGRA_2x_SOC
Mike Rapoportcca414b2011-02-07 10:10:53 +020095 select TEGRA_PCI
96 help
97 Support for CompuLab TrimSlice platform
98
Olof Johanssond9a51fe2011-02-19 17:25:32 -080099config MACH_WARIO
100 bool "Wario board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +0200101 depends on ARCH_TEGRA_2x_SOC
Olof Johanssond9a51fe2011-02-19 17:25:32 -0800102 select MACH_SEABOARD
103 help
104 Support for the Wario version of Seaboard
105
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300106config MACH_VENTANA
107 bool "Ventana board"
Peter De Schrijverb2bbbc42011-12-14 17:03:14 +0200108 depends on ARCH_TEGRA_2x_SOC
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300109 select MACH_TEGRA_DT
110 help
111 Support for the nVidia Ventana development platform
112
Erik Gillingc5f80062010-01-21 16:53:02 -0800113choice
Stephen Warren80881da2012-03-26 12:49:57 -0600114 prompt "Default low-level debug console UART"
Erik Gillingc5f80062010-01-21 16:53:02 -0800115 default TEGRA_DEBUG_UART_NONE
116
117config TEGRA_DEBUG_UART_NONE
118 bool "None"
119
120config TEGRA_DEBUG_UARTA
121 bool "UART-A"
122
123config TEGRA_DEBUG_UARTB
124 bool "UART-B"
125
126config TEGRA_DEBUG_UARTC
127 bool "UART-C"
128
129config TEGRA_DEBUG_UARTD
130 bool "UART-D"
131
132config TEGRA_DEBUG_UARTE
133 bool "UART-E"
134
135endchoice
136
Stephen Warren80881da2012-03-26 12:49:57 -0600137choice
138 prompt "Automatic low-level debug console UART"
139 default TEGRA_DEBUG_UART_AUTO_NONE
140
141config TEGRA_DEBUG_UART_AUTO_NONE
142 bool "None"
143
144config TEGRA_DEBUG_UART_AUTO_ODMDATA
145 bool "Via ODMDATA"
146 help
147 Automatically determines which UART to use for low-level debug based
148 on the ODMDATA value. This value is part of the BCT, and is written
149 to the boot memory device using nvflash, or other flashing tool.
150 When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
151 0/1/2/3/4 are UART A/B/C/D/E.
152
153config TEGRA_DEBUG_UART_AUTO_SCRATCH
154 bool "Via UART scratch register"
155 help
156 Automatically determines which UART to use for low-level debug based
157 on the UART scratch register value. Some bootloaders put ASCII 'D'
158 in this register when they initialize their own console UART output.
159 Using this option allows the kernel to automatically pick the same
160 UART.
161
162endchoice
163
Colin Cross4de3a8f2010-04-05 13:16:42 -0700164config TEGRA_SYSTEM_DMA
165 bool "Enable system DMA driver for NVIDIA Tegra SoCs"
166 default y
167 help
168 Adds system DMA functionality for NVIDIA Tegra SoCs, used by
169 several Tegra device drivers
170
Colin Crossefdf72a2011-02-12 18:22:49 -0800171config TEGRA_EMC_SCALING_ENABLE
172 bool "Enable scaling the memory frequency"
Mark Brown38376862011-02-22 20:35:24 +0000173
174endif