Scott Wood | 15f8c60 | 2007-09-28 14:06:16 -0500 | [diff] [blame] | 1 | #ifndef __CPM_H |
| 2 | #define __CPM_H |
| 3 | |
| 4 | #include <linux/compiler.h> |
| 5 | #include <linux/types.h> |
Laurent Pinchart | e193325 | 2008-07-28 10:43:22 +0200 | [diff] [blame] | 6 | #include <linux/of.h> |
Scott Wood | 15f8c60 | 2007-09-28 14:06:16 -0500 | [diff] [blame] | 7 | |
Anton Vorontsov | 8095298 | 2009-10-12 20:49:16 +0400 | [diff] [blame^] | 8 | /* |
| 9 | * USB Controller pram common to QE and CPM. |
| 10 | */ |
| 11 | struct usb_ctlr { |
| 12 | u8 usb_usmod; |
| 13 | u8 usb_usadr; |
| 14 | u8 usb_uscom; |
| 15 | u8 res1[1]; |
| 16 | __be16 usb_usep[4]; |
| 17 | u8 res2[4]; |
| 18 | __be16 usb_usber; |
| 19 | u8 res3[2]; |
| 20 | __be16 usb_usbmr; |
| 21 | u8 res4[1]; |
| 22 | u8 usb_usbs; |
| 23 | /* Fields down below are QE-only */ |
| 24 | __be16 usb_ussft; |
| 25 | u8 res5[2]; |
| 26 | __be16 usb_usfrn; |
| 27 | u8 res6[0x22]; |
| 28 | } __attribute__ ((packed)); |
| 29 | |
Laurent Pinchart | e24e788 | 2008-04-10 17:00:53 +0200 | [diff] [blame] | 30 | /* Opcodes common to CPM1 and CPM2 |
| 31 | */ |
| 32 | #define CPM_CR_INIT_TRX ((ushort)0x0000) |
| 33 | #define CPM_CR_INIT_RX ((ushort)0x0001) |
| 34 | #define CPM_CR_INIT_TX ((ushort)0x0002) |
| 35 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) |
| 36 | #define CPM_CR_STOP_TX ((ushort)0x0004) |
| 37 | #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) |
| 38 | #define CPM_CR_RESTART_TX ((ushort)0x0006) |
| 39 | #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) |
| 40 | #define CPM_CR_SET_GADDR ((ushort)0x0008) |
| 41 | #define CPM_CR_SET_TIMER ((ushort)0x0008) |
| 42 | #define CPM_CR_STOP_IDMA ((ushort)0x000b) |
| 43 | |
Jochen Friedrich | 44f25fb | 2008-01-24 16:20:05 +0100 | [diff] [blame] | 44 | /* Buffer descriptors used by many of the CPM protocols. */ |
| 45 | typedef struct cpm_buf_desc { |
| 46 | ushort cbd_sc; /* Status and Control */ |
| 47 | ushort cbd_datlen; /* Data length in buffer */ |
| 48 | uint cbd_bufaddr; /* Buffer address in host memory */ |
| 49 | } cbd_t; |
| 50 | |
| 51 | /* Buffer descriptor control/status used by serial |
| 52 | */ |
| 53 | |
| 54 | #define BD_SC_EMPTY (0x8000) /* Receive is empty */ |
| 55 | #define BD_SC_READY (0x8000) /* Transmit is ready */ |
| 56 | #define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ |
| 57 | #define BD_SC_INTRPT (0x1000) /* Interrupt on change */ |
| 58 | #define BD_SC_LAST (0x0800) /* Last buffer in frame */ |
| 59 | #define BD_SC_TC (0x0400) /* Transmit CRC */ |
| 60 | #define BD_SC_CM (0x0200) /* Continous mode */ |
| 61 | #define BD_SC_ID (0x0100) /* Rec'd too many idles */ |
| 62 | #define BD_SC_P (0x0100) /* xmt preamble */ |
| 63 | #define BD_SC_BR (0x0020) /* Break received */ |
| 64 | #define BD_SC_FR (0x0010) /* Framing error */ |
| 65 | #define BD_SC_PR (0x0008) /* Parity error */ |
| 66 | #define BD_SC_NAK (0x0004) /* NAK - did not respond */ |
| 67 | #define BD_SC_OV (0x0002) /* Overrun */ |
| 68 | #define BD_SC_UN (0x0002) /* Underrun */ |
| 69 | #define BD_SC_CD (0x0001) /* */ |
| 70 | #define BD_SC_CL (0x0001) /* Collision */ |
| 71 | |
| 72 | /* Buffer descriptor control/status used by Ethernet receive. |
| 73 | * Common to SCC and FCC. |
| 74 | */ |
| 75 | #define BD_ENET_RX_EMPTY (0x8000) |
| 76 | #define BD_ENET_RX_WRAP (0x2000) |
| 77 | #define BD_ENET_RX_INTR (0x1000) |
| 78 | #define BD_ENET_RX_LAST (0x0800) |
| 79 | #define BD_ENET_RX_FIRST (0x0400) |
| 80 | #define BD_ENET_RX_MISS (0x0100) |
| 81 | #define BD_ENET_RX_BC (0x0080) /* FCC Only */ |
| 82 | #define BD_ENET_RX_MC (0x0040) /* FCC Only */ |
| 83 | #define BD_ENET_RX_LG (0x0020) |
| 84 | #define BD_ENET_RX_NO (0x0010) |
| 85 | #define BD_ENET_RX_SH (0x0008) |
| 86 | #define BD_ENET_RX_CR (0x0004) |
| 87 | #define BD_ENET_RX_OV (0x0002) |
| 88 | #define BD_ENET_RX_CL (0x0001) |
| 89 | #define BD_ENET_RX_STATS (0x01ff) /* All status bits */ |
| 90 | |
| 91 | /* Buffer descriptor control/status used by Ethernet transmit. |
| 92 | * Common to SCC and FCC. |
| 93 | */ |
| 94 | #define BD_ENET_TX_READY (0x8000) |
| 95 | #define BD_ENET_TX_PAD (0x4000) |
| 96 | #define BD_ENET_TX_WRAP (0x2000) |
| 97 | #define BD_ENET_TX_INTR (0x1000) |
| 98 | #define BD_ENET_TX_LAST (0x0800) |
| 99 | #define BD_ENET_TX_TC (0x0400) |
| 100 | #define BD_ENET_TX_DEF (0x0200) |
| 101 | #define BD_ENET_TX_HB (0x0100) |
| 102 | #define BD_ENET_TX_LC (0x0080) |
| 103 | #define BD_ENET_TX_RL (0x0040) |
| 104 | #define BD_ENET_TX_RCMASK (0x003c) |
| 105 | #define BD_ENET_TX_UN (0x0002) |
| 106 | #define BD_ENET_TX_CSL (0x0001) |
| 107 | #define BD_ENET_TX_STATS (0x03ff) /* All status bits */ |
| 108 | |
| 109 | /* Buffer descriptor control/status used by Transparent mode SCC. |
| 110 | */ |
| 111 | #define BD_SCC_TX_LAST (0x0800) |
| 112 | |
| 113 | /* Buffer descriptor control/status used by I2C. |
| 114 | */ |
| 115 | #define BD_I2C_START (0x0400) |
| 116 | |
Scott Wood | 15f8c60 | 2007-09-28 14:06:16 -0500 | [diff] [blame] | 117 | int cpm_muram_init(void); |
| 118 | unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); |
| 119 | int cpm_muram_free(unsigned long offset); |
| 120 | unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); |
| 121 | void __iomem *cpm_muram_addr(unsigned long offset); |
Anton Vorontsov | 5093bb9 | 2008-05-23 20:39:06 +0400 | [diff] [blame] | 122 | unsigned long cpm_muram_offset(void __iomem *addr); |
Scott Wood | 15f8c60 | 2007-09-28 14:06:16 -0500 | [diff] [blame] | 123 | dma_addr_t cpm_muram_dma(void __iomem *addr); |
Jochen Friedrich | 362f9b6 | 2007-11-26 18:03:40 +0100 | [diff] [blame] | 124 | int cpm_command(u32 command, u8 opcode); |
Scott Wood | 15f8c60 | 2007-09-28 14:06:16 -0500 | [diff] [blame] | 125 | |
Laurent Pinchart | e193325 | 2008-07-28 10:43:22 +0200 | [diff] [blame] | 126 | int cpm2_gpiochip_add32(struct device_node *np); |
| 127 | |
Scott Wood | 15f8c60 | 2007-09-28 14:06:16 -0500 | [diff] [blame] | 128 | #endif |