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Muralidharan Karicheri7b140b82009-06-19 09:20:16 -03001/*
2 * Copyright (C) 2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * vpss - video processing subsystem module header file.
19 *
20 * Include this header file if a driver needs to configure vpss system
21 * module. It exports a set of library functions for video drivers to
22 * configure vpss system module functions such as clock enable/disable,
23 * vpss interrupt mux to arm, and other common vpss system module
24 * functions.
25 */
26#ifndef _VPSS_H
27#define _VPSS_H
28
29/* selector for ccdc input selection on DM355 */
30enum vpss_ccdc_source_sel {
31 VPSS_CCDCIN,
Murali Karicheri85b848c2010-02-21 15:51:14 -030032 VPSS_HSSIIN,
33 VPSS_PGLPBK, /* for DM365 only */
34 VPSS_CCDCPG /* for DM365 only */
35};
36
37struct vpss_sync_pol {
38 unsigned int ccdpg_hdpol:1;
39 unsigned int ccdpg_vdpol:1;
40};
41
42struct vpss_pg_frame_size {
43 short hlpfr;
44 short pplen;
Muralidharan Karicheri7b140b82009-06-19 09:20:16 -030045};
46
Justin P. Mattockeb78bd72010-12-30 15:08:03 -080047/* Used for enable/disable VPSS Clock */
Muralidharan Karicheri7b140b82009-06-19 09:20:16 -030048enum vpss_clock_sel {
49 /* DM355/DM365 */
50 VPSS_CCDC_CLOCK,
51 VPSS_IPIPE_CLOCK,
52 VPSS_H3A_CLOCK,
53 VPSS_CFALD_CLOCK,
54 /*
55 * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
56 * following applies:-
57 * en = 0 selects ENC_CLK
58 * en = 1 selects ENC_CLK/2
59 */
60 VPSS_VENC_CLOCK_SEL,
61 VPSS_VPBE_CLOCK,
Murali Karicheri85b848c2010-02-21 15:51:14 -030062 /* DM365 only clocks */
63 VPSS_IPIPEIF_CLOCK,
64 VPSS_RSZ_CLOCK,
65 VPSS_BL_CLOCK,
66 /*
67 * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
68 * following applies:-
69 * en = 0 disable internal PCLK
70 * en = 1 enables internal PCLK
71 */
72 VPSS_PCLK_INTERNAL,
73 /*
74 * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
75 * following applies:-
76 * en = 0 enables MMR clock
77 * en = 1 enables VPSS clock
78 */
79 VPSS_PSYNC_CLOCK_SEL,
80 VPSS_LDC_CLOCK_SEL,
81 VPSS_OSD_CLOCK_SEL,
82 VPSS_FDIF_CLOCK,
83 VPSS_LDC_CLOCK
Muralidharan Karicheri7b140b82009-06-19 09:20:16 -030084};
85
86/* select input to ccdc on dm355 */
87int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
88/* enable/disable a vpss clock, 0 - success, -1 - failure */
89int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
Murali Karicheri85b848c2010-02-21 15:51:14 -030090/* set sync polarity, only for DM365*/
91void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
92/* set the PG_FRAME_SIZE register, only for DM365 */
93void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
Muralidharan Karicheri7b140b82009-06-19 09:20:16 -030094
95/* wbl reset for dm644x */
96enum vpss_wbl_sel {
97 VPSS_PCR_AEW_WBL_0 = 16,
98 VPSS_PCR_AF_WBL_0,
99 VPSS_PCR_RSZ4_WBL_0,
100 VPSS_PCR_RSZ3_WBL_0,
101 VPSS_PCR_RSZ2_WBL_0,
102 VPSS_PCR_RSZ1_WBL_0,
103 VPSS_PCR_PREV_WBL_0,
104 VPSS_PCR_CCDC_WBL_O,
105};
Murali Karicheri85b848c2010-02-21 15:51:14 -0300106/* clear wbl overflow flag for DM6446 */
Muralidharan Karicheri7b140b82009-06-19 09:20:16 -0300107int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
108#endif