blob: 78ff09d70de4a455480000ebd2b38c5383eaf612 [file] [log] [blame]
Michael Chanb6016b72005-05-26 13:03:09 -07001/* bnx2.h: Broadcom NX2 network driver.
2 *
Michael Chan206cc832006-01-23 16:14:05 -08003 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
Michael Chanb6016b72005-05-26 13:03:09 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13#ifndef BNX2_H
14#define BNX2_H
15
Michael Chanb6016b72005-05-26 13:03:09 -070016/* Hardware data structures and register definitions automatically
17 * generated from RTL code. Do not modify.
18 */
19
20/*
21 * tx_bd definition
22 */
23struct tx_bd {
24 u32 tx_bd_haddr_hi;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040025 u32 tx_bd_haddr_lo;
26 u32 tx_bd_mss_nbytes;
27 u32 tx_bd_vlan_tag_flags;
Michael Chanb6016b72005-05-26 13:03:09 -070028 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
29 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
30 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
31 #define TX_BD_FLAGS_VLAN_TAG (1<<3)
32 #define TX_BD_FLAGS_COAL_NOW (1<<4)
33 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
34 #define TX_BD_FLAGS_END (1<<6)
35 #define TX_BD_FLAGS_START (1<<7)
36 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
37 #define TX_BD_FLAGS_SW_FLAGS (1<<13)
38 #define TX_BD_FLAGS_SW_SNAP (1<<14)
39 #define TX_BD_FLAGS_SW_LSO (1<<15)
40
41};
42
43
44/*
45 * rx_bd definition
46 */
47struct rx_bd {
48 u32 rx_bd_haddr_hi;
49 u32 rx_bd_haddr_lo;
50 u32 rx_bd_len;
51 u32 rx_bd_flags;
52 #define RX_BD_FLAGS_NOPUSH (1<<0)
53 #define RX_BD_FLAGS_DUMMY (1<<1)
54 #define RX_BD_FLAGS_END (1<<2)
55 #define RX_BD_FLAGS_START (1<<3)
56
57};
58
59
60/*
61 * status_block definition
62 */
63struct status_block {
64 u32 status_attn_bits;
65 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
66 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
67 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
68 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
69 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
70 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
71 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
72 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
73 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
74 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
75 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
76 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
77 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
78 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
79 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
80 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
81 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
82 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
83 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
84 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
85 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
86 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
87 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
88 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
89 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
90 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
91 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
92 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
93 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
94
95 u32 status_attn_bits_ack;
96#if defined(__BIG_ENDIAN)
97 u16 status_tx_quick_consumer_index0;
98 u16 status_tx_quick_consumer_index1;
99 u16 status_tx_quick_consumer_index2;
100 u16 status_tx_quick_consumer_index3;
101 u16 status_rx_quick_consumer_index0;
102 u16 status_rx_quick_consumer_index1;
103 u16 status_rx_quick_consumer_index2;
104 u16 status_rx_quick_consumer_index3;
105 u16 status_rx_quick_consumer_index4;
106 u16 status_rx_quick_consumer_index5;
107 u16 status_rx_quick_consumer_index6;
108 u16 status_rx_quick_consumer_index7;
109 u16 status_rx_quick_consumer_index8;
110 u16 status_rx_quick_consumer_index9;
111 u16 status_rx_quick_consumer_index10;
112 u16 status_rx_quick_consumer_index11;
113 u16 status_rx_quick_consumer_index12;
114 u16 status_rx_quick_consumer_index13;
115 u16 status_rx_quick_consumer_index14;
116 u16 status_rx_quick_consumer_index15;
117 u16 status_completion_producer_index;
118 u16 status_cmd_consumer_index;
119 u16 status_idx;
120 u16 status_unused;
121#elif defined(__LITTLE_ENDIAN)
122 u16 status_tx_quick_consumer_index1;
123 u16 status_tx_quick_consumer_index0;
124 u16 status_tx_quick_consumer_index3;
125 u16 status_tx_quick_consumer_index2;
126 u16 status_rx_quick_consumer_index1;
127 u16 status_rx_quick_consumer_index0;
128 u16 status_rx_quick_consumer_index3;
129 u16 status_rx_quick_consumer_index2;
130 u16 status_rx_quick_consumer_index5;
131 u16 status_rx_quick_consumer_index4;
132 u16 status_rx_quick_consumer_index7;
133 u16 status_rx_quick_consumer_index6;
134 u16 status_rx_quick_consumer_index9;
135 u16 status_rx_quick_consumer_index8;
136 u16 status_rx_quick_consumer_index11;
137 u16 status_rx_quick_consumer_index10;
138 u16 status_rx_quick_consumer_index13;
139 u16 status_rx_quick_consumer_index12;
140 u16 status_rx_quick_consumer_index15;
141 u16 status_rx_quick_consumer_index14;
142 u16 status_cmd_consumer_index;
143 u16 status_completion_producer_index;
144 u16 status_unused;
145 u16 status_idx;
146#endif
147};
148
149
150/*
151 * statistics_block definition
152 */
153struct statistics_block {
154 u32 stat_IfHCInOctets_hi;
155 u32 stat_IfHCInOctets_lo;
156 u32 stat_IfHCInBadOctets_hi;
157 u32 stat_IfHCInBadOctets_lo;
158 u32 stat_IfHCOutOctets_hi;
159 u32 stat_IfHCOutOctets_lo;
160 u32 stat_IfHCOutBadOctets_hi;
161 u32 stat_IfHCOutBadOctets_lo;
162 u32 stat_IfHCInUcastPkts_hi;
163 u32 stat_IfHCInUcastPkts_lo;
164 u32 stat_IfHCInMulticastPkts_hi;
165 u32 stat_IfHCInMulticastPkts_lo;
166 u32 stat_IfHCInBroadcastPkts_hi;
167 u32 stat_IfHCInBroadcastPkts_lo;
168 u32 stat_IfHCOutUcastPkts_hi;
169 u32 stat_IfHCOutUcastPkts_lo;
170 u32 stat_IfHCOutMulticastPkts_hi;
171 u32 stat_IfHCOutMulticastPkts_lo;
172 u32 stat_IfHCOutBroadcastPkts_hi;
173 u32 stat_IfHCOutBroadcastPkts_lo;
174 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
175 u32 stat_Dot3StatsCarrierSenseErrors;
176 u32 stat_Dot3StatsFCSErrors;
177 u32 stat_Dot3StatsAlignmentErrors;
178 u32 stat_Dot3StatsSingleCollisionFrames;
179 u32 stat_Dot3StatsMultipleCollisionFrames;
180 u32 stat_Dot3StatsDeferredTransmissions;
181 u32 stat_Dot3StatsExcessiveCollisions;
182 u32 stat_Dot3StatsLateCollisions;
183 u32 stat_EtherStatsCollisions;
184 u32 stat_EtherStatsFragments;
185 u32 stat_EtherStatsJabbers;
186 u32 stat_EtherStatsUndersizePkts;
187 u32 stat_EtherStatsOverrsizePkts;
188 u32 stat_EtherStatsPktsRx64Octets;
189 u32 stat_EtherStatsPktsRx65Octetsto127Octets;
190 u32 stat_EtherStatsPktsRx128Octetsto255Octets;
191 u32 stat_EtherStatsPktsRx256Octetsto511Octets;
192 u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
193 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
194 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
195 u32 stat_EtherStatsPktsTx64Octets;
196 u32 stat_EtherStatsPktsTx65Octetsto127Octets;
197 u32 stat_EtherStatsPktsTx128Octetsto255Octets;
198 u32 stat_EtherStatsPktsTx256Octetsto511Octets;
199 u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
200 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
201 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
202 u32 stat_XonPauseFramesReceived;
203 u32 stat_XoffPauseFramesReceived;
204 u32 stat_OutXonSent;
205 u32 stat_OutXoffSent;
206 u32 stat_FlowControlDone;
207 u32 stat_MacControlFramesReceived;
208 u32 stat_XoffStateEntered;
209 u32 stat_IfInFramesL2FilterDiscards;
210 u32 stat_IfInRuleCheckerDiscards;
211 u32 stat_IfInFTQDiscards;
212 u32 stat_IfInMBUFDiscards;
213 u32 stat_IfInRuleCheckerP4Hit;
214 u32 stat_CatchupInRuleCheckerDiscards;
215 u32 stat_CatchupInFTQDiscards;
216 u32 stat_CatchupInMBUFDiscards;
217 u32 stat_CatchupInRuleCheckerP4Hit;
218 u32 stat_GenStat00;
219 u32 stat_GenStat01;
220 u32 stat_GenStat02;
221 u32 stat_GenStat03;
222 u32 stat_GenStat04;
223 u32 stat_GenStat05;
224 u32 stat_GenStat06;
225 u32 stat_GenStat07;
226 u32 stat_GenStat08;
227 u32 stat_GenStat09;
228 u32 stat_GenStat10;
229 u32 stat_GenStat11;
230 u32 stat_GenStat12;
231 u32 stat_GenStat13;
232 u32 stat_GenStat14;
233 u32 stat_GenStat15;
Michael Chancea94db2006-06-12 22:16:13 -0700234 u32 stat_FwRxDrop;
Michael Chanb6016b72005-05-26 13:03:09 -0700235};
236
237
238/*
239 * l2_fhdr definition
240 */
241struct l2_fhdr {
Michael Chanade2bfe2006-01-23 16:09:51 -0800242 u32 l2_fhdr_status;
Michael Chanb6016b72005-05-26 13:03:09 -0700243 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
244 #define L2_FHDR_STATUS_RULE_P2 (1<<3)
245 #define L2_FHDR_STATUS_RULE_P3 (1<<4)
246 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
247 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
248 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
249 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
250 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
251 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
252 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
253
Michael Chanade2bfe2006-01-23 16:09:51 -0800254 #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
255 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
256 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
257 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
258 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
259 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
260 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
261
Michael Chanb6016b72005-05-26 13:03:09 -0700262 u32 l2_fhdr_hash;
263#if defined(__BIG_ENDIAN)
264 u16 l2_fhdr_pkt_len;
265 u16 l2_fhdr_vlan_tag;
266 u16 l2_fhdr_ip_xsum;
267 u16 l2_fhdr_tcp_udp_xsum;
268#elif defined(__LITTLE_ENDIAN)
269 u16 l2_fhdr_vlan_tag;
270 u16 l2_fhdr_pkt_len;
271 u16 l2_fhdr_tcp_udp_xsum;
272 u16 l2_fhdr_ip_xsum;
273#endif
274};
275
276
277/*
278 * l2_context definition
279 */
280#define BNX2_L2CTX_TYPE 0x00000000
281#define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
282#define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
283#define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
284#define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
285
286#define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
287#define BNX2_L2CTX_EST_NBD 0x00000088
288#define BNX2_L2CTX_CMD_TYPE 0x00000088
289#define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
290#define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
291#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
292
293#define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
294#define BNX2_L2CTX_TSCH_BSEQ 0x00000094
295#define BNX2_L2CTX_TBDR_BSEQ 0x00000098
296#define BNX2_L2CTX_TBDR_BOFF 0x0000009c
297#define BNX2_L2CTX_TBDR_BIDX 0x0000009c
298#define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
299#define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
300#define BNX2_L2CTX_TXP_BOFF 0x000000a8
301#define BNX2_L2CTX_TXP_BIDX 0x000000a8
302#define BNX2_L2CTX_TXP_BSEQ 0x000000ac
303
304
305/*
306 * l2_bd_chain_context definition
307 */
308#define BNX2_L2CTX_BD_PRE_READ 0x00000000
309#define BNX2_L2CTX_CTX_SIZE 0x00000000
310#define BNX2_L2CTX_CTX_TYPE 0x00000000
311#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
312#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
313#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
314#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
315
316#define BNX2_L2CTX_HOST_BDIDX 0x00000004
317#define BNX2_L2CTX_HOST_BSEQ 0x00000008
318#define BNX2_L2CTX_NX_BSEQ 0x0000000c
319#define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
320#define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
321#define BNX2_L2CTX_NX_BDIDX 0x00000018
322
323
324/*
325 * pci_config_l definition
326 * offset: 0000
327 */
328#define BNX2_PCICFG_MISC_CONFIG 0x00000068
329#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
330#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
331#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
332#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
333#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
334#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
335#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
336#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
337#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
338#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
339
340#define BNX2_PCICFG_MISC_STATUS 0x0000006c
341#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
342#define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
343#define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
344#define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
345#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
346#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
347#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
348#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
349#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
350
351#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
352#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
353#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
354#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
355#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
356#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
357#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
358#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
359#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
360#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
361#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
362#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
363#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
364#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
365#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
366#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
367#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
368#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
369#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
370#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
371#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
372#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
373#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
374#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
375#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
376#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
377#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
378#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
379#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
380#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
381
382#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
383#define BNX2_PCICFG_REG_WINDOW 0x00000080
384#define BNX2_PCICFG_INT_ACK_CMD 0x00000084
385#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
386#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
387#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
388#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
389
390#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
391#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
392#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
393#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
394
395
396/*
397 * pci_reg definition
398 * offset: 0x400
399 */
400#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
401#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
402
403#define BNX2_PCI_CONFIG_1 0x00000404
404#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
405#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
406#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
407#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
408#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
409#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
410#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
411#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
412#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
413#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
414#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
415#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
416#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
417#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
418#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
419#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
420#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
421#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
422
423#define BNX2_PCI_CONFIG_2 0x00000408
424#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
425#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
426#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
427#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
428#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
429#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
430#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
431#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
432#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
433#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
434#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
435#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
436#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
437#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
438#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
439#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
440#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
441#define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
442#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
443#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
444#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
445#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
446#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
447#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
448#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
449#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
450#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
451#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
452#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
453#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
454#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
455#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
456#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
457#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
458#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
459#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
460#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
461#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
462#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
463#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
464#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
465#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
466#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
467#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
468#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
469#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
470#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
471
472#define BNX2_PCI_CONFIG_3 0x0000040c
473#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
474#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
475#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
476#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
477#define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
478#define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
479#define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
480
481#define BNX2_PCI_PM_DATA_A 0x00000410
482#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
483#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
484#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
485#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
486
487#define BNX2_PCI_PM_DATA_B 0x00000414
488#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
489#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
490#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
491#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
492
493#define BNX2_PCI_SWAP_DIAG0 0x00000418
494#define BNX2_PCI_SWAP_DIAG1 0x0000041c
495#define BNX2_PCI_EXP_ROM_ADDR 0x00000420
496#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
497#define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
498
499#define BNX2_PCI_EXP_ROM_DATA 0x00000424
500#define BNX2_PCI_VPD_INTF 0x00000428
501#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
502
503#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
504#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
505#define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15)
506
507#define BNX2_PCI_VPD_DATA 0x00000430
508#define BNX2_PCI_ID_VAL1 0x00000434
509#define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
510#define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
511
512#define BNX2_PCI_ID_VAL2 0x00000438
513#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
514#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
515
516#define BNX2_PCI_ID_VAL3 0x0000043c
517#define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
518#define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
519
520#define BNX2_PCI_ID_VAL4 0x00000440
521#define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
522#define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
523#define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
524#define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
525#define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
526#define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
527#define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
528#define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
529#define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
530#define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
531#define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
532#define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
533#define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
534#define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
535#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
536#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
537#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
538#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
539#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
540#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
541#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
542#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
543#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
544#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
545#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
546#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
547#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
548#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
549#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
550#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
551
552#define BNX2_PCI_ID_VAL5 0x00000444
553#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
554#define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
555#define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
556#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
557#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
558#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
559
560#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
561#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
562#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
563#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
564#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
565
566#define BNX2_PCI_ID_VAL6 0x0000044c
567#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
568#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
569#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
570
571#define BNX2_PCI_MSI_DATA 0x00000450
572#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
573
574#define BNX2_PCI_MSI_ADDR_H 0x00000454
575#define BNX2_PCI_MSI_ADDR_L 0x00000458
576
577
578/*
579 * misc_reg definition
580 * offset: 0x800
581 */
582#define BNX2_MISC_COMMAND 0x00000800
583#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
584#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
585#define BNX2_MISC_COMMAND_CORE_RESET (1L<<4)
586#define BNX2_MISC_COMMAND_HARD_RESET (1L<<5)
587#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
588#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
589
590#define BNX2_MISC_CFG 0x00000804
591#define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
592#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
593#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
594#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
595#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
596#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
597#define BNX2_MISC_CFG_BIST_EN (1L<<3)
598#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
599#define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5)
600#define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6)
601#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
602#define BNX2_MISC_CFG_LEDMODE (0x3L<<8)
603#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
604#define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
605#define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
606
607#define BNX2_MISC_ID 0x00000808
608#define BNX2_MISC_ID_BOND_ID (0xfL<<0)
609#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
610#define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
611#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
612
613#define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
614#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
615#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
616#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
617#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
618#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
619#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
620#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
621#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
622#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
623#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
624#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
625#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
626#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
627#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
628#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
629#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
630#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
631#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
632#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
633#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
634#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
635#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
636#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
637#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
638#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
639#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
640#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
641#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
642
643#define BNX2_MISC_ENABLE_SET_BITS 0x00000810
644#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
645#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
646#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
647#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
648#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
649#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
650#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
651#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
652#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
653#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
654#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
655#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
656#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
657#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
658#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
659#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
660#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
661#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
662#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
663#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
664#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
665#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
666#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
667#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
668#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
669#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
670#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
671#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
672
673#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
674#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
675#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
676#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
677#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
678#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
679#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
680#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
681#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
682#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
683#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
684#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
685#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
686#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
687#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
688#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
689#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
690#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
691#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
692#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
693#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
694#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
695#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
696#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
697#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
698#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
699#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
700#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
701#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
702
703#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
704#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
705#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
706#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
707#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
708#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
709#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
710#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
711#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
712#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
713#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
714#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
715#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
716#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
717#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
718#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
719#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
720#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
721#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
722#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
723#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
724#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
725#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
726#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
727#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
728#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
729#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
730#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
731#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
732#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
733
734#define BNX2_MISC_GPIO 0x0000081c
735#define BNX2_MISC_GPIO_VALUE (0xffL<<0)
736#define BNX2_MISC_GPIO_SET (0xffL<<8)
737#define BNX2_MISC_GPIO_CLR (0xffL<<16)
738#define BNX2_MISC_GPIO_FLOAT (0xffL<<24)
739
740#define BNX2_MISC_GPIO_INT 0x00000820
741#define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0)
742#define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
743#define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16)
744#define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
745
746#define BNX2_MISC_CONFIG_LFSR 0x00000824
747#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
748
749#define BNX2_MISC_LFSR_MASK_BITS 0x00000828
750#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
751#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
752#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
753#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
754#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
755#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
756#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
757#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
758#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
759#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
760#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
761#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
762#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
763#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
764#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
765#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
766#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
767#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
768#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
769#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
770#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
771#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
772#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
773#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
774#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
775#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
776#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
777#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
778
779#define BNX2_MISC_ARB_REQ0 0x0000082c
780#define BNX2_MISC_ARB_REQ1 0x00000830
781#define BNX2_MISC_ARB_REQ2 0x00000834
782#define BNX2_MISC_ARB_REQ3 0x00000838
783#define BNX2_MISC_ARB_REQ4 0x0000083c
784#define BNX2_MISC_ARB_FREE0 0x00000840
785#define BNX2_MISC_ARB_FREE1 0x00000844
786#define BNX2_MISC_ARB_FREE2 0x00000848
787#define BNX2_MISC_ARB_FREE3 0x0000084c
788#define BNX2_MISC_ARB_FREE4 0x00000850
789#define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
790#define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
791#define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
792#define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
793#define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
794#define BNX2_MISC_ARB_GNT0 0x00000868
795#define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
796#define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
797#define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
798#define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
799#define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
800#define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
801#define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
802#define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
803
804#define BNX2_MISC_ARB_GNT1 0x0000086c
805#define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
806#define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
807#define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
808#define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
809#define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
810#define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
811#define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
812#define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
813
814#define BNX2_MISC_ARB_GNT2 0x00000870
815#define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
816#define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
817#define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
818#define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
819#define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
820#define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
821#define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
822#define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
823
824#define BNX2_MISC_ARB_GNT3 0x00000874
825#define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
826#define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
827#define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
828#define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
829#define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
830#define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
831#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
832#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
833
834#define BNX2_MISC_PRBS_CONTROL 0x00000878
835#define BNX2_MISC_PRBS_CONTROL_EN (1L<<0)
836#define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1)
837#define BNX2_MISC_PRBS_CONTROL_INV (1L<<2)
838#define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
839#define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
840#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
841#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
842#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
843#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
844
845#define BNX2_MISC_PRBS_STATUS 0x0000087c
846#define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
847#define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
848#define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
849#define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
850
851#define BNX2_MISC_SM_ASF_CONTROL 0x00000880
852#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
853#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
854#define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
855#define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
856#define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
857#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
858#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
859#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
860#define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
861#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
862#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
863#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
864#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
865#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
866#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
867#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
868#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
869
870#define BNX2_MISC_SMB_IN 0x00000884
871#define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
872#define BNX2_MISC_SMB_IN_RDY (1L<<8)
873#define BNX2_MISC_SMB_IN_DONE (1L<<9)
874#define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
875#define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
876#define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
877#define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
878#define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
879#define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
880#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
881
882#define BNX2_MISC_SMB_OUT 0x00000888
883#define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
884#define BNX2_MISC_SMB_OUT_RDY (1L<<8)
885#define BNX2_MISC_SMB_OUT_START (1L<<9)
886#define BNX2_MISC_SMB_OUT_LAST (1L<<10)
887#define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
888#define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
889#define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
890#define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
891#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
892#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
893#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
894#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
895#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
896#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
897#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
898#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
899#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
900#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
901#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
902#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
903#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
904#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
905#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
906
907#define BNX2_MISC_SMB_WATCHDOG 0x0000088c
908#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
909
910#define BNX2_MISC_SMB_HEARTBEAT 0x00000890
911#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
912
913#define BNX2_MISC_SMB_POLL_ASF 0x00000894
914#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
915
916#define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
917#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
918
919#define BNX2_MISC_SMB_RETRAN 0x0000089c
920#define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
921
922#define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
923#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
924
925#define BNX2_MISC_PERR_ENA0 0x000008a4
926#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
927#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
928#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
929#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
930#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
931#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
932#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
933#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
934#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
935#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
936#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
937#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
938#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
939#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
940#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
941#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
942#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
943#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
944#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
945#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
946#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
947#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
948#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
949#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
950#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
951#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
952#define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
953#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
954#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
955#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
956#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
957#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
958
959#define BNX2_MISC_PERR_ENA1 0x000008a8
960#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
961#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
962#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
963#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
964#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
965#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
966#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
967#define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
968#define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
969#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
970#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
971#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
972#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
973#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
974#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
975#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
976#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
977#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
978#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
979#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
980#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
981#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
982#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
983#define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
984#define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
985#define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
986#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
987#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
988#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
989#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
990#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
991#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
992
993#define BNX2_MISC_PERR_ENA2 0x000008ac
994#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
995#define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
996#define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
997#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
998#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
999#define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1000#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1001#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1002#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1003
1004#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
1005#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1006#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1007
1008#define BNX2_MISC_VREG_CONTROL 0x000008b4
1009#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1010#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1011
1012#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1013#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1014
1015#define BNX2_MISC_UNUSED0 0x000008bc
1016
1017
1018/*
1019 * nvm_reg definition
1020 * offset: 0x6400
1021 */
1022#define BNX2_NVM_COMMAND 0x00006400
1023#define BNX2_NVM_COMMAND_RST (1L<<0)
1024#define BNX2_NVM_COMMAND_DONE (1L<<3)
1025#define BNX2_NVM_COMMAND_DOIT (1L<<4)
1026#define BNX2_NVM_COMMAND_WR (1L<<5)
1027#define BNX2_NVM_COMMAND_ERASE (1L<<6)
1028#define BNX2_NVM_COMMAND_FIRST (1L<<7)
1029#define BNX2_NVM_COMMAND_LAST (1L<<8)
1030#define BNX2_NVM_COMMAND_WREN (1L<<16)
1031#define BNX2_NVM_COMMAND_WRDI (1L<<17)
1032#define BNX2_NVM_COMMAND_EWSR (1L<<18)
1033#define BNX2_NVM_COMMAND_WRSR (1L<<19)
1034
1035#define BNX2_NVM_STATUS 0x00006404
1036#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1037#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1038#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1039
1040#define BNX2_NVM_WRITE 0x00006408
1041#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1042#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1043#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1044#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1045#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1046#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1047#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1048#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1049
1050#define BNX2_NVM_ADDR 0x0000640c
1051#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1052#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1053#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1054#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1055#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1056#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1057#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1058#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1059
1060#define BNX2_NVM_READ 0x00006410
1061#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1062#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1063#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1064#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1065#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1066#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1067#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1068#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1069
1070#define BNX2_NVM_CFG1 0x00006414
1071#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
1072#define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
1073#define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
1074#define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
1075#define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
1076#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1077#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1078#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1079#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1080#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
1081#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
1082#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1083
1084#define BNX2_NVM_CFG2 0x00006418
1085#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
1086#define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
1087#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
1088
1089#define BNX2_NVM_CFG3 0x0000641c
1090#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1091#define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
1092#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1093#define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
1094
1095#define BNX2_NVM_SW_ARB 0x00006420
1096#define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1097#define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1098#define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1099#define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1100#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1101#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1102#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1103#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1104#define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1105#define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1106#define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1107#define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1108#define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
1109#define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
1110#define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
1111#define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
1112
1113#define BNX2_NVM_ACCESS_ENABLE 0x00006424
1114#define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
1115#define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1116
1117#define BNX2_NVM_WRITE1 0x00006428
1118#define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
1119#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1120#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
1121
1122
1123
1124/*
1125 * dma_reg definition
1126 * offset: 0xc00
1127 */
1128#define BNX2_DMA_COMMAND 0x00000c00
1129#define BNX2_DMA_COMMAND_ENABLE (1L<<0)
1130
1131#define BNX2_DMA_STATUS 0x00000c04
1132#define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1133#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1134#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1135#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1136#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1137#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1138#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1139#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1140#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1141#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1142#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1143
1144#define BNX2_DMA_CONFIG 0x00000c08
1145#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1146#define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1147#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1148#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1149#define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
1150#define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1151#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1152#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1153#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1154#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1155#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1156#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1157#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1158#define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1159#define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1160#define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1161#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1162#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1163#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1164
1165#define BNX2_DMA_BLACKOUT 0x00000c0c
1166#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1167#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1168#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1169
1170#define BNX2_DMA_RCHAN_STAT 0x00000c30
1171#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1172#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1173#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1174#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1175#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1176#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1177#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1178#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1179#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1180#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1181#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1182#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1183#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1184#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1185#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1186#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1187
1188#define BNX2_DMA_WCHAN_STAT 0x00000c34
1189#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1190#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1191#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1192#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1193#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1194#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1195#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1196#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1197#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1198#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1199#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1200#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1201#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1202#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1203#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1204#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1205
1206#define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38
1207#define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1208#define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1209#define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1210#define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1211#define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1212#define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1213#define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1214#define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1215
1216#define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1217#define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1218#define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1219#define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1220#define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1221#define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1222#define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1223#define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1224#define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1225
1226#define BNX2_DMA_RCHAN_STAT_00 0x00000c40
1227#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1228
1229#define BNX2_DMA_RCHAN_STAT_01 0x00000c44
1230#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1231
1232#define BNX2_DMA_RCHAN_STAT_02 0x00000c48
1233#define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1234#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1235#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1236#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1237
1238#define BNX2_DMA_RCHAN_STAT_10 0x00000c4c
1239#define BNX2_DMA_RCHAN_STAT_11 0x00000c50
1240#define BNX2_DMA_RCHAN_STAT_12 0x00000c54
1241#define BNX2_DMA_RCHAN_STAT_20 0x00000c58
1242#define BNX2_DMA_RCHAN_STAT_21 0x00000c5c
1243#define BNX2_DMA_RCHAN_STAT_22 0x00000c60
1244#define BNX2_DMA_RCHAN_STAT_30 0x00000c64
1245#define BNX2_DMA_RCHAN_STAT_31 0x00000c68
1246#define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
1247#define BNX2_DMA_RCHAN_STAT_40 0x00000c70
1248#define BNX2_DMA_RCHAN_STAT_41 0x00000c74
1249#define BNX2_DMA_RCHAN_STAT_42 0x00000c78
1250#define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
1251#define BNX2_DMA_RCHAN_STAT_51 0x00000c80
1252#define BNX2_DMA_RCHAN_STAT_52 0x00000c84
1253#define BNX2_DMA_RCHAN_STAT_60 0x00000c88
1254#define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
1255#define BNX2_DMA_RCHAN_STAT_62 0x00000c90
1256#define BNX2_DMA_RCHAN_STAT_70 0x00000c94
1257#define BNX2_DMA_RCHAN_STAT_71 0x00000c98
1258#define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
1259#define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
1260#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1261
1262#define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
1263#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1264
1265#define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
1266#define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
1267#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
1268#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
1269#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1270
1271#define BNX2_DMA_WCHAN_STAT_10 0x00000cac
1272#define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
1273#define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
1274#define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
1275#define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
1276#define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
1277#define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
1278#define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
1279#define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
1280#define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
1281#define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
1282#define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
1283#define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
1284#define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
1285#define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
1286#define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
1287#define BNX2_DMA_WCHAN_STAT_61 0x00000cec
1288#define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
1289#define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
1290#define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
1291#define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
1292#define BNX2_DMA_ARB_STAT_00 0x00000d00
1293#define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
1294#define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
1295#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
1296
1297#define BNX2_DMA_ARB_STAT_01 0x00000d04
1298#define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
1299#define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
1300#define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
1301#define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
1302#define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
1303#define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
1304#define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
1305#define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
1306
1307#define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
1308#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
1309#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
1310#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
1311#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
1312#define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
1313
1314#define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
1315#define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
1316#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
1317#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
1318#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
1319#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
1320#define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
1321
1322#define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
1323#define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
1324#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
1325#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
1326#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
1327#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
1328#define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
1329
1330#define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
1331
1332
1333/*
1334 * context_reg definition
1335 * offset: 0x1000
1336 */
1337#define BNX2_CTX_COMMAND 0x00001000
1338#define BNX2_CTX_COMMAND_ENABLED (1L<<0)
1339
1340#define BNX2_CTX_STATUS 0x00001004
1341#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
1342#define BNX2_CTX_STATUS_READ_STAT (1L<<16)
1343#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
1344#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
1345#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
1346
1347#define BNX2_CTX_VIRT_ADDR 0x00001008
1348#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
1349
1350#define BNX2_CTX_PAGE_TBL 0x0000100c
1351#define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
1352
1353#define BNX2_CTX_DATA_ADR 0x00001010
1354#define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
1355
1356#define BNX2_CTX_DATA 0x00001014
1357#define BNX2_CTX_LOCK 0x00001018
1358#define BNX2_CTX_LOCK_TYPE (0x7L<<0)
1359#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
1360#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
1361#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
1362#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
1363#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
1364#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
1365#define BNX2_CTX_LOCK_GRANTED (1L<<26)
1366#define BNX2_CTX_LOCK_MODE (0x7L<<27)
1367#define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
1368#define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
1369#define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
1370#define BNX2_CTX_LOCK_STATUS (1L<<30)
1371#define BNX2_CTX_LOCK_REQ (1L<<31)
1372
1373#define BNX2_CTX_ACCESS_STATUS 0x00001040
1374#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
1375#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
1376#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
1377#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
1378#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
1379
1380#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
1381#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
1382#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
1383
1384#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
1385#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
1386#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
1387#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
1388
1389#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
1390#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
1391#define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
1392#define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
1393#define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
1394#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
1395#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
1396#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
1397
1398
1399/*
1400 * emac_reg definition
1401 * offset: 0x1400
1402 */
1403#define BNX2_EMAC_MODE 0x00001400
1404#define BNX2_EMAC_MODE_RESET (1L<<0)
1405#define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
1406#define BNX2_EMAC_MODE_PORT (0x3L<<2)
1407#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
1408#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
1409#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
Michael Chan5b0c76a2005-11-04 08:45:49 -08001410#define BNX2_EMAC_MODE_PORT_MII_10 (3L<<2)
Michael Chanb6016b72005-05-26 13:03:09 -07001411#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
Michael Chan5b0c76a2005-11-04 08:45:49 -08001412#define BNX2_EMAC_MODE_25G (1L<<5)
Michael Chanb6016b72005-05-26 13:03:09 -07001413#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
1414#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
1415#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
1416#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
1417#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
1418#define BNX2_EMAC_MODE_MPKT (1L<<18)
1419#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
1420#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
1421
1422#define BNX2_EMAC_STATUS 0x00001404
1423#define BNX2_EMAC_STATUS_LINK (1L<<11)
1424#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
1425#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
1426#define BNX2_EMAC_STATUS_MI_INT (1L<<23)
1427#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
1428#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
1429
1430#define BNX2_EMAC_ATTENTION_ENA 0x00001408
1431#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
1432#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
1433#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
1434#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
1435
1436#define BNX2_EMAC_LED 0x0000140c
1437#define BNX2_EMAC_LED_OVERRIDE (1L<<0)
1438#define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
1439#define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
1440#define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
1441#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
1442#define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
1443#define BNX2_EMAC_LED_TRAFFIC (1L<<6)
1444#define BNX2_EMAC_LED_1000MB (1L<<7)
1445#define BNX2_EMAC_LED_100MB (1L<<8)
1446#define BNX2_EMAC_LED_10MB (1L<<9)
1447#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
1448#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
1449#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
1450
1451#define BNX2_EMAC_MAC_MATCH0 0x00001410
1452#define BNX2_EMAC_MAC_MATCH1 0x00001414
1453#define BNX2_EMAC_MAC_MATCH2 0x00001418
1454#define BNX2_EMAC_MAC_MATCH3 0x0000141c
1455#define BNX2_EMAC_MAC_MATCH4 0x00001420
1456#define BNX2_EMAC_MAC_MATCH5 0x00001424
1457#define BNX2_EMAC_MAC_MATCH6 0x00001428
1458#define BNX2_EMAC_MAC_MATCH7 0x0000142c
1459#define BNX2_EMAC_MAC_MATCH8 0x00001430
1460#define BNX2_EMAC_MAC_MATCH9 0x00001434
1461#define BNX2_EMAC_MAC_MATCH10 0x00001438
1462#define BNX2_EMAC_MAC_MATCH11 0x0000143c
1463#define BNX2_EMAC_MAC_MATCH12 0x00001440
1464#define BNX2_EMAC_MAC_MATCH13 0x00001444
1465#define BNX2_EMAC_MAC_MATCH14 0x00001448
1466#define BNX2_EMAC_MAC_MATCH15 0x0000144c
1467#define BNX2_EMAC_MAC_MATCH16 0x00001450
1468#define BNX2_EMAC_MAC_MATCH17 0x00001454
1469#define BNX2_EMAC_MAC_MATCH18 0x00001458
1470#define BNX2_EMAC_MAC_MATCH19 0x0000145c
1471#define BNX2_EMAC_MAC_MATCH20 0x00001460
1472#define BNX2_EMAC_MAC_MATCH21 0x00001464
1473#define BNX2_EMAC_MAC_MATCH22 0x00001468
1474#define BNX2_EMAC_MAC_MATCH23 0x0000146c
1475#define BNX2_EMAC_MAC_MATCH24 0x00001470
1476#define BNX2_EMAC_MAC_MATCH25 0x00001474
1477#define BNX2_EMAC_MAC_MATCH26 0x00001478
1478#define BNX2_EMAC_MAC_MATCH27 0x0000147c
1479#define BNX2_EMAC_MAC_MATCH28 0x00001480
1480#define BNX2_EMAC_MAC_MATCH29 0x00001484
1481#define BNX2_EMAC_MAC_MATCH30 0x00001488
1482#define BNX2_EMAC_MAC_MATCH31 0x0000148c
1483#define BNX2_EMAC_BACKOFF_SEED 0x00001498
1484#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
1485
1486#define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
1487#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
1488#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
1489
1490#define BNX2_EMAC_SERDES_CNTL 0x000014a4
1491#define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
1492#define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
1493#define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
1494#define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
1495#define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
1496#define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
1497#define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
1498#define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
1499#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
1500#define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
1501#define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
1502#define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
1503#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
1504#define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
1505#define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
1506#define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
1507
1508#define BNX2_EMAC_SERDES_STATUS 0x000014a8
1509#define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
1510#define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
1511
1512#define BNX2_EMAC_MDIO_COMM 0x000014ac
1513#define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
1514#define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
1515#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
1516#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
1517#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
1518#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
1519#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
1520#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
1521#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
1522#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
1523#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
1524
1525#define BNX2_EMAC_MDIO_STATUS 0x000014b0
1526#define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
1527#define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
1528
1529#define BNX2_EMAC_MDIO_MODE 0x000014b4
1530#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
1531#define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
1532#define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
1533#define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
1534#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
1535#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
1536#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
1537#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
1538
1539#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
1540#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
1541
1542#define BNX2_EMAC_TX_MODE 0x000014bc
1543#define BNX2_EMAC_TX_MODE_RESET (1L<<0)
1544#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1545#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
1546#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
1547#define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
1548#define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
1549
1550#define BNX2_EMAC_TX_STATUS 0x000014c0
1551#define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
1552#define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
1553#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
1554#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
1555#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
1556
1557#define BNX2_EMAC_TX_LENGTHS 0x000014c4
1558#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
1559#define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
1560#define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
1561
1562#define BNX2_EMAC_RX_MODE 0x000014c8
1563#define BNX2_EMAC_RX_MODE_RESET (1L<<0)
1564#define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
1565#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
1566#define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
1567#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
1568#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
1569#define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
1570#define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
1571#define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
1572#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
1573#define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
1574#define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
1575
1576#define BNX2_EMAC_RX_STATUS 0x000014cc
1577#define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
1578#define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
1579#define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
1580
1581#define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
1582#define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
1583#define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
1584#define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
1585#define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
1586#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
1587#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
1588#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
1589#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
1590#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
1591#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
1592#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
1593#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
1594#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
1595#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
1596#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
1597#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
1598#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
1599#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
1600#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
1601#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
1602#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
1603#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
1604#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
1605#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
1606#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
1607#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
1608#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
1609#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
1610#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
1611#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
1612#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
1613#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
1614#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
1615#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
1616#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
1617#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
1618#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
1619#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
1620#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
1621#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
1622#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
1623
1624#define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
1625#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
1626#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
1627#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
1628#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
1629#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
1630#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
1631#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
1632#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
1633#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
1634#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
1635#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
1636#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
1637#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
1638#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
1639#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
1640#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
1641#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
1642#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
1643#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
1644#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
1645#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
1646#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
1647#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
1648#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
1649#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
1650#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
1651#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
1652
1653#define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
1654#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
1655#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
1656
1657#define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
1658#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
1659#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
1660#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
1661#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
1662#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
1663#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
1664#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
1665#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
1666#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
1667#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
1668#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
1669#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
1670#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
1671#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
1672#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
1673#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
1674#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
1675#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
1676#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
1677#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
1678#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
1679#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
1680#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
1681#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
1682#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
1683#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
1684#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
1685#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
1686#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
1687#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
1688#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
1689#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
1690#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
1691#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
1692#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
1693#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
1694#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
1695#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
1696#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
1697#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
1698#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
1699#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
1700#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
1701#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
1702#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
1703#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
1704#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
1705#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
1706#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
1707
1708#define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
1709#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
1710#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
1711#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
1712#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
1713#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
1714#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
1715#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
1716#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
1717#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
1718#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
1719#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
1720#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
1721#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
1722#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
1723#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
1724#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
1725#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
1726#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
1727#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
1728#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
1729#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
1730#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
1731#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
1732#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
1733#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
1734#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
1735
1736#define BNX2_EMAC_RX_STAT_AC0 0x00001580
1737#define BNX2_EMAC_RX_STAT_AC1 0x00001584
1738#define BNX2_EMAC_RX_STAT_AC2 0x00001588
1739#define BNX2_EMAC_RX_STAT_AC3 0x0000158c
1740#define BNX2_EMAC_RX_STAT_AC4 0x00001590
1741#define BNX2_EMAC_RX_STAT_AC5 0x00001594
1742#define BNX2_EMAC_RX_STAT_AC6 0x00001598
1743#define BNX2_EMAC_RX_STAT_AC7 0x0000159c
1744#define BNX2_EMAC_RX_STAT_AC8 0x000015a0
1745#define BNX2_EMAC_RX_STAT_AC9 0x000015a4
1746#define BNX2_EMAC_RX_STAT_AC10 0x000015a8
1747#define BNX2_EMAC_RX_STAT_AC11 0x000015ac
1748#define BNX2_EMAC_RX_STAT_AC12 0x000015b0
1749#define BNX2_EMAC_RX_STAT_AC13 0x000015b4
1750#define BNX2_EMAC_RX_STAT_AC14 0x000015b8
1751#define BNX2_EMAC_RX_STAT_AC15 0x000015bc
1752#define BNX2_EMAC_RX_STAT_AC16 0x000015c0
1753#define BNX2_EMAC_RX_STAT_AC17 0x000015c4
1754#define BNX2_EMAC_RX_STAT_AC18 0x000015c8
1755#define BNX2_EMAC_RX_STAT_AC19 0x000015cc
1756#define BNX2_EMAC_RX_STAT_AC20 0x000015d0
1757#define BNX2_EMAC_RX_STAT_AC21 0x000015d4
1758#define BNX2_EMAC_RX_STAT_AC22 0x000015d8
1759#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
1760#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
1761#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
1762#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
1763#define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
1764#define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
1765#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
1766#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
1767#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
1768#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
1769#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
1770#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
1771#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
1772#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
1773#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
1774#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
1775#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
1776#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
1777#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
1778#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
1779#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
1780#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
1781#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
1782#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
1783#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
1784#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
1785#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
1786#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
1787#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
1788#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
1789#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
1790#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
1791#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
1792#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
1793#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
1794#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
1795#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
1796#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
1797#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
1798#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
1799#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
1800#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
1801#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
1802#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
1803
1804#define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
1805#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
1806#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
1807#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
1808#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
1809
1810#define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
1811#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
1812#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
1813#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
1814#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
1815#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
1816#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
1817#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
1818#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
1819#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
1820#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
1821#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
1822#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
1823#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
1824#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
1825#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
1826#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
1827#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
1828#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
1829#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
1830#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
1831#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
1832#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
1833#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
1834#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
1835#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
1836#define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
1837#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
1838#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
1839
1840#define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
1841#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
1842#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
1843#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
1844#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
1845#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
1846#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
1847#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
1848#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
1849#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
1850#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
1851#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
1852#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
1853#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
1854#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
1855#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
1856#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
1857#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
1858#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
1859#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
1860#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
1861#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
1862#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
1863#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
1864#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
1865#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
1866#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
1867#define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
1868
1869#define BNX2_EMAC_TX_STAT_AC0 0x00001680
1870#define BNX2_EMAC_TX_STAT_AC1 0x00001684
1871#define BNX2_EMAC_TX_STAT_AC2 0x00001688
1872#define BNX2_EMAC_TX_STAT_AC3 0x0000168c
1873#define BNX2_EMAC_TX_STAT_AC4 0x00001690
1874#define BNX2_EMAC_TX_STAT_AC5 0x00001694
1875#define BNX2_EMAC_TX_STAT_AC6 0x00001698
1876#define BNX2_EMAC_TX_STAT_AC7 0x0000169c
1877#define BNX2_EMAC_TX_STAT_AC8 0x000016a0
1878#define BNX2_EMAC_TX_STAT_AC9 0x000016a4
1879#define BNX2_EMAC_TX_STAT_AC10 0x000016a8
1880#define BNX2_EMAC_TX_STAT_AC11 0x000016ac
1881#define BNX2_EMAC_TX_STAT_AC12 0x000016b0
1882#define BNX2_EMAC_TX_STAT_AC13 0x000016b4
1883#define BNX2_EMAC_TX_STAT_AC14 0x000016b8
1884#define BNX2_EMAC_TX_STAT_AC15 0x000016bc
1885#define BNX2_EMAC_TX_STAT_AC16 0x000016c0
1886#define BNX2_EMAC_TX_STAT_AC17 0x000016c4
1887#define BNX2_EMAC_TX_STAT_AC18 0x000016c8
1888#define BNX2_EMAC_TX_STAT_AC19 0x000016cc
1889#define BNX2_EMAC_TX_STAT_AC20 0x000016d0
1890#define BNX2_EMAC_TX_STAT_AC21 0x000016d4
1891#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
1892
1893
1894/*
1895 * rpm_reg definition
1896 * offset: 0x1800
1897 */
1898#define BNX2_RPM_COMMAND 0x00001800
1899#define BNX2_RPM_COMMAND_ENABLED (1L<<0)
1900#define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
1901
1902#define BNX2_RPM_STATUS 0x00001804
1903#define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
1904#define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
1905
1906#define BNX2_RPM_CONFIG 0x00001808
1907#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
1908#define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
1909#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
1910#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
1911#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
1912#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
1913
1914#define BNX2_RPM_VLAN_MATCH0 0x00001810
1915#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
1916
1917#define BNX2_RPM_VLAN_MATCH1 0x00001814
1918#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
1919
1920#define BNX2_RPM_VLAN_MATCH2 0x00001818
1921#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
1922
1923#define BNX2_RPM_VLAN_MATCH3 0x0000181c
1924#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
1925
1926#define BNX2_RPM_SORT_USER0 0x00001820
1927#define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
1928#define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
1929#define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
1930#define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
1931#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
1932#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
1933#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
1934#define BNX2_RPM_SORT_USER0_ENA (1L<<31)
1935
1936#define BNX2_RPM_SORT_USER1 0x00001824
1937#define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
1938#define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
1939#define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
1940#define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
1941#define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
1942#define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
1943#define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
1944#define BNX2_RPM_SORT_USER1_ENA (1L<<31)
1945
1946#define BNX2_RPM_SORT_USER2 0x00001828
1947#define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
1948#define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
1949#define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
1950#define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
1951#define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
1952#define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
1953#define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
1954#define BNX2_RPM_SORT_USER2_ENA (1L<<31)
1955
1956#define BNX2_RPM_SORT_USER3 0x0000182c
1957#define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
1958#define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
1959#define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
1960#define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
1961#define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
1962#define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
1963#define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
1964#define BNX2_RPM_SORT_USER3_ENA (1L<<31)
1965
1966#define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
1967#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
1968#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
1969#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
1970#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
1971#define BNX2_RPM_STAT_AC0 0x00001880
1972#define BNX2_RPM_STAT_AC1 0x00001884
1973#define BNX2_RPM_STAT_AC2 0x00001888
1974#define BNX2_RPM_STAT_AC3 0x0000188c
1975#define BNX2_RPM_STAT_AC4 0x00001890
1976#define BNX2_RPM_RC_CNTL_0 0x00001900
1977#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
1978#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
1979#define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
1980#define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
1981#define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
1982#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
1983#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
1984#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
1985#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
1986#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
1987#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
1988#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
1989#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
1990#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
1991#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
1992#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
1993#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
1994#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
1995#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
1996#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
1997#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
1998#define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
1999#define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
2000#define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
2001
2002#define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
2003#define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2004#define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2005
2006#define BNX2_RPM_RC_CNTL_1 0x00001908
2007#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2008#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
2009
2010#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
2011#define BNX2_RPM_RC_CNTL_2 0x00001910
2012#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2013#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
2014
2015#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
2016#define BNX2_RPM_RC_CNTL_3 0x00001918
2017#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2018#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
2019
2020#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
2021#define BNX2_RPM_RC_CNTL_4 0x00001920
2022#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2023#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
2024
2025#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
2026#define BNX2_RPM_RC_CNTL_5 0x00001928
2027#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2028#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
2029
2030#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
2031#define BNX2_RPM_RC_CNTL_6 0x00001930
2032#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2033#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
2034
2035#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
2036#define BNX2_RPM_RC_CNTL_7 0x00001938
2037#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2038#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
2039
2040#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
2041#define BNX2_RPM_RC_CNTL_8 0x00001940
2042#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2043#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
2044
2045#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
2046#define BNX2_RPM_RC_CNTL_9 0x00001948
2047#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2048#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
2049
2050#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
2051#define BNX2_RPM_RC_CNTL_10 0x00001950
2052#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2053#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
2054
2055#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
2056#define BNX2_RPM_RC_CNTL_11 0x00001958
2057#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2058#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
2059
2060#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
2061#define BNX2_RPM_RC_CNTL_12 0x00001960
2062#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2063#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
2064
2065#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
2066#define BNX2_RPM_RC_CNTL_13 0x00001968
2067#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2068#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
2069
2070#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
2071#define BNX2_RPM_RC_CNTL_14 0x00001970
2072#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2073#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
2074
2075#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
2076#define BNX2_RPM_RC_CNTL_15 0x00001978
2077#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2078#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
2079
2080#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
2081#define BNX2_RPM_RC_CONFIG 0x00001980
2082#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2083#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2084
2085#define BNX2_RPM_DEBUG0 0x00001984
2086#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2087#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2088#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2089#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2090#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2091#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2092#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2093#define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
2094#define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
2095#define BNX2_RPM_DEBUG0_DONE (1L<<24)
2096#define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2097#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2098#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2099#define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2100#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2101
2102#define BNX2_RPM_DEBUG1 0x00001988
2103#define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2104#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2105#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2106#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2107#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2108#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2109#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2110#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2111#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2112#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2113#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2114#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2115#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2116#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2117#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2118#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2119#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2120#define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2121#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2122#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2123#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2124#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2125
2126#define BNX2_RPM_DEBUG2 0x0000198c
2127#define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2128#define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2129#define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2130#define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2131#define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2132#define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2133#define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2134#define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
2135#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2136#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2137
2138#define BNX2_RPM_DEBUG3 0x00001990
2139#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2140#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2141#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2142#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2143#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2144#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2145#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2146#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2147#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2148#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2149#define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2150#define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
2151#define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2152#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2153#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2154#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2155#define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2156#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2157#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2158#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2159#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2160#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2161#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2162#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2163#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2164#define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2165#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2166#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2167#define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2168#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2169#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2170#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2171
2172#define BNX2_RPM_DEBUG4 0x00001994
2173#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2174#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2175#define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2176#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2177
2178#define BNX2_RPM_DEBUG5 0x00001998
2179#define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2180#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2181#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2182#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2183#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2184#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2185#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2186#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2187#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2188#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2189#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2190#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2191#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2192#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2193#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2194#define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2195
2196#define BNX2_RPM_DEBUG6 0x0000199c
2197#define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2198#define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
2199
2200#define BNX2_RPM_DEBUG7 0x000019a0
2201#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2202
2203#define BNX2_RPM_DEBUG8 0x000019a4
2204#define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2205#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2206#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2207#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2208#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2209#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2210#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2211#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
2212#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
2213#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
2214#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
2215#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
2216#define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
2217#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
2218#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
2219#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
2220#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
2221#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
2222#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
2223#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
2224#define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
2225#define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
2226#define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
2227#define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
2228#define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
2229#define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
2230
2231#define BNX2_RPM_DEBUG9 0x000019a8
2232#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
2233#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
2234#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
2235#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
2236#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2237#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2238#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
2239
2240#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
2241#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
2242#define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
2243#define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
2244#define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
2245#define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
2246#define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
2247#define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
2248#define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
2249#define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
2250#define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
2251#define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
2252#define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
2253#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
2254#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
2255#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
2256
2257
2258/*
2259 * rbuf_reg definition
2260 * offset: 0x200000
2261 */
2262#define BNX2_RBUF_COMMAND 0x00200000
2263#define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
2264#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
2265#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
2266#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
2267#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
2268
2269#define BNX2_RBUF_STATUS1 0x00200004
2270#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2271
2272#define BNX2_RBUF_STATUS2 0x00200008
2273#define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
2274#define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
2275
2276#define BNX2_RBUF_CONFIG 0x0020000c
2277#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
2278#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
2279
2280#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
2281#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
2282
2283#define BNX2_RBUF_FW_BUF_FREE 0x00200014
2284#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2285#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2286#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
2287
2288#define BNX2_RBUF_FW_BUF_SEL 0x00200018
2289#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2290#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2291#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
2292
2293#define BNX2_RBUF_CONFIG2 0x0020001c
2294#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
2295#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
2296
2297#define BNX2_RBUF_CONFIG3 0x00200020
2298#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
2299#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
2300
2301#define BNX2_RBUF_PKT_DATA 0x00208000
2302#define BNX2_RBUF_CLIST_DATA 0x00210000
2303#define BNX2_RBUF_BUF_DATA 0x00220000
2304
2305
2306/*
2307 * rv2p_reg definition
2308 * offset: 0x2800
2309 */
2310#define BNX2_RV2P_COMMAND 0x00002800
2311#define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
2312#define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
2313#define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
2314#define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
2315#define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
2316#define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
2317#define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
2318#define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
2319#define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
2320#define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
2321#define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
2322#define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
2323
2324#define BNX2_RV2P_STATUS 0x00002804
2325#define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
2326#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
2327#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
2328#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
2329#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
2330#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
2331#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
2332
2333#define BNX2_RV2P_CONFIG 0x00002808
2334#define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
2335#define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
2336#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
2337#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
2338#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
2339#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
2340#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
2341#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
2342#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
2343#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
2344#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
2345#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
2346#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
2347#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
2348#define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
2349#define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
2350#define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
2351#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
2352#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
2353#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
2354#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
2355#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
2356#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
2357#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
2358#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
2359#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
2360#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
2361#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
2362
2363#define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
2364#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
2365
2366#define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
2367#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
2368
2369#define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
2370#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
2371
2372#define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
2373#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
2374
2375#define BNX2_RV2P_INSTR_HIGH 0x00002830
2376#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
2377
2378#define BNX2_RV2P_INSTR_LOW 0x00002834
2379#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
2380#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
2381#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
2382
2383#define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
2384#define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
2385#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
2386
2387#define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
2388#define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
2389#define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
2390#define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
2391#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2392#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2393#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2394#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2395#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2396#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2397
2398#define BNX2_RV2P_PFTQ_DATA 0x00002b40
2399#define BNX2_RV2P_PFTQ_CMD 0x00002b78
2400#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
2401#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
2402#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
2403#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
2404#define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
2405#define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
2406#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
2407#define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
2408#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
2409#define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
2410#define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
2411
2412#define BNX2_RV2P_PFTQ_CTL 0x00002b7c
2413#define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
2414#define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
2415#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
2416#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2417#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2418
2419#define BNX2_RV2P_TFTQ_DATA 0x00002b80
2420#define BNX2_RV2P_TFTQ_CMD 0x00002bb8
2421#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
2422#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
2423#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
2424#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
2425#define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
2426#define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
2427#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
2428#define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
2429#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
2430#define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
2431#define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
2432
2433#define BNX2_RV2P_TFTQ_CTL 0x00002bbc
2434#define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
2435#define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
2436#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
2437#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2438#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2439
2440#define BNX2_RV2P_MFTQ_DATA 0x00002bc0
2441#define BNX2_RV2P_MFTQ_CMD 0x00002bf8
2442#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
2443#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
2444#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
2445#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
2446#define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
2447#define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
2448#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
2449#define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
2450#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
2451#define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
2452#define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
2453
2454#define BNX2_RV2P_MFTQ_CTL 0x00002bfc
2455#define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
2456#define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
2457#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
2458#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2459#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2460
2461
2462
2463/*
2464 * mq_reg definition
2465 * offset: 0x3c00
2466 */
2467#define BNX2_MQ_COMMAND 0x00003c00
2468#define BNX2_MQ_COMMAND_ENABLED (1L<<0)
2469#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
2470#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
2471#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
2472
2473#define BNX2_MQ_STATUS 0x00003c04
2474#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
2475#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
2476#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
2477
2478#define BNX2_MQ_CONFIG 0x00003c08
2479#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
2480#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
2481#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
2482#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
2483#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
2484#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
2485#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
2486#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
2487#define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
2488#define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
2489
2490#define BNX2_MQ_ENQUEUE1 0x00003c0c
2491#define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
2492#define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
2493#define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
2494#define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
2495
2496#define BNX2_MQ_ENQUEUE2 0x00003c10
2497#define BNX2_MQ_BAD_WR_ADDR 0x00003c14
2498#define BNX2_MQ_BAD_RD_ADDR 0x00003c18
2499#define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
2500#define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
2501
2502#define BNX2_MQ_KNL_WIND_END 0x00003c20
2503#define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
2504
2505#define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
2506#define BNX2_MQ_KNL_TX_MASK1 0x00003c28
2507#define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
2508#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
2509#define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
2510#define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
2511#define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
2512#define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
2513#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
2514#define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
2515#define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
2516#define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
2517#define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
2518#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
2519#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
2520#define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
2521#define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
2522#define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
2523#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
2524#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
2525#define BNX2_MQ_MEM_WR_ADDR 0x00003c74
2526#define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
2527
2528#define BNX2_MQ_MEM_WR_DATA0 0x00003c78
2529#define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
2530
2531#define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
2532#define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
2533
2534#define BNX2_MQ_MEM_WR_DATA2 0x00003c80
2535#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
2536
2537#define BNX2_MQ_MEM_RD_ADDR 0x00003c84
2538#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
2539
2540#define BNX2_MQ_MEM_RD_DATA0 0x00003c88
2541#define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
2542
2543#define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
2544#define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
2545
2546#define BNX2_MQ_MEM_RD_DATA2 0x00003c90
2547#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
2548
2549
2550
2551/*
2552 * tbdr_reg definition
2553 * offset: 0x5000
2554 */
2555#define BNX2_TBDR_COMMAND 0x00005000
2556#define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
2557#define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
2558#define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
2559
2560#define BNX2_TBDR_STATUS 0x00005004
2561#define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
2562#define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
2563#define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
2564#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
2565#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
2566#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
2567#define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
2568
2569#define BNX2_TBDR_CONFIG 0x00005008
2570#define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
2571#define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
2572#define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
2573#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
2574#define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
2575#define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
2576#define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
2577#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
2578#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
2579#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
2580#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
2581#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
2582#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
2583#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
2584#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
2585#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
2586#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
2587#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
2588
2589#define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
2590#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2591#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2592#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2593#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2594#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2595#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2596
2597#define BNX2_TBDR_FTQ_DATA 0x000053c0
2598#define BNX2_TBDR_FTQ_CMD 0x000053f8
2599#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
2600#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
2601#define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
2602#define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
2603#define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
2604#define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
2605#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
2606#define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
2607#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
2608#define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
2609#define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
2610
2611#define BNX2_TBDR_FTQ_CTL 0x000053fc
2612#define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
2613#define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
2614#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2615#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2616#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2617
2618
2619
2620/*
2621 * tdma_reg definition
2622 * offset: 0x5c00
2623 */
2624#define BNX2_TDMA_COMMAND 0x00005c00
2625#define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
2626#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
2627#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
2628
2629#define BNX2_TDMA_STATUS 0x00005c04
2630#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
2631#define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
2632#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
2633#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
2634#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
2635#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
2636
2637#define BNX2_TDMA_CONFIG 0x00005c08
2638#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
2639#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
2640#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
2641#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
2642#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
2643#define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
2644#define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
2645#define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
2646#define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
2647#define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
2648#define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
2649#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
2650#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
2651#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
2652#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
2653
2654#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
2655#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
2656
2657#define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
2658#define BNX2_TDMA_DBG_TRIGGER 0x00005c14
2659#define BNX2_TDMA_DMAD_FSM 0x00005c80
2660#define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
2661#define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
2662#define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
2663#define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
2664#define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
2665#define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
2666#define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
2667
2668#define BNX2_TDMA_DMAD_STATUS 0x00005c84
2669#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
2670#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
2671#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
2672#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
2673
2674#define BNX2_TDMA_DR_INTF_FSM 0x00005c88
2675#define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
2676#define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
2677#define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
2678#define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
2679#define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
2680
2681#define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
2682#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
2683#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
2684#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
2685#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
2686#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
2687
2688#define BNX2_TDMA_FTQ_DATA 0x00005fc0
2689#define BNX2_TDMA_FTQ_CMD 0x00005ff8
2690#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
2691#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
2692#define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
2693#define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
2694#define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
2695#define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
2696#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
2697#define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
2698#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
2699#define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
2700#define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
2701
2702#define BNX2_TDMA_FTQ_CTL 0x00005ffc
2703#define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
2704#define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
2705#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2706#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2707#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2708
2709
2710
2711/*
2712 * hc_reg definition
2713 * offset: 0x6800
2714 */
2715#define BNX2_HC_COMMAND 0x00006800
2716#define BNX2_HC_COMMAND_ENABLE (1L<<0)
2717#define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
2718#define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
2719#define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
2720#define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
2721#define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
2722#define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
2723#define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
2724#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
2725#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
2726#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
2727
2728#define BNX2_HC_STATUS 0x00006804
2729#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
2730#define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
2731#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
2732#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
2733#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
2734#define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
2735#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
2736#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
2737#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
2738#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
2739
2740#define BNX2_HC_CONFIG 0x00006808
2741#define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
2742#define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
2743#define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
2744#define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
2745#define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
2746#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
2747#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
2748#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
2749
2750#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
2751#define BNX2_HC_STATUS_ADDR_L 0x00006810
2752#define BNX2_HC_STATUS_ADDR_H 0x00006814
2753#define BNX2_HC_STATISTICS_ADDR_L 0x00006818
2754#define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
2755#define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
2756#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2757#define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
2758
2759#define BNX2_HC_COMP_PROD_TRIP 0x00006824
2760#define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
2761#define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
2762
2763#define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
2764#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2765#define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
2766
2767#define BNX2_HC_RX_TICKS 0x0000682c
2768#define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
2769#define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
2770
2771#define BNX2_HC_TX_TICKS 0x00006830
2772#define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
2773#define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
2774
2775#define BNX2_HC_COM_TICKS 0x00006834
2776#define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
2777#define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
2778
2779#define BNX2_HC_CMD_TICKS 0x00006838
2780#define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
2781#define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
2782
2783#define BNX2_HC_PERIODIC_TICKS 0x0000683c
2784#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
2785
2786#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
2787#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
2788
2789#define BNX2_HC_STATS_TICKS 0x00006844
2790#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
2791
2792#define BNX2_HC_STAT_MEM_DATA 0x0000684c
2793#define BNX2_HC_STAT_GEN_SEL_0 0x00006850
2794#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
2795#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
2796#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
2797#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
2798#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
2799#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
2800#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
2801#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
2802#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
2803#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
2804#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
2805#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
2806#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
2807#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
2808#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
2809#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
2810#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
2811#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
2812#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
2813#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
2814#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
2815#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
2816#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
2817#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
2818#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
2819#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
2820#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
2821#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
2822#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
2823#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
2824#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
2825#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
2826#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
2827#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
2828#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
2829#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
2830#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
2831#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
2832#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
2833#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
2834#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
2835#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
2836#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
2837#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
2838#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
2839#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
2840#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
2841#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
2842#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
2843#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
2844#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
2845#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
2846#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
2847#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
2848#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
2849#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
2850#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
2851#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
2852#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
2853#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
2854#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
2855#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
2856#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
2857#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
2858#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
2859#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
2860#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
2861#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
2862#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
2863#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
2864#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
2865#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
2866#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
2867#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
2868#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
2869#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
2870#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
2871#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
2872#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
2873#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
2874#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
2875#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
2876#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
2877#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
2878#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
2879#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
2880#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
2881#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
2882#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
2883#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
2884#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
2885#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
2886#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
2887#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
2888#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
2889#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
2890#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
2891#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
2892#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
2893#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
2894#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
2895#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
2896#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
2897#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
2898#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
2899#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
2900#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
2901#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
2902#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
2903#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
2904#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
2905#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
2906#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
2907#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
2908#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
2909#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
2910#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
2911#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
2912#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
2913#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
2914#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
2915#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
2916#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
2917#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
2918#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
2919#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
2920
2921#define BNX2_HC_STAT_GEN_SEL_1 0x00006854
2922#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
2923#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
2924#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
2925#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
2926
2927#define BNX2_HC_STAT_GEN_SEL_2 0x00006858
2928#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
2929#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
2930#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
2931#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
2932
2933#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
2934#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
2935#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
2936#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
2937#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
2938
2939#define BNX2_HC_STAT_GEN_STAT0 0x00006888
2940#define BNX2_HC_STAT_GEN_STAT1 0x0000688c
2941#define BNX2_HC_STAT_GEN_STAT2 0x00006890
2942#define BNX2_HC_STAT_GEN_STAT3 0x00006894
2943#define BNX2_HC_STAT_GEN_STAT4 0x00006898
2944#define BNX2_HC_STAT_GEN_STAT5 0x0000689c
2945#define BNX2_HC_STAT_GEN_STAT6 0x000068a0
2946#define BNX2_HC_STAT_GEN_STAT7 0x000068a4
2947#define BNX2_HC_STAT_GEN_STAT8 0x000068a8
2948#define BNX2_HC_STAT_GEN_STAT9 0x000068ac
2949#define BNX2_HC_STAT_GEN_STAT10 0x000068b0
2950#define BNX2_HC_STAT_GEN_STAT11 0x000068b4
2951#define BNX2_HC_STAT_GEN_STAT12 0x000068b8
2952#define BNX2_HC_STAT_GEN_STAT13 0x000068bc
2953#define BNX2_HC_STAT_GEN_STAT14 0x000068c0
2954#define BNX2_HC_STAT_GEN_STAT15 0x000068c4
2955#define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
2956#define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
2957#define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
2958#define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
2959#define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
2960#define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
2961#define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
2962#define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
2963#define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
2964#define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
2965#define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
2966#define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
2967#define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
2968#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
2969#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
2970#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
2971#define BNX2_HC_VIS 0x00006908
2972#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
2973#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
2974#define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
2975#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
2976#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
2977#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
2978#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
2979#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
2980#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
2981#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
2982#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
2983#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
2984#define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
2985#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
2986#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
2987#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
2988#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
2989#define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
2990#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
2991#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
2992#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
2993#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
2994#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
2995#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
2996#define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
2997#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
2998#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
2999#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3000#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3001
3002#define BNX2_HC_VIS_1 0x0000690c
3003#define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3004#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3005#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3006#define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3007#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3008#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3009#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3010#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3011#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3012#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3013#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3014#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3015#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3016#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3017#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3018#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3019#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3020#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3021#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3022#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3023#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3024#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3025#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3026#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3027#define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
3028#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3029#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3030#define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3031#define BNX2_HC_VIS_1_INT_B (1L<<27)
3032
3033#define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
3034#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3035#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3036#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3037#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3038#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3039#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3040
3041
3042
3043/*
3044 * txp_reg definition
3045 * offset: 0x40000
3046 */
3047#define BNX2_TXP_CPU_MODE 0x00045000
3048#define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3049#define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
3050#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3051#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3052#define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3053#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3054#define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3055#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3056#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3057#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3058#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3059
3060#define BNX2_TXP_CPU_STATE 0x00045004
3061#define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3062#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3063#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3064#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3065#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3066#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3067#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3068#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3069#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3070#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3071#define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3072#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3073#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3074#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3075
3076#define BNX2_TXP_CPU_EVENT_MASK 0x00045008
3077#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3078#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3079#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3080#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3081#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3082#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3083#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3084#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3085#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3086#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3087#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3088
3089#define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3090#define BNX2_TXP_CPU_INSTRUCTION 0x00045020
3091#define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
3092#define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3093#define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3094#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3095#define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
3096#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3097#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3098
3099#define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3100#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3101#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3102#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3103#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3104#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3105#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3106
3107#define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3108#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3109#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3110#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3111#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3112
3113#define BNX2_TXP_CPU_REG_FILE 0x00045200
3114#define BNX2_TXP_FTQ_DATA 0x000453c0
3115#define BNX2_TXP_FTQ_CMD 0x000453f8
3116#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3117#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
3118#define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3119#define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3120#define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3121#define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
3122#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3123#define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3124#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3125#define BNX2_TXP_FTQ_CMD_POP (1L<<30)
3126#define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
3127
3128#define BNX2_TXP_FTQ_CTL 0x000453fc
3129#define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
3130#define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3131#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3132#define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3133#define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3134
3135#define BNX2_TXP_SCRATCH 0x00060000
3136
3137
3138/*
3139 * tpat_reg definition
3140 * offset: 0x80000
3141 */
3142#define BNX2_TPAT_CPU_MODE 0x00085000
3143#define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3144#define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3145#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3146#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3147#define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3148#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3149#define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3150#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3151#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3152#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3153#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3154
3155#define BNX2_TPAT_CPU_STATE 0x00085004
3156#define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3157#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3158#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3159#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3160#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3161#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3162#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3163#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3164#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3165#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3166#define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3167#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3168#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3169#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3170
3171#define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
3172#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3173#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3174#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3175#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3176#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3177#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3178#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3179#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3180#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3181#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3182#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3183
3184#define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3185#define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
3186#define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
3187#define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3188#define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3189#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3190#define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
3191#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3192#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3193
3194#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3195#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3196#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3197#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3198#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3199#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3200#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3201
3202#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
3203#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3204#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3205#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3206#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3207
3208#define BNX2_TPAT_CPU_REG_FILE 0x00085200
3209#define BNX2_TPAT_FTQ_DATA 0x000853c0
3210#define BNX2_TPAT_FTQ_CMD 0x000853f8
3211#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3212#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
3213#define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
3214#define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
3215#define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
3216#define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
3217#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
3218#define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
3219#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
3220#define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
3221#define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
3222
3223#define BNX2_TPAT_FTQ_CTL 0x000853fc
3224#define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
3225#define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
3226#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3227#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3228#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3229
3230#define BNX2_TPAT_SCRATCH 0x000a0000
3231
3232
3233/*
3234 * rxp_reg definition
3235 * offset: 0xc0000
3236 */
3237#define BNX2_RXP_CPU_MODE 0x000c5000
3238#define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
3239#define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
3240#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3241#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3242#define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
3243#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3244#define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
3245#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3246#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3247#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3248#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3249
3250#define BNX2_RXP_CPU_STATE 0x000c5004
3251#define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
3252#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3253#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3254#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3255#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3256#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3257#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3258#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3259#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
3260#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3261#define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
3262#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3263#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3264#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
3265
3266#define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
3267#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3268#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3269#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3270#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3271#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3272#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3273#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3274#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3275#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3276#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3277#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3278
3279#define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
3280#define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
3281#define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
3282#define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
3283#define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
3284#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
3285#define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
3286#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3287#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3288
3289#define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
3290#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3291#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3292#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3293#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3294#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3295#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3296
3297#define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
3298#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3299#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3300#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3301#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3302
3303#define BNX2_RXP_CPU_REG_FILE 0x000c5200
3304#define BNX2_RXP_CFTQ_DATA 0x000c5380
3305#define BNX2_RXP_CFTQ_CMD 0x000c53b8
3306#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3307#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
3308#define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
3309#define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
3310#define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
3311#define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
3312#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
3313#define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
3314#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
3315#define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
3316#define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
3317
3318#define BNX2_RXP_CFTQ_CTL 0x000c53bc
3319#define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
3320#define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
3321#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
3322#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3323#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3324
3325#define BNX2_RXP_FTQ_DATA 0x000c53c0
3326#define BNX2_RXP_FTQ_CMD 0x000c53f8
3327#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3328#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
3329#define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3330#define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3331#define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
3332#define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
3333#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3334#define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
3335#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3336#define BNX2_RXP_FTQ_CMD_POP (1L<<30)
3337#define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
3338
3339#define BNX2_RXP_FTQ_CTL 0x000c53fc
3340#define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
3341#define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
3342#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3343#define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3344#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3345
3346#define BNX2_RXP_SCRATCH 0x000e0000
3347
3348
3349/*
3350 * com_reg definition
3351 * offset: 0x100000
3352 */
3353#define BNX2_COM_CPU_MODE 0x00105000
3354#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
3355#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
3356#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3357#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3358#define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
3359#define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
3360#define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
3361#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3362#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3363#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3364#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3365
3366#define BNX2_COM_CPU_STATE 0x00105004
3367#define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
3368#define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
3369#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3370#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3371#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3372#define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
3373#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
3374#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3375#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
3376#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3377#define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
3378#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3379#define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
3380#define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
3381
3382#define BNX2_COM_CPU_EVENT_MASK 0x00105008
3383#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3384#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3385#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3386#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3387#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3388#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3389#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3390#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3391#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3392#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3393#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3394
3395#define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
3396#define BNX2_COM_CPU_INSTRUCTION 0x00105020
3397#define BNX2_COM_CPU_DATA_ACCESS 0x00105024
3398#define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
3399#define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
3400#define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
3401#define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
3402#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3403#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3404
3405#define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
3406#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3407#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3408#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3409#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3410#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3411#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3412
3413#define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
3414#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3415#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3416#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3417#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3418
3419#define BNX2_COM_CPU_REG_FILE 0x00105200
3420#define BNX2_COM_COMXQ_FTQ_DATA 0x00105340
3421#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
3422#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3423#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
3424#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3425#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3426#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
3427#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
3428#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3429#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
3430#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3431#define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
3432#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
3433
3434#define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
3435#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
3436#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
3437#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3438#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3439#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3440
3441#define BNX2_COM_COMTQ_FTQ_DATA 0x00105380
3442#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
3443#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3444#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
3445#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3446#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3447#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
3448#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
3449#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3450#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
3451#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3452#define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
3453#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
3454
3455#define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
3456#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
3457#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
3458#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3459#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3460#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3461
3462#define BNX2_COM_COMQ_FTQ_DATA 0x001053c0
3463#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
3464#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3465#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
3466#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3467#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3468#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
3469#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
3470#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3471#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
3472#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3473#define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
3474#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
3475
3476#define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
3477#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
3478#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
3479#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3480#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3481#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3482
3483#define BNX2_COM_SCRATCH 0x00120000
3484
Michael Chancea94db2006-06-12 22:16:13 -07003485#define BNX2_FW_RX_DROP_COUNT 0x00120084
3486
Michael Chanb6016b72005-05-26 13:03:09 -07003487
3488/*
3489 * cp_reg definition
3490 * offset: 0x180000
3491 */
3492#define BNX2_CP_CPU_MODE 0x00185000
3493#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
3494#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
3495#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3496#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3497#define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
3498#define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3499#define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
3500#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3501#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3502#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3503#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3504
3505#define BNX2_CP_CPU_STATE 0x00185004
3506#define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
3507#define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3508#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3509#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3510#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3511#define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3512#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
3513#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3514#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
3515#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3516#define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
3517#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3518#define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3519#define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
3520
3521#define BNX2_CP_CPU_EVENT_MASK 0x00185008
3522#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3523#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3524#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3525#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3526#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3527#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3528#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3529#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3530#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3531#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3532#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3533
3534#define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
3535#define BNX2_CP_CPU_INSTRUCTION 0x00185020
3536#define BNX2_CP_CPU_DATA_ACCESS 0x00185024
3537#define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
3538#define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
3539#define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
3540#define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
3541#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3542#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3543
3544#define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
3545#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3546#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3547#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3548#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3549#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3550#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3551
3552#define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
3553#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3554#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3555#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3556#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3557
3558#define BNX2_CP_CPU_REG_FILE 0x00185200
3559#define BNX2_CP_CPQ_FTQ_DATA 0x001853c0
3560#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
3561#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3562#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
3563#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3564#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3565#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
3566#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
3567#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3568#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
3569#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3570#define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
3571#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
3572
3573#define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
3574#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
3575#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
3576#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3577#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3578#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3579
3580#define BNX2_CP_SCRATCH 0x001a0000
3581
3582
3583/*
3584 * mcp_reg definition
3585 * offset: 0x140000
3586 */
3587#define BNX2_MCP_CPU_MODE 0x00145000
3588#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
3589#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
3590#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3591#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3592#define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
3593#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3594#define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
3595#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3596#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3597#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3598#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3599
3600#define BNX2_MCP_CPU_STATE 0x00145004
3601#define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
3602#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3603#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3604#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3605#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3606#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3607#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
3608#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3609#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
3610#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3611#define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
3612#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3613#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3614#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
3615
3616#define BNX2_MCP_CPU_EVENT_MASK 0x00145008
3617#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3618#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3619#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3620#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3621#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3622#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3623#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3624#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3625#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3626#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3627#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3628
3629#define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
3630#define BNX2_MCP_CPU_INSTRUCTION 0x00145020
3631#define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
3632#define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
3633#define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
3634#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
3635#define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
3636#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3637#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3638
3639#define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
3640#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3641#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3642#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3643#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3644#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3645#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3646
3647#define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
3648#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3649#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3650#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3651#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3652
3653#define BNX2_MCP_CPU_REG_FILE 0x00145200
3654#define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0
3655#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
3656#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3657#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
3658#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3659#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3660#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
3661#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
3662#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3663#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
3664#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3665#define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
3666#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
3667
3668#define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
3669#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
3670#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
3671#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3672#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3673#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3674
3675#define BNX2_MCP_ROM 0x00150000
3676#define BNX2_MCP_SCRATCH 0x00160000
3677
Michael Chane3648b32005-11-04 08:51:21 -08003678#define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
3679#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
3680#define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
3681#define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
3682#define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
3683
3684#define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
3685#define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
3686
Michael Chanb6016b72005-05-26 13:03:09 -07003687
3688#define NUM_MC_HASH_REGISTERS 8
3689
3690
3691/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
3692#define PHY_BCM5706_PHY_ID 0x00206160
3693
3694#define PHY_ID(id) ((id) & 0xfffffff0)
3695#define PHY_REV_ID(id) ((id) & 0xf)
3696
Michael Chan5b0c76a2005-11-04 08:45:49 -08003697/* 5708 Serdes PHY registers */
3698
Michael Chan80be4432006-11-19 14:07:28 -08003699#define BCM5708S_BMCR_FORCE_2500 0x20
3700
Michael Chan5b0c76a2005-11-04 08:45:49 -08003701#define BCM5708S_UP1 0xb
3702
3703#define BCM5708S_UP1_2G5 0x1
3704
3705#define BCM5708S_BLK_ADDR 0x1f
3706
3707#define BCM5708S_BLK_ADDR_DIG 0x0000
3708#define BCM5708S_BLK_ADDR_DIG3 0x0002
3709#define BCM5708S_BLK_ADDR_TX_MISC 0x0005
3710
3711/* Digital Block */
3712#define BCM5708S_1000X_CTL1 0x10
3713
3714#define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
3715#define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
3716
3717#define BCM5708S_1000X_CTL2 0x11
3718
3719#define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
3720
3721#define BCM5708S_1000X_STAT1 0x14
3722
3723#define BCM5708S_1000X_STAT1_SGMII 0x0001
3724#define BCM5708S_1000X_STAT1_LINK 0x0002
3725#define BCM5708S_1000X_STAT1_FD 0x0004
3726#define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
3727#define BCM5708S_1000X_STAT1_SPEED_10 0x0000
3728#define BCM5708S_1000X_STAT1_SPEED_100 0x0008
3729#define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
3730#define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
3731#define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
3732#define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
3733
3734/* Digital3 Block */
3735#define BCM5708S_DIG_3_0 0x10
3736
3737#define BCM5708S_DIG_3_0_USE_IEEE 0x0001
3738
3739/* Tx/Misc Block */
3740#define BCM5708S_TX_ACTL1 0x15
3741
3742#define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
3743
3744#define BCM5708S_TX_ACTL3 0x17
3745
Michael Chanb6016b72005-05-26 13:03:09 -07003746#define MIN_ETHERNET_PACKET_SIZE 60
3747#define MAX_ETHERNET_PACKET_SIZE 1514
3748#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
3749
3750#define RX_COPY_THRESH 92
3751
3752#define DMA_READ_CHANS 5
3753#define DMA_WRITE_CHANS 3
3754
Michael Chanc86a31f2006-06-13 15:03:47 -07003755/* Use CPU native page size up to 16K for the ring sizes. */
3756#if (PAGE_SHIFT > 14)
3757#define BCM_PAGE_BITS 14
3758#else
3759#define BCM_PAGE_BITS PAGE_SHIFT
3760#endif
Michael Chanb6016b72005-05-26 13:03:09 -07003761#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
3762
3763#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
3764#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
3765
Michael Chan13daffa2006-03-20 17:49:20 -08003766#define MAX_RX_RINGS 4
Michael Chanb6016b72005-05-26 13:03:09 -07003767#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
3768#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
Michael Chan13daffa2006-03-20 17:49:20 -08003769#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
Michael Chanb6016b72005-05-26 13:03:09 -07003770
3771#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
3772 (MAX_TX_DESC_CNT - 1)) ? \
3773 (x) + 2 : (x) + 1
3774
3775#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
3776
3777#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
3778 (MAX_RX_DESC_CNT - 1)) ? \
3779 (x) + 2 : (x) + 1
3780
Michael Chan13daffa2006-03-20 17:49:20 -08003781#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
Michael Chanb6016b72005-05-26 13:03:09 -07003782
Michael Chanc86a31f2006-06-13 15:03:47 -07003783#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4))
Michael Chan13daffa2006-03-20 17:49:20 -08003784#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
Michael Chanb6016b72005-05-26 13:03:09 -07003785
3786/* Context size. */
3787#define CTX_SHIFT 7
3788#define CTX_SIZE (1 << CTX_SHIFT)
3789#define CTX_MASK (CTX_SIZE - 1)
3790#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
3791#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
3792
3793#define PHY_CTX_SHIFT 6
3794#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
3795#define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
3796#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
3797#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
3798
3799#define MB_KERNEL_CTX_SHIFT 8
3800#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
3801#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
3802#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
3803
3804#define MAX_CID_CNT 0x4000
3805#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
3806#define INVALID_CID_ADDR 0xffffffff
3807
3808#define TX_CID 16
3809#define RX_CID 0
3810
3811#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
3812#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
3813
3814struct sw_bd {
3815 struct sk_buff *skb;
3816 DECLARE_PCI_UNMAP_ADDR(mapping)
3817};
3818
3819/* Buffered flash (Atmel: AT45DB011B) specific information */
3820#define SEEPROM_PAGE_BITS 2
3821#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
3822#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
3823#define SEEPROM_PAGE_SIZE 4
3824#define SEEPROM_TOTAL_SIZE 65536
3825
3826#define BUFFERED_FLASH_PAGE_BITS 9
3827#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
3828#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
3829#define BUFFERED_FLASH_PAGE_SIZE 264
Michael Chan37137702005-11-04 08:49:17 -08003830#define BUFFERED_FLASH_TOTAL_SIZE 0x21000
Michael Chanb6016b72005-05-26 13:03:09 -07003831
3832#define SAIFUN_FLASH_PAGE_BITS 8
3833#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
3834#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
3835#define SAIFUN_FLASH_PAGE_SIZE 256
3836#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
3837
Michael Chan37137702005-11-04 08:49:17 -08003838#define ST_MICRO_FLASH_PAGE_BITS 8
3839#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
3840#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
3841#define ST_MICRO_FLASH_PAGE_SIZE 256
3842#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
3843
Michael Chanb6016b72005-05-26 13:03:09 -07003844#define NVRAM_TIMEOUT_COUNT 30000
3845
3846
3847#define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
3848 BNX2_NVM_CFG1_BUFFER_MODE | \
3849 BNX2_NVM_CFG1_PROTECT_MODE | \
3850 BNX2_NVM_CFG1_FLASH_SIZE)
3851
Michael Chan37137702005-11-04 08:49:17 -08003852#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
3853
Michael Chanb6016b72005-05-26 13:03:09 -07003854struct flash_spec {
3855 u32 strapping;
3856 u32 config1;
3857 u32 config2;
3858 u32 config3;
3859 u32 write1;
3860 u32 buffered;
3861 u32 page_bits;
3862 u32 page_size;
3863 u32 addr_mask;
3864 u32 total_size;
3865 u8 *name;
3866};
3867
3868struct bnx2 {
3869 /* Fields used in the tx and intr/napi performance paths are grouped */
3870 /* together in the beginning of the structure. */
3871 void __iomem *regview;
3872
3873 struct net_device *dev;
3874 struct pci_dev *pdev;
3875
3876 atomic_t intr_sem;
3877
3878 struct status_block *status_blk;
3879 u32 last_status_idx;
3880
Michael Chan13daffa2006-03-20 17:49:20 -08003881 u32 flags;
3882#define PCIX_FLAG 1
3883#define PCI_32BIT_FLAG 2
3884#define ONE_TDMA_FLAG 4 /* no longer used */
3885#define NO_WOL_FLAG 8
3886#define USING_DAC_FLAG 0x10
3887#define USING_MSI_FLAG 0x20
3888#define ASF_ENABLE_FLAG 0x40
3889
Michael Chan29b12172006-03-23 01:13:43 -08003890 /* Put tx producer and consumer fields in separate cache lines. */
Michael Chanb6016b72005-05-26 13:03:09 -07003891
Michael Chan29b12172006-03-23 01:13:43 -08003892 u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
3893 u16 tx_prod;
3894
Michael Chan29b12172006-03-23 01:13:43 -08003895 u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
3896 u16 hw_tx_cons;
Michael Chanf4e418f2005-11-04 08:53:48 -08003897
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003898#ifdef BCM_VLAN
Michael Chanb6016b72005-05-26 13:03:09 -07003899 struct vlan_group *vlgrp;
3900#endif
3901
3902 u32 rx_offset;
3903 u32 rx_buf_use_size; /* useable size */
3904 u32 rx_buf_size; /* with alignment */
Michael Chan13daffa2006-03-20 17:49:20 -08003905 u32 rx_max_ring_idx;
3906
Michael Chanb6016b72005-05-26 13:03:09 -07003907 u32 rx_prod_bseq;
3908 u16 rx_prod;
3909 u16 rx_cons;
Michael Chan29b12172006-03-23 01:13:43 -08003910 u16 hw_rx_cons;
Michael Chanb6016b72005-05-26 13:03:09 -07003911
3912 u32 rx_csum;
3913
Michael Chan13daffa2006-03-20 17:49:20 -08003914 struct sw_bd *rx_buf_ring;
3915 struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
3916
Michael Chan2f8af122006-08-15 01:39:10 -07003917 /* TX constants */
3918 struct tx_bd *tx_desc_ring;
3919 struct sw_bd *tx_buf_ring;
3920 int tx_ring_size;
3921 u32 tx_wake_thresh;
Michael Chanb6016b72005-05-26 13:03:09 -07003922
Michael Chan13daffa2006-03-20 17:49:20 -08003923 /* End of fields used in the performance code paths. */
Michael Chanb6016b72005-05-26 13:03:09 -07003924
3925 char *name;
3926
3927 int timer_interval;
Michael Chancd339a02005-08-25 15:35:24 -07003928 int current_interval;
Michael Chanb6016b72005-05-26 13:03:09 -07003929 struct timer_list timer;
3930 struct work_struct reset_task;
Michael Chanafdc08b2005-08-25 15:34:29 -07003931 int in_reset_task;
Michael Chanb6016b72005-05-26 13:03:09 -07003932
3933 /* Used to synchronize phy accesses. */
3934 spinlock_t phy_lock;
3935
Michael Chanb6016b72005-05-26 13:03:09 -07003936 u32 phy_flags;
3937#define PHY_SERDES_FLAG 1
3938#define PHY_CRC_FIX_FLAG 2
3939#define PHY_PARALLEL_DETECT_FLAG 4
Michael Chan5b0c76a2005-11-04 08:45:49 -08003940#define PHY_2_5G_CAPABLE_FLAG 8
Michael Chanb6016b72005-05-26 13:03:09 -07003941#define PHY_INT_MODE_MASK_FLAG 0x300
3942#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
3943#define PHY_INT_MODE_LINK_READY_FLAG 0x200
3944
3945 u32 chip_id;
3946 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
3947#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
3948#define CHIP_NUM_5706 0x57060000
Michael Chan5b0c76a2005-11-04 08:45:49 -08003949#define CHIP_NUM_5708 0x57080000
Michael Chanb6016b72005-05-26 13:03:09 -07003950
3951#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
3952#define CHIP_REV_Ax 0x00000000
3953#define CHIP_REV_Bx 0x00001000
3954#define CHIP_REV_Cx 0x00002000
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003955
Michael Chanb6016b72005-05-26 13:03:09 -07003956#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
3957#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
3958
3959#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
3960#define CHIP_ID_5706_A0 0x57060000
3961#define CHIP_ID_5706_A1 0x57060010
Michael Chan5b0c76a2005-11-04 08:45:49 -08003962#define CHIP_ID_5706_A2 0x57060020
3963#define CHIP_ID_5708_A0 0x57080000
3964#define CHIP_ID_5708_B0 0x57081000
Michael Chandda1e392006-01-23 16:08:14 -08003965#define CHIP_ID_5708_B1 0x57081010
Michael Chanb6016b72005-05-26 13:03:09 -07003966
3967#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
3968
3969/* A serdes chip will have the first bit of the bond id set. */
3970#define CHIP_BOND_ID_SERDES_BIT 0x01
3971
3972 u32 phy_addr;
3973 u32 phy_id;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003974
Michael Chanb6016b72005-05-26 13:03:09 -07003975 u16 bus_speed_mhz;
3976 u8 wol;
3977
Michael Chanb090ae22006-01-23 16:07:10 -08003978 u8 pad;
Michael Chanb6016b72005-05-26 13:03:09 -07003979
3980 u16 fw_wr_seq;
3981 u16 fw_drv_pulse_wr_seq;
3982
Michael Chanb6016b72005-05-26 13:03:09 -07003983 dma_addr_t tx_desc_mapping;
3984
3985
Michael Chan13daffa2006-03-20 17:49:20 -08003986 int rx_max_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003987 int rx_ring_size;
Michael Chan13daffa2006-03-20 17:49:20 -08003988 dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
Michael Chanb6016b72005-05-26 13:03:09 -07003989
3990 u16 tx_quick_cons_trip;
3991 u16 tx_quick_cons_trip_int;
3992 u16 rx_quick_cons_trip;
3993 u16 rx_quick_cons_trip_int;
3994 u16 comp_prod_trip;
3995 u16 comp_prod_trip_int;
3996 u16 tx_ticks;
3997 u16 tx_ticks_int;
3998 u16 com_ticks;
3999 u16 com_ticks_int;
4000 u16 cmd_ticks;
4001 u16 cmd_ticks_int;
4002 u16 rx_ticks;
4003 u16 rx_ticks_int;
4004
4005 u32 stats_ticks;
4006
4007 dma_addr_t status_blk_mapping;
4008
4009 struct statistics_block *stats_blk;
4010 dma_addr_t stats_blk_mapping;
4011
Michael Chanbf5295b2006-03-23 01:11:56 -08004012 u32 hc_cmd;
Michael Chanb6016b72005-05-26 13:03:09 -07004013 u32 rx_mode;
4014
4015 u16 req_line_speed;
4016 u8 req_duplex;
4017
4018 u8 link_up;
4019
4020 u16 line_speed;
4021 u8 duplex;
4022 u8 flow_ctrl; /* actual flow ctrl settings */
4023 /* may be different from */
4024 /* req_flow_ctrl if autoneg */
4025#define FLOW_CTRL_TX 1
4026#define FLOW_CTRL_RX 2
4027
4028 u32 advertising;
4029
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004030 u8 req_flow_ctrl; /* flow ctrl advertisement */
Michael Chanb6016b72005-05-26 13:03:09 -07004031 /* settings or forced */
4032 /* settings */
4033 u8 autoneg;
4034#define AUTONEG_SPEED 1
4035#define AUTONEG_FLOW_CTRL 2
4036
4037 u8 loopback;
4038#define MAC_LOOPBACK 1
4039#define PHY_LOOPBACK 2
4040
4041 u8 serdes_an_pending;
Michael Chancd339a02005-08-25 15:35:24 -07004042#define SERDES_AN_TIMEOUT (HZ / 3)
Michael Chanb6016b72005-05-26 13:03:09 -07004043
4044 u8 mac_addr[8];
4045
Michael Chane3648b32005-11-04 08:51:21 -08004046 u32 shmem_base;
4047
Michael Chanb6016b72005-05-26 13:03:09 -07004048 u32 fw_ver;
4049
4050 int pm_cap;
4051 int pcix_cap;
4052
4053 struct net_device_stats net_stats;
4054
4055 struct flash_spec *flash_info;
Michael Chan1122db72006-01-23 16:11:42 -08004056 u32 flash_size;
Michael Chan0f31f992006-03-23 01:12:38 -08004057
4058 int status_stats_size;
Michael Chanfba9fe92006-06-12 22:21:25 -07004059
4060 struct z_stream_s *strm;
4061 void *gunzip_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07004062};
4063
4064static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
4065static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
4066
4067#define REG_RD(bp, offset) \
4068 readl(bp->regview + offset)
4069
4070#define REG_WR(bp, offset, val) \
4071 writel(val, bp->regview + offset)
4072
4073#define REG_WR16(bp, offset, val) \
4074 writew(val, bp->regview + offset)
4075
4076#define REG_RD_IND(bp, offset) \
4077 bnx2_reg_rd_ind(bp, offset)
4078
4079#define REG_WR_IND(bp, offset, val) \
4080 bnx2_reg_wr_ind(bp, offset, val)
4081
4082/* Indirect context access. Unlike the MBQ_WR, these macros will not
4083 * trigger a chip event. */
4084static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
4085
4086#define CTX_WR(bp, cid_addr, offset, val) \
4087 bnx2_ctx_wr(bp, cid_addr, offset, val)
4088
4089struct cpu_reg {
4090 u32 mode;
4091 u32 mode_value_halt;
4092 u32 mode_value_sstep;
4093
4094 u32 state;
4095 u32 state_value_clear;
4096
4097 u32 gpr0;
4098 u32 evmask;
4099 u32 pc;
4100 u32 inst;
4101 u32 bp;
4102
4103 u32 spad_base;
4104
4105 u32 mips_view_base;
4106};
4107
4108struct fw_info {
4109 u32 ver_major;
4110 u32 ver_minor;
4111 u32 ver_fix;
4112
4113 u32 start_addr;
4114
4115 /* Text section. */
4116 u32 text_addr;
4117 u32 text_len;
4118 u32 text_index;
4119 u32 *text;
4120
4121 /* Data section. */
4122 u32 data_addr;
4123 u32 data_len;
4124 u32 data_index;
4125 u32 *data;
4126
4127 /* SBSS section. */
4128 u32 sbss_addr;
4129 u32 sbss_len;
4130 u32 sbss_index;
4131 u32 *sbss;
4132
4133 /* BSS section. */
4134 u32 bss_addr;
4135 u32 bss_len;
4136 u32 bss_index;
4137 u32 *bss;
4138
4139 /* Read-only section. */
4140 u32 rodata_addr;
4141 u32 rodata_len;
4142 u32 rodata_index;
4143 u32 *rodata;
4144};
4145
4146#define RV2P_PROC1 0
4147#define RV2P_PROC2 1
4148
4149
4150/* This value (in milliseconds) determines the frequency of the driver
4151 * issuing the PULSE message code. The firmware monitors this periodic
4152 * pulse to determine when to switch to an OS-absent mode. */
4153#define DRV_PULSE_PERIOD_MS 250
4154
4155/* This value (in milliseconds) determines how long the driver should
4156 * wait for an acknowledgement from the firmware before timing out. Once
4157 * the firmware has timed out, the driver will assume there is no firmware
4158 * running and there won't be any firmware-driver synchronization during a
4159 * driver reset. */
Michael Chanb090ae22006-01-23 16:07:10 -08004160#define FW_ACK_TIME_OUT_MS 100
Michael Chanb6016b72005-05-26 13:03:09 -07004161
4162
4163#define BNX2_DRV_RESET_SIGNATURE 0x00000000
4164#define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
4165//#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
4166
4167#define BNX2_DRV_MB 0x00000004
4168#define BNX2_DRV_MSG_CODE 0xff000000
4169#define BNX2_DRV_MSG_CODE_RESET 0x01000000
4170#define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
4171#define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
4172#define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
4173#define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
4174#define BNX2_DRV_MSG_CODE_PULSE 0x06000000
4175#define BNX2_DRV_MSG_CODE_DIAG 0x07000000
4176#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
Michael Chan6c4f0952006-06-29 12:38:15 -07004177#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
Michael Chanb6016b72005-05-26 13:03:09 -07004178
4179#define BNX2_DRV_MSG_DATA 0x00ff0000
4180#define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
4181#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
4182#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
4183#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004184
Michael Chanb6016b72005-05-26 13:03:09 -07004185#define BNX2_DRV_MSG_SEQ 0x0000ffff
4186
4187#define BNX2_FW_MB 0x00000008
4188#define BNX2_FW_MSG_ACK 0x0000ffff
4189#define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
4190#define BNX2_FW_MSG_STATUS_OK 0x00000000
4191#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
4192
4193#define BNX2_LINK_STATUS 0x0000000c
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004194#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
4195#define BNX2_LINK_STATUS_LINK_UP 0x1
4196#define BNX2_LINK_STATUS_LINK_DOWN 0x0
Michael Chane3648b32005-11-04 08:51:21 -08004197#define BNX2_LINK_STATUS_SPEED_MASK 0x1e
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004198#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
4199#define BNX2_LINK_STATUS_10HALF (1<<1)
4200#define BNX2_LINK_STATUS_10FULL (2<<1)
4201#define BNX2_LINK_STATUS_100HALF (3<<1)
4202#define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
4203#define BNX2_LINK_STATUS_100FULL (5<<1)
4204#define BNX2_LINK_STATUS_1000HALF (6<<1)
4205#define BNX2_LINK_STATUS_1000FULL (7<<1)
4206#define BNX2_LINK_STATUS_2500HALF (8<<1)
4207#define BNX2_LINK_STATUS_2500FULL (9<<1)
4208#define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
4209#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
4210#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
4211#define BNX2_LINK_STATUS_RESERVED (1<<8)
4212#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
4213#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
4214#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
4215#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
4216#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
4217#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
4218#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
4219#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
4220#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
4221#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
4222#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
4223#define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
4224#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
4225#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
Michael Chanb6016b72005-05-26 13:03:09 -07004226
4227#define BNX2_DRV_PULSE_MB 0x00000010
Michael Chan5b0c76a2005-11-04 08:45:49 -08004228#define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
Michael Chanb6016b72005-05-26 13:03:09 -07004229
4230/* Indicate to the firmware not to go into the
4231 * OS absent when it is not getting driver pulse.
4232 * This is used for debugging. */
Michael Chan5b0c76a2005-11-04 08:45:49 -08004233#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
Michael Chanb6016b72005-05-26 13:03:09 -07004234
4235#define BNX2_DEV_INFO_SIGNATURE 0x00000020
4236#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
4237#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
4238#define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
4239#define BNX2_DEV_INFO_SECONDARY_PORT 0x80
4240#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
4241
4242#define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
4243
4244#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
4245#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
4246#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
4247#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
4248#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
4249
4250#define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
4251#define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
4252#define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
4253#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
4254#define BNX2_SHARED_HW_CFG_PHY_COPPER 0
4255#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
Michael Chan5b0c76a2005-11-04 08:45:49 -08004256#define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
4257#define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
Michael Chanb6016b72005-05-26 13:03:09 -07004258#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
4259#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
4260#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
4261#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
4262#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
4263
Michael Chan1122db72006-01-23 16:11:42 -08004264#define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
4265#define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
4266
Michael Chanb6016b72005-05-26 13:03:09 -07004267#define BNX2_DEV_INFO_BC_REV 0x0000004c
4268
4269#define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
4270#define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
4271
4272#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
4273#define BNX2_PORT_HW_CFG_CONFIG 0x00000058
Michael Chan5b0c76a2005-11-04 08:45:49 -08004274#define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
Michael Chancd339a02005-08-25 15:35:24 -07004275#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
4276#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
4277#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
Michael Chan5b0c76a2005-11-04 08:45:49 -08004278#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
Michael Chanb6016b72005-05-26 13:03:09 -07004279
4280#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
4281#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
4282#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
4283#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
4284#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
4285#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
4286
4287#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
4288
4289#define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
4290#define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
4291#define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
4292
4293#define BNX2_SHARED_FEATURE 0x000000c8
4294#define BNX2_SHARED_FEATURE_MASK 0xffffffff
4295
4296#define BNX2_PORT_FEATURE 0x000000d8
4297#define BNX2_PORT2_FEATURE 0x00000014c
4298#define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
4299#define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
4300#define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
4301#define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
4302#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
4303#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
4304#define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
4305#define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
4306#define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
4307#define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
4308#define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
4309#define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
4310#define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
4311#define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
4312#define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
4313#define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
4314#define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
4315#define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
4316#define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
4317#define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
4318#define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
4319
4320#define BNX2_PORT_FEATURE_WOL 0xdc
4321#define BNX2_PORT2_FEATURE_WOL 0x150
4322#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
4323#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
4324#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
4325#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
4326#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
4327#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
4328#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
4329#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
4330#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
4331#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
4332#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
4333#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
4334#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
4335#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
4336#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
4337#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
4338#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
4339
4340#define BNX2_PORT_FEATURE_MBA 0xe0
4341#define BNX2_PORT2_FEATURE_MBA 0x154
4342#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
4343#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
4344#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
4345#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
4346#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
4347#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
4348#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
4349#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
4350#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
4351#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
4352#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
4353#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
4354#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
4355#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
4356#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
4357#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
4358#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
4359#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
4360#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
4361#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
4362#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
4363#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
4364#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
4365#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
4366#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
4367#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
4368#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
4369#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
4370#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
4371#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
4372#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
4373#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
4374#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
4375#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
4376#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
4377#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
4378#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
4379#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
4380#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
4381#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
4382#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
4383#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
4384#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
4385
4386#define BNX2_PORT_FEATURE_IMD 0xe4
4387#define BNX2_PORT2_FEATURE_IMD 0x158
4388#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
4389#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
4390
4391#define BNX2_PORT_FEATURE_VLAN 0xe8
4392#define BNX2_PORT2_FEATURE_VLAN 0x15c
4393#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
4394#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
4395
4396#define BNX2_BC_STATE_RESET_TYPE 0x000001c0
4397#define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
4398#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
4399#define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
4400 0x00010000)
4401#define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
4402 0x00020000)
4403#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
4404 0x00030000)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004405#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
Michael Chanb6016b72005-05-26 13:03:09 -07004406#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
4407 DRV_MSG_CODE_RESET)
4408#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
4409 DRV_MSG_CODE_UNLOAD)
4410#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
4411 DRV_MSG_CODE_SHUTDOWN)
4412#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
4413 DRV_MSG_CODE_WOL)
4414#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
4415 DRV_MSG_CODE_DIAG)
4416#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
4417 (msg))
4418
4419#define BNX2_BC_STATE 0x000001c4
4420#define BNX2_BC_STATE_ERR_MASK 0x0000ff00
4421#define BNX2_BC_STATE_SIGN 0x42530000
4422#define BNX2_BC_STATE_SIGN_MASK 0xffff0000
4423#define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
4424#define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
4425#define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
4426#define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
4427#define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
4428#define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
4429#define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
4430#define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
4431#define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
4432#define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
4433#define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
4434#define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
4435#define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
4436#define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
4437#define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
4438#define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
4439#define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
4440#define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
4441#define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
4442#define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
4443#define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
4444#define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
4445#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
4446#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
4447#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004448
Michael Chanb6016b72005-05-26 13:03:09 -07004449#define BNX2_BC_STATE_DEBUG_CMD 0x1dc
4450#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
4451#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
4452#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
4453#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
4454
4455#define HOST_VIEW_SHMEM_BASE 0x167c00
4456
4457#endif