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Linus Torvalds1da177e2005-04-16 15:20:36 -07001README on the IOBARRIER for CardEngine IO
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3
4Due to an unfortunate oversight when the Card Engines were designed,
5the signals that control access to some peripherals, most notably the
6SMC91C9111 ethernet controller, are not properly handled.
7
8The symptom is that some back to back IO with the peripheral returns
9unreliable data. With the SMC chip, you'll see errors about the bank
10register being 'screwed'.
11
12The cause is that the AEN signal to the SMC chip does not transition
13for every memory access. It is driven through the CPLD from the CS7
14line of the CPU's static memory controller which is optimized to
15eliminate unnecessary transitions. Yet, the SMC requires a transition
16for every write access. The Sharp website has more information about
17the effect this power-conserving feature has on peripheral
18interfacing.
19
20The solution is to follow every write access to the SMC chip with an
21access to another memory region that will force the CPU to release the
22chip select line. It is important to guarantee that this access
23forces the CPU off-chip. We map a page of SDRAM as if it were an
24uncacheable IO device and read from it after every SMC IO write
25operation.
26
27 SMC IO
28 BARRIER IO
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30Only this sequence is important. It does not matter that there is no
31BARRIER IO before the access to the SMC chip because the AEN latch
32only needs occurs after the SMC IO write cycle. The routines that
33implement this work-around make an additional concession which is to
34disable interrupts during the IO sequence. Other hardware devices
35(the LogicPD CPLD) have registers in the same the physical memory
36region as the SMC chip. An interrupt might allow an access to one of
37those registers while SMC IO is being performed.
38
39You might be tempted to think that we have to access another device
40attached to the static memory controller, but the empirical evidence
41indicates that this is not so. Mapping 0x00000000 (flash) and
420xc0000000 (SDRAM) appear to have the same effect. Using SDRAM seems
43to be faster. Choosing to access an undecoded memory region is not
44desirable as there is no way to know how that chip select will be used
45in the future.