Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx |
| 3 | * |
| 4 | * Copyright (C) 2011 Nokia Corporation |
| 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #include <plat/omap_hwmod.h> |
| 12 | #include <plat/serial.h> |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 13 | #include <plat/dma.h> |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 14 | #include <plat/dmtimer.h> |
| 15 | #include <plat/mcspi.h> |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 16 | |
| 17 | #include <mach/irqs.h> |
| 18 | |
| 19 | #include "omap_hwmod_common_data.h" |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 20 | #include "wd_timer.h" |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 21 | |
| 22 | struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { |
| 23 | { .irq = 48, }, |
| 24 | { .irq = -1 } |
| 25 | }; |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 26 | |
| 27 | struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { |
| 28 | { .name = "dispc", .dma_req = 5 }, |
| 29 | { .dma_req = -1 } |
| 30 | }; |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 31 | /* OMAP2xxx Timer Common */ |
| 32 | static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { |
| 33 | .rev_offs = 0x0000, |
| 34 | .sysc_offs = 0x0010, |
| 35 | .syss_offs = 0x0014, |
| 36 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
| 37 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 38 | SYSC_HAS_AUTOIDLE), |
| 39 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 40 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 41 | }; |
| 42 | |
| 43 | struct omap_hwmod_class omap2xxx_timer_hwmod_class = { |
| 44 | .name = "timer", |
| 45 | .sysc = &omap2xxx_timer_sysc, |
| 46 | .rev = OMAP_TIMER_IP_VERSION_1, |
| 47 | }; |
| 48 | |
| 49 | /* |
| 50 | * 'wd_timer' class |
| 51 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 52 | * overflow condition |
| 53 | */ |
| 54 | |
| 55 | static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = { |
| 56 | .rev_offs = 0x0000, |
| 57 | .sysc_offs = 0x0010, |
| 58 | .syss_offs = 0x0014, |
| 59 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 60 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 61 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 62 | }; |
| 63 | |
| 64 | struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { |
| 65 | .name = "wd_timer", |
| 66 | .sysc = &omap2xxx_wd_timer_sysc, |
| 67 | .pre_shutdown = &omap2_wd_timer_disable |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * 'gpio' class |
| 72 | * general purpose io module |
| 73 | */ |
| 74 | static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = { |
| 75 | .rev_offs = 0x0000, |
| 76 | .sysc_offs = 0x0010, |
| 77 | .syss_offs = 0x0014, |
| 78 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 79 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 80 | SYSS_HAS_RESET_STATUS), |
| 81 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 82 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 83 | }; |
| 84 | |
| 85 | struct omap_hwmod_class omap2xxx_gpio_hwmod_class = { |
| 86 | .name = "gpio", |
| 87 | .sysc = &omap2xxx_gpio_sysc, |
| 88 | .rev = 0, |
| 89 | }; |
| 90 | |
| 91 | /* system dma */ |
| 92 | static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = { |
| 93 | .rev_offs = 0x0000, |
| 94 | .sysc_offs = 0x002c, |
| 95 | .syss_offs = 0x0028, |
| 96 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | |
| 97 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | |
| 98 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 99 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 100 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 101 | }; |
| 102 | |
| 103 | struct omap_hwmod_class omap2xxx_dma_hwmod_class = { |
| 104 | .name = "dma", |
| 105 | .sysc = &omap2xxx_dma_sysc, |
| 106 | }; |
| 107 | |
| 108 | /* |
| 109 | * 'mailbox' class |
| 110 | * mailbox module allowing communication between the on-chip processors |
| 111 | * using a queued mailbox-interrupt mechanism. |
| 112 | */ |
| 113 | |
| 114 | static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = { |
| 115 | .rev_offs = 0x000, |
| 116 | .sysc_offs = 0x010, |
| 117 | .syss_offs = 0x014, |
| 118 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 119 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 120 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 121 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 122 | }; |
| 123 | |
| 124 | struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = { |
| 125 | .name = "mailbox", |
| 126 | .sysc = &omap2xxx_mailbox_sysc, |
| 127 | }; |
| 128 | |
| 129 | /* |
| 130 | * 'mcspi' class |
| 131 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 132 | * bus |
| 133 | */ |
| 134 | |
| 135 | static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { |
| 136 | .rev_offs = 0x0000, |
| 137 | .sysc_offs = 0x0010, |
| 138 | .syss_offs = 0x0014, |
| 139 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 140 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 141 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 142 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 143 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 144 | }; |
| 145 | |
| 146 | struct omap_hwmod_class omap2xxx_mcspi_class = { |
| 147 | .name = "mcspi", |
| 148 | .sysc = &omap2xxx_mcspi_sysc, |
| 149 | .rev = OMAP2_MCSPI_REV, |
| 150 | }; |