blob: b8061519ce776b7dbc049815c4fbff21daa073ef [file] [log] [blame]
Russell Kingd2bab052005-05-10 14:23:01 +01001/*
2 * linux/arch/arm/lib/copypage-armv4mc.S
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles the mini data cache, as found on SA11x0 and XScale
11 * processors. When we copy a user page page, we map it in such a way
12 * that accesses to this page will not touch the main data cache, but
13 * will be cached in the mini data cache. This prevents us thrashing
14 * the main data cache on page faults.
15 */
16#include <linux/init.h>
17#include <linux/mm.h>
Russell King063b0a42008-10-31 15:08:35 +000018#include <linux/highmem.h>
Russell Kingd2bab052005-05-10 14:23:01 +010019
Russell Kingd2bab052005-05-10 14:23:01 +010020#include <asm/pgtable.h>
21#include <asm/tlbflush.h>
Richard Purdie1c9d3df2006-12-30 16:08:50 +010022#include <asm/cacheflush.h>
Russell Kingd2bab052005-05-10 14:23:01 +010023
Russell King1b2e2b72006-08-21 17:06:38 +010024#include "mm.h"
25
Russell Kingd2bab052005-05-10 14:23:01 +010026/*
27 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
28 * specific hacks for copying pages efficiently.
29 */
30#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
Russell Kingbb30f362008-09-06 20:04:59 +010031 L_PTE_MT_MINICACHE)
Russell Kingd2bab052005-05-10 14:23:01 +010032
Russell Kingd2bab052005-05-10 14:23:01 +010033static DEFINE_SPINLOCK(minicache_lock);
34
35/*
Russell King063b0a42008-10-31 15:08:35 +000036 * ARMv4 mini-dcache optimised copy_user_highpage
Russell Kingd2bab052005-05-10 14:23:01 +010037 *
38 * We flush the destination cache lines just before we write the data into the
39 * corresponding address. Since the Dcache is read-allocate, this removes the
40 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
41 * and merged as appropriate.
42 *
43 * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
44 * instruction. If your processor does not supply this, you have to write your
Russell King063b0a42008-10-31 15:08:35 +000045 * own copy_user_highpage that does the right thing.
Russell Kingd2bab052005-05-10 14:23:01 +010046 */
Uwe Kleine-König446c92b2009-03-12 18:03:16 +010047static void __naked
Russell Kingd2bab052005-05-10 14:23:01 +010048mc_copy_user_page(void *from, void *to)
49{
50 asm volatile(
51 "stmfd sp!, {r4, lr} @ 2\n\
52 mov r4, %2 @ 1\n\
53 ldmia %0!, {r2, r3, ip, lr} @ 4\n\
541: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
55 stmia %1!, {r2, r3, ip, lr} @ 4\n\
56 ldmia %0!, {r2, r3, ip, lr} @ 4+1\n\
57 stmia %1!, {r2, r3, ip, lr} @ 4\n\
58 ldmia %0!, {r2, r3, ip, lr} @ 4\n\
59 mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\
60 stmia %1!, {r2, r3, ip, lr} @ 4\n\
61 ldmia %0!, {r2, r3, ip, lr} @ 4\n\
62 subs r4, r4, #1 @ 1\n\
63 stmia %1!, {r2, r3, ip, lr} @ 4\n\
64 ldmneia %0!, {r2, r3, ip, lr} @ 4\n\
65 bne 1b @ 1\n\
66 ldmfd sp!, {r4, pc} @ 3"
67 :
68 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64));
69}
70
Russell King7dd8c4f2009-01-18 16:24:19 +000071void v4_mc_copy_user_highpage(struct page *to, struct page *from,
Russell Kingf00a75c2009-10-05 15:17:45 +010072 unsigned long vaddr, struct vm_area_struct *vma)
Russell Kingd2bab052005-05-10 14:23:01 +010073{
Russell King063b0a42008-10-31 15:08:35 +000074 void *kto = kmap_atomic(to, KM_USER1);
Richard Purdie1c9d3df2006-12-30 16:08:50 +010075
Catalin Marinasc0177802010-09-13 15:57:36 +010076 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
Russell King063b0a42008-10-31 15:08:35 +000077 __flush_dcache_page(page_mapping(from), from);
Richard Purdie1c9d3df2006-12-30 16:08:50 +010078
Russell Kingd2bab052005-05-10 14:23:01 +010079 spin_lock(&minicache_lock);
80
Russell King063b0a42008-10-31 15:08:35 +000081 set_pte_ext(TOP_PTE(0xffff8000), pfn_pte(page_to_pfn(from), minicache_pgprot), 0);
Russell King8711a1b2005-05-16 23:36:22 +010082 flush_tlb_kernel_page(0xffff8000);
Russell Kingd2bab052005-05-10 14:23:01 +010083
Russell King8711a1b2005-05-16 23:36:22 +010084 mc_copy_user_page((void *)0xffff8000, kto);
Russell Kingd2bab052005-05-10 14:23:01 +010085
86 spin_unlock(&minicache_lock);
Russell King063b0a42008-10-31 15:08:35 +000087
88 kunmap_atomic(kto, KM_USER1);
Russell Kingd2bab052005-05-10 14:23:01 +010089}
90
91/*
92 * ARMv4 optimised clear_user_page
93 */
Russell King303c6442008-10-31 16:32:19 +000094void v4_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
Russell Kingd2bab052005-05-10 14:23:01 +010095{
Nicolas Pitre43ae2862008-11-04 02:42:27 -050096 void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
Russell King303c6442008-10-31 16:32:19 +000097 asm volatile("\
Nicolas Pitre43ae2862008-11-04 02:42:27 -050098 mov r1, %2 @ 1\n\
Russell Kingd2bab052005-05-10 14:23:01 +010099 mov r2, #0 @ 1\n\
100 mov r3, #0 @ 1\n\
101 mov ip, #0 @ 1\n\
102 mov lr, #0 @ 1\n\
Russell King303c6442008-10-31 16:32:19 +00001031: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
104 stmia %0!, {r2, r3, ip, lr} @ 4\n\
105 stmia %0!, {r2, r3, ip, lr} @ 4\n\
106 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\
107 stmia %0!, {r2, r3, ip, lr} @ 4\n\
108 stmia %0!, {r2, r3, ip, lr} @ 4\n\
Russell Kingd2bab052005-05-10 14:23:01 +0100109 subs r1, r1, #1 @ 1\n\
Russell King303c6442008-10-31 16:32:19 +0000110 bne 1b @ 1"
Nicolas Pitre43ae2862008-11-04 02:42:27 -0500111 : "=r" (ptr)
112 : "0" (kaddr), "I" (PAGE_SIZE / 64)
Russell King303c6442008-10-31 16:32:19 +0000113 : "r1", "r2", "r3", "ip", "lr");
114 kunmap_atomic(kaddr, KM_USER0);
Russell Kingd2bab052005-05-10 14:23:01 +0100115}
116
117struct cpu_user_fns v4_mc_user_fns __initdata = {
Russell King303c6442008-10-31 16:32:19 +0000118 .cpu_clear_user_highpage = v4_mc_clear_user_highpage,
Russell King063b0a42008-10-31 15:08:35 +0000119 .cpu_copy_user_highpage = v4_mc_copy_user_highpage,
Russell Kingd2bab052005-05-10 14:23:01 +0100120};