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Bard Liao07cf7cba2014-06-20 14:41:13 +08001/*
2 * rt286.c -- RT286 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <sound/jack.h>
29#include <linux/workqueue.h>
30#include <sound/rt286.h>
31#include <sound/hda_verbs.h>
32
33#include "rt286.h"
34
35#define RT286_VENDOR_ID 0x10ec0286
36
37struct rt286_priv {
38 struct regmap *regmap;
Bard Liao07cf7cba2014-06-20 14:41:13 +080039 struct rt286_platform_data pdata;
40 struct i2c_client *i2c;
41 struct snd_soc_jack *jack;
42 struct delayed_work jack_detect_work;
43 int sys_clk;
44 struct reg_default *index_cache;
45};
46
47static struct reg_default rt286_index_def[] = {
48 { 0x01, 0xaaaa },
49 { 0x02, 0x8aaa },
50 { 0x03, 0x0002 },
51 { 0x04, 0xaf01 },
52 { 0x08, 0x000d },
53 { 0x09, 0xd810 },
54 { 0x0a, 0x0060 },
55 { 0x0b, 0x0000 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080056 { 0x0d, 0x2800 },
Bard Liao07cf7cba2014-06-20 14:41:13 +080057 { 0x0f, 0x0000 },
58 { 0x19, 0x0a17 },
59 { 0x20, 0x0020 },
60 { 0x33, 0x0208 },
61 { 0x49, 0x0004 },
62 { 0x4f, 0x50e9 },
63 { 0x50, 0x2c00 },
64 { 0x63, 0x2902 },
Bard Liaobc6c4e42014-07-07 19:15:30 +080065 { 0x67, 0x1111 },
66 { 0x68, 0x1016 },
67 { 0x69, 0x273f },
Bard Liao07cf7cba2014-06-20 14:41:13 +080068};
69#define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
70
71static const struct reg_default rt286_reg[] = {
72 { 0x00170500, 0x00000400 },
73 { 0x00220000, 0x00000031 },
74 { 0x00239000, 0x0000007f },
75 { 0x0023a000, 0x0000007f },
76 { 0x00270500, 0x00000400 },
77 { 0x00370500, 0x00000400 },
78 { 0x00870500, 0x00000400 },
79 { 0x00920000, 0x00000031 },
80 { 0x00935000, 0x000000c3 },
81 { 0x00936000, 0x000000c3 },
82 { 0x00970500, 0x00000400 },
83 { 0x00b37000, 0x00000097 },
84 { 0x00b37200, 0x00000097 },
85 { 0x00b37300, 0x00000097 },
86 { 0x00c37000, 0x00000000 },
87 { 0x00c37100, 0x00000080 },
88 { 0x01270500, 0x00000400 },
89 { 0x01370500, 0x00000400 },
90 { 0x01371f00, 0x411111f0 },
91 { 0x01439000, 0x00000080 },
92 { 0x0143a000, 0x00000080 },
93 { 0x01470700, 0x00000000 },
94 { 0x01470500, 0x00000400 },
95 { 0x01470c00, 0x00000000 },
96 { 0x01470100, 0x00000000 },
97 { 0x01837000, 0x00000000 },
98 { 0x01870500, 0x00000400 },
99 { 0x02050000, 0x00000000 },
100 { 0x02139000, 0x00000080 },
101 { 0x0213a000, 0x00000080 },
102 { 0x02170100, 0x00000000 },
103 { 0x02170500, 0x00000400 },
104 { 0x02170700, 0x00000000 },
105 { 0x02270100, 0x00000000 },
106 { 0x02370100, 0x00000000 },
107 { 0x02040000, 0x00004002 },
108 { 0x01870700, 0x00000020 },
109 { 0x00830000, 0x000000c3 },
110 { 0x00930000, 0x000000c3 },
111 { 0x01270700, 0x00000000 },
112};
113
114static bool rt286_volatile_register(struct device *dev, unsigned int reg)
115{
116 switch (reg) {
117 case 0 ... 0xff:
118 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
119 case RT286_GET_HP_SENSE:
120 case RT286_GET_MIC1_SENSE:
121 case RT286_PROC_COEF:
122 return true;
123 default:
124 return false;
125 }
126
127
128}
129
130static bool rt286_readable_register(struct device *dev, unsigned int reg)
131{
132 switch (reg) {
133 case 0 ... 0xff:
134 case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
135 case RT286_GET_HP_SENSE:
136 case RT286_GET_MIC1_SENSE:
137 case RT286_SET_AUDIO_POWER:
138 case RT286_SET_HPO_POWER:
139 case RT286_SET_SPK_POWER:
140 case RT286_SET_DMIC1_POWER:
141 case RT286_SPK_MUX:
142 case RT286_HPO_MUX:
143 case RT286_ADC0_MUX:
144 case RT286_ADC1_MUX:
145 case RT286_SET_MIC1:
146 case RT286_SET_PIN_HPO:
147 case RT286_SET_PIN_SPK:
148 case RT286_SET_PIN_DMIC1:
149 case RT286_SPK_EAPD:
150 case RT286_SET_AMP_GAIN_HPO:
151 case RT286_SET_DMIC2_DEFAULT:
152 case RT286_DACL_GAIN:
153 case RT286_DACR_GAIN:
154 case RT286_ADCL_GAIN:
155 case RT286_ADCR_GAIN:
156 case RT286_MIC_GAIN:
157 case RT286_SPOL_GAIN:
158 case RT286_SPOR_GAIN:
159 case RT286_HPOL_GAIN:
160 case RT286_HPOR_GAIN:
161 case RT286_F_DAC_SWITCH:
162 case RT286_F_RECMIX_SWITCH:
163 case RT286_REC_MIC_SWITCH:
164 case RT286_REC_I2S_SWITCH:
165 case RT286_REC_LINE_SWITCH:
166 case RT286_REC_BEEP_SWITCH:
167 case RT286_DAC_FORMAT:
168 case RT286_ADC_FORMAT:
169 case RT286_COEF_INDEX:
170 case RT286_PROC_COEF:
171 case RT286_SET_AMP_GAIN_ADC_IN1:
172 case RT286_SET_AMP_GAIN_ADC_IN2:
173 case RT286_SET_POWER(RT286_DAC_OUT1):
174 case RT286_SET_POWER(RT286_DAC_OUT2):
175 case RT286_SET_POWER(RT286_ADC_IN1):
176 case RT286_SET_POWER(RT286_ADC_IN2):
177 case RT286_SET_POWER(RT286_DMIC2):
178 case RT286_SET_POWER(RT286_MIC1):
179 return true;
180 default:
181 return false;
182 }
183}
184
185static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
186{
187 struct i2c_client *client = context;
188 struct rt286_priv *rt286 = i2c_get_clientdata(client);
189 u8 data[4];
190 int ret, i;
191
192 /*handle index registers*/
193 if (reg <= 0xff) {
194 rt286_hw_write(client, RT286_COEF_INDEX, reg);
195 reg = RT286_PROC_COEF;
196 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
197 if (reg == rt286->index_cache[i].reg) {
198 rt286->index_cache[i].def = value;
199 break;
200 }
201
202 }
203 }
204
205 data[0] = (reg >> 24) & 0xff;
206 data[1] = (reg >> 16) & 0xff;
207 /*
208 * 4 bit VID: reg should be 0
209 * 12 bit VID: value should be 0
210 * So we use an OR operator to handle it rather than use if condition.
211 */
212 data[2] = ((reg >> 8) & 0xff) | ((value >> 8) & 0xff);
213 data[3] = value & 0xff;
214
215 ret = i2c_master_send(client, data, 4);
216
217 if (ret == 4)
218 return 0;
219 else
220 pr_err("ret=%d\n", ret);
221 if (ret < 0)
222 return ret;
223 else
224 return -EIO;
225}
226
227static int rt286_hw_read(void *context, unsigned int reg, unsigned int *value)
228{
229 struct i2c_client *client = context;
230 struct i2c_msg xfer[2];
231 int ret;
232 __be32 be_reg;
233 unsigned int index, vid, buf = 0x0;
234
235 /*handle index registers*/
236 if (reg <= 0xff) {
237 rt286_hw_write(client, RT286_COEF_INDEX, reg);
238 reg = RT286_PROC_COEF;
239 }
240
241 reg = reg | 0x80000;
242 vid = (reg >> 8) & 0xfff;
243
244 if (AC_VERB_GET_AMP_GAIN_MUTE == (vid & 0xf00)) {
245 index = (reg >> 8) & 0xf;
246 reg = (reg & ~0xf0f) | index;
247 }
248 be_reg = cpu_to_be32(reg);
249
250 /* Write register */
251 xfer[0].addr = client->addr;
252 xfer[0].flags = 0;
253 xfer[0].len = 4;
254 xfer[0].buf = (u8 *)&be_reg;
255
256 /* Read data */
257 xfer[1].addr = client->addr;
258 xfer[1].flags = I2C_M_RD;
259 xfer[1].len = 4;
260 xfer[1].buf = (u8 *)&buf;
261
262 ret = i2c_transfer(client->adapter, xfer, 2);
263 if (ret < 0)
264 return ret;
265 else if (ret != 2)
266 return -EIO;
267
268 *value = be32_to_cpu(buf);
269
270 return 0;
271}
272
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200273#ifdef CONFIG_PM
Bard Liao07cf7cba2014-06-20 14:41:13 +0800274static void rt286_index_sync(struct snd_soc_codec *codec)
275{
276 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
277 int i;
278
279 for (i = 0; i < INDEX_CACHE_SIZE; i++) {
280 snd_soc_write(codec, rt286->index_cache[i].reg,
281 rt286->index_cache[i].def);
282 }
283}
Thierry Reding81f3dfe2014-10-02 09:27:03 +0200284#endif
Bard Liao07cf7cba2014-06-20 14:41:13 +0800285
286static int rt286_support_power_controls[] = {
287 RT286_DAC_OUT1,
288 RT286_DAC_OUT2,
289 RT286_ADC_IN1,
290 RT286_ADC_IN2,
291 RT286_MIC1,
292 RT286_DMIC1,
293 RT286_DMIC2,
294 RT286_SPK_OUT,
295 RT286_HP_OUT,
296};
297#define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
298
Bard Liao90f601e2014-07-29 13:50:57 +0800299static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
Bard Liao07cf7cba2014-06-20 14:41:13 +0800300{
Bard Liao07cf7cba2014-06-20 14:41:13 +0800301 unsigned int val, buf;
302 int i;
303
304 *hp = false;
305 *mic = false;
306
307 if (rt286->pdata.cbj_en) {
Bard Liao90f601e2014-07-29 13:50:57 +0800308 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800309 *hp = buf & 0x80000000;
310 if (*hp) {
311 /* power on HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800312 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800313 RT286_POWER_CTRL1, 0x1001, 0x0);
314 /* power LDO1 */
Bard Liao90f601e2014-07-29 13:50:57 +0800315 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800316 RT286_POWER_CTRL2, 0x4, 0x4);
Bard Liao90f601e2014-07-29 13:50:57 +0800317 regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
318 regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800319
320 msleep(200);
321 i = 40;
322 while (((val & 0x0800) == 0) && (i > 0)) {
Bard Liao90f601e2014-07-29 13:50:57 +0800323 regmap_read(rt286->regmap,
324 RT286_CBJ_CTRL2, &val);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800325 i--;
326 msleep(20);
327 }
328
329 if (0x0400 == (val & 0x0700)) {
330 *mic = false;
331
Bard Liao90f601e2014-07-29 13:50:57 +0800332 regmap_write(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800333 RT286_SET_MIC1, 0x20);
334 /* power off HV,VERF */
Bard Liao90f601e2014-07-29 13:50:57 +0800335 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800336 RT286_POWER_CTRL1, 0x1001, 0x1001);
Bard Liao90f601e2014-07-29 13:50:57 +0800337 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800338 RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
Bard Liao90f601e2014-07-29 13:50:57 +0800339 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800340 RT286_CBJ_CTRL1, 0x0030, 0x0000);
Bard Liao90f601e2014-07-29 13:50:57 +0800341 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800342 RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
343 } else if ((0x0200 == (val & 0x0700)) ||
344 (0x0100 == (val & 0x0700))) {
345 *mic = true;
Bard Liao90f601e2014-07-29 13:50:57 +0800346 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800347 RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
Bard Liao90f601e2014-07-29 13:50:57 +0800348 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800349 RT286_CBJ_CTRL1, 0x0030, 0x0020);
Bard Liao90f601e2014-07-29 13:50:57 +0800350 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800351 RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
352 } else {
353 *mic = false;
354 }
355
Bard Liao90f601e2014-07-29 13:50:57 +0800356 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800357 RT286_MISC_CTRL1,
358 0x0060, 0x0000);
359 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800360 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800361 RT286_MISC_CTRL1,
362 0x0060, 0x0020);
Bard Liao90f601e2014-07-29 13:50:57 +0800363 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800364 RT286_A_BIAS_CTRL3,
365 0xc000, 0x8000);
Bard Liao90f601e2014-07-29 13:50:57 +0800366 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800367 RT286_CBJ_CTRL1,
368 0x0030, 0x0020);
Bard Liao90f601e2014-07-29 13:50:57 +0800369 regmap_update_bits(rt286->regmap,
Bard Liao07cf7cba2014-06-20 14:41:13 +0800370 RT286_A_BIAS_CTRL2,
371 0xc000, 0x8000);
372
373 *mic = false;
374 }
375 } else {
Bard Liao90f601e2014-07-29 13:50:57 +0800376 regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800377 *hp = buf & 0x80000000;
Bard Liao90f601e2014-07-29 13:50:57 +0800378 regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800379 *mic = buf & 0x80000000;
380 }
381
382 return 0;
383}
384
385static void rt286_jack_detect_work(struct work_struct *work)
386{
387 struct rt286_priv *rt286 =
388 container_of(work, struct rt286_priv, jack_detect_work.work);
389 int status = 0;
390 bool hp = false;
391 bool mic = false;
392
Bard Liao90f601e2014-07-29 13:50:57 +0800393 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800394
395 if (hp == true)
396 status |= SND_JACK_HEADPHONE;
397
398 if (mic == true)
399 status |= SND_JACK_MICROPHONE;
400
401 snd_soc_jack_report(rt286->jack, status,
402 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
403}
404
405int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
406{
407 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
408
409 rt286->jack = jack;
410
411 /* Send an initial empty report */
412 snd_soc_jack_report(rt286->jack, 0,
413 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
414
415 return 0;
416}
417EXPORT_SYMBOL_GPL(rt286_mic_detect);
418
419static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
420static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
421
422static const struct snd_kcontrol_new rt286_snd_controls[] = {
423 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
424 RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
425 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
426 RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
427 SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
428 0, 0x3, 0, mic_vol_tlv),
429 SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
430 RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
431};
432
433/* Digital Mixer */
434static const struct snd_kcontrol_new rt286_front_mix[] = {
435 SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
436 RT286_MUTE_SFT, 1, 1),
437 SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
438 RT286_MUTE_SFT, 1, 1),
439};
440
441/* Analog Input Mixer */
442static const struct snd_kcontrol_new rt286_rec_mix[] = {
443 SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
444 RT286_MUTE_SFT, 1, 1),
445 SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
446 RT286_MUTE_SFT, 1, 1),
447 SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
448 RT286_MUTE_SFT, 1, 1),
449 SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
450 RT286_MUTE_SFT, 1, 1),
451};
452
453static const struct snd_kcontrol_new spo_enable_control =
454 SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
455 RT286_SET_PIN_SFT, 1, 0);
456
457static const struct snd_kcontrol_new hpol_enable_control =
458 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
459 RT286_MUTE_SFT, 1, 1);
460
461static const struct snd_kcontrol_new hpor_enable_control =
462 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
463 RT286_MUTE_SFT, 1, 1);
464
465/* ADC0 source */
466static const char * const rt286_adc_src[] = {
467 "Mic", "RECMIX", "Dmic"
468};
469
470static const int rt286_adc_values[] = {
471 0, 4, 5,
472};
473
474static SOC_VALUE_ENUM_SINGLE_DECL(
475 rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
476 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
477
478static const struct snd_kcontrol_new rt286_adc0_mux =
479 SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
480
481static SOC_VALUE_ENUM_SINGLE_DECL(
482 rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
483 RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
484
485static const struct snd_kcontrol_new rt286_adc1_mux =
486 SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
487
488static const char * const rt286_dac_src[] = {
489 "Front", "Surround"
490};
491/* HP-OUT source */
492static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
493 0, rt286_dac_src);
494
495static const struct snd_kcontrol_new rt286_hpo_mux =
496SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
497
498/* SPK-OUT source */
499static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
500 0, rt286_dac_src);
501
502static const struct snd_kcontrol_new rt286_spo_mux =
503SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
504
505static int rt286_spk_event(struct snd_soc_dapm_widget *w,
506 struct snd_kcontrol *kcontrol, int event)
507{
508 struct snd_soc_codec *codec = w->codec;
509
510 switch (event) {
511 case SND_SOC_DAPM_POST_PMU:
512 snd_soc_write(codec,
513 RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
514 break;
515 case SND_SOC_DAPM_PRE_PMD:
516 snd_soc_write(codec,
517 RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
518 break;
519
520 default:
521 return 0;
522 }
523
524 return 0;
525}
526
527static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
528 struct snd_kcontrol *kcontrol, int event)
529{
530 struct snd_soc_codec *codec = w->codec;
531
532 switch (event) {
533 case SND_SOC_DAPM_POST_PMU:
534 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
535 break;
536 case SND_SOC_DAPM_PRE_PMD:
537 snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
538 break;
539 default:
540 return 0;
541 }
542
543 return 0;
544}
545
546static int rt286_adc_event(struct snd_soc_dapm_widget *w,
547 struct snd_kcontrol *kcontrol, int event)
548{
549 struct snd_soc_codec *codec = w->codec;
550 unsigned int nid;
551
552 nid = (w->reg >> 20) & 0xff;
553
554 switch (event) {
555 case SND_SOC_DAPM_POST_PMU:
556 snd_soc_update_bits(codec,
557 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
558 0x7080, 0x7000);
559 break;
560 case SND_SOC_DAPM_PRE_PMD:
561 snd_soc_update_bits(codec,
562 VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
563 0x7080, 0x7080);
564 break;
565 default:
566 return 0;
567 }
568
569 return 0;
570}
571
572static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
573 /* Input Lines */
574 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
575 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
576 SND_SOC_DAPM_INPUT("MIC1"),
577 SND_SOC_DAPM_INPUT("LINE1"),
578 SND_SOC_DAPM_INPUT("Beep"),
579
580 /* DMIC */
581 SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
582 NULL, 0, rt286_set_dmic1_event,
583 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
584 SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
585 NULL, 0),
586 SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
587 0, 0, NULL, 0),
588
589 /* REC Mixer */
590 SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
591 rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
592
593 /* ADCs */
594 SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
595 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
596
597 /* ADC Mux */
598 SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
599 &rt286_adc0_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD |
600 SND_SOC_DAPM_POST_PMU),
601 SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
602 &rt286_adc1_mux, rt286_adc_event, SND_SOC_DAPM_PRE_PMD |
603 SND_SOC_DAPM_POST_PMU),
604
605 /* Audio Interface */
606 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
607 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
608 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
609 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
610
611 /* Output Side */
612 /* DACs */
613 SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
614 SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
615
616 /* Output Mux */
617 SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
618 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
619
620 SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
621 RT286_SET_PIN_SFT, 0, NULL, 0),
622
623 /* Output Mixer */
624 SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
625 rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
626 SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
627 NULL, 0),
628
629 /* Output Pga */
630 SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
631 &spo_enable_control, rt286_spk_event,
632 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
633 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
634 &hpol_enable_control),
635 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
636 &hpor_enable_control),
637
638 /* Output Lines */
639 SND_SOC_DAPM_OUTPUT("SPOL"),
640 SND_SOC_DAPM_OUTPUT("SPOR"),
641 SND_SOC_DAPM_OUTPUT("HPO Pin"),
642 SND_SOC_DAPM_OUTPUT("SPDIF"),
643};
644
645static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
646 {"DMIC1", NULL, "DMIC1 Pin"},
647 {"DMIC2", NULL, "DMIC2 Pin"},
648 {"DMIC1", NULL, "DMIC Receiver"},
649 {"DMIC2", NULL, "DMIC Receiver"},
650
651 {"RECMIX", "Beep Switch", "Beep"},
652 {"RECMIX", "Line1 Switch", "LINE1"},
653 {"RECMIX", "Mic1 Switch", "MIC1"},
654
655 {"ADC 0 Mux", "Dmic", "DMIC1"},
656 {"ADC 0 Mux", "RECMIX", "RECMIX"},
657 {"ADC 0 Mux", "Mic", "MIC1"},
658 {"ADC 1 Mux", "Dmic", "DMIC2"},
659 {"ADC 1 Mux", "RECMIX", "RECMIX"},
660 {"ADC 1 Mux", "Mic", "MIC1"},
661
662 {"ADC 0", NULL, "ADC 0 Mux"},
663 {"ADC 1", NULL, "ADC 1 Mux"},
664
665 {"AIF1TX", NULL, "ADC 0"},
666 {"AIF2TX", NULL, "ADC 1"},
667
668 {"DAC 0", NULL, "AIF1RX"},
669 {"DAC 1", NULL, "AIF2RX"},
670
671 {"Front", "DAC Switch", "DAC 0"},
672 {"Front", "RECMIX Switch", "RECMIX"},
673
674 {"Surround", NULL, "DAC 1"},
675
676 {"SPK Mux", "Front", "Front"},
677 {"SPK Mux", "Surround", "Surround"},
678
679 {"HPO Mux", "Front", "Front"},
680 {"HPO Mux", "Surround", "Surround"},
681
682 {"SPO", "Switch", "SPK Mux"},
683 {"HPO L", "Switch", "HPO Mux"},
684 {"HPO R", "Switch", "HPO Mux"},
685 {"HPO L", NULL, "HP Power"},
686 {"HPO R", NULL, "HP Power"},
687
688 {"SPOL", NULL, "SPO"},
689 {"SPOR", NULL, "SPO"},
690 {"HPO Pin", NULL, "HPO L"},
691 {"HPO Pin", NULL, "HPO R"},
692};
693
694static int rt286_hw_params(struct snd_pcm_substream *substream,
695 struct snd_pcm_hw_params *params,
696 struct snd_soc_dai *dai)
697{
698 struct snd_soc_codec *codec = dai->codec;
699 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
700 unsigned int val = 0;
701 int d_len_code;
702
703 switch (params_rate(params)) {
704 /* bit 14 0:48K 1:44.1K */
705 case 44100:
706 val |= 0x4000;
707 break;
708 case 48000:
709 break;
710 default:
711 dev_err(codec->dev, "Unsupported sample rate %d\n",
712 params_rate(params));
713 return -EINVAL;
714 }
715 switch (rt286->sys_clk) {
716 case 12288000:
717 case 24576000:
718 if (params_rate(params) != 48000) {
719 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
720 params_rate(params), rt286->sys_clk);
721 return -EINVAL;
722 }
723 break;
724 case 11289600:
725 case 22579200:
726 if (params_rate(params) != 44100) {
727 dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
728 params_rate(params), rt286->sys_clk);
729 return -EINVAL;
730 }
731 break;
732 }
733
734 if (params_channels(params) <= 16) {
735 /* bit 3:0 Number of Channel */
736 val |= (params_channels(params) - 1);
737 } else {
738 dev_err(codec->dev, "Unsupported channels %d\n",
739 params_channels(params));
740 return -EINVAL;
741 }
742
743 d_len_code = 0;
744 switch (params_width(params)) {
745 /* bit 6:4 Bits per Sample */
746 case 16:
747 d_len_code = 0;
748 val |= (0x1 << 4);
749 break;
750 case 32:
751 d_len_code = 2;
752 val |= (0x4 << 4);
753 break;
754 case 20:
755 d_len_code = 1;
756 val |= (0x2 << 4);
757 break;
758 case 24:
759 d_len_code = 2;
760 val |= (0x3 << 4);
761 break;
762 case 8:
763 d_len_code = 3;
764 break;
765 default:
766 return -EINVAL;
767 }
768
769 snd_soc_update_bits(codec,
770 RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
771 dev_dbg(codec->dev, "format val = 0x%x\n", val);
772
773 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
774 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
775 else
776 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
777
778 return 0;
779}
780
781static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
782{
783 struct snd_soc_codec *codec = dai->codec;
784
785 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
786 case SND_SOC_DAIFMT_CBM_CFM:
787 snd_soc_update_bits(codec,
788 RT286_I2S_CTRL1, 0x800, 0x800);
789 break;
790 case SND_SOC_DAIFMT_CBS_CFS:
791 snd_soc_update_bits(codec,
792 RT286_I2S_CTRL1, 0x800, 0x0);
793 break;
794 default:
795 return -EINVAL;
796 }
797
798 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
799 case SND_SOC_DAIFMT_I2S:
800 snd_soc_update_bits(codec,
801 RT286_I2S_CTRL1, 0x300, 0x0);
802 break;
803 case SND_SOC_DAIFMT_LEFT_J:
804 snd_soc_update_bits(codec,
805 RT286_I2S_CTRL1, 0x300, 0x1 << 8);
806 break;
807 case SND_SOC_DAIFMT_DSP_A:
808 snd_soc_update_bits(codec,
809 RT286_I2S_CTRL1, 0x300, 0x2 << 8);
810 break;
811 case SND_SOC_DAIFMT_DSP_B:
812 snd_soc_update_bits(codec,
813 RT286_I2S_CTRL1, 0x300, 0x3 << 8);
814 break;
815 default:
816 return -EINVAL;
817 }
818 /* bit 15 Stream Type 0:PCM 1:Non-PCM */
819 snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
820 snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
821
822 return 0;
823}
824
825static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
826 int clk_id, unsigned int freq, int dir)
827{
828 struct snd_soc_codec *codec = dai->codec;
829 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
830
831 dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
832
833 if (RT286_SCLK_S_MCLK == clk_id) {
834 snd_soc_update_bits(codec,
835 RT286_I2S_CTRL2, 0x0100, 0x0);
836 snd_soc_update_bits(codec,
837 RT286_PLL_CTRL1, 0x20, 0x20);
838 } else {
839 snd_soc_update_bits(codec,
840 RT286_I2S_CTRL2, 0x0100, 0x0100);
841 snd_soc_update_bits(codec,
842 RT286_PLL_CTRL, 0x4, 0x4);
843 snd_soc_update_bits(codec,
844 RT286_PLL_CTRL1, 0x20, 0x0);
845 }
846
847 switch (freq) {
848 case 19200000:
849 if (RT286_SCLK_S_MCLK == clk_id) {
850 dev_err(codec->dev, "Should not use MCLK\n");
851 return -EINVAL;
852 }
853 snd_soc_update_bits(codec,
854 RT286_I2S_CTRL2, 0x40, 0x40);
855 break;
856 case 24000000:
857 if (RT286_SCLK_S_MCLK == clk_id) {
858 dev_err(codec->dev, "Should not use MCLK\n");
859 return -EINVAL;
860 }
861 snd_soc_update_bits(codec,
862 RT286_I2S_CTRL2, 0x40, 0x0);
863 break;
864 case 12288000:
865 case 11289600:
866 snd_soc_update_bits(codec,
867 RT286_I2S_CTRL2, 0x8, 0x0);
868 snd_soc_update_bits(codec,
869 RT286_CLK_DIV, 0xfc1e, 0x0004);
870 break;
871 case 24576000:
872 case 22579200:
873 snd_soc_update_bits(codec,
874 RT286_I2S_CTRL2, 0x8, 0x8);
875 snd_soc_update_bits(codec,
876 RT286_CLK_DIV, 0xfc1e, 0x5406);
877 break;
878 default:
879 dev_err(codec->dev, "Unsupported system clock\n");
880 return -EINVAL;
881 }
882
883 rt286->sys_clk = freq;
884
885 return 0;
886}
887
888static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
889{
890 struct snd_soc_codec *codec = dai->codec;
891
892 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
893 if (50 == ratio)
894 snd_soc_update_bits(codec,
895 RT286_I2S_CTRL1, 0x1000, 0x1000);
896 else
897 snd_soc_update_bits(codec,
898 RT286_I2S_CTRL1, 0x1000, 0x0);
899
900
901 return 0;
902}
903
904static int rt286_set_bias_level(struct snd_soc_codec *codec,
905 enum snd_soc_bias_level level)
906{
907 switch (level) {
908 case SND_SOC_BIAS_PREPARE:
Bard Liaobc6c4e42014-07-07 19:15:30 +0800909 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Bard Liao07cf7cba2014-06-20 14:41:13 +0800910 snd_soc_write(codec,
911 RT286_SET_AUDIO_POWER, AC_PWRST_D0);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800912 snd_soc_update_bits(codec,
913 RT286_DC_GAIN, 0x200, 0x200);
914 }
915 break;
916
917 case SND_SOC_BIAS_ON:
918 mdelay(10);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800919 break;
920
921 case SND_SOC_BIAS_STANDBY:
922 snd_soc_write(codec,
923 RT286_SET_AUDIO_POWER, AC_PWRST_D3);
Bard Liaobc6c4e42014-07-07 19:15:30 +0800924 snd_soc_update_bits(codec,
925 RT286_DC_GAIN, 0x200, 0x0);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800926 break;
927
928 default:
929 break;
930 }
931 codec->dapm.bias_level = level;
932
933 return 0;
934}
935
936static irqreturn_t rt286_irq(int irq, void *data)
937{
938 struct rt286_priv *rt286 = data;
939 bool hp = false;
940 bool mic = false;
941 int status = 0;
942
Bard Liao90f601e2014-07-29 13:50:57 +0800943 rt286_jack_detect(rt286, &hp, &mic);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800944
945 /* Clear IRQ */
Bard Liao90f601e2014-07-29 13:50:57 +0800946 regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800947
948 if (hp == true)
949 status |= SND_JACK_HEADPHONE;
950
951 if (mic == true)
952 status |= SND_JACK_MICROPHONE;
953
954 snd_soc_jack_report(rt286->jack, status,
955 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
956
957 pm_wakeup_event(&rt286->i2c->dev, 300);
958
959 return IRQ_HANDLED;
960}
961
962static int rt286_probe(struct snd_soc_codec *codec)
963{
964 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
Bard Liao07cf7cba2014-06-20 14:41:13 +0800965
966 codec->dapm.bias_level = SND_SOC_BIAS_OFF;
Bard Liao90f601e2014-07-29 13:50:57 +0800967
968 if (rt286->i2c->irq) {
969 regmap_update_bits(rt286->regmap,
970 RT286_IRQ_CTRL, 0x2, 0x2);
971
972 INIT_DELAYED_WORK(&rt286->jack_detect_work,
973 rt286_jack_detect_work);
974 schedule_delayed_work(&rt286->jack_detect_work,
975 msecs_to_jiffies(1250));
976 }
Bard Liao07cf7cba2014-06-20 14:41:13 +0800977
Bard Liao07cf7cba2014-06-20 14:41:13 +0800978 return 0;
979}
980
981static int rt286_remove(struct snd_soc_codec *codec)
982{
983 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
984
985 cancel_delayed_work_sync(&rt286->jack_detect_work);
986
987 return 0;
988}
989
990#ifdef CONFIG_PM
991static int rt286_suspend(struct snd_soc_codec *codec)
992{
993 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
994
995 regcache_cache_only(rt286->regmap, true);
996 regcache_mark_dirty(rt286->regmap);
997
998 return 0;
999}
1000
1001static int rt286_resume(struct snd_soc_codec *codec)
1002{
1003 struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
1004
1005 regcache_cache_only(rt286->regmap, false);
1006 rt286_index_sync(codec);
1007 regcache_sync(rt286->regmap);
1008
1009 return 0;
1010}
1011#else
1012#define rt286_suspend NULL
1013#define rt286_resume NULL
1014#endif
1015
1016#define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1017#define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1018 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1019
1020static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
1021 .hw_params = rt286_hw_params,
1022 .set_fmt = rt286_set_dai_fmt,
1023 .set_sysclk = rt286_set_dai_sysclk,
1024 .set_bclk_ratio = rt286_set_bclk_ratio,
1025};
1026
1027static struct snd_soc_dai_driver rt286_dai[] = {
1028 {
1029 .name = "rt286-aif1",
1030 .id = RT286_AIF1,
1031 .playback = {
1032 .stream_name = "AIF1 Playback",
1033 .channels_min = 1,
1034 .channels_max = 2,
1035 .rates = RT286_STEREO_RATES,
1036 .formats = RT286_FORMATS,
1037 },
1038 .capture = {
1039 .stream_name = "AIF1 Capture",
1040 .channels_min = 1,
1041 .channels_max = 2,
1042 .rates = RT286_STEREO_RATES,
1043 .formats = RT286_FORMATS,
1044 },
1045 .ops = &rt286_aif_dai_ops,
1046 .symmetric_rates = 1,
1047 },
1048 {
1049 .name = "rt286-aif2",
1050 .id = RT286_AIF2,
1051 .playback = {
1052 .stream_name = "AIF2 Playback",
1053 .channels_min = 1,
1054 .channels_max = 2,
1055 .rates = RT286_STEREO_RATES,
1056 .formats = RT286_FORMATS,
1057 },
1058 .capture = {
1059 .stream_name = "AIF2 Capture",
1060 .channels_min = 1,
1061 .channels_max = 2,
1062 .rates = RT286_STEREO_RATES,
1063 .formats = RT286_FORMATS,
1064 },
1065 .ops = &rt286_aif_dai_ops,
1066 .symmetric_rates = 1,
1067 },
1068
1069};
1070
1071static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
1072 .probe = rt286_probe,
1073 .remove = rt286_remove,
1074 .suspend = rt286_suspend,
1075 .resume = rt286_resume,
1076 .set_bias_level = rt286_set_bias_level,
1077 .idle_bias_off = true,
1078 .controls = rt286_snd_controls,
1079 .num_controls = ARRAY_SIZE(rt286_snd_controls),
1080 .dapm_widgets = rt286_dapm_widgets,
1081 .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
1082 .dapm_routes = rt286_dapm_routes,
1083 .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
1084};
1085
1086static const struct regmap_config rt286_regmap = {
1087 .reg_bits = 32,
1088 .val_bits = 32,
1089 .max_register = 0x02370100,
1090 .volatile_reg = rt286_volatile_register,
1091 .readable_reg = rt286_readable_register,
1092 .reg_write = rt286_hw_write,
1093 .reg_read = rt286_hw_read,
1094 .cache_type = REGCACHE_RBTREE,
1095 .reg_defaults = rt286_reg,
1096 .num_reg_defaults = ARRAY_SIZE(rt286_reg),
1097};
1098
1099static const struct i2c_device_id rt286_i2c_id[] = {
1100 {"rt286", 0},
1101 {}
1102};
1103MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
1104
1105static const struct acpi_device_id rt286_acpi_match[] = {
1106 { "INT343A", 0 },
1107 {},
1108};
1109MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
1110
1111static int rt286_i2c_probe(struct i2c_client *i2c,
1112 const struct i2c_device_id *id)
1113{
1114 struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
1115 struct rt286_priv *rt286;
Bard Liao61a414c2014-07-07 16:48:38 +08001116 int i, ret;
Bard Liao07cf7cba2014-06-20 14:41:13 +08001117
1118 rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
1119 GFP_KERNEL);
1120 if (NULL == rt286)
1121 return -ENOMEM;
1122
1123 rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
1124 if (IS_ERR(rt286->regmap)) {
1125 ret = PTR_ERR(rt286->regmap);
1126 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1127 ret);
1128 return ret;
1129 }
1130
Bard Liao4b21768a2014-07-07 16:48:37 +08001131 regmap_read(rt286->regmap,
1132 RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
1133 if (ret != RT286_VENDOR_ID) {
1134 dev_err(&i2c->dev,
1135 "Device with ID register %x is not rt286\n", ret);
1136 return -ENODEV;
1137 }
1138
Bard Liao07cf7cba2014-06-20 14:41:13 +08001139 rt286->index_cache = rt286_index_def;
1140 rt286->i2c = i2c;
1141 i2c_set_clientdata(i2c, rt286);
1142
1143 if (pdata)
1144 rt286->pdata = *pdata;
1145
Bard Liao61a414c2014-07-07 16:48:38 +08001146 regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
1147
1148 for (i = 0; i < RT286_POWER_REG_LEN; i++)
1149 regmap_write(rt286->regmap,
1150 RT286_SET_POWER(rt286_support_power_controls[i]),
1151 AC_PWRST_D1);
1152
1153 if (!rt286->pdata.cbj_en) {
1154 regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
1155 regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
1156 regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
1157 regmap_update_bits(rt286->regmap,
1158 RT286_CBJ_CTRL1, 0xf000, 0xb000);
1159 } else {
1160 regmap_update_bits(rt286->regmap,
1161 RT286_CBJ_CTRL1, 0xf000, 0x5000);
1162 }
1163
1164 mdelay(10);
1165
1166 if (!rt286->pdata.gpio2_en)
1167 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
1168 else
1169 regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
1170
1171 mdelay(10);
1172
1173 /*Power down LDO2*/
1174 regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0x8, 0x0);
1175
Bard Liaobc6c4e42014-07-07 19:15:30 +08001176 /*Set depop parameter*/
1177 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
1178 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
1179 regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
1180
Bard Liao61a414c2014-07-07 16:48:38 +08001181 if (rt286->i2c->irq) {
Bard Liao61a414c2014-07-07 16:48:38 +08001182 ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
1183 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
1184 if (ret != 0) {
1185 dev_err(&i2c->dev,
1186 "Failed to reguest IRQ: %d\n", ret);
1187 return ret;
1188 }
1189 }
1190
Bard Liao07cf7cba2014-06-20 14:41:13 +08001191 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
1192 rt286_dai, ARRAY_SIZE(rt286_dai));
1193
1194 return ret;
1195}
1196
1197static int rt286_i2c_remove(struct i2c_client *i2c)
1198{
1199 struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
1200
1201 if (i2c->irq)
1202 free_irq(i2c->irq, rt286);
1203 snd_soc_unregister_codec(&i2c->dev);
1204
1205 return 0;
1206}
1207
1208
Bard Liao23c4fd52014-07-14 10:18:04 +08001209static struct i2c_driver rt286_i2c_driver = {
Bard Liao07cf7cba2014-06-20 14:41:13 +08001210 .driver = {
1211 .name = "rt286",
1212 .owner = THIS_MODULE,
1213 .acpi_match_table = ACPI_PTR(rt286_acpi_match),
1214 },
1215 .probe = rt286_i2c_probe,
1216 .remove = rt286_i2c_remove,
1217 .id_table = rt286_i2c_id,
1218};
1219
1220module_i2c_driver(rt286_i2c_driver);
1221
1222MODULE_DESCRIPTION("ASoC RT286 driver");
1223MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1224MODULE_LICENSE("GPL");