Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Intel GTT (Graphics Translation Table) routines |
| 3 | * |
| 4 | * Caveat: This driver implements the linux agp interface, but this is far from |
| 5 | * a agp driver! GTT support ended up here for purely historical reasons: The |
| 6 | * old userspace intel graphics drivers needed an interface to map memory into |
| 7 | * the GTT. And the drm provides a default interface for graphic devices sitting |
| 8 | * on an agp port. So it made sense to fake the GTT support as an agp port to |
| 9 | * avoid having to create a new api. |
| 10 | * |
| 11 | * With gem this does not make much sense anymore, just needlessly complicates |
| 12 | * the code. But as long as the old graphics stack is still support, it's stuck |
| 13 | * here. |
| 14 | * |
| 15 | * /fairy-tale-mode off |
| 16 | */ |
| 17 | |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/pagemap.h> |
| 23 | #include <linux/agp_backend.h> |
| 24 | #include <asm/smp.h> |
| 25 | #include "agp.h" |
| 26 | #include "intel-agp.h" |
| 27 | #include <linux/intel-gtt.h> |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 28 | #include <drm/intel-gtt.h> |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 29 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 30 | /* |
| 31 | * If we have Intel graphics, we're not going to have anything other than |
| 32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent |
| 33 | * on the Intel IOMMU support (CONFIG_DMAR). |
| 34 | * Only newer chipsets need to bother with this, of course. |
| 35 | */ |
| 36 | #ifdef CONFIG_DMAR |
| 37 | #define USE_PCI_DMA_API 1 |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 38 | #else |
| 39 | #define USE_PCI_DMA_API 0 |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 40 | #endif |
| 41 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 42 | #define AGP_DCACHE_MEMORY 1 |
| 43 | #define AGP_PHYS_MEMORY 2 |
| 44 | #define INTEL_AGP_CACHED_MEMORY 3 |
| 45 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 46 | struct intel_gtt_driver { |
| 47 | unsigned int gen : 8; |
| 48 | unsigned int is_g33 : 1; |
| 49 | unsigned int is_pineview : 1; |
| 50 | unsigned int is_ironlake : 1; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 51 | unsigned int has_pgtbl_enable : 1; |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 52 | unsigned int dma_mask_size : 8; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 53 | /* Chipset specific GTT setup */ |
| 54 | int (*setup)(void); |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 55 | /* This should undo anything done in ->setup() save the unmapping |
| 56 | * of the mmio register file, that's done in the generic code. */ |
| 57 | void (*cleanup)(void); |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 58 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
| 59 | /* Flags is a more or less chipset specific opaque value. |
| 60 | * For chipsets that need to support old ums (non-gem) code, this |
| 61 | * needs to be identical to the various supported agp memory types! */ |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 62 | bool (*check_flags)(unsigned int flags); |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 63 | void (*chipset_flush)(void); |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 64 | }; |
| 65 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 66 | static struct _intel_private { |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 67 | struct intel_gtt base; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 68 | const struct intel_gtt_driver *driver; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 69 | struct pci_dev *pcidev; /* device one */ |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 70 | struct pci_dev *bridge_dev; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 71 | u8 __iomem *registers; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 72 | phys_addr_t gtt_bus_addr; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 73 | phys_addr_t gma_bus_addr; |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 74 | u32 PGETBL_save; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 75 | u32 __iomem *gtt; /* I915G */ |
| 76 | int num_dcache_entries; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 77 | union { |
| 78 | void __iomem *i9xx_flush_page; |
| 79 | void *i8xx_flush_page; |
| 80 | }; |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 81 | char *i81x_gtt_table; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 82 | struct page *i8xx_page; |
| 83 | struct resource ifp_resource; |
| 84 | int resource_valid; |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 85 | struct page *scratch_page; |
| 86 | dma_addr_t scratch_page_dma; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 87 | } intel_private; |
| 88 | |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 89 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
| 90 | off_t pg_start, int type); |
| 91 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 92 | #define INTEL_GTT_GEN intel_private.driver->gen |
| 93 | #define IS_G33 intel_private.driver->is_g33 |
| 94 | #define IS_PINEVIEW intel_private.driver->is_pineview |
| 95 | #define IS_IRONLAKE intel_private.driver->is_ironlake |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 96 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 97 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 98 | static void intel_agp_free_sglist(struct agp_memory *mem) |
| 99 | { |
| 100 | struct sg_table st; |
| 101 | |
| 102 | st.sgl = mem->sg_list; |
| 103 | st.orig_nents = st.nents = mem->page_count; |
| 104 | |
| 105 | sg_free_table(&st); |
| 106 | |
| 107 | mem->sg_list = NULL; |
| 108 | mem->num_sg = 0; |
| 109 | } |
| 110 | |
| 111 | static int intel_agp_map_memory(struct agp_memory *mem) |
| 112 | { |
| 113 | struct sg_table st; |
| 114 | struct scatterlist *sg; |
| 115 | int i; |
| 116 | |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 117 | if (mem->sg_list) |
| 118 | return 0; /* already mapped (for e.g. resume */ |
| 119 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 120 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); |
| 121 | |
| 122 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 123 | goto err; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 124 | |
| 125 | mem->sg_list = sg = st.sgl; |
| 126 | |
| 127 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) |
| 128 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); |
| 129 | |
| 130 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, |
| 131 | mem->page_count, PCI_DMA_BIDIRECTIONAL); |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 132 | if (unlikely(!mem->num_sg)) |
| 133 | goto err; |
| 134 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 135 | return 0; |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 136 | |
| 137 | err: |
| 138 | sg_free_table(&st); |
| 139 | return -ENOMEM; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static void intel_agp_unmap_memory(struct agp_memory *mem) |
| 143 | { |
| 144 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
| 145 | |
| 146 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, |
| 147 | mem->page_count, PCI_DMA_BIDIRECTIONAL); |
| 148 | intel_agp_free_sglist(mem); |
| 149 | } |
| 150 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 151 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 152 | { |
| 153 | return; |
| 154 | } |
| 155 | |
| 156 | /* Exists to support ARGB cursors */ |
| 157 | static struct page *i8xx_alloc_pages(void) |
| 158 | { |
| 159 | struct page *page; |
| 160 | |
| 161 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
| 162 | if (page == NULL) |
| 163 | return NULL; |
| 164 | |
| 165 | if (set_pages_uc(page, 4) < 0) { |
| 166 | set_pages_wb(page, 4); |
| 167 | __free_pages(page, 2); |
| 168 | return NULL; |
| 169 | } |
| 170 | get_page(page); |
| 171 | atomic_inc(&agp_bridge->current_memory_agp); |
| 172 | return page; |
| 173 | } |
| 174 | |
| 175 | static void i8xx_destroy_pages(struct page *page) |
| 176 | { |
| 177 | if (page == NULL) |
| 178 | return; |
| 179 | |
| 180 | set_pages_wb(page, 4); |
| 181 | put_page(page); |
| 182 | __free_pages(page, 2); |
| 183 | atomic_dec(&agp_bridge->current_memory_agp); |
| 184 | } |
| 185 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 186 | #define I810_GTT_ORDER 4 |
| 187 | static int i810_setup(void) |
| 188 | { |
| 189 | u32 reg_addr; |
| 190 | char *gtt_table; |
| 191 | |
| 192 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ |
| 193 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); |
| 194 | if (gtt_table == NULL) |
| 195 | return -ENOMEM; |
| 196 | intel_private.i81x_gtt_table = gtt_table; |
| 197 | |
| 198 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); |
| 199 | reg_addr &= 0xfff80000; |
| 200 | |
| 201 | intel_private.registers = ioremap(reg_addr, KB(64)); |
| 202 | if (!intel_private.registers) |
| 203 | return -ENOMEM; |
| 204 | |
| 205 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, |
| 206 | intel_private.registers+I810_PGETBL_CTL); |
| 207 | |
| 208 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
| 209 | |
| 210 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
| 211 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
| 212 | dev_info(&intel_private.pcidev->dev, |
| 213 | "detected 4MB dedicated video ram\n"); |
| 214 | intel_private.num_dcache_entries = 1024; |
| 215 | } |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
| 220 | static void i810_cleanup(void) |
| 221 | { |
| 222 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
| 223 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); |
| 224 | } |
| 225 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 226 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
| 227 | int type) |
| 228 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 229 | int i; |
| 230 | |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 231 | if (type == AGP_DCACHE_MEMORY) { |
| 232 | if ((pg_start + mem->page_count) |
| 233 | > intel_private.num_dcache_entries) |
| 234 | return -EINVAL; |
| 235 | |
| 236 | if (!mem->is_flushed) |
| 237 | global_cache_flush(); |
| 238 | |
| 239 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
| 240 | dma_addr_t addr = i << PAGE_SHIFT; |
| 241 | intel_private.driver->write_entry(addr, |
| 242 | i, type); |
| 243 | } |
| 244 | readl(intel_private.gtt+i-1); |
| 245 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 246 | return 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 247 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 248 | |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 249 | return intel_fake_agp_insert_entries(mem, pg_start, type); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | /* |
| 253 | * The i810/i830 requires a physical address to program its mouse |
| 254 | * pointer into hardware. |
| 255 | * However the Xserver still writes to it through the agp aperture. |
| 256 | */ |
| 257 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) |
| 258 | { |
| 259 | struct agp_memory *new; |
| 260 | struct page *page; |
| 261 | |
| 262 | switch (pg_count) { |
| 263 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
| 264 | break; |
| 265 | case 4: |
| 266 | /* kludge to get 4 physical pages for ARGB cursor */ |
| 267 | page = i8xx_alloc_pages(); |
| 268 | break; |
| 269 | default: |
| 270 | return NULL; |
| 271 | } |
| 272 | |
| 273 | if (page == NULL) |
| 274 | return NULL; |
| 275 | |
| 276 | new = agp_create_memory(pg_count); |
| 277 | if (new == NULL) |
| 278 | return NULL; |
| 279 | |
| 280 | new->pages[0] = page; |
| 281 | if (pg_count == 4) { |
| 282 | /* kludge to get 4 physical pages for ARGB cursor */ |
| 283 | new->pages[1] = new->pages[0] + 1; |
| 284 | new->pages[2] = new->pages[1] + 1; |
| 285 | new->pages[3] = new->pages[2] + 1; |
| 286 | } |
| 287 | new->page_count = pg_count; |
| 288 | new->num_scratch_pages = pg_count; |
| 289 | new->type = AGP_PHYS_MEMORY; |
| 290 | new->physical = page_to_phys(new->pages[0]); |
| 291 | return new; |
| 292 | } |
| 293 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 294 | static void intel_i810_free_by_type(struct agp_memory *curr) |
| 295 | { |
| 296 | agp_free_key(curr->key); |
| 297 | if (curr->type == AGP_PHYS_MEMORY) { |
| 298 | if (curr->page_count == 4) |
| 299 | i8xx_destroy_pages(curr->pages[0]); |
| 300 | else { |
| 301 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
| 302 | AGP_PAGE_DESTROY_UNMAP); |
| 303 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
| 304 | AGP_PAGE_DESTROY_FREE); |
| 305 | } |
| 306 | agp_free_page_array(curr); |
| 307 | } |
| 308 | kfree(curr); |
| 309 | } |
| 310 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 311 | static int intel_gtt_setup_scratch_page(void) |
| 312 | { |
| 313 | struct page *page; |
| 314 | dma_addr_t dma_addr; |
| 315 | |
| 316 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
| 317 | if (page == NULL) |
| 318 | return -ENOMEM; |
| 319 | get_page(page); |
| 320 | set_pages_uc(page, 1); |
| 321 | |
| 322 | if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { |
| 323 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
| 324 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 325 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) |
| 326 | return -EINVAL; |
| 327 | |
| 328 | intel_private.scratch_page_dma = dma_addr; |
| 329 | } else |
| 330 | intel_private.scratch_page_dma = page_to_phys(page); |
| 331 | |
| 332 | intel_private.scratch_page = page; |
| 333 | |
| 334 | return 0; |
| 335 | } |
| 336 | |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 337 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
| 338 | unsigned int flags) |
| 339 | { |
| 340 | u32 pte_flags = I810_PTE_VALID; |
| 341 | |
| 342 | switch (flags) { |
| 343 | case AGP_DCACHE_MEMORY: |
| 344 | pte_flags |= I810_PTE_LOCAL; |
| 345 | break; |
| 346 | case AGP_USER_CACHED_MEMORY: |
| 347 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
| 348 | break; |
| 349 | } |
| 350 | |
| 351 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 352 | } |
| 353 | |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 354 | static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = { |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 355 | {32, 8192, 3}, |
| 356 | {64, 16384, 4}, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 357 | {128, 32768, 5}, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 358 | {256, 65536, 6}, |
| 359 | {512, 131072, 7}, |
| 360 | }; |
| 361 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 362 | static unsigned int intel_gtt_stolen_size(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 363 | { |
| 364 | u16 gmch_ctrl; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 365 | u8 rdct; |
| 366 | int local = 0; |
| 367 | static const int ddt[4] = { 0, 16, 32, 64 }; |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 368 | unsigned int stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 369 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 370 | if (INTEL_GTT_GEN == 1) |
| 371 | return 0; /* no stolen mem on i81x */ |
| 372 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 373 | pci_read_config_word(intel_private.bridge_dev, |
| 374 | I830_GMCH_CTRL, &gmch_ctrl); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 375 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 376 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
| 377 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 378 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
| 379 | case I830_GMCH_GMS_STOLEN_512: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 380 | stolen_size = KB(512); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 381 | break; |
| 382 | case I830_GMCH_GMS_STOLEN_1024: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 383 | stolen_size = MB(1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 384 | break; |
| 385 | case I830_GMCH_GMS_STOLEN_8192: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 386 | stolen_size = MB(8); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 387 | break; |
| 388 | case I830_GMCH_GMS_LOCAL: |
| 389 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 390 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 391 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
| 392 | local = 1; |
| 393 | break; |
| 394 | default: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 395 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 396 | break; |
| 397 | } |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 398 | } else if (INTEL_GTT_GEN == 6) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 399 | /* |
| 400 | * SandyBridge has new memory control reg at 0x50.w |
| 401 | */ |
| 402 | u16 snb_gmch_ctl; |
| 403 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 404 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { |
| 405 | case SNB_GMCH_GMS_STOLEN_32M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 406 | stolen_size = MB(32); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 407 | break; |
| 408 | case SNB_GMCH_GMS_STOLEN_64M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 409 | stolen_size = MB(64); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 410 | break; |
| 411 | case SNB_GMCH_GMS_STOLEN_96M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 412 | stolen_size = MB(96); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 413 | break; |
| 414 | case SNB_GMCH_GMS_STOLEN_128M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 415 | stolen_size = MB(128); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 416 | break; |
| 417 | case SNB_GMCH_GMS_STOLEN_160M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 418 | stolen_size = MB(160); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 419 | break; |
| 420 | case SNB_GMCH_GMS_STOLEN_192M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 421 | stolen_size = MB(192); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 422 | break; |
| 423 | case SNB_GMCH_GMS_STOLEN_224M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 424 | stolen_size = MB(224); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 425 | break; |
| 426 | case SNB_GMCH_GMS_STOLEN_256M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 427 | stolen_size = MB(256); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 428 | break; |
| 429 | case SNB_GMCH_GMS_STOLEN_288M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 430 | stolen_size = MB(288); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 431 | break; |
| 432 | case SNB_GMCH_GMS_STOLEN_320M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 433 | stolen_size = MB(320); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 434 | break; |
| 435 | case SNB_GMCH_GMS_STOLEN_352M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 436 | stolen_size = MB(352); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 437 | break; |
| 438 | case SNB_GMCH_GMS_STOLEN_384M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 439 | stolen_size = MB(384); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 440 | break; |
| 441 | case SNB_GMCH_GMS_STOLEN_416M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 442 | stolen_size = MB(416); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 443 | break; |
| 444 | case SNB_GMCH_GMS_STOLEN_448M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 445 | stolen_size = MB(448); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 446 | break; |
| 447 | case SNB_GMCH_GMS_STOLEN_480M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 448 | stolen_size = MB(480); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 449 | break; |
| 450 | case SNB_GMCH_GMS_STOLEN_512M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 451 | stolen_size = MB(512); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 452 | break; |
| 453 | } |
| 454 | } else { |
| 455 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
| 456 | case I855_GMCH_GMS_STOLEN_1M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 457 | stolen_size = MB(1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 458 | break; |
| 459 | case I855_GMCH_GMS_STOLEN_4M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 460 | stolen_size = MB(4); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 461 | break; |
| 462 | case I855_GMCH_GMS_STOLEN_8M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 463 | stolen_size = MB(8); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 464 | break; |
| 465 | case I855_GMCH_GMS_STOLEN_16M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 466 | stolen_size = MB(16); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 467 | break; |
| 468 | case I855_GMCH_GMS_STOLEN_32M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 469 | stolen_size = MB(32); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 470 | break; |
| 471 | case I915_GMCH_GMS_STOLEN_48M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 472 | stolen_size = MB(48); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 473 | break; |
| 474 | case I915_GMCH_GMS_STOLEN_64M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 475 | stolen_size = MB(64); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 476 | break; |
| 477 | case G33_GMCH_GMS_STOLEN_128M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 478 | stolen_size = MB(128); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 479 | break; |
| 480 | case G33_GMCH_GMS_STOLEN_256M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 481 | stolen_size = MB(256); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 482 | break; |
| 483 | case INTEL_GMCH_GMS_STOLEN_96M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 484 | stolen_size = MB(96); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 485 | break; |
| 486 | case INTEL_GMCH_GMS_STOLEN_160M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 487 | stolen_size = MB(160); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 488 | break; |
| 489 | case INTEL_GMCH_GMS_STOLEN_224M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 490 | stolen_size = MB(224); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 491 | break; |
| 492 | case INTEL_GMCH_GMS_STOLEN_352M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 493 | stolen_size = MB(352); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 494 | break; |
| 495 | default: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 496 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 497 | break; |
| 498 | } |
| 499 | } |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 500 | |
Chris Wilson | 1b6064d | 2010-11-23 12:33:54 +0000 | [diff] [blame] | 501 | if (stolen_size > 0) { |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 502 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 503 | stolen_size / KB(1), local ? "local" : "stolen"); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 504 | } else { |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 505 | dev_info(&intel_private.bridge_dev->dev, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 506 | "no pre-allocated video memory detected\n"); |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 507 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 508 | } |
| 509 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 510 | return stolen_size; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 511 | } |
| 512 | |
Daniel Vetter | 2017284 | 2010-09-24 18:25:59 +0200 | [diff] [blame] | 513 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
| 514 | { |
| 515 | u32 pgetbl_ctl, pgetbl_ctl2; |
| 516 | |
| 517 | /* ensure that ppgtt is disabled */ |
| 518 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); |
| 519 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; |
| 520 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); |
| 521 | |
| 522 | /* write the new ggtt size */ |
| 523 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
| 524 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; |
| 525 | pgetbl_ctl |= size_flag; |
| 526 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); |
| 527 | } |
| 528 | |
| 529 | static unsigned int i965_gtt_total_entries(void) |
| 530 | { |
| 531 | int size; |
| 532 | u32 pgetbl_ctl; |
| 533 | u16 gmch_ctl; |
| 534 | |
| 535 | pci_read_config_word(intel_private.bridge_dev, |
| 536 | I830_GMCH_CTRL, &gmch_ctl); |
| 537 | |
| 538 | if (INTEL_GTT_GEN == 5) { |
| 539 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { |
| 540 | case G4x_GMCH_SIZE_1M: |
| 541 | case G4x_GMCH_SIZE_VT_1M: |
| 542 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); |
| 543 | break; |
| 544 | case G4x_GMCH_SIZE_VT_1_5M: |
| 545 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); |
| 546 | break; |
| 547 | case G4x_GMCH_SIZE_2M: |
| 548 | case G4x_GMCH_SIZE_VT_2M: |
| 549 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); |
| 550 | break; |
| 551 | } |
| 552 | } |
| 553 | |
| 554 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
| 555 | |
| 556 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { |
| 557 | case I965_PGETBL_SIZE_128KB: |
| 558 | size = KB(128); |
| 559 | break; |
| 560 | case I965_PGETBL_SIZE_256KB: |
| 561 | size = KB(256); |
| 562 | break; |
| 563 | case I965_PGETBL_SIZE_512KB: |
| 564 | size = KB(512); |
| 565 | break; |
| 566 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ |
| 567 | case I965_PGETBL_SIZE_1MB: |
| 568 | size = KB(1024); |
| 569 | break; |
| 570 | case I965_PGETBL_SIZE_2MB: |
| 571 | size = KB(2048); |
| 572 | break; |
| 573 | case I965_PGETBL_SIZE_1_5MB: |
| 574 | size = KB(1024 + 512); |
| 575 | break; |
| 576 | default: |
| 577 | dev_info(&intel_private.pcidev->dev, |
| 578 | "unknown page table size, assuming 512KB\n"); |
| 579 | size = KB(512); |
| 580 | } |
| 581 | |
| 582 | return size/4; |
| 583 | } |
| 584 | |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 585 | static unsigned int intel_gtt_total_entries(void) |
| 586 | { |
| 587 | int size; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 588 | |
Daniel Vetter | 2017284 | 2010-09-24 18:25:59 +0200 | [diff] [blame] | 589 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
| 590 | return i965_gtt_total_entries(); |
| 591 | else if (INTEL_GTT_GEN == 6) { |
Daniel Vetter | 210b23c | 2010-08-28 16:14:32 +0200 | [diff] [blame] | 592 | u16 snb_gmch_ctl; |
| 593 | |
| 594 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 595 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { |
| 596 | default: |
| 597 | case SNB_GTT_SIZE_0M: |
| 598 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); |
| 599 | size = MB(0); |
| 600 | break; |
| 601 | case SNB_GTT_SIZE_1M: |
| 602 | size = MB(1); |
| 603 | break; |
| 604 | case SNB_GTT_SIZE_2M: |
| 605 | size = MB(2); |
| 606 | break; |
| 607 | } |
| 608 | return size/4; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 609 | } else { |
| 610 | /* On previous hardware, the GTT size was just what was |
| 611 | * required to map the aperture. |
| 612 | */ |
Daniel Vetter | e5e408f | 2010-08-28 11:04:32 +0200 | [diff] [blame] | 613 | return intel_private.base.gtt_mappable_entries; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 614 | } |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 615 | } |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 616 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 617 | static unsigned int intel_gtt_mappable_entries(void) |
| 618 | { |
| 619 | unsigned int aperture_size; |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 620 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 621 | if (INTEL_GTT_GEN == 1) { |
| 622 | u32 smram_miscc; |
| 623 | |
| 624 | pci_read_config_dword(intel_private.bridge_dev, |
| 625 | I810_SMRAM_MISCC, &smram_miscc); |
| 626 | |
| 627 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) |
| 628 | == I810_GFX_MEM_WIN_32M) |
| 629 | aperture_size = MB(32); |
| 630 | else |
| 631 | aperture_size = MB(64); |
| 632 | } else if (INTEL_GTT_GEN == 2) { |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 633 | u16 gmch_ctrl; |
| 634 | |
| 635 | pci_read_config_word(intel_private.bridge_dev, |
| 636 | I830_GMCH_CTRL, &gmch_ctrl); |
| 637 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 638 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 639 | aperture_size = MB(64); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 640 | else |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 641 | aperture_size = MB(128); |
Daniel Vetter | 239918f | 2010-08-31 22:30:43 +0200 | [diff] [blame] | 642 | } else { |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 643 | /* 9xx supports large sizes, just look at the length */ |
| 644 | aperture_size = pci_resource_len(intel_private.pcidev, 2); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | return aperture_size >> PAGE_SHIFT; |
| 648 | } |
| 649 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 650 | static void intel_gtt_teardown_scratch_page(void) |
| 651 | { |
| 652 | set_pages_wb(intel_private.scratch_page, 1); |
| 653 | pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, |
| 654 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 655 | put_page(intel_private.scratch_page); |
| 656 | __free_page(intel_private.scratch_page); |
| 657 | } |
| 658 | |
| 659 | static void intel_gtt_cleanup(void) |
| 660 | { |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 661 | intel_private.driver->cleanup(); |
| 662 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 663 | iounmap(intel_private.gtt); |
| 664 | iounmap(intel_private.registers); |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 665 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 666 | intel_gtt_teardown_scratch_page(); |
| 667 | } |
| 668 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 669 | static int intel_gtt_init(void) |
| 670 | { |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 671 | u32 gtt_map_size; |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 672 | int ret; |
| 673 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 674 | ret = intel_private.driver->setup(); |
| 675 | if (ret != 0) |
| 676 | return ret; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 677 | |
| 678 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); |
| 679 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); |
| 680 | |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 681 | /* save the PGETBL reg for resume */ |
| 682 | intel_private.PGETBL_save = |
| 683 | readl(intel_private.registers+I810_PGETBL_CTL) |
| 684 | & ~I810_PGETBL_ENABLED; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 685 | /* we only ever restore the register when enabling the PGTBL... */ |
| 686 | if (HAS_PGTBL_EN) |
| 687 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 688 | |
Daniel Vetter | 0af9e92 | 2010-09-12 14:04:03 +0200 | [diff] [blame] | 689 | dev_info(&intel_private.bridge_dev->dev, |
| 690 | "detected gtt size: %dK total, %dK mappable\n", |
| 691 | intel_private.base.gtt_total_entries * 4, |
| 692 | intel_private.base.gtt_mappable_entries * 4); |
| 693 | |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 694 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
| 695 | |
| 696 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, |
| 697 | gtt_map_size); |
| 698 | if (!intel_private.gtt) { |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 699 | intel_private.driver->cleanup(); |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 700 | iounmap(intel_private.registers); |
| 701 | return -ENOMEM; |
| 702 | } |
| 703 | |
| 704 | global_cache_flush(); /* FIXME: ? */ |
| 705 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 706 | intel_private.base.stolen_size = intel_gtt_stolen_size(); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 707 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 708 | ret = intel_gtt_setup_scratch_page(); |
| 709 | if (ret != 0) { |
| 710 | intel_gtt_cleanup(); |
| 711 | return ret; |
| 712 | } |
| 713 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 714 | return 0; |
| 715 | } |
| 716 | |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 717 | static int intel_fake_agp_fetch_size(void) |
| 718 | { |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 719 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 720 | unsigned int aper_size; |
| 721 | int i; |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 722 | |
| 723 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) |
| 724 | / MB(1); |
| 725 | |
| 726 | for (i = 0; i < num_sizes; i++) { |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 727 | if (aper_size == intel_fake_agp_sizes[i].size) { |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 728 | agp_bridge->current_size = |
| 729 | (void *) (intel_fake_agp_sizes + i); |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 730 | return aper_size; |
| 731 | } |
| 732 | } |
| 733 | |
| 734 | return 0; |
| 735 | } |
| 736 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 737 | static void i830_cleanup(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 738 | { |
| 739 | kunmap(intel_private.i8xx_page); |
| 740 | intel_private.i8xx_flush_page = NULL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 741 | |
| 742 | __free_page(intel_private.i8xx_page); |
| 743 | intel_private.i8xx_page = NULL; |
| 744 | } |
| 745 | |
| 746 | static void intel_i830_setup_flush(void) |
| 747 | { |
| 748 | /* return if we've already set the flush mechanism up */ |
| 749 | if (intel_private.i8xx_page) |
| 750 | return; |
| 751 | |
Jan Beulich | e61cb0d | 2010-09-24 13:25:30 +0100 | [diff] [blame] | 752 | intel_private.i8xx_page = alloc_page(GFP_KERNEL); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 753 | if (!intel_private.i8xx_page) |
| 754 | return; |
| 755 | |
| 756 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); |
| 757 | if (!intel_private.i8xx_flush_page) |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 758 | i830_cleanup(); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | /* The chipset_flush interface needs to get data that has already been |
| 762 | * flushed out of the CPU all the way out to main memory, because the GPU |
| 763 | * doesn't snoop those buffers. |
| 764 | * |
| 765 | * The 8xx series doesn't have the same lovely interface for flushing the |
| 766 | * chipset write buffers that the later chips do. According to the 865 |
| 767 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in |
| 768 | * that buffer out, we just fill 1KB and clflush it out, on the assumption |
| 769 | * that it'll push whatever was in there out. It appears to work. |
| 770 | */ |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 771 | static void i830_chipset_flush(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 772 | { |
| 773 | unsigned int *pg = intel_private.i8xx_flush_page; |
| 774 | |
| 775 | memset(pg, 0, 1024); |
| 776 | |
| 777 | if (cpu_has_clflush) |
| 778 | clflush_cache_range(pg, 1024); |
| 779 | else if (wbinvd_on_all_cpus() != 0) |
| 780 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); |
| 781 | } |
| 782 | |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 783 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
| 784 | unsigned int flags) |
| 785 | { |
| 786 | u32 pte_flags = I810_PTE_VALID; |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 787 | |
Daniel Vetter | b47cf66 | 2010-11-04 18:41:50 +0100 | [diff] [blame] | 788 | if (flags == AGP_USER_CACHED_MEMORY) |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 789 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 790 | |
| 791 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 792 | } |
| 793 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 794 | static bool intel_enable_gtt(void) |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 795 | { |
Chris Wilson | 3f08e4e | 2010-09-14 20:15:22 +0100 | [diff] [blame] | 796 | u32 gma_addr; |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 797 | u8 __iomem *reg; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 798 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 799 | if (INTEL_GTT_GEN <= 2) |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 800 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, |
| 801 | &gma_addr); |
| 802 | else |
| 803 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, |
| 804 | &gma_addr); |
| 805 | |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 806 | intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
| 807 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 808 | if (INTEL_GTT_GEN >= 6) |
| 809 | return true; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 810 | |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 811 | if (INTEL_GTT_GEN == 2) { |
| 812 | u16 gmch_ctrl; |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 813 | |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 814 | pci_read_config_word(intel_private.bridge_dev, |
| 815 | I830_GMCH_CTRL, &gmch_ctrl); |
| 816 | gmch_ctrl |= I830_GMCH_ENABLED; |
| 817 | pci_write_config_word(intel_private.bridge_dev, |
| 818 | I830_GMCH_CTRL, gmch_ctrl); |
| 819 | |
| 820 | pci_read_config_word(intel_private.bridge_dev, |
| 821 | I830_GMCH_CTRL, &gmch_ctrl); |
| 822 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { |
| 823 | dev_err(&intel_private.pcidev->dev, |
| 824 | "failed to enable the GTT: GMCH_CTRL=%x\n", |
| 825 | gmch_ctrl); |
| 826 | return false; |
| 827 | } |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 828 | } |
| 829 | |
| 830 | reg = intel_private.registers+I810_PGETBL_CTL; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 831 | writel(intel_private.PGETBL_save, reg); |
| 832 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 833 | dev_err(&intel_private.pcidev->dev, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 834 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 835 | readl(reg), intel_private.PGETBL_save); |
| 836 | return false; |
| 837 | } |
| 838 | |
| 839 | return true; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | static int i830_setup(void) |
| 843 | { |
| 844 | u32 reg_addr; |
| 845 | |
| 846 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); |
| 847 | reg_addr &= 0xfff80000; |
| 848 | |
| 849 | intel_private.registers = ioremap(reg_addr, KB(64)); |
| 850 | if (!intel_private.registers) |
| 851 | return -ENOMEM; |
| 852 | |
| 853 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
| 854 | |
| 855 | intel_i830_setup_flush(); |
| 856 | |
| 857 | return 0; |
| 858 | } |
| 859 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 860 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 861 | { |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 862 | agp_bridge->gatt_table_real = NULL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 863 | agp_bridge->gatt_table = NULL; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 864 | agp_bridge->gatt_bus_addr = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 865 | |
| 866 | return 0; |
| 867 | } |
| 868 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 869 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 870 | { |
| 871 | return 0; |
| 872 | } |
| 873 | |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 874 | static int intel_fake_agp_configure(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 875 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 876 | int i; |
| 877 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 878 | if (!intel_enable_gtt()) |
| 879 | return -EIO; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 880 | |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 881 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 882 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 883 | for (i = 0; i < intel_private.base.gtt_total_entries; i++) { |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 884 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
| 885 | i, 0); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 886 | } |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 887 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 888 | |
| 889 | global_cache_flush(); |
| 890 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 891 | return 0; |
| 892 | } |
| 893 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 894 | static bool i830_check_flags(unsigned int flags) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 895 | { |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 896 | switch (flags) { |
| 897 | case 0: |
| 898 | case AGP_PHYS_MEMORY: |
| 899 | case AGP_USER_CACHED_MEMORY: |
| 900 | case AGP_USER_MEMORY: |
| 901 | return true; |
| 902 | } |
| 903 | |
| 904 | return false; |
| 905 | } |
| 906 | |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 907 | static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
| 908 | unsigned int sg_len, |
| 909 | unsigned int pg_start, |
| 910 | unsigned int flags) |
| 911 | { |
| 912 | struct scatterlist *sg; |
| 913 | unsigned int len, m; |
| 914 | int i, j; |
| 915 | |
| 916 | j = pg_start; |
| 917 | |
| 918 | /* sg may merge pages, but we have to separate |
| 919 | * per-page addr for GTT */ |
| 920 | for_each_sg(sg_list, sg, sg_len, i) { |
| 921 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
| 922 | for (m = 0; m < len; m++) { |
| 923 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
| 924 | intel_private.driver->write_entry(addr, |
| 925 | j, flags); |
| 926 | j++; |
| 927 | } |
| 928 | } |
| 929 | readl(intel_private.gtt+j-1); |
| 930 | } |
| 931 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 932 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
| 933 | off_t pg_start, int type) |
| 934 | { |
| 935 | int i, j; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 936 | int ret = -EINVAL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 937 | |
| 938 | if (mem->page_count == 0) |
| 939 | goto out; |
| 940 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 941 | if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 942 | goto out_err; |
| 943 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 944 | if (type != mem->type) |
| 945 | goto out_err; |
| 946 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 947 | if (!intel_private.driver->check_flags(type)) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 948 | goto out_err; |
| 949 | |
| 950 | if (!mem->is_flushed) |
| 951 | global_cache_flush(); |
| 952 | |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 953 | if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { |
| 954 | ret = intel_agp_map_memory(mem); |
| 955 | if (ret != 0) |
| 956 | return ret; |
| 957 | |
| 958 | intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, |
| 959 | pg_start, type); |
| 960 | } else { |
| 961 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
| 962 | dma_addr_t addr = page_to_phys(mem->pages[i]); |
| 963 | intel_private.driver->write_entry(addr, |
| 964 | j, type); |
| 965 | } |
| 966 | readl(intel_private.gtt+j-1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 967 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 968 | |
| 969 | out: |
| 970 | ret = 0; |
| 971 | out_err: |
| 972 | mem->is_flushed = true; |
| 973 | return ret; |
| 974 | } |
| 975 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 976 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
| 977 | off_t pg_start, int type) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 978 | { |
| 979 | int i; |
| 980 | |
| 981 | if (mem->page_count == 0) |
| 982 | return 0; |
| 983 | |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 984 | if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) |
| 985 | intel_agp_unmap_memory(mem); |
| 986 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 987 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 988 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
| 989 | i, 0); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 990 | } |
Daniel Vetter | fdfb58a | 2010-08-29 00:15:03 +0200 | [diff] [blame] | 991 | readl(intel_private.gtt+i-1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 992 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 993 | return 0; |
| 994 | } |
| 995 | |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 996 | static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge) |
| 997 | { |
| 998 | intel_private.driver->chipset_flush(); |
| 999 | } |
| 1000 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1001 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
| 1002 | int type) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1003 | { |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1004 | struct agp_memory *new; |
| 1005 | |
| 1006 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { |
| 1007 | if (pg_count != intel_private.num_dcache_entries) |
| 1008 | return NULL; |
| 1009 | |
| 1010 | new = agp_create_memory(1); |
| 1011 | if (new == NULL) |
| 1012 | return NULL; |
| 1013 | |
| 1014 | new->type = AGP_DCACHE_MEMORY; |
| 1015 | new->page_count = pg_count; |
| 1016 | new->num_scratch_pages = 0; |
| 1017 | agp_free_page_array(new); |
| 1018 | return new; |
| 1019 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1020 | if (type == AGP_PHYS_MEMORY) |
| 1021 | return alloc_agpphysmem_i8xx(pg_count, type); |
| 1022 | /* always return NULL for other allocation types for now */ |
| 1023 | return NULL; |
| 1024 | } |
| 1025 | |
| 1026 | static int intel_alloc_chipset_flush_resource(void) |
| 1027 | { |
| 1028 | int ret; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1029 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1030 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1031 | pcibios_align_resource, intel_private.bridge_dev); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1032 | |
| 1033 | return ret; |
| 1034 | } |
| 1035 | |
| 1036 | static void intel_i915_setup_chipset_flush(void) |
| 1037 | { |
| 1038 | int ret; |
| 1039 | u32 temp; |
| 1040 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1041 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1042 | if (!(temp & 0x1)) { |
| 1043 | intel_alloc_chipset_flush_resource(); |
| 1044 | intel_private.resource_valid = 1; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1045 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1046 | } else { |
| 1047 | temp &= ~1; |
| 1048 | |
| 1049 | intel_private.resource_valid = 1; |
| 1050 | intel_private.ifp_resource.start = temp; |
| 1051 | intel_private.ifp_resource.end = temp + PAGE_SIZE; |
| 1052 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
| 1053 | /* some BIOSes reserve this area in a pnp some don't */ |
| 1054 | if (ret) |
| 1055 | intel_private.resource_valid = 0; |
| 1056 | } |
| 1057 | } |
| 1058 | |
| 1059 | static void intel_i965_g33_setup_chipset_flush(void) |
| 1060 | { |
| 1061 | u32 temp_hi, temp_lo; |
| 1062 | int ret; |
| 1063 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1064 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
| 1065 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1066 | |
| 1067 | if (!(temp_lo & 0x1)) { |
| 1068 | |
| 1069 | intel_alloc_chipset_flush_resource(); |
| 1070 | |
| 1071 | intel_private.resource_valid = 1; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1072 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1073 | upper_32_bits(intel_private.ifp_resource.start)); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1074 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1075 | } else { |
| 1076 | u64 l64; |
| 1077 | |
| 1078 | temp_lo &= ~0x1; |
| 1079 | l64 = ((u64)temp_hi << 32) | temp_lo; |
| 1080 | |
| 1081 | intel_private.resource_valid = 1; |
| 1082 | intel_private.ifp_resource.start = l64; |
| 1083 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; |
| 1084 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
| 1085 | /* some BIOSes reserve this area in a pnp some don't */ |
| 1086 | if (ret) |
| 1087 | intel_private.resource_valid = 0; |
| 1088 | } |
| 1089 | } |
| 1090 | |
| 1091 | static void intel_i9xx_setup_flush(void) |
| 1092 | { |
| 1093 | /* return if already configured */ |
| 1094 | if (intel_private.ifp_resource.start) |
| 1095 | return; |
| 1096 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1097 | if (INTEL_GTT_GEN == 6) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1098 | return; |
| 1099 | |
| 1100 | /* setup a resource for this object */ |
| 1101 | intel_private.ifp_resource.name = "Intel Flush Page"; |
| 1102 | intel_private.ifp_resource.flags = IORESOURCE_MEM; |
| 1103 | |
| 1104 | /* Setup chipset flush for 915 */ |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1105 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1106 | intel_i965_g33_setup_chipset_flush(); |
| 1107 | } else { |
| 1108 | intel_i915_setup_chipset_flush(); |
| 1109 | } |
| 1110 | |
Chris Wilson | df51e7a | 2010-09-04 14:57:27 +0100 | [diff] [blame] | 1111 | if (intel_private.ifp_resource.start) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1112 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
Chris Wilson | df51e7a | 2010-09-04 14:57:27 +0100 | [diff] [blame] | 1113 | if (!intel_private.i9xx_flush_page) |
| 1114 | dev_err(&intel_private.pcidev->dev, |
| 1115 | "can't ioremap flush page - no chipset flushing\n"); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1116 | } |
| 1117 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1118 | static void i9xx_cleanup(void) |
| 1119 | { |
| 1120 | if (intel_private.i9xx_flush_page) |
| 1121 | iounmap(intel_private.i9xx_flush_page); |
| 1122 | if (intel_private.resource_valid) |
| 1123 | release_resource(&intel_private.ifp_resource); |
| 1124 | intel_private.ifp_resource.start = 0; |
| 1125 | intel_private.resource_valid = 0; |
| 1126 | } |
| 1127 | |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1128 | static void i9xx_chipset_flush(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1129 | { |
| 1130 | if (intel_private.i9xx_flush_page) |
| 1131 | writel(1, intel_private.i9xx_flush_page); |
| 1132 | } |
| 1133 | |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1134 | static void i965_write_entry(dma_addr_t addr, unsigned int entry, |
| 1135 | unsigned int flags) |
| 1136 | { |
| 1137 | /* Shift high bits down */ |
| 1138 | addr |= (addr >> 28) & 0xf0; |
| 1139 | writel(addr | I810_PTE_VALID, intel_private.gtt + entry); |
| 1140 | } |
| 1141 | |
Daniel Vetter | 90cb149 | 2010-09-11 23:55:20 +0200 | [diff] [blame] | 1142 | static bool gen6_check_flags(unsigned int flags) |
| 1143 | { |
| 1144 | return true; |
| 1145 | } |
| 1146 | |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1147 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
| 1148 | unsigned int flags) |
| 1149 | { |
| 1150 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
| 1151 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; |
| 1152 | u32 pte_flags; |
| 1153 | |
Zhenyu Wang | 897ef19 | 2010-11-02 17:30:47 +0800 | [diff] [blame] | 1154 | if (type_mask == AGP_USER_MEMORY) |
Chris Wilson | 85ccc35 | 2010-10-22 14:59:29 +0100 | [diff] [blame] | 1155 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1156 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
Zhenyu Wang | d110852 | 2010-11-02 17:30:46 +0800 | [diff] [blame] | 1157 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1158 | if (gfdt) |
| 1159 | pte_flags |= GEN6_PTE_GFDT; |
| 1160 | } else { /* set 'normal'/'cached' to LLC by default */ |
Zhenyu Wang | d110852 | 2010-11-02 17:30:46 +0800 | [diff] [blame] | 1161 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1162 | if (gfdt) |
| 1163 | pte_flags |= GEN6_PTE_GFDT; |
| 1164 | } |
| 1165 | |
| 1166 | /* gen6 has bit11-4 for physical addr bit39-32 */ |
| 1167 | addr |= (addr >> 28) & 0xff0; |
| 1168 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 1169 | } |
| 1170 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1171 | static void gen6_cleanup(void) |
| 1172 | { |
| 1173 | } |
| 1174 | |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1175 | static int i9xx_setup(void) |
| 1176 | { |
| 1177 | u32 reg_addr; |
| 1178 | |
| 1179 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
| 1180 | |
| 1181 | reg_addr &= 0xfff80000; |
| 1182 | |
| 1183 | intel_private.registers = ioremap(reg_addr, 128 * 4096); |
| 1184 | if (!intel_private.registers) |
| 1185 | return -ENOMEM; |
| 1186 | |
| 1187 | if (INTEL_GTT_GEN == 3) { |
| 1188 | u32 gtt_addr; |
Chris Wilson | 3f08e4e | 2010-09-14 20:15:22 +0100 | [diff] [blame] | 1189 | |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1190 | pci_read_config_dword(intel_private.pcidev, |
| 1191 | I915_PTEADDR, >t_addr); |
| 1192 | intel_private.gtt_bus_addr = gtt_addr; |
| 1193 | } else { |
| 1194 | u32 gtt_offset; |
| 1195 | |
| 1196 | switch (INTEL_GTT_GEN) { |
| 1197 | case 5: |
| 1198 | case 6: |
| 1199 | gtt_offset = MB(2); |
| 1200 | break; |
| 1201 | case 4: |
| 1202 | default: |
| 1203 | gtt_offset = KB(512); |
| 1204 | break; |
| 1205 | } |
| 1206 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; |
| 1207 | } |
| 1208 | |
| 1209 | intel_i9xx_setup_flush(); |
| 1210 | |
| 1211 | return 0; |
| 1212 | } |
| 1213 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1214 | static const struct agp_bridge_driver intel_810_driver = { |
| 1215 | .owner = THIS_MODULE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1216 | .size_type = FIXED_APER_SIZE, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 1217 | .aperture_sizes = intel_fake_agp_sizes, |
| 1218 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), |
| 1219 | .configure = intel_fake_agp_configure, |
| 1220 | .fetch_size = intel_fake_agp_fetch_size, |
| 1221 | .cleanup = intel_gtt_cleanup, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1222 | .agp_enable = intel_fake_agp_enable, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1223 | .cache_flush = global_cache_flush, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 1224 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
| 1225 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1226 | .insert_memory = intel_i810_insert_entries, |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1227 | .remove_memory = intel_fake_agp_remove_entries, |
| 1228 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1229 | .free_by_type = intel_i810_free_by_type, |
| 1230 | .agp_alloc_page = agp_generic_alloc_page, |
| 1231 | .agp_alloc_pages = agp_generic_alloc_pages, |
| 1232 | .agp_destroy_page = agp_generic_destroy_page, |
| 1233 | .agp_destroy_pages = agp_generic_destroy_pages, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1234 | }; |
| 1235 | |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1236 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1237 | .owner = THIS_MODULE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1238 | .size_type = FIXED_APER_SIZE, |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 1239 | .aperture_sizes = intel_fake_agp_sizes, |
| 1240 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1241 | .configure = intel_fake_agp_configure, |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 1242 | .fetch_size = intel_fake_agp_fetch_size, |
Daniel Vetter | fdfb58a | 2010-08-29 00:15:03 +0200 | [diff] [blame] | 1243 | .cleanup = intel_gtt_cleanup, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1244 | .agp_enable = intel_fake_agp_enable, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1245 | .cache_flush = global_cache_flush, |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 1246 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1247 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1248 | .insert_memory = intel_fake_agp_insert_entries, |
| 1249 | .remove_memory = intel_fake_agp_remove_entries, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1250 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1251 | .free_by_type = intel_i810_free_by_type, |
| 1252 | .agp_alloc_page = agp_generic_alloc_page, |
| 1253 | .agp_alloc_pages = agp_generic_alloc_pages, |
| 1254 | .agp_destroy_page = agp_generic_destroy_page, |
| 1255 | .agp_destroy_pages = agp_generic_destroy_pages, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1256 | .chipset_flush = intel_fake_agp_chipset_flush, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1257 | }; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1258 | |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1259 | static const struct intel_gtt_driver i81x_gtt_driver = { |
| 1260 | .gen = 1, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 1261 | .has_pgtbl_enable = 1, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1262 | .dma_mask_size = 32, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 1263 | .setup = i810_setup, |
| 1264 | .cleanup = i810_cleanup, |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1265 | .check_flags = i830_check_flags, |
| 1266 | .write_entry = i810_write_entry, |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1267 | }; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1268 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
| 1269 | .gen = 2, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1270 | .has_pgtbl_enable = 1, |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 1271 | .setup = i830_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1272 | .cleanup = i830_cleanup, |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 1273 | .write_entry = i830_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1274 | .dma_mask_size = 32, |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 1275 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1276 | .chipset_flush = i830_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1277 | }; |
| 1278 | static const struct intel_gtt_driver i915_gtt_driver = { |
| 1279 | .gen = 3, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1280 | .has_pgtbl_enable = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1281 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1282 | .cleanup = i9xx_cleanup, |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 1283 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1284 | .write_entry = i830_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1285 | .dma_mask_size = 32, |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 1286 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1287 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1288 | }; |
| 1289 | static const struct intel_gtt_driver g33_gtt_driver = { |
| 1290 | .gen = 3, |
| 1291 | .is_g33 = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1292 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1293 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1294 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1295 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1296 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1297 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1298 | }; |
| 1299 | static const struct intel_gtt_driver pineview_gtt_driver = { |
| 1300 | .gen = 3, |
| 1301 | .is_pineview = 1, .is_g33 = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1302 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1303 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1304 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1305 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1306 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1307 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1308 | }; |
| 1309 | static const struct intel_gtt_driver i965_gtt_driver = { |
| 1310 | .gen = 4, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1311 | .has_pgtbl_enable = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1312 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1313 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1314 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1315 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1316 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1317 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1318 | }; |
| 1319 | static const struct intel_gtt_driver g4x_gtt_driver = { |
| 1320 | .gen = 5, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1321 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1322 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1323 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1324 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1325 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1326 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1327 | }; |
| 1328 | static const struct intel_gtt_driver ironlake_gtt_driver = { |
| 1329 | .gen = 5, |
| 1330 | .is_ironlake = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1331 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1332 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1333 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1334 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1335 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1336 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1337 | }; |
| 1338 | static const struct intel_gtt_driver sandybridge_gtt_driver = { |
| 1339 | .gen = 6, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1340 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1341 | .cleanup = gen6_cleanup, |
Daniel Vetter | 97ef1bd | 2010-09-09 17:52:20 +0200 | [diff] [blame] | 1342 | .write_entry = gen6_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1343 | .dma_mask_size = 40, |
Daniel Vetter | 90cb149 | 2010-09-11 23:55:20 +0200 | [diff] [blame] | 1344 | .check_flags = gen6_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1345 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1346 | }; |
| 1347 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1348 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
| 1349 | * driver and gmch_driver must be non-null, and find_gmch will determine |
| 1350 | * which one should be used if a gmch_chip_id is present. |
| 1351 | */ |
| 1352 | static const struct intel_gtt_driver_description { |
| 1353 | unsigned int gmch_chip_id; |
| 1354 | char *name; |
| 1355 | const struct agp_bridge_driver *gmch_driver; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1356 | const struct intel_gtt_driver *gtt_driver; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1357 | } intel_gtt_chipsets[] = { |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1358 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver, |
| 1359 | &i81x_gtt_driver}, |
| 1360 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver, |
| 1361 | &i81x_gtt_driver}, |
| 1362 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver, |
| 1363 | &i81x_gtt_driver}, |
| 1364 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver, |
| 1365 | &i81x_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1366 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1367 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1368 | { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1369 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1370 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1371 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1372 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1373 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1374 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1375 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1376 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1377 | &intel_fake_agp_driver, &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1378 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1379 | &intel_fake_agp_driver, &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1380 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1381 | &intel_fake_agp_driver, &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1382 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1383 | &intel_fake_agp_driver, &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1384 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1385 | &intel_fake_agp_driver, &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1386 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1387 | &intel_fake_agp_driver, &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1388 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1389 | &intel_fake_agp_driver, &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1390 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1391 | &intel_fake_agp_driver, &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1392 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1393 | &intel_fake_agp_driver, &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1394 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1395 | &intel_fake_agp_driver, &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1396 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1397 | &intel_fake_agp_driver, &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1398 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1399 | &intel_fake_agp_driver, &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1400 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1401 | &intel_fake_agp_driver, &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1402 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1403 | &intel_fake_agp_driver, &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1404 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1405 | &intel_fake_agp_driver, &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1406 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1407 | &intel_fake_agp_driver, &pineview_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1408 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1409 | &intel_fake_agp_driver, &pineview_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1410 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1411 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1412 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1413 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1414 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1415 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1416 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1417 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1418 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1419 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Chris Wilson | e9e5f8e | 2010-09-21 11:19:32 +0100 | [diff] [blame] | 1420 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1421 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1422 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1423 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1424 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1425 | "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1426 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1427 | "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1428 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1429 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1430 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1431 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1432 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1433 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1434 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1435 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1436 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1437 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1438 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1439 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1440 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1441 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1442 | { 0, NULL, NULL } |
| 1443 | }; |
| 1444 | |
| 1445 | static int find_gmch(u16 device) |
| 1446 | { |
| 1447 | struct pci_dev *gmch_device; |
| 1448 | |
| 1449 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
| 1450 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { |
| 1451 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1452 | device, gmch_device); |
| 1453 | } |
| 1454 | |
| 1455 | if (!gmch_device) |
| 1456 | return 0; |
| 1457 | |
| 1458 | intel_private.pcidev = gmch_device; |
| 1459 | return 1; |
| 1460 | } |
| 1461 | |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1462 | int intel_gmch_probe(struct pci_dev *pdev, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1463 | struct agp_bridge_data *bridge) |
| 1464 | { |
| 1465 | int i, mask; |
| 1466 | bridge->driver = NULL; |
| 1467 | |
| 1468 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
| 1469 | if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { |
| 1470 | bridge->driver = |
| 1471 | intel_gtt_chipsets[i].gmch_driver; |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1472 | intel_private.driver = |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1473 | intel_gtt_chipsets[i].gtt_driver; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1474 | break; |
| 1475 | } |
| 1476 | } |
| 1477 | |
| 1478 | if (!bridge->driver) |
| 1479 | return 0; |
| 1480 | |
| 1481 | bridge->dev_private_data = &intel_private; |
| 1482 | bridge->dev = pdev; |
| 1483 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1484 | intel_private.bridge_dev = pci_dev_get(pdev); |
| 1485 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1486 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
| 1487 | |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1488 | mask = intel_private.driver->dma_mask_size; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1489 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
| 1490 | dev_err(&intel_private.pcidev->dev, |
| 1491 | "set gfx device dma mask %d-bit failed!\n", mask); |
| 1492 | else |
| 1493 | pci_set_consistent_dma_mask(intel_private.pcidev, |
| 1494 | DMA_BIT_MASK(mask)); |
| 1495 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame^] | 1496 | /*if (bridge->driver == &intel_810_driver) |
| 1497 | return 1;*/ |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 1498 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 1499 | if (intel_gtt_init() != 0) |
| 1500 | return 0; |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 1501 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1502 | return 1; |
| 1503 | } |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1504 | EXPORT_SYMBOL(intel_gmch_probe); |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1505 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 1506 | const struct intel_gtt *intel_gtt_get(void) |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 1507 | { |
| 1508 | return &intel_private.base; |
| 1509 | } |
| 1510 | EXPORT_SYMBOL(intel_gtt_get); |
| 1511 | |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1512 | void intel_gmch_remove(struct pci_dev *pdev) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1513 | { |
| 1514 | if (intel_private.pcidev) |
| 1515 | pci_dev_put(intel_private.pcidev); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1516 | if (intel_private.bridge_dev) |
| 1517 | pci_dev_put(intel_private.bridge_dev); |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1518 | } |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1519 | EXPORT_SYMBOL(intel_gmch_remove); |
| 1520 | |
| 1521 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
| 1522 | MODULE_LICENSE("GPL and additional rights"); |