blob: 533b24180a1ec4346db1b562522be49f17735f01 [file] [log] [blame]
Sahitya Tummala56874732015-05-21 08:24:03 +05301/*
Ritesh Harjani82124772014-11-04 15:34:00 +05302 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
Sahitya Tummala56874732015-05-21 08:24:03 +05303 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef __SDHCI_MSM_H__
16#define __SDHCI_MSM_H__
17
18#include <linux/mmc/mmc.h>
Gilad Bronerc788a672015-09-08 15:39:11 +030019#include <linux/pm_qos.h>
Sahitya Tummala56874732015-05-21 08:24:03 +053020#include "sdhci-pltfm.h"
21
22/* This structure keeps information per regulator */
23struct sdhci_msm_reg_data {
24 /* voltage regulator handle */
25 struct regulator *reg;
26 /* regulator name */
27 const char *name;
28 /* voltage level to be set */
29 u32 low_vol_level;
30 u32 high_vol_level;
31 /* Load values for low power and high power mode */
32 u32 lpm_uA;
33 u32 hpm_uA;
34
35 /* is this regulator enabled? */
36 bool is_enabled;
37 /* is this regulator needs to be always on? */
38 bool is_always_on;
39 /* is low power mode setting required for this regulator? */
40 bool lpm_sup;
41 bool set_voltage_sup;
42};
43
44/*
45 * This structure keeps information for all the
46 * regulators required for a SDCC slot.
47 */
48struct sdhci_msm_slot_reg_data {
49 /* keeps VDD/VCC regulator info */
50 struct sdhci_msm_reg_data *vdd_data;
51 /* keeps VDD IO regulator info */
52 struct sdhci_msm_reg_data *vdd_io_data;
53};
54
55struct sdhci_msm_gpio {
56 u32 no;
57 const char *name;
58 bool is_enabled;
59};
60
61struct sdhci_msm_gpio_data {
62 struct sdhci_msm_gpio *gpio;
63 u8 size;
64};
65
66struct sdhci_msm_pin_data {
67 /*
68 * = 1 if controller pins are using gpios
69 * = 0 if controller has dedicated MSM pads
70 */
71 u8 is_gpio;
72 struct sdhci_msm_gpio_data *gpio_data;
73};
74
75struct sdhci_pinctrl_data {
76 struct pinctrl *pctrl;
77 struct pinctrl_state *pins_active;
78 struct pinctrl_state *pins_sleep;
79};
80
81struct sdhci_msm_bus_voting_data {
82 struct msm_bus_scale_pdata *bus_pdata;
83 unsigned int *bw_vecs;
84 unsigned int bw_vecs_size;
85};
86
Gilad Bronerc788a672015-09-08 15:39:11 +030087struct sdhci_msm_cpu_group_map {
88 int nr_groups;
89 cpumask_t *mask;
90};
91
92struct sdhci_msm_pm_qos_latency {
93 s32 latency[SDHCI_POWER_POLICY_NUM];
94};
95
96struct sdhci_msm_pm_qos_data {
97 struct sdhci_msm_cpu_group_map cpu_group_map;
98 enum pm_qos_req_type irq_req_type;
99 int irq_cpu;
100 struct sdhci_msm_pm_qos_latency irq_latency;
101 struct sdhci_msm_pm_qos_latency *cmdq_latency;
102 struct sdhci_msm_pm_qos_latency *latency;
103 bool irq_valid;
104 bool cmdq_valid;
105 bool legacy_valid;
106};
107
Gilad Broner44445992015-09-29 16:05:39 +0300108/*
109 * PM QoS for group voting management - each cpu group defined is associated
110 * with 1 instance of this structure.
111 */
112struct sdhci_msm_pm_qos_group {
113 struct pm_qos_request req;
Asutosh Das36c2e922015-12-01 12:19:58 +0530114 struct delayed_work unvote_work;
Gilad Broner44445992015-09-29 16:05:39 +0300115 atomic_t counter;
116 s32 latency;
117};
118
119/* PM QoS HW IRQ voting */
120struct sdhci_msm_pm_qos_irq {
121 struct pm_qos_request req;
Asutosh Das36c2e922015-12-01 12:19:58 +0530122 struct delayed_work unvote_work;
Gilad Broner68c54562015-09-20 11:59:46 +0300123 struct device_attribute enable_attr;
124 struct device_attribute status_attr;
Gilad Broner44445992015-09-29 16:05:39 +0300125 atomic_t counter;
126 s32 latency;
127 bool enabled;
128};
129
Sahitya Tummala56874732015-05-21 08:24:03 +0530130struct sdhci_msm_pltfm_data {
131 /* Supported UHS-I Modes */
132 u32 caps;
133
134 /* More capabilities */
135 u32 caps2;
136
137 unsigned long mmc_bus_width;
138 struct sdhci_msm_slot_reg_data *vreg_data;
139 bool nonremovable;
140 bool nonhotplug;
141 bool largeaddressbus;
142 bool pin_cfg_sts;
143 struct sdhci_msm_pin_data *pin_data;
144 struct sdhci_pinctrl_data *pctrl_data;
Sahitya Tummala56874732015-05-21 08:24:03 +0530145 int status_gpio; /* card detection GPIO that is configured as IRQ */
146 struct sdhci_msm_bus_voting_data *voting_data;
147 u32 *sup_clk_table;
148 unsigned char sup_clk_cnt;
Ritesh Harjani42876f42015-11-17 17:46:51 +0530149 int sdiowakeup_irq;
Sahitya Tummala719c6b52015-05-21 08:28:19 +0530150 u32 *sup_ice_clk_table;
151 unsigned char sup_ice_clk_cnt;
Gilad Bronerc788a672015-09-08 15:39:11 +0300152 struct sdhci_msm_pm_qos_data pm_qos_data;
Pavan Anamula5a256df2015-10-16 14:38:28 +0530153 bool core_3_0v_support;
Sahitya Tummala56874732015-05-21 08:24:03 +0530154};
155
156struct sdhci_msm_bus_vote {
157 uint32_t client_handle;
158 uint32_t curr_vote;
159 int min_bw_vote;
160 int max_bw_vote;
161 bool is_max_bw_needed;
162 struct delayed_work vote_work;
163 struct device_attribute max_bus_bw;
164};
165
Sahitya Tummala719c6b52015-05-21 08:28:19 +0530166struct sdhci_msm_ice_data {
167 struct qcom_ice_variant_ops *vops;
168 struct completion async_done;
169 struct platform_device *pdev;
170 int state;
171};
172
Sahitya Tummala56874732015-05-21 08:24:03 +0530173struct sdhci_msm_host {
174 struct platform_device *pdev;
175 void __iomem *core_mem; /* MSM SDCC mapped address */
Ritesh Harjani82124772014-11-04 15:34:00 +0530176 void __iomem *cryptoio; /* ICE HCI mapped address */
177 bool ice_hci_support;
Sahitya Tummala56874732015-05-21 08:24:03 +0530178 int pwr_irq; /* power irq */
179 struct clk *clk; /* main SD/MMC bus clock */
180 struct clk *pclk; /* SDHC peripheral bus clock */
181 struct clk *bus_clk; /* SDHC bus voter clock */
182 struct clk *ff_clk; /* CDC calibration fixed feedback clock */
183 struct clk *sleep_clk; /* CDC calibration sleep clock */
Sahitya Tummala719c6b52015-05-21 08:28:19 +0530184 struct clk *ice_clk; /* SDHC peripheral ICE clock */
Sahitya Tummala56874732015-05-21 08:24:03 +0530185 atomic_t clks_on; /* Set if clocks are enabled */
186 struct sdhci_msm_pltfm_data *pdata;
187 struct mmc_host *mmc;
188 struct sdhci_pltfm_data sdhci_msm_pdata;
189 u32 curr_pwr_state;
190 u32 curr_io_level;
191 struct completion pwr_irq_completion;
192 struct sdhci_msm_bus_vote msm_bus_vote;
193 struct device_attribute polling;
194 u32 clk_rate; /* Keeps track of current clock rate that is set */
195 bool tuning_done;
196 bool calibration_done;
197 u8 saved_tuning_phase;
198 bool en_auto_cmd21;
199 struct device_attribute auto_cmd21_attr;
Ritesh Harjani42876f42015-11-17 17:46:51 +0530200 bool is_sdiowakeup_enabled;
Ritesh Harjanib5c8e172015-12-17 19:59:04 +0530201 bool sdio_pending_processing;
Sahitya Tummala56874732015-05-21 08:24:03 +0530202 atomic_t controller_clock;
203 bool use_cdclp533;
204 bool use_updated_dll_reset;
205 bool use_14lpp_dll;
Ritesh Harjaniea709662015-05-27 15:40:24 +0530206 bool enhanced_strobe;
Venkat Gopalakrishnanb47cf402015-09-04 18:32:25 -0700207 bool rclk_delay_fix;
Sahitya Tummala56874732015-05-21 08:24:03 +0530208 u32 caps_0;
Sahitya Tummala719c6b52015-05-21 08:28:19 +0530209 struct sdhci_msm_ice_data ice;
210 u32 ice_clk_rate;
Gilad Broner44445992015-09-29 16:05:39 +0300211 struct sdhci_msm_pm_qos_group *pm_qos;
Gilad Broner07d92eb2015-09-29 16:57:21 +0300212 int pm_qos_prev_cpu;
Gilad Broner68c54562015-09-20 11:59:46 +0300213 struct device_attribute pm_qos_group_enable_attr;
214 struct device_attribute pm_qos_group_status_attr;
Gilad Broner44445992015-09-29 16:05:39 +0300215 bool pm_qos_group_enable;
216 struct sdhci_msm_pm_qos_irq pm_qos_irq;
Sahitya Tummala0523cda2015-11-17 09:24:53 +0530217 bool tuning_in_progress;
Sayali Lokhandef0ee1ff2016-08-25 20:46:01 +0530218 bool mci_removed;
219 const struct sdhci_msm_offset *offset;
Sahitya Tummala56874732015-05-21 08:24:03 +0530220};
Subhash Jadavaniebcd00d2015-07-09 17:28:42 -0700221
222extern char *saved_command_line;
223
Gilad Broner44445992015-09-29 16:05:39 +0300224void sdhci_msm_pm_qos_irq_init(struct sdhci_host *host);
225void sdhci_msm_pm_qos_irq_vote(struct sdhci_host *host);
226void sdhci_msm_pm_qos_irq_unvote(struct sdhci_host *host, bool async);
227
228void sdhci_msm_pm_qos_cpu_init(struct sdhci_host *host,
229 struct sdhci_msm_pm_qos_latency *latency);
230void sdhci_msm_pm_qos_cpu_vote(struct sdhci_host *host,
231 struct sdhci_msm_pm_qos_latency *latency, int cpu);
Gilad Broner07d92eb2015-09-29 16:57:21 +0300232bool sdhci_msm_pm_qos_cpu_unvote(struct sdhci_host *host, int cpu, bool async);
Gilad Broner44445992015-09-29 16:05:39 +0300233
234
Sahitya Tummala56874732015-05-21 08:24:03 +0530235#endif /* __SDHCI_MSM_H__ */