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gerrit-public.fairphone.software / kernel / msm-4.9 / 82a618da1bc21dd9ff9a6fa66acbd7ec545b72c5 / . / arch / arm / boot / dts / imx51.dtsi
blob: 2781e47cff0d96bce5b2eab2dc394c9a8a730646 [file] [log] [blame]
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]24 };
25
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
31 };
32
33 clocks {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 ckil {
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
40 };
41
42 ckih1 {
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
45 };
46
47 ckih2 {
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
50 };
51
52 osc {
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
55 };
56 };
57
58 soc {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
63 ranges;
64
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]72 aips@70000000 { /* AIPS1 */
73 compatible = "fsl,aips-bus", "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x70000000 0x10000000>;
77 ranges;
78
79 spba@70000000 {
80 compatible = "fsl,spba-bus", "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0x70000000 0x40000>;
84 ranges;
85
86 esdhc@70004000 { /* ESDHC1 */
87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>;
89 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]92 status = "disabled";
93 };
94
95 esdhc@70008000 { /* ESDHC2 */
96 compatible = "fsl,imx51-esdhc";
97 reg = <0x70008000 0x4000>;
98 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]101 status = "disabled";
102 };
103
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]104 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]105 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
106 reg = <0x7000c000 0x4000>;
107 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]108 clocks = <&clks 32>, <&clks 33>;
109 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]110 status = "disabled";
111 };
112
113 ecspi@70010000 { /* ECSPI1 */
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "fsl,imx51-ecspi";
117 reg = <0x70010000 0x4000>;
118 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]119 clocks = <&clks 51>, <&clks 52>;
120 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]121 status = "disabled";
122 };
123
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]124 ssi2: ssi@70014000 {
125 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
126 reg = <0x70014000 0x4000>;
127 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]128 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]129 fsl,fifo-depth = <15>;
130 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
131 status = "disabled";
132 };
133
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]134 esdhc@70020000 { /* ESDHC3 */
135 compatible = "fsl,imx51-esdhc";
136 reg = <0x70020000 0x4000>;
137 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]138 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
139 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]140 status = "disabled";
141 };
142
143 esdhc@70024000 { /* ESDHC4 */
144 compatible = "fsl,imx51-esdhc";
145 reg = <0x70024000 0x4000>;
146 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]147 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
148 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]149 status = "disabled";
150 };
151 };
152
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]153 usb@73f80000 {
154 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
155 reg = <0x73f80000 0x0200>;
156 interrupts = <18>;
157 status = "disabled";
158 };
159
160 usb@73f80200 {
161 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
162 reg = <0x73f80200 0x0200>;
163 interrupts = <14>;
164 status = "disabled";
165 };
166
167 usb@73f80400 {
168 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
169 reg = <0x73f80400 0x0200>;
170 interrupts = <16>;
171 status = "disabled";
172 };
173
174 usb@73f80600 {
175 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
176 reg = <0x73f80600 0x0200>;
177 interrupts = <17>;
178 status = "disabled";
179 };
180
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]181 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]182 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]183 reg = <0x73f84000 0x4000>;
184 interrupts = <50 51>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]188 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]189 };
190
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]191 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]192 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]193 reg = <0x73f88000 0x4000>;
194 interrupts = <52 53>;
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]198 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]199 };
200
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]201 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]202 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]203 reg = <0x73f8c000 0x4000>;
204 interrupts = <54 55>;
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]208 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]209 };
210
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]211 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]212 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]213 reg = <0x73f90000 0x4000>;
214 interrupts = <56 57>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]218 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]219 };
220
221 wdog@73f98000 { /* WDOG1 */
222 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
223 reg = <0x73f98000 0x4000>;
224 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]225 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]226 };
227
228 wdog@73f9c000 { /* WDOG2 */
229 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
230 reg = <0x73f9c000 0x4000>;
231 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]232 clocks = <&clks 0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]233 status = "disabled";
234 };
235
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]236 iomuxc@73fa8000 {
237 compatible = "fsl,imx51-iomuxc";
238 reg = <0x73fa8000 0x4000>;
239
240 audmux {
241 pinctrl_audmux_1: audmuxgrp-1 {
242 fsl,pins = <
243 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
244 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
245 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
246 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
247 >;
248 };
249 };
250
251 fec {
252 pinctrl_fec_1: fecgrp-1 {
253 fsl,pins = <
254 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
255 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
256 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
257 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
258 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
259 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
260 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
261 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
262 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
263 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
264 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
265 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
266 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
267 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
268 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
269 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
270 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
271 >;
272 };
273 };
274
275 ecspi1 {
276 pinctrl_ecspi1_1: ecspi1grp-1 {
277 fsl,pins = <
278 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
279 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
280 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
281 >;
282 };
283 };
284
285 esdhc1 {
286 pinctrl_esdhc1_1: esdhc1grp-1 {
287 fsl,pins = <
288 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
289 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
290 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
291 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
292 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
293 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
294 >;
295 };
296 };
297
298 esdhc2 {
299 pinctrl_esdhc2_1: esdhc2grp-1 {
300 fsl,pins = <
301 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
302 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
303 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
304 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
305 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
306 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
307 >;
308 };
309 };
310
311 i2c2 {
312 pinctrl_i2c2_1: i2c2grp-1 {
313 fsl,pins = <
314 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
315 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
316 >;
317 };
318 };
319
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]320 ipu_disp1 {
321 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
322 fsl,pins = <
323 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
324 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
325 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
326 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
327 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
328 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
329 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
330 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
331 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
332 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
333 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
334 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
335 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
336 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
337 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
338 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
339 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
340 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
341 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
342 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
343 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
344 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
345 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
346 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
347 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
348 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
349 >;
350 };
351 };
352
353 ipu_disp2 {
354 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
355 fsl,pins = <
356 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
357 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
358 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
359 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
360 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
361 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
362 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
363 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
364 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
365 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
366 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
367 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
368 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
369 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
370 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
371 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
372 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
373 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
374 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
375 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
376 >;
377 };
378 };
379
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]380 uart1 {
381 pinctrl_uart1_1: uart1grp-1 {
382 fsl,pins = <
383 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
384 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
385 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
386 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
387 >;
388 };
389 };
390
391 uart2 {
392 pinctrl_uart2_1: uart2grp-1 {
393 fsl,pins = <
394 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
395 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
396 >;
397 };
398 };
399
400 uart3 {
401 pinctrl_uart3_1: uart3grp-1 {
402 fsl,pins = <
403 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
404 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
405 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
406 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
407 >;
408 };
409 };
410 };
411
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame^]412 pwm1: pwm@73fb4000 {
413 #pwm-cells = <2>;
414 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
415 reg = <0x73fb4000 0x4000>;
416 clocks = <&clks 37>, <&clks 38>;
417 clock-names = "ipg", "per";
418 interrupts = <61>;
419 };
420
421 pwm2: pwm@73fb8000 {
422 #pwm-cells = <2>;
423 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
424 reg = <0x73fb8000 0x4000>;
425 clocks = <&clks 39>, <&clks 40>;
426 clock-names = "ipg", "per";
427 interrupts = <94>;
428 };
429
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]430 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]431 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
432 reg = <0x73fbc000 0x4000>;
433 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]434 clocks = <&clks 28>, <&clks 29>;
435 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]436 status = "disabled";
437 };
438
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]439 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]440 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
441 reg = <0x73fc0000 0x4000>;
442 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]443 clocks = <&clks 30>, <&clks 31>;
444 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]445 status = "disabled";
446 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]447
448 clks: ccm@73fd4000{
449 compatible = "fsl,imx51-ccm";
450 reg = <0x73fd4000 0x4000>;
451 interrupts = <0 71 0x04 0 72 0x04>;
452 #clock-cells = <1>;
453 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]454 };
455
456 aips@80000000 { /* AIPS2 */
457 compatible = "fsl,aips-bus", "simple-bus";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 reg = <0x80000000 0x10000000>;
461 ranges;
462
463 ecspi@83fac000 { /* ECSPI2 */
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "fsl,imx51-ecspi";
467 reg = <0x83fac000 0x4000>;
468 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]469 clocks = <&clks 53>, <&clks 54>;
470 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]471 status = "disabled";
472 };
473
474 sdma@83fb0000 {
475 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
476 reg = <0x83fb0000 0x4000>;
477 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]478 clocks = <&clks 56>, <&clks 56>;
479 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]480 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]481 };
482
483 cspi@83fc0000 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
487 reg = <0x83fc0000 0x4000>;
488 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]489 clocks = <&clks 55>, <&clks 0>;
490 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]491 status = "disabled";
492 };
493
494 i2c@83fc4000 { /* I2C2 */
495 #address-cells = <1>;
496 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]497 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]498 reg = <0x83fc4000 0x4000>;
499 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]500 clocks = <&clks 35>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]501 status = "disabled";
502 };
503
504 i2c@83fc8000 { /* I2C1 */
505 #address-cells = <1>;
506 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]507 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]508 reg = <0x83fc8000 0x4000>;
509 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]510 clocks = <&clks 34>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]511 status = "disabled";
512 };
513
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]514 ssi1: ssi@83fcc000 {
515 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
516 reg = <0x83fcc000 0x4000>;
517 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]518 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]519 fsl,fifo-depth = <15>;
520 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
521 status = "disabled";
522 };
523
524 audmux@83fd0000 {
525 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
526 reg = <0x83fd0000 0x4000>;
527 status = "disabled";
528 };
529
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]530 nand@83fdb000 {
531 compatible = "fsl,imx51-nand";
532 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
533 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]534 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]535 status = "disabled";
536 };
537
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]538 ssi3: ssi@83fe8000 {
539 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
540 reg = <0x83fe8000 0x4000>;
541 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]542 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]543 fsl,fifo-depth = <15>;
544 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
545 status = "disabled";
546 };
547
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]548 ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]549 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
550 reg = <0x83fec000 0x4000>;
551 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]552 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
553 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800[diff] [blame]554 status = "disabled";
555 };
556 };
557 };
558};