Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * net/dsa/mv88e6123_61_65.c - Marvell 88e6123/6161/6165 switch chip support |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 3 | * Copyright (c) 2008-2009 Marvell Semiconductor |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | */ |
| 10 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 11 | #include <linux/delay.h> |
| 12 | #include <linux/jiffies.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 13 | #include <linux/list.h> |
Paul Gortmaker | 2bbba27 | 2012-01-24 10:41:40 +0000 | [diff] [blame] | 14 | #include <linux/module.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 15 | #include <linux/netdevice.h> |
| 16 | #include <linux/phy.h> |
Ben Hutchings | c8f0b86 | 2011-11-27 17:06:08 +0000 | [diff] [blame] | 17 | #include <net/dsa.h> |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 18 | #include "mv88e6xxx.h" |
| 19 | |
| 20 | static char *mv88e6123_61_65_probe(struct mii_bus *bus, int sw_addr) |
| 21 | { |
| 22 | int ret; |
| 23 | |
| 24 | ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03); |
| 25 | if (ret >= 0) { |
Chris Healy | edd664b | 2012-01-22 21:20:54 +0000 | [diff] [blame] | 26 | if (ret == 0x1212) |
| 27 | return "Marvell 88E6123 (A1)"; |
| 28 | if (ret == 0x1213) |
| 29 | return "Marvell 88E6123 (A2)"; |
| 30 | if ((ret & 0xfff0) == 0x1210) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 31 | return "Marvell 88E6123"; |
Chris Healy | edd664b | 2012-01-22 21:20:54 +0000 | [diff] [blame] | 32 | |
| 33 | if (ret == 0x1612) |
| 34 | return "Marvell 88E6161 (A1)"; |
| 35 | if (ret == 0x1613) |
| 36 | return "Marvell 88E6161 (A2)"; |
| 37 | if ((ret & 0xfff0) == 0x1610) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 38 | return "Marvell 88E6161"; |
Chris Healy | edd664b | 2012-01-22 21:20:54 +0000 | [diff] [blame] | 39 | |
| 40 | if (ret == 0x1652) |
| 41 | return "Marvell 88E6165 (A1)"; |
| 42 | if (ret == 0x1653) |
| 43 | return "Marvell 88e6165 (A2)"; |
| 44 | if ((ret & 0xfff0) == 0x1650) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 45 | return "Marvell 88E6165"; |
| 46 | } |
| 47 | |
| 48 | return NULL; |
| 49 | } |
| 50 | |
| 51 | static int mv88e6123_61_65_switch_reset(struct dsa_switch *ds) |
| 52 | { |
| 53 | int i; |
| 54 | int ret; |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 55 | unsigned long timeout; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 56 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 57 | /* Set all ports to the disabled state. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 58 | for (i = 0; i < 8; i++) { |
| 59 | ret = REG_READ(REG_PORT(i), 0x04); |
| 60 | REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); |
| 61 | } |
| 62 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 63 | /* Wait for transmit queues to drain. */ |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 64 | usleep_range(2000, 4000); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 65 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 66 | /* Reset the switch. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 67 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); |
| 68 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 69 | /* Wait up to one second for reset to complete. */ |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 70 | timeout = jiffies + 1 * HZ; |
| 71 | while (time_before(jiffies, timeout)) { |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 72 | ret = REG_READ(REG_GLOBAL, 0x00); |
| 73 | if ((ret & 0xc800) == 0xc800) |
| 74 | break; |
| 75 | |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 76 | usleep_range(1000, 2000); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 77 | } |
Barry Grussling | 19b2f97 | 2013-01-08 16:05:54 +0000 | [diff] [blame] | 78 | if (time_after(jiffies, timeout)) |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 79 | return -ETIMEDOUT; |
| 80 | |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static int mv88e6123_61_65_setup_global(struct dsa_switch *ds) |
| 85 | { |
| 86 | int ret; |
| 87 | int i; |
| 88 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 89 | /* Disable the PHY polling unit (since there won't be any |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 90 | * external PHYs to poll), don't discard packets with |
| 91 | * excessive collisions, and mask all interrupt sources. |
| 92 | */ |
| 93 | REG_WRITE(REG_GLOBAL, 0x04, 0x0000); |
| 94 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 95 | /* Set the default address aging time to 5 minutes, and |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 96 | * enable address learn messages to be sent to all message |
| 97 | * ports. |
| 98 | */ |
| 99 | REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); |
| 100 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 101 | /* Configure the priority mapping registers. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 102 | ret = mv88e6xxx_config_prio(ds); |
| 103 | if (ret < 0) |
| 104 | return ret; |
| 105 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 106 | /* Configure the upstream port, and configure the upstream |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 107 | * port as the port to which ingress and egress monitor frames |
| 108 | * are to be sent. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 109 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 110 | REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 111 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 112 | /* Disable remote management for now, and set the switch's |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 113 | * DSA device number. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 114 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 115 | REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 116 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 117 | /* Send all frames with destination addresses matching |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 118 | * 01:80:c2:00:00:2x to the CPU port. |
| 119 | */ |
| 120 | REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); |
| 121 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 122 | /* Send all frames with destination addresses matching |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 123 | * 01:80:c2:00:00:0x to the CPU port. |
| 124 | */ |
| 125 | REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); |
| 126 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 127 | /* Disable the loopback filter, disable flow control |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 128 | * messages, disable flood broadcast override, disable |
| 129 | * removing of provider tags, disable ATU age violation |
| 130 | * interrupts, disable tag flow control, force flow |
| 131 | * control priority to the highest, and send all special |
| 132 | * multicast frames to the CPU at the highest priority. |
| 133 | */ |
| 134 | REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); |
| 135 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 136 | /* Program the DSA routing table. */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 137 | for (i = 0; i < 32; i++) { |
| 138 | int nexthop; |
| 139 | |
| 140 | nexthop = 0x1f; |
| 141 | if (i != ds->index && i < ds->dst->pd->nr_chips) |
| 142 | nexthop = ds->pd->rtable[i] & 0x1f; |
| 143 | |
| 144 | REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop); |
| 145 | } |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 146 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 147 | /* Clear all trunk masks. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 148 | for (i = 0; i < 8; i++) |
| 149 | REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0xff); |
| 150 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 151 | /* Clear all trunk mappings. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 152 | for (i = 0; i < 16; i++) |
| 153 | REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11)); |
| 154 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 155 | /* Disable ingress rate limiting by resetting all ingress |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 156 | * rate limit registers to their initial state. |
| 157 | */ |
| 158 | for (i = 0; i < 6; i++) |
| 159 | REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8)); |
| 160 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 161 | /* Initialise cross-chip port VLAN table to reset defaults. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 162 | REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000); |
| 163 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 164 | /* Clear the priority override table. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 165 | for (i = 0; i < 16; i++) |
| 166 | REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8)); |
| 167 | |
| 168 | /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */ |
| 169 | |
| 170 | return 0; |
| 171 | } |
| 172 | |
| 173 | static int mv88e6123_61_65_setup_port(struct dsa_switch *ds, int p) |
| 174 | { |
| 175 | int addr = REG_PORT(p); |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 176 | u16 val; |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 177 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 178 | /* MAC Forcing register: don't force link, speed, duplex |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 179 | * or flow control state to any particular values on physical |
| 180 | * ports, but force the CPU port and all DSA ports to 1000 Mb/s |
| 181 | * full duplex. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 182 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 183 | if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) |
| 184 | REG_WRITE(addr, 0x01, 0x003e); |
| 185 | else |
| 186 | REG_WRITE(addr, 0x01, 0x0003); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 187 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 188 | /* Do not limit the period of time that this port can be |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 189 | * paused for by the remote end or the period of time that |
| 190 | * this port can pause the remote end. |
| 191 | */ |
| 192 | REG_WRITE(addr, 0x02, 0x0000); |
| 193 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 194 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 195 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
| 196 | * tunneling, determine priority by looking at 802.1p and IP |
| 197 | * priority fields (IP prio has precedence), and set STP state |
| 198 | * to Forwarding. |
| 199 | * |
| 200 | * If this is the CPU link, use DSA or EDSA tagging depending |
| 201 | * on which tagging mode was configured. |
| 202 | * |
| 203 | * If this is a link to another switch, use DSA tagging mode. |
| 204 | * |
| 205 | * If this is the upstream port for this switch, enable |
| 206 | * forwarding of unknown unicasts and multicasts. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 207 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 208 | val = 0x0433; |
| 209 | if (dsa_is_cpu_port(ds, p)) { |
| 210 | if (ds->dst->tag_protocol == htons(ETH_P_EDSA)) |
| 211 | val |= 0x3300; |
| 212 | else |
| 213 | val |= 0x0100; |
| 214 | } |
| 215 | if (ds->dsa_port_mask & (1 << p)) |
| 216 | val |= 0x0100; |
| 217 | if (p == dsa_upstream_port(ds)) |
| 218 | val |= 0x000c; |
| 219 | REG_WRITE(addr, 0x04, val); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 220 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 221 | /* Port Control 1: disable trunking. Also, if this is the |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 222 | * CPU port, enable learn messages to be sent to this port. |
| 223 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 224 | REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 225 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 226 | /* Port based VLAN map: give each port its own address |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 227 | * database, allow the CPU port to talk to each of the 'real' |
| 228 | * ports, and allow each of the 'real' ports to only talk to |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 229 | * the upstream port. |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 230 | */ |
Lennert Buytenhek | e84665c | 2009-03-20 09:52:09 +0000 | [diff] [blame] | 231 | val = (p & 0xf) << 12; |
| 232 | if (dsa_is_cpu_port(ds, p)) |
| 233 | val |= ds->phys_port_mask; |
| 234 | else |
| 235 | val |= 1 << dsa_upstream_port(ds); |
| 236 | REG_WRITE(addr, 0x06, val); |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 237 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 238 | /* Default VLAN ID and priority: don't set a default VLAN |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 239 | * ID, and set the default packet priority to zero. |
| 240 | */ |
| 241 | REG_WRITE(addr, 0x07, 0x0000); |
| 242 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 243 | /* Port Control 2: don't force a good FCS, set the maximum |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 244 | * frame size to 10240 bytes, don't let the switch add or |
| 245 | * strip 802.1q tags, don't discard tagged or untagged frames |
| 246 | * on this port, do a destination address lookup on all |
| 247 | * received packets as usual, disable ARP mirroring and don't |
| 248 | * send a copy of all transmitted/received frames on this port |
| 249 | * to the CPU. |
| 250 | */ |
| 251 | REG_WRITE(addr, 0x08, 0x2080); |
| 252 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 253 | /* Egress rate control: disable egress rate control. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 254 | REG_WRITE(addr, 0x09, 0x0001); |
| 255 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 256 | /* Egress rate control 2: disable egress rate control. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 257 | REG_WRITE(addr, 0x0a, 0x0000); |
| 258 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 259 | /* Port Association Vector: when learning source addresses |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 260 | * of packets, add the address to the address database using |
| 261 | * a port bitmap that has only the bit for this port set and |
| 262 | * the other bits clear. |
| 263 | */ |
| 264 | REG_WRITE(addr, 0x0b, 1 << p); |
| 265 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 266 | /* Port ATU control: disable limiting the number of address |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 267 | * database entries that this port is allowed to use. |
| 268 | */ |
| 269 | REG_WRITE(addr, 0x0c, 0x0000); |
| 270 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 271 | /* Priority Override: disable DA, SA and VTU priority override. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 272 | REG_WRITE(addr, 0x0d, 0x0000); |
| 273 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 274 | /* Port Ethertype: use the Ethertype DSA Ethertype value. */ |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 275 | REG_WRITE(addr, 0x0f, ETH_P_EDSA); |
| 276 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 277 | /* Tag Remap: use an identity 802.1p prio -> switch prio |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 278 | * mapping. |
| 279 | */ |
| 280 | REG_WRITE(addr, 0x18, 0x3210); |
| 281 | |
Barry Grussling | 3675c8d | 2013-01-08 16:05:53 +0000 | [diff] [blame] | 282 | /* Tag Remap 2: use an identity 802.1p prio -> switch prio |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 283 | * mapping. |
| 284 | */ |
| 285 | REG_WRITE(addr, 0x19, 0x7654); |
| 286 | |
| 287 | return 0; |
| 288 | } |
| 289 | |
| 290 | static int mv88e6123_61_65_setup(struct dsa_switch *ds) |
| 291 | { |
| 292 | struct mv88e6xxx_priv_state *ps = (void *)(ds + 1); |
| 293 | int i; |
| 294 | int ret; |
| 295 | |
| 296 | mutex_init(&ps->smi_mutex); |
| 297 | mutex_init(&ps->stats_mutex); |
| 298 | |
| 299 | ret = mv88e6123_61_65_switch_reset(ds); |
| 300 | if (ret < 0) |
| 301 | return ret; |
| 302 | |
| 303 | /* @@@ initialise vtu and atu */ |
| 304 | |
| 305 | ret = mv88e6123_61_65_setup_global(ds); |
| 306 | if (ret < 0) |
| 307 | return ret; |
| 308 | |
| 309 | for (i = 0; i < 6; i++) { |
| 310 | ret = mv88e6123_61_65_setup_port(ds, i); |
| 311 | if (ret < 0) |
| 312 | return ret; |
| 313 | } |
| 314 | |
| 315 | return 0; |
| 316 | } |
| 317 | |
| 318 | static int mv88e6123_61_65_port_to_phy_addr(int port) |
| 319 | { |
| 320 | if (port >= 0 && port <= 4) |
| 321 | return port; |
| 322 | return -1; |
| 323 | } |
| 324 | |
| 325 | static int |
| 326 | mv88e6123_61_65_phy_read(struct dsa_switch *ds, int port, int regnum) |
| 327 | { |
| 328 | int addr = mv88e6123_61_65_port_to_phy_addr(port); |
| 329 | return mv88e6xxx_phy_read(ds, addr, regnum); |
| 330 | } |
| 331 | |
| 332 | static int |
| 333 | mv88e6123_61_65_phy_write(struct dsa_switch *ds, |
| 334 | int port, int regnum, u16 val) |
| 335 | { |
| 336 | int addr = mv88e6123_61_65_port_to_phy_addr(port); |
| 337 | return mv88e6xxx_phy_write(ds, addr, regnum, val); |
| 338 | } |
| 339 | |
| 340 | static struct mv88e6xxx_hw_stat mv88e6123_61_65_hw_stats[] = { |
| 341 | { "in_good_octets", 8, 0x00, }, |
| 342 | { "in_bad_octets", 4, 0x02, }, |
| 343 | { "in_unicast", 4, 0x04, }, |
| 344 | { "in_broadcasts", 4, 0x06, }, |
| 345 | { "in_multicasts", 4, 0x07, }, |
| 346 | { "in_pause", 4, 0x16, }, |
| 347 | { "in_undersize", 4, 0x18, }, |
| 348 | { "in_fragments", 4, 0x19, }, |
| 349 | { "in_oversize", 4, 0x1a, }, |
| 350 | { "in_jabber", 4, 0x1b, }, |
| 351 | { "in_rx_error", 4, 0x1c, }, |
| 352 | { "in_fcs_error", 4, 0x1d, }, |
| 353 | { "out_octets", 8, 0x0e, }, |
| 354 | { "out_unicast", 4, 0x10, }, |
| 355 | { "out_broadcasts", 4, 0x13, }, |
| 356 | { "out_multicasts", 4, 0x12, }, |
| 357 | { "out_pause", 4, 0x15, }, |
| 358 | { "excessive", 4, 0x11, }, |
| 359 | { "collisions", 4, 0x1e, }, |
| 360 | { "deferred", 4, 0x05, }, |
| 361 | { "single", 4, 0x14, }, |
| 362 | { "multiple", 4, 0x17, }, |
| 363 | { "out_fcs_error", 4, 0x03, }, |
| 364 | { "late", 4, 0x1f, }, |
| 365 | { "hist_64bytes", 4, 0x08, }, |
| 366 | { "hist_65_127bytes", 4, 0x09, }, |
| 367 | { "hist_128_255bytes", 4, 0x0a, }, |
| 368 | { "hist_256_511bytes", 4, 0x0b, }, |
| 369 | { "hist_512_1023bytes", 4, 0x0c, }, |
| 370 | { "hist_1024_max_bytes", 4, 0x0d, }, |
| 371 | }; |
| 372 | |
| 373 | static void |
| 374 | mv88e6123_61_65_get_strings(struct dsa_switch *ds, int port, uint8_t *data) |
| 375 | { |
| 376 | mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), |
| 377 | mv88e6123_61_65_hw_stats, port, data); |
| 378 | } |
| 379 | |
| 380 | static void |
| 381 | mv88e6123_61_65_get_ethtool_stats(struct dsa_switch *ds, |
| 382 | int port, uint64_t *data) |
| 383 | { |
| 384 | mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6123_61_65_hw_stats), |
| 385 | mv88e6123_61_65_hw_stats, port, data); |
| 386 | } |
| 387 | |
| 388 | static int mv88e6123_61_65_get_sset_count(struct dsa_switch *ds) |
| 389 | { |
| 390 | return ARRAY_SIZE(mv88e6123_61_65_hw_stats); |
| 391 | } |
| 392 | |
Ben Hutchings | 98e6730 | 2011-11-25 14:36:19 +0000 | [diff] [blame] | 393 | struct dsa_switch_driver mv88e6123_61_65_switch_driver = { |
Harvey Harrison | 09640e6 | 2009-02-01 00:45:17 -0800 | [diff] [blame] | 394 | .tag_protocol = cpu_to_be16(ETH_P_EDSA), |
Lennert Buytenhek | 91da11f | 2008-10-07 13:44:02 +0000 | [diff] [blame] | 395 | .priv_size = sizeof(struct mv88e6xxx_priv_state), |
| 396 | .probe = mv88e6123_61_65_probe, |
| 397 | .setup = mv88e6123_61_65_setup, |
| 398 | .set_addr = mv88e6xxx_set_addr_indirect, |
| 399 | .phy_read = mv88e6123_61_65_phy_read, |
| 400 | .phy_write = mv88e6123_61_65_phy_write, |
| 401 | .poll_link = mv88e6xxx_poll_link, |
| 402 | .get_strings = mv88e6123_61_65_get_strings, |
| 403 | .get_ethtool_stats = mv88e6123_61_65_get_ethtool_stats, |
| 404 | .get_sset_count = mv88e6123_61_65_get_sset_count, |
| 405 | }; |
Ben Hutchings | 3d825ed | 2011-11-25 14:37:16 +0000 | [diff] [blame] | 406 | |
| 407 | MODULE_ALIAS("platform:mv88e6123"); |
| 408 | MODULE_ALIAS("platform:mv88e6161"); |
| 409 | MODULE_ALIAS("platform:mv88e6165"); |