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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel AGPGART routines.
3 */
4
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/init.h>
Ahmed S. Darwish1eaf1222007-02-06 18:08:28 +02008#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/pagemap.h>
10#include <linux/agp_backend.h>
11#include "agp.h"
12
Carlos Martíne914a362008-01-24 10:34:09 +100013#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
Eric Anholt65c25aa2006-09-06 11:57:18 -040015#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
Zhenyu Wang9119f852008-01-23 15:49:26 +100017#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
Eric Anholt65c25aa2006-09-06 11:57:18 -040019#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
Wang Zhenyu4598af32007-04-09 08:51:36 +080023#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
Zhenyu Wangdde47872007-07-26 09:18:09 +080025#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
Wang Zhenyuc8eebfd2007-05-31 11:34:06 +080026#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
Zhenyu Wangdde47872007-07-26 09:18:09 +080027#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
Wang Zhenyudf80b142007-05-31 11:51:12 +080028#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
Wang Zhenyu874808c62007-06-06 11:16:25 +080029#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
Zhenyu Wang99d32bd2008-07-30 12:26:50 -070035#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
36#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100037#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
Eric Anholt65c25aa2006-09-06 11:57:18 -040043
Dave Airlief011ae72008-01-25 11:23:04 +100044/* cover 915 and 945 variants */
45#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
46 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
51
Eric Anholt65c25aa2006-09-06 11:57:18 -040052#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
Dave Airlief011ae72008-01-25 11:23:04 +100053 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
54 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
Eric Anholt82e14a62008-10-14 11:28:58 -070057 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
Eric Anholt65c25aa2006-09-06 11:57:18 -040058
Wang Zhenyu874808c62007-06-06 11:16:25 +080059#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
60 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
Eric Anholt65c25aa2006-09-06 11:57:18 -040062
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100063#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
64 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
Eric Anholt82e14a62008-10-14 11:28:58 -070065 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB)
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100067
Thomas Hellstroma030ce42007-01-23 10:33:43 +010068extern int agp_memory_reserved;
69
70
Linus Torvalds1da177e2005-04-16 15:20:36 -070071/* Intel 815 register */
72#define INTEL_815_APCONT 0x51
73#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
74
75/* Intel i820 registers */
76#define INTEL_I820_RDCR 0x51
77#define INTEL_I820_ERRSTS 0xc8
78
79/* Intel i840 registers */
80#define INTEL_I840_MCHCFG 0x50
81#define INTEL_I840_ERRSTS 0xc8
82
83/* Intel i850 registers */
84#define INTEL_I850_MCHCFG 0x50
85#define INTEL_I850_ERRSTS 0xc8
86
87/* intel 915G registers */
88#define I915_GMADDR 0x18
89#define I915_MMADDR 0x10
90#define I915_PTEADDR 0x1C
91#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
92#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100093#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
94#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
95#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
96#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
97#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
98#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
99
Dave Airlie6c00a612007-10-29 18:06:10 +1000100#define I915_IFPADDR 0x60
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Eric Anholt65c25aa2006-09-06 11:57:18 -0400102/* Intel 965G registers */
103#define I965_MSAC 0x62
Dave Airlie6c00a612007-10-29 18:06:10 +1000104#define I965_IFPADDR 0x70
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105
106/* Intel 7505 registers */
107#define INTEL_I7505_APSIZE 0x74
108#define INTEL_I7505_NCAPID 0x60
109#define INTEL_I7505_NISTAT 0x6c
110#define INTEL_I7505_ATTBASE 0x78
111#define INTEL_I7505_ERRSTS 0x42
112#define INTEL_I7505_AGPCTRL 0x70
113#define INTEL_I7505_MCHCFG 0x50
114
Dave Jonese5524f32007-02-22 18:41:28 -0500115static const struct aper_size_info_fixed intel_i810_sizes[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116{
117 {64, 16384, 4},
118 /* The 32M mode still requires a 64k gatt */
119 {32, 8192, 4}
120};
121
122#define AGP_DCACHE_MEMORY 1
123#define AGP_PHYS_MEMORY 2
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100124#define INTEL_AGP_CACHED_MEMORY 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126static struct gatt_mask intel_i810_masks[] =
127{
128 {.mask = I810_PTE_VALID, .type = 0},
129 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100130 {.mask = I810_PTE_VALID, .type = 0},
131 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
132 .type = INTEL_AGP_CACHED_MEMORY}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133};
134
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800135static struct _intel_private {
136 struct pci_dev *pcidev; /* device one */
137 u8 __iomem *registers;
138 u32 __iomem *gtt; /* I915G */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 int num_dcache_entries;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800140 /* gtt_entries is the number of gtt entries that are already mapped
141 * to stolen memory. Stolen memory is larger than the memory mapped
142 * through gtt_entries, as it includes some reserved space for the BIOS
143 * popup and for the GTT.
144 */
145 int gtt_entries; /* i830+ */
Dave Airlie2162e6a2007-11-21 16:36:31 +1000146 union {
147 void __iomem *i9xx_flush_page;
148 void *i8xx_flush_page;
149 };
150 struct page *i8xx_page;
Dave Airlie6c00a612007-10-29 18:06:10 +1000151 struct resource ifp_resource;
Dave Airlie4d64dd92008-01-23 15:34:29 +1000152 int resource_valid;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800153} intel_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154
155static int intel_i810_fetch_size(void)
156{
157 u32 smram_miscc;
158 struct aper_size_info_fixed *values;
159
160 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
161 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
162
163 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700164 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 return 0;
166 }
167 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
168 agp_bridge->previous_size =
169 agp_bridge->current_size = (void *) (values + 1);
170 agp_bridge->aperture_size_idx = 1;
171 return values[1].size;
172 } else {
173 agp_bridge->previous_size =
174 agp_bridge->current_size = (void *) (values);
175 agp_bridge->aperture_size_idx = 0;
176 return values[0].size;
177 }
178
179 return 0;
180}
181
182static int intel_i810_configure(void)
183{
184 struct aper_size_info_fixed *current_size;
185 u32 temp;
186 int i;
187
188 current_size = A_SIZE_FIX(agp_bridge->current_size);
189
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800190 if (!intel_private.registers) {
191 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
Dave Jonese4ac5e42007-02-04 17:37:42 -0500192 temp &= 0xfff80000;
193
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800194 intel_private.registers = ioremap(temp, 128 * 4096);
195 if (!intel_private.registers) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700196 dev_err(&intel_private.pcidev->dev,
197 "can't remap memory\n");
Dave Jonese4ac5e42007-02-04 17:37:42 -0500198 return -ENOMEM;
199 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 }
201
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800202 if ((readl(intel_private.registers+I810_DRAM_CTL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
204 /* This will need to be dynamically assigned */
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700205 dev_info(&intel_private.pcidev->dev,
206 "detected 4MB dedicated video ram\n");
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800207 intel_private.num_dcache_entries = 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800209 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800211 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
212 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
214 if (agp_bridge->driver->needs_scratch_page) {
215 for (i = 0; i < current_size->num_entries; i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800216 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
217 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 }
219 }
220 global_cache_flush();
221 return 0;
222}
223
224static void intel_i810_cleanup(void)
225{
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800226 writel(0, intel_private.registers+I810_PGETBL_CTL);
227 readl(intel_private.registers); /* PCI Posting. */
228 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229}
230
231static void intel_i810_tlbflush(struct agp_memory *mem)
232{
233 return;
234}
235
236static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
237{
238 return;
239}
240
241/* Exists to support ARGB cursors */
242static void *i8xx_alloc_pages(void)
243{
Dave Airlief011ae72008-01-25 11:23:04 +1000244 struct page *page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245
Linus Torvalds66c669b2006-11-22 14:55:29 -0800246 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 if (page == NULL)
248 return NULL;
249
Arjan van de Ven6d238cc2008-01-30 13:34:06 +0100250 if (set_pages_uc(page, 4) < 0) {
251 set_pages_wb(page, 4);
Jan Beulich89cf7cc2007-04-02 14:50:14 +0100252 __free_pages(page, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 return NULL;
254 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 get_page(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 atomic_inc(&agp_bridge->current_memory_agp);
257 return page_address(page);
258}
259
260static void i8xx_destroy_pages(void *addr)
261{
262 struct page *page;
263
264 if (addr == NULL)
265 return;
266
267 page = virt_to_page(addr);
Arjan van de Ven6d238cc2008-01-30 13:34:06 +0100268 set_pages_wb(page, 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 put_page(page);
Jan Beulich89cf7cc2007-04-02 14:50:14 +0100270 __free_pages(page, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 atomic_dec(&agp_bridge->current_memory_agp);
272}
273
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100274static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
275 int type)
276{
277 if (type < AGP_USER_TYPES)
278 return type;
279 else if (type == AGP_USER_CACHED_MEMORY)
280 return INTEL_AGP_CACHED_MEMORY;
281 else
282 return 0;
283}
284
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
286 int type)
287{
288 int i, j, num_entries;
289 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100290 int ret = -EINVAL;
291 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100293 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100294 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100295
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 temp = agp_bridge->current_size;
297 num_entries = A_SIZE_FIX(temp)->num_entries;
298
Dave Jones6a92a4e2006-02-28 00:54:25 -0500299 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100300 goto out_err;
301
Dave Jones6a92a4e2006-02-28 00:54:25 -0500302
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100304 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
305 ret = -EBUSY;
306 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 }
309
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100310 if (type != mem->type)
311 goto out_err;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100312
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100313 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
314
315 switch (mask_type) {
316 case AGP_DCACHE_MEMORY:
317 if (!mem->is_flushed)
318 global_cache_flush();
319 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
320 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800321 intel_private.registers+I810_PTE_BASE+(i*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100322 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800323 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100324 break;
325 case AGP_PHYS_MEMORY:
326 case AGP_NORMAL_MEMORY:
327 if (!mem->is_flushed)
328 global_cache_flush();
329 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
330 writel(agp_bridge->driver->mask_memory(agp_bridge,
331 mem->memory[i],
332 mask_type),
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800333 intel_private.registers+I810_PTE_BASE+(j*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100334 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800335 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100336 break;
337 default:
338 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700339 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340
341 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100342out:
343 ret = 0;
344out_err:
Dave Airlie9516b032008-06-19 10:42:17 +1000345 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100346 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347}
348
349static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
350 int type)
351{
352 int i;
353
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100354 if (mem->page_count == 0)
355 return 0;
356
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800358 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800360 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 agp_bridge->driver->tlb_flush(mem);
363 return 0;
364}
365
366/*
367 * The i810/i830 requires a physical address to program its mouse
368 * pointer into hardware.
369 * However the Xserver still writes to it through the agp aperture.
370 */
371static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
372{
373 struct agp_memory *new;
374 void *addr;
375
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 switch (pg_count) {
377 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
378 break;
379 case 4:
380 /* kludge to get 4 physical pages for ARGB cursor */
381 addr = i8xx_alloc_pages();
382 break;
383 default:
384 return NULL;
385 }
386
387 if (addr == NULL)
388 return NULL;
389
390 new = agp_create_memory(pg_count);
391 if (new == NULL)
392 return NULL;
393
Keir Fraser07eee782005-03-30 13:17:04 -0800394 new->memory[0] = virt_to_gart(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 if (pg_count == 4) {
396 /* kludge to get 4 physical pages for ARGB cursor */
397 new->memory[1] = new->memory[0] + PAGE_SIZE;
398 new->memory[2] = new->memory[1] + PAGE_SIZE;
399 new->memory[3] = new->memory[2] + PAGE_SIZE;
400 }
401 new->page_count = pg_count;
402 new->num_scratch_pages = pg_count;
403 new->type = AGP_PHYS_MEMORY;
404 new->physical = new->memory[0];
405 return new;
406}
407
408static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
409{
410 struct agp_memory *new;
411
412 if (type == AGP_DCACHE_MEMORY) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800413 if (pg_count != intel_private.num_dcache_entries)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414 return NULL;
415
416 new = agp_create_memory(1);
417 if (new == NULL)
418 return NULL;
419
420 new->type = AGP_DCACHE_MEMORY;
421 new->page_count = pg_count;
422 new->num_scratch_pages = 0;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100423 agp_free_page_array(new);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 return new;
425 }
426 if (type == AGP_PHYS_MEMORY)
427 return alloc_agpphysmem_i8xx(pg_count, type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 return NULL;
429}
430
431static void intel_i810_free_by_type(struct agp_memory *curr)
432{
433 agp_free_key(curr->key);
Dave Jones6a92a4e2006-02-28 00:54:25 -0500434 if (curr->type == AGP_PHYS_MEMORY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 if (curr->page_count == 4)
Keir Fraser07eee782005-03-30 13:17:04 -0800436 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
Alan Hourihane88d51962005-11-06 23:35:34 -0800437 else {
Jan Beulichda503fa2008-06-18 09:28:00 +0100438 void *va = gart_to_virt(curr->memory[0]);
439
440 agp_bridge->driver->agp_destroy_page(va,
Dave Airliea2721e92007-10-15 10:19:16 +1000441 AGP_PAGE_DESTROY_UNMAP);
Jan Beulichda503fa2008-06-18 09:28:00 +0100442 agp_bridge->driver->agp_destroy_page(va,
Dave Airliea2721e92007-10-15 10:19:16 +1000443 AGP_PAGE_DESTROY_FREE);
Alan Hourihane88d51962005-11-06 23:35:34 -0800444 }
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100445 agp_free_page_array(curr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 }
447 kfree(curr);
448}
449
450static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
451 unsigned long addr, int type)
452{
453 /* Type checking must be done elsewhere */
454 return addr | bridge->driver->masks[type].mask;
455}
456
457static struct aper_size_info_fixed intel_i830_sizes[] =
458{
459 {128, 32768, 5},
460 /* The 64M mode still requires a 128k gatt */
461 {64, 16384, 5},
462 {256, 65536, 6},
Eric Anholt65c25aa2006-09-06 11:57:18 -0400463 {512, 131072, 7},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464};
465
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466static void intel_i830_init_gtt_entries(void)
467{
468 u16 gmch_ctrl;
469 int gtt_entries;
470 u8 rdct;
471 int local = 0;
472 static const int ddt[4] = { 0, 16, 32, 64 };
Eric Anholtc41e0de2006-12-19 12:57:24 -0800473 int size; /* reserved space (in kb) at the top of stolen memory */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
Dave Airlief011ae72008-01-25 11:23:04 +1000475 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
Eric Anholtc41e0de2006-12-19 12:57:24 -0800477 if (IS_I965) {
478 u32 pgetbl_ctl;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800479 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
Eric Anholtc41e0de2006-12-19 12:57:24 -0800480
Eric Anholtc41e0de2006-12-19 12:57:24 -0800481 /* The 965 has a field telling us the size of the GTT,
482 * which may be larger than what is necessary to map the
483 * aperture.
484 */
485 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
486 case I965_PGETBL_SIZE_128KB:
487 size = 128;
488 break;
489 case I965_PGETBL_SIZE_256KB:
490 size = 256;
491 break;
492 case I965_PGETBL_SIZE_512KB:
493 size = 512;
494 break;
Zhenyu Wang4e8b6e22008-01-23 14:54:37 +1000495 case I965_PGETBL_SIZE_1MB:
496 size = 1024;
497 break;
498 case I965_PGETBL_SIZE_2MB:
499 size = 2048;
500 break;
501 case I965_PGETBL_SIZE_1_5MB:
502 size = 1024 + 512;
503 break;
Eric Anholtc41e0de2006-12-19 12:57:24 -0800504 default:
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700505 dev_info(&intel_private.pcidev->dev,
506 "unknown page table size, assuming 512KB\n");
Eric Anholtc41e0de2006-12-19 12:57:24 -0800507 size = 512;
508 }
509 size += 4; /* add in BIOS popup space */
Wang Zhenyu874808c62007-06-06 11:16:25 +0800510 } else if (IS_G33) {
511 /* G33's GTT size defined in gmch_ctrl */
512 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
513 case G33_PGETBL_SIZE_1M:
514 size = 1024;
515 break;
516 case G33_PGETBL_SIZE_2M:
517 size = 2048;
518 break;
519 default:
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700520 dev_info(&agp_bridge->dev->dev,
521 "unknown page table size 0x%x, assuming 512KB\n",
Wang Zhenyu874808c62007-06-06 11:16:25 +0800522 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
523 size = 512;
524 }
525 size += 4;
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000526 } else if (IS_G4X) {
527 /* On 4 series hardware, GTT stolen is separate from graphics
Eric Anholt82e14a62008-10-14 11:28:58 -0700528 * stolen, ignore it in stolen gtt entries counting. However,
529 * 4KB of the stolen memory doesn't get mapped to the GTT.
530 */
531 size = 4;
Eric Anholtc41e0de2006-12-19 12:57:24 -0800532 } else {
533 /* On previous hardware, the GTT size was just what was
534 * required to map the aperture.
535 */
536 size = agp_bridge->driver->fetch_size() + 4;
537 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
539 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
540 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
541 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
542 case I830_GMCH_GMS_STOLEN_512:
543 gtt_entries = KB(512) - KB(size);
544 break;
545 case I830_GMCH_GMS_STOLEN_1024:
546 gtt_entries = MB(1) - KB(size);
547 break;
548 case I830_GMCH_GMS_STOLEN_8192:
549 gtt_entries = MB(8) - KB(size);
550 break;
551 case I830_GMCH_GMS_LOCAL:
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800552 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
554 MB(ddt[I830_RDRAM_DDT(rdct)]);
555 local = 1;
556 break;
557 default:
558 gtt_entries = 0;
559 break;
560 }
561 } else {
Dave Airliee67aa272007-09-18 22:46:35 -0700562 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 case I855_GMCH_GMS_STOLEN_1M:
564 gtt_entries = MB(1) - KB(size);
565 break;
566 case I855_GMCH_GMS_STOLEN_4M:
567 gtt_entries = MB(4) - KB(size);
568 break;
569 case I855_GMCH_GMS_STOLEN_8M:
570 gtt_entries = MB(8) - KB(size);
571 break;
572 case I855_GMCH_GMS_STOLEN_16M:
573 gtt_entries = MB(16) - KB(size);
574 break;
575 case I855_GMCH_GMS_STOLEN_32M:
576 gtt_entries = MB(32) - KB(size);
577 break;
578 case I915_GMCH_GMS_STOLEN_48M:
579 /* Check it's really I915G */
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000580 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581 gtt_entries = MB(48) - KB(size);
582 else
583 gtt_entries = 0;
584 break;
585 case I915_GMCH_GMS_STOLEN_64M:
586 /* Check it's really I915G */
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000587 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588 gtt_entries = MB(64) - KB(size);
589 else
590 gtt_entries = 0;
Wang Zhenyu874808c62007-06-06 11:16:25 +0800591 break;
592 case G33_GMCH_GMS_STOLEN_128M:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000593 if (IS_G33 || IS_I965 || IS_G4X)
Wang Zhenyu874808c62007-06-06 11:16:25 +0800594 gtt_entries = MB(128) - KB(size);
595 else
596 gtt_entries = 0;
597 break;
598 case G33_GMCH_GMS_STOLEN_256M:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000599 if (IS_G33 || IS_I965 || IS_G4X)
Wang Zhenyu874808c62007-06-06 11:16:25 +0800600 gtt_entries = MB(256) - KB(size);
601 else
602 gtt_entries = 0;
603 break;
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000604 case INTEL_GMCH_GMS_STOLEN_96M:
605 if (IS_I965 || IS_G4X)
606 gtt_entries = MB(96) - KB(size);
607 else
608 gtt_entries = 0;
609 break;
610 case INTEL_GMCH_GMS_STOLEN_160M:
611 if (IS_I965 || IS_G4X)
612 gtt_entries = MB(160) - KB(size);
613 else
614 gtt_entries = 0;
615 break;
616 case INTEL_GMCH_GMS_STOLEN_224M:
617 if (IS_I965 || IS_G4X)
618 gtt_entries = MB(224) - KB(size);
619 else
620 gtt_entries = 0;
621 break;
622 case INTEL_GMCH_GMS_STOLEN_352M:
623 if (IS_I965 || IS_G4X)
624 gtt_entries = MB(352) - KB(size);
625 else
626 gtt_entries = 0;
627 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 default:
629 gtt_entries = 0;
630 break;
631 }
632 }
633 if (gtt_entries > 0)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700634 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700635 gtt_entries / KB(1), local ? "local" : "stolen");
636 else
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700637 dev_info(&agp_bridge->dev->dev,
638 "no pre-allocated video memory detected\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639 gtt_entries /= KB(4);
640
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800641 intel_private.gtt_entries = gtt_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642}
643
Dave Airlie2162e6a2007-11-21 16:36:31 +1000644static void intel_i830_fini_flush(void)
645{
646 kunmap(intel_private.i8xx_page);
647 intel_private.i8xx_flush_page = NULL;
648 unmap_page_from_agp(intel_private.i8xx_page);
Dave Airlie2162e6a2007-11-21 16:36:31 +1000649
650 __free_page(intel_private.i8xx_page);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000651 intel_private.i8xx_page = NULL;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000652}
653
654static void intel_i830_setup_flush(void)
655{
Dave Airlie4d64dd92008-01-23 15:34:29 +1000656 /* return if we've already set the flush mechanism up */
657 if (intel_private.i8xx_page)
658 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000659
660 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
Dave Airlief011ae72008-01-25 11:23:04 +1000661 if (!intel_private.i8xx_page)
Dave Airlie2162e6a2007-11-21 16:36:31 +1000662 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000663
664 /* make page uncached */
665 map_page_into_agp(intel_private.i8xx_page);
Dave Airlie2162e6a2007-11-21 16:36:31 +1000666
667 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
668 if (!intel_private.i8xx_flush_page)
669 intel_i830_fini_flush();
670}
671
672static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
673{
674 unsigned int *pg = intel_private.i8xx_flush_page;
675 int i;
676
Dave Airlief011ae72008-01-25 11:23:04 +1000677 for (i = 0; i < 256; i += 2)
Dave Airlie2162e6a2007-11-21 16:36:31 +1000678 *(pg + i) = i;
Dave Airlief011ae72008-01-25 11:23:04 +1000679
Dave Airlie2162e6a2007-11-21 16:36:31 +1000680 wmb();
681}
682
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683/* The intel i830 automatically initializes the agp aperture during POST.
684 * Use the memory already set aside for in the GTT.
685 */
686static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
687{
688 int page_order;
689 struct aper_size_info_fixed *size;
690 int num_entries;
691 u32 temp;
692
693 size = agp_bridge->current_size;
694 page_order = size->page_order;
695 num_entries = size->num_entries;
696 agp_bridge->gatt_table_real = NULL;
697
Dave Airlief011ae72008-01-25 11:23:04 +1000698 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700699 temp &= 0xfff80000;
700
Dave Airlief011ae72008-01-25 11:23:04 +1000701 intel_private.registers = ioremap(temp, 128 * 4096);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800702 if (!intel_private.registers)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 return -ENOMEM;
704
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800705 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 global_cache_flush(); /* FIXME: ?? */
707
708 /* we have to call this as early as possible after the MMIO base address is known */
709 intel_i830_init_gtt_entries();
710
711 agp_bridge->gatt_table = NULL;
712
713 agp_bridge->gatt_bus_addr = temp;
714
715 return 0;
716}
717
718/* Return the gatt table to a sane state. Use the top of stolen
719 * memory for the GTT.
720 */
721static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
722{
723 return 0;
724}
725
726static int intel_i830_fetch_size(void)
727{
728 u16 gmch_ctrl;
729 struct aper_size_info_fixed *values;
730
731 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
732
733 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
734 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
735 /* 855GM/852GM/865G has 128MB aperture size */
736 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
737 agp_bridge->aperture_size_idx = 0;
738 return values[0].size;
739 }
740
Dave Airlief011ae72008-01-25 11:23:04 +1000741 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742
743 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
744 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
745 agp_bridge->aperture_size_idx = 0;
746 return values[0].size;
747 } else {
748 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
749 agp_bridge->aperture_size_idx = 1;
750 return values[1].size;
751 }
752
753 return 0;
754}
755
756static int intel_i830_configure(void)
757{
758 struct aper_size_info_fixed *current_size;
759 u32 temp;
760 u16 gmch_ctrl;
761 int i;
762
763 current_size = A_SIZE_FIX(agp_bridge->current_size);
764
Dave Airlief011ae72008-01-25 11:23:04 +1000765 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700766 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
767
Dave Airlief011ae72008-01-25 11:23:04 +1000768 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 gmch_ctrl |= I830_GMCH_ENABLED;
Dave Airlief011ae72008-01-25 11:23:04 +1000770 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800772 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
773 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
775 if (agp_bridge->driver->needs_scratch_page) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800776 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
777 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
778 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700779 }
780 }
781
782 global_cache_flush();
Dave Airlie2162e6a2007-11-21 16:36:31 +1000783
784 intel_i830_setup_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785 return 0;
786}
787
788static void intel_i830_cleanup(void)
789{
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800790 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700791}
792
Dave Airlief011ae72008-01-25 11:23:04 +1000793static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
794 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795{
Dave Airlief011ae72008-01-25 11:23:04 +1000796 int i, j, num_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100798 int ret = -EINVAL;
799 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100801 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100802 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100803
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 temp = agp_bridge->current_size;
805 num_entries = A_SIZE_FIX(temp)->num_entries;
806
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800807 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700808 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
809 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
810 pg_start, intel_private.gtt_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700812 dev_info(&intel_private.pcidev->dev,
813 "trying to insert into local/stolen memory\n");
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100814 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815 }
816
817 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100818 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819
820 /* The i830 can't check the GTT for entries since its read only,
821 * depend on the caller to make the correct offset decisions.
822 */
823
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100824 if (type != mem->type)
825 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100827 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
828
829 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
830 mask_type != INTEL_AGP_CACHED_MEMORY)
831 goto out_err;
832
833 if (!mem->is_flushed)
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100834 global_cache_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835
836 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
837 writel(agp_bridge->driver->mask_memory(agp_bridge,
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100838 mem->memory[i], mask_type),
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800839 intel_private.registers+I810_PTE_BASE+(j*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800841 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100843
844out:
845 ret = 0;
846out_err:
Dave Airlie9516b032008-06-19 10:42:17 +1000847 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100848 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849}
850
Dave Airlief011ae72008-01-25 11:23:04 +1000851static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
852 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853{
854 int i;
855
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100856 if (mem->page_count == 0)
857 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800859 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700860 dev_info(&intel_private.pcidev->dev,
861 "trying to disable local/stolen memory\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 return -EINVAL;
863 }
864
865 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800866 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800868 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 agp_bridge->driver->tlb_flush(mem);
871 return 0;
872}
873
Dave Airlief011ae72008-01-25 11:23:04 +1000874static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700875{
876 if (type == AGP_PHYS_MEMORY)
877 return alloc_agpphysmem_i8xx(pg_count, type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878 /* always return NULL for other allocation types for now */
879 return NULL;
880}
881
Dave Airlie6c00a612007-10-29 18:06:10 +1000882static int intel_alloc_chipset_flush_resource(void)
883{
884 int ret;
885 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
886 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
887 pcibios_align_resource, agp_bridge->dev);
Dave Airlie6c00a612007-10-29 18:06:10 +1000888
Dave Airlie2162e6a2007-11-21 16:36:31 +1000889 return ret;
Dave Airlie6c00a612007-10-29 18:06:10 +1000890}
891
892static void intel_i915_setup_chipset_flush(void)
893{
894 int ret;
895 u32 temp;
896
897 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
898 if (!(temp & 0x1)) {
899 intel_alloc_chipset_flush_resource();
Dave Airlie4d64dd92008-01-23 15:34:29 +1000900 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000901 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
902 } else {
903 temp &= ~1;
904
Dave Airlie4d64dd92008-01-23 15:34:29 +1000905 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000906 intel_private.ifp_resource.start = temp;
907 intel_private.ifp_resource.end = temp + PAGE_SIZE;
908 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000909 /* some BIOSes reserve this area in a pnp some don't */
910 if (ret)
911 intel_private.resource_valid = 0;
Dave Airlie6c00a612007-10-29 18:06:10 +1000912 }
913}
914
915static void intel_i965_g33_setup_chipset_flush(void)
916{
917 u32 temp_hi, temp_lo;
918 int ret;
919
920 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
921 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
922
923 if (!(temp_lo & 0x1)) {
924
925 intel_alloc_chipset_flush_resource();
926
Dave Airlie4d64dd92008-01-23 15:34:29 +1000927 intel_private.resource_valid = 1;
Andrew Morton1fa4db72007-11-29 10:00:48 +1000928 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
929 upper_32_bits(intel_private.ifp_resource.start));
Dave Airlie6c00a612007-10-29 18:06:10 +1000930 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
Dave Airlie6c00a612007-10-29 18:06:10 +1000931 } else {
932 u64 l64;
Dave Airlief011ae72008-01-25 11:23:04 +1000933
Dave Airlie6c00a612007-10-29 18:06:10 +1000934 temp_lo &= ~0x1;
935 l64 = ((u64)temp_hi << 32) | temp_lo;
936
Dave Airlie4d64dd92008-01-23 15:34:29 +1000937 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000938 intel_private.ifp_resource.start = l64;
939 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
940 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000941 /* some BIOSes reserve this area in a pnp some don't */
942 if (ret)
943 intel_private.resource_valid = 0;
Dave Airlie6c00a612007-10-29 18:06:10 +1000944 }
945}
946
Dave Airlie2162e6a2007-11-21 16:36:31 +1000947static void intel_i9xx_setup_flush(void)
948{
Dave Airlie4d64dd92008-01-23 15:34:29 +1000949 /* return if already configured */
950 if (intel_private.ifp_resource.start)
951 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000952
Dave Airlie4d64dd92008-01-23 15:34:29 +1000953 /* setup a resource for this object */
Dave Airlie2162e6a2007-11-21 16:36:31 +1000954 intel_private.ifp_resource.name = "Intel Flush Page";
955 intel_private.ifp_resource.flags = IORESOURCE_MEM;
956
957 /* Setup chipset flush for 915 */
Zhenyu Wang7d15ddf2008-06-20 11:48:06 +1000958 if (IS_I965 || IS_G33 || IS_G4X) {
Dave Airlie2162e6a2007-11-21 16:36:31 +1000959 intel_i965_g33_setup_chipset_flush();
960 } else {
961 intel_i915_setup_chipset_flush();
962 }
963
964 if (intel_private.ifp_resource.start) {
965 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
966 if (!intel_private.i9xx_flush_page)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700967 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
Dave Airlie2162e6a2007-11-21 16:36:31 +1000968 }
969}
970
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971static int intel_i915_configure(void)
972{
973 struct aper_size_info_fixed *current_size;
974 u32 temp;
975 u16 gmch_ctrl;
976 int i;
977
978 current_size = A_SIZE_FIX(agp_bridge->current_size);
979
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800980 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981
982 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
983
Dave Airlief011ae72008-01-25 11:23:04 +1000984 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 gmch_ctrl |= I830_GMCH_ENABLED;
Dave Airlief011ae72008-01-25 11:23:04 +1000986 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700987
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800988 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
989 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990
991 if (agp_bridge->driver->needs_scratch_page) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800992 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
993 writel(agp_bridge->scratch_page, intel_private.gtt+i);
994 readl(intel_private.gtt+i); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 }
996 }
997
998 global_cache_flush();
Dave Airlie6c00a612007-10-29 18:06:10 +1000999
Dave Airlie2162e6a2007-11-21 16:36:31 +10001000 intel_i9xx_setup_flush();
Dave Airlief011ae72008-01-25 11:23:04 +10001001
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002 return 0;
1003}
1004
1005static void intel_i915_cleanup(void)
1006{
Dave Airlie2162e6a2007-11-21 16:36:31 +10001007 if (intel_private.i9xx_flush_page)
1008 iounmap(intel_private.i9xx_flush_page);
Dave Airlie4d64dd92008-01-23 15:34:29 +10001009 if (intel_private.resource_valid)
1010 release_resource(&intel_private.ifp_resource);
1011 intel_private.ifp_resource.start = 0;
1012 intel_private.resource_valid = 0;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001013 iounmap(intel_private.gtt);
1014 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015}
1016
Dave Airlie6c00a612007-10-29 18:06:10 +10001017static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1018{
Dave Airlie2162e6a2007-11-21 16:36:31 +10001019 if (intel_private.i9xx_flush_page)
1020 writel(1, intel_private.i9xx_flush_page);
Dave Airlie6c00a612007-10-29 18:06:10 +10001021}
1022
Dave Airlief011ae72008-01-25 11:23:04 +10001023static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1024 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025{
Dave Airlief011ae72008-01-25 11:23:04 +10001026 int i, j, num_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001027 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001028 int ret = -EINVAL;
1029 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001031 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001032 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001033
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 temp = agp_bridge->current_size;
1035 num_entries = A_SIZE_FIX(temp)->num_entries;
1036
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001037 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001038 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1039 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1040 pg_start, intel_private.gtt_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001042 dev_info(&intel_private.pcidev->dev,
1043 "trying to insert into local/stolen memory\n");
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001044 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045 }
1046
1047 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001048 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001050 /* The i915 can't check the GTT for entries since its read only,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051 * depend on the caller to make the correct offset decisions.
1052 */
1053
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001054 if (type != mem->type)
1055 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001057 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1058
1059 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1060 mask_type != INTEL_AGP_CACHED_MEMORY)
1061 goto out_err;
1062
1063 if (!mem->is_flushed)
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001064 global_cache_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065
1066 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1067 writel(agp_bridge->driver->mask_memory(agp_bridge,
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001068 mem->memory[i], mask_type), intel_private.gtt+j);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069 }
1070
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001071 readl(intel_private.gtt+j-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001073
1074 out:
1075 ret = 0;
1076 out_err:
Dave Airlie9516b032008-06-19 10:42:17 +10001077 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001078 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079}
1080
Dave Airlief011ae72008-01-25 11:23:04 +10001081static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1082 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083{
1084 int i;
1085
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001086 if (mem->page_count == 0)
1087 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001089 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001090 dev_info(&intel_private.pcidev->dev,
1091 "trying to disable local/stolen memory\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092 return -EINVAL;
1093 }
1094
Dave Airlief011ae72008-01-25 11:23:04 +10001095 for (i = pg_start; i < (mem->page_count + pg_start); i++)
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001096 writel(agp_bridge->scratch_page, intel_private.gtt+i);
Dave Airlief011ae72008-01-25 11:23:04 +10001097
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001098 readl(intel_private.gtt+i-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099
Linus Torvalds1da177e2005-04-16 15:20:36 -07001100 agp_bridge->driver->tlb_flush(mem);
1101 return 0;
1102}
1103
Eric Anholtc41e0de2006-12-19 12:57:24 -08001104/* Return the aperture size by just checking the resource length. The effect
1105 * described in the spec of the MSAC registers is just changing of the
1106 * resource size.
1107 */
1108static int intel_i9xx_fetch_size(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109{
Ahmed S. Darwish1eaf1222007-02-06 18:08:28 +02001110 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
Eric Anholtc41e0de2006-12-19 12:57:24 -08001111 int aper_size; /* size in megabytes */
1112 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001114 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115
Eric Anholtc41e0de2006-12-19 12:57:24 -08001116 for (i = 0; i < num_sizes; i++) {
1117 if (aper_size == intel_i830_sizes[i].size) {
1118 agp_bridge->current_size = intel_i830_sizes + i;
1119 agp_bridge->previous_size = agp_bridge->current_size;
1120 return aper_size;
1121 }
1122 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123
Eric Anholtc41e0de2006-12-19 12:57:24 -08001124 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125}
1126
1127/* The intel i915 automatically initializes the agp aperture during POST.
1128 * Use the memory already set aside for in the GTT.
1129 */
1130static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1131{
1132 int page_order;
1133 struct aper_size_info_fixed *size;
1134 int num_entries;
1135 u32 temp, temp2;
Zhenyu Wang47406222007-09-11 15:23:58 -07001136 int gtt_map_size = 256 * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001137
1138 size = agp_bridge->current_size;
1139 page_order = size->page_order;
1140 num_entries = size->num_entries;
1141 agp_bridge->gatt_table_real = NULL;
1142
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001143 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
Dave Airlief011ae72008-01-25 11:23:04 +10001144 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001145
Zhenyu Wang47406222007-09-11 15:23:58 -07001146 if (IS_G33)
1147 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1148 intel_private.gtt = ioremap(temp2, gtt_map_size);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001149 if (!intel_private.gtt)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150 return -ENOMEM;
1151
1152 temp &= 0xfff80000;
1153
Dave Airlief011ae72008-01-25 11:23:04 +10001154 intel_private.registers = ioremap(temp, 128 * 4096);
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001155 if (!intel_private.registers) {
1156 iounmap(intel_private.gtt);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 return -ENOMEM;
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001158 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001160 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001161 global_cache_flush(); /* FIXME: ? */
1162
1163 /* we have to call this as early as possible after the MMIO base address is known */
1164 intel_i830_init_gtt_entries();
1165
1166 agp_bridge->gatt_table = NULL;
1167
1168 agp_bridge->gatt_bus_addr = temp;
1169
1170 return 0;
1171}
Linus Torvalds7d915a32006-11-22 09:37:54 -08001172
1173/*
1174 * The i965 supports 36-bit physical addresses, but to keep
1175 * the format of the GTT the same, the bits that don't fit
1176 * in a 32-bit word are shifted down to bits 4..7.
1177 *
1178 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1179 * is always zero on 32-bit architectures, so no need to make
1180 * this conditional.
1181 */
1182static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1183 unsigned long addr, int type)
1184{
1185 /* Shift high bits down */
1186 addr |= (addr >> 28) & 0xf0;
1187
1188 /* Type checking must be done elsewhere */
1189 return addr | bridge->driver->masks[type].mask;
1190}
1191
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001192static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1193{
1194 switch (agp_bridge->dev->device) {
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07001195 case PCI_DEVICE_ID_INTEL_GM45_HB:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001196 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1197 case PCI_DEVICE_ID_INTEL_Q45_HB:
1198 case PCI_DEVICE_ID_INTEL_G45_HB:
1199 *gtt_offset = *gtt_size = MB(2);
1200 break;
1201 default:
1202 *gtt_offset = *gtt_size = KB(512);
1203 }
1204}
1205
Eric Anholt65c25aa2006-09-06 11:57:18 -04001206/* The intel i965 automatically initializes the agp aperture during POST.
Eric Anholtc41e0de2006-12-19 12:57:24 -08001207 * Use the memory already set aside for in the GTT.
1208 */
Eric Anholt65c25aa2006-09-06 11:57:18 -04001209static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1210{
Dave Airlie62c96b92008-06-19 14:27:53 +10001211 int page_order;
1212 struct aper_size_info_fixed *size;
1213 int num_entries;
1214 u32 temp;
1215 int gtt_offset, gtt_size;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001216
Dave Airlie62c96b92008-06-19 14:27:53 +10001217 size = agp_bridge->current_size;
1218 page_order = size->page_order;
1219 num_entries = size->num_entries;
1220 agp_bridge->gatt_table_real = NULL;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001221
Dave Airlie62c96b92008-06-19 14:27:53 +10001222 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001223
Dave Airlie62c96b92008-06-19 14:27:53 +10001224 temp &= 0xfff00000;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001225
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001226 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001227
Dave Airlie62c96b92008-06-19 14:27:53 +10001228 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001229
Dave Airlie62c96b92008-06-19 14:27:53 +10001230 if (!intel_private.gtt)
1231 return -ENOMEM;
Zhenyu Wang4e8b6e22008-01-23 14:54:37 +10001232
Dave Airlie62c96b92008-06-19 14:27:53 +10001233 intel_private.registers = ioremap(temp, 128 * 4096);
1234 if (!intel_private.registers) {
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001235 iounmap(intel_private.gtt);
1236 return -ENOMEM;
1237 }
Eric Anholt65c25aa2006-09-06 11:57:18 -04001238
Dave Airlie62c96b92008-06-19 14:27:53 +10001239 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1240 global_cache_flush(); /* FIXME: ? */
Eric Anholt65c25aa2006-09-06 11:57:18 -04001241
Dave Airlie62c96b92008-06-19 14:27:53 +10001242 /* we have to call this as early as possible after the MMIO base address is known */
1243 intel_i830_init_gtt_entries();
Eric Anholt65c25aa2006-09-06 11:57:18 -04001244
Dave Airlie62c96b92008-06-19 14:27:53 +10001245 agp_bridge->gatt_table = NULL;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001246
Dave Airlie62c96b92008-06-19 14:27:53 +10001247 agp_bridge->gatt_bus_addr = temp;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001248
Dave Airlie62c96b92008-06-19 14:27:53 +10001249 return 0;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001250}
1251
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252
1253static int intel_fetch_size(void)
1254{
1255 int i;
1256 u16 temp;
1257 struct aper_size_info_16 *values;
1258
1259 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1260 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1261
1262 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1263 if (temp == values[i].size_value) {
1264 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1265 agp_bridge->aperture_size_idx = i;
1266 return values[i].size;
1267 }
1268 }
1269
1270 return 0;
1271}
1272
1273static int __intel_8xx_fetch_size(u8 temp)
1274{
1275 int i;
1276 struct aper_size_info_8 *values;
1277
1278 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1279
1280 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1281 if (temp == values[i].size_value) {
1282 agp_bridge->previous_size =
1283 agp_bridge->current_size = (void *) (values + i);
1284 agp_bridge->aperture_size_idx = i;
1285 return values[i].size;
1286 }
1287 }
1288 return 0;
1289}
1290
1291static int intel_8xx_fetch_size(void)
1292{
1293 u8 temp;
1294
1295 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1296 return __intel_8xx_fetch_size(temp);
1297}
1298
1299static int intel_815_fetch_size(void)
1300{
1301 u8 temp;
1302
1303 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1304 * one non-reserved bit, so mask the others out ... */
1305 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1306 temp &= (1 << 3);
1307
1308 return __intel_8xx_fetch_size(temp);
1309}
1310
1311static void intel_tlbflush(struct agp_memory *mem)
1312{
1313 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1314 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1315}
1316
1317
1318static void intel_8xx_tlbflush(struct agp_memory *mem)
1319{
1320 u32 temp;
1321 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1322 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1323 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1324 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1325}
1326
1327
1328static void intel_cleanup(void)
1329{
1330 u16 temp;
1331 struct aper_size_info_16 *previous_size;
1332
1333 previous_size = A_SIZE_16(agp_bridge->previous_size);
1334 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1335 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1336 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1337}
1338
1339
1340static void intel_8xx_cleanup(void)
1341{
1342 u16 temp;
1343 struct aper_size_info_8 *previous_size;
1344
1345 previous_size = A_SIZE_8(agp_bridge->previous_size);
1346 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1347 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1348 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1349}
1350
1351
1352static int intel_configure(void)
1353{
1354 u32 temp;
1355 u16 temp2;
1356 struct aper_size_info_16 *current_size;
1357
1358 current_size = A_SIZE_16(agp_bridge->current_size);
1359
1360 /* aperture size */
1361 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1362
1363 /* address to map to */
1364 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1365 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1366
1367 /* attbase - aperture base */
1368 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1369
1370 /* agpctrl */
1371 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1372
1373 /* paccfg/nbxcfg */
1374 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1375 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1376 (temp2 & ~(1 << 10)) | (1 << 9));
1377 /* clear any possible error conditions */
1378 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1379 return 0;
1380}
1381
1382static int intel_815_configure(void)
1383{
1384 u32 temp, addr;
1385 u8 temp2;
1386 struct aper_size_info_8 *current_size;
1387
1388 /* attbase - aperture base */
1389 /* the Intel 815 chipset spec. says that bits 29-31 in the
1390 * ATTBASE register are reserved -> try not to write them */
1391 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001392 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393 return -EINVAL;
1394 }
1395
1396 current_size = A_SIZE_8(agp_bridge->current_size);
1397
1398 /* aperture size */
1399 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1400 current_size->size_value);
1401
1402 /* address to map to */
1403 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1404 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1405
1406 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1407 addr &= INTEL_815_ATTBASE_MASK;
1408 addr |= agp_bridge->gatt_bus_addr;
1409 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1410
1411 /* agpctrl */
1412 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1413
1414 /* apcont */
1415 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1416 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1417
1418 /* clear any possible error conditions */
1419 /* Oddness : this chipset seems to have no ERRSTS register ! */
1420 return 0;
1421}
1422
1423static void intel_820_tlbflush(struct agp_memory *mem)
1424{
1425 return;
1426}
1427
1428static void intel_820_cleanup(void)
1429{
1430 u8 temp;
1431 struct aper_size_info_8 *previous_size;
1432
1433 previous_size = A_SIZE_8(agp_bridge->previous_size);
1434 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1435 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1436 temp & ~(1 << 1));
1437 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1438 previous_size->size_value);
1439}
1440
1441
1442static int intel_820_configure(void)
1443{
1444 u32 temp;
1445 u8 temp2;
1446 struct aper_size_info_8 *current_size;
1447
1448 current_size = A_SIZE_8(agp_bridge->current_size);
1449
1450 /* aperture size */
1451 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1452
1453 /* address to map to */
1454 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1455 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1456
1457 /* attbase - aperture base */
1458 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1459
1460 /* agpctrl */
1461 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1462
1463 /* global enable aperture access */
1464 /* This flag is not accessed through MCHCFG register as in */
1465 /* i850 chipset. */
1466 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1467 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1468 /* clear any possible AGP-related error conditions */
1469 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1470 return 0;
1471}
1472
1473static int intel_840_configure(void)
1474{
1475 u32 temp;
1476 u16 temp2;
1477 struct aper_size_info_8 *current_size;
1478
1479 current_size = A_SIZE_8(agp_bridge->current_size);
1480
1481 /* aperture size */
1482 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1483
1484 /* address to map to */
1485 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1486 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1487
1488 /* attbase - aperture base */
1489 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1490
1491 /* agpctrl */
1492 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1493
1494 /* mcgcfg */
1495 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1496 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1497 /* clear any possible error conditions */
1498 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1499 return 0;
1500}
1501
1502static int intel_845_configure(void)
1503{
1504 u32 temp;
1505 u8 temp2;
1506 struct aper_size_info_8 *current_size;
1507
1508 current_size = A_SIZE_8(agp_bridge->current_size);
1509
1510 /* aperture size */
1511 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1512
Matthew Garrettb0825482005-07-29 14:03:39 -07001513 if (agp_bridge->apbase_config != 0) {
1514 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1515 agp_bridge->apbase_config);
1516 } else {
1517 /* address to map to */
1518 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1519 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1520 agp_bridge->apbase_config = temp;
1521 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001522
1523 /* attbase - aperture base */
1524 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1525
1526 /* agpctrl */
1527 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1528
1529 /* agpm */
1530 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1531 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1532 /* clear any possible error conditions */
1533 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
Dave Airlie2162e6a2007-11-21 16:36:31 +10001534
1535 intel_i830_setup_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001536 return 0;
1537}
1538
1539static int intel_850_configure(void)
1540{
1541 u32 temp;
1542 u16 temp2;
1543 struct aper_size_info_8 *current_size;
1544
1545 current_size = A_SIZE_8(agp_bridge->current_size);
1546
1547 /* aperture size */
1548 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1549
1550 /* address to map to */
1551 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1552 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1553
1554 /* attbase - aperture base */
1555 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1556
1557 /* agpctrl */
1558 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1559
1560 /* mcgcfg */
1561 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1562 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1563 /* clear any possible AGP-related error conditions */
1564 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1565 return 0;
1566}
1567
1568static int intel_860_configure(void)
1569{
1570 u32 temp;
1571 u16 temp2;
1572 struct aper_size_info_8 *current_size;
1573
1574 current_size = A_SIZE_8(agp_bridge->current_size);
1575
1576 /* aperture size */
1577 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1578
1579 /* address to map to */
1580 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1581 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1582
1583 /* attbase - aperture base */
1584 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1585
1586 /* agpctrl */
1587 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1588
1589 /* mcgcfg */
1590 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1591 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1592 /* clear any possible AGP-related error conditions */
1593 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1594 return 0;
1595}
1596
1597static int intel_830mp_configure(void)
1598{
1599 u32 temp;
1600 u16 temp2;
1601 struct aper_size_info_8 *current_size;
1602
1603 current_size = A_SIZE_8(agp_bridge->current_size);
1604
1605 /* aperture size */
1606 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1607
1608 /* address to map to */
1609 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1610 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1611
1612 /* attbase - aperture base */
1613 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1614
1615 /* agpctrl */
1616 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1617
1618 /* gmch */
1619 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1620 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1621 /* clear any possible AGP-related error conditions */
1622 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1623 return 0;
1624}
1625
1626static int intel_7505_configure(void)
1627{
1628 u32 temp;
1629 u16 temp2;
1630 struct aper_size_info_8 *current_size;
1631
1632 current_size = A_SIZE_8(agp_bridge->current_size);
1633
1634 /* aperture size */
1635 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1636
1637 /* address to map to */
1638 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1639 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1640
1641 /* attbase - aperture base */
1642 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1643
1644 /* agpctrl */
1645 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1646
1647 /* mchcfg */
1648 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1649 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1650
1651 return 0;
1652}
1653
1654/* Setup function */
Dave Jonese5524f32007-02-22 18:41:28 -05001655static const struct gatt_mask intel_generic_masks[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001656{
1657 {.mask = 0x00000017, .type = 0}
1658};
1659
Dave Jonese5524f32007-02-22 18:41:28 -05001660static const struct aper_size_info_8 intel_815_sizes[2] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001661{
1662 {64, 16384, 4, 0},
1663 {32, 8192, 3, 8},
1664};
1665
Dave Jonese5524f32007-02-22 18:41:28 -05001666static const struct aper_size_info_8 intel_8xx_sizes[7] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001667{
1668 {256, 65536, 6, 0},
1669 {128, 32768, 5, 32},
1670 {64, 16384, 4, 48},
1671 {32, 8192, 3, 56},
1672 {16, 4096, 2, 60},
1673 {8, 2048, 1, 62},
1674 {4, 1024, 0, 63}
1675};
1676
Dave Jonese5524f32007-02-22 18:41:28 -05001677static const struct aper_size_info_16 intel_generic_sizes[7] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001678{
1679 {256, 65536, 6, 0},
1680 {128, 32768, 5, 32},
1681 {64, 16384, 4, 48},
1682 {32, 8192, 3, 56},
1683 {16, 4096, 2, 60},
1684 {8, 2048, 1, 62},
1685 {4, 1024, 0, 63}
1686};
1687
Dave Jonese5524f32007-02-22 18:41:28 -05001688static const struct aper_size_info_8 intel_830mp_sizes[4] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689{
1690 {256, 65536, 6, 0},
1691 {128, 32768, 5, 32},
1692 {64, 16384, 4, 48},
1693 {32, 8192, 3, 56}
1694};
1695
Dave Jonese5524f32007-02-22 18:41:28 -05001696static const struct agp_bridge_driver intel_generic_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697 .owner = THIS_MODULE,
1698 .aperture_sizes = intel_generic_sizes,
1699 .size_type = U16_APER_SIZE,
1700 .num_aperture_sizes = 7,
1701 .configure = intel_configure,
1702 .fetch_size = intel_fetch_size,
1703 .cleanup = intel_cleanup,
1704 .tlb_flush = intel_tlbflush,
1705 .mask_memory = agp_generic_mask_memory,
1706 .masks = intel_generic_masks,
1707 .agp_enable = agp_generic_enable,
1708 .cache_flush = global_cache_flush,
1709 .create_gatt_table = agp_generic_create_gatt_table,
1710 .free_gatt_table = agp_generic_free_gatt_table,
1711 .insert_memory = agp_generic_insert_memory,
1712 .remove_memory = agp_generic_remove_memory,
1713 .alloc_by_type = agp_generic_alloc_by_type,
1714 .free_by_type = agp_generic_free_by_type,
1715 .agp_alloc_page = agp_generic_alloc_page,
1716 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001717 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001718};
1719
Dave Jonese5524f32007-02-22 18:41:28 -05001720static const struct agp_bridge_driver intel_810_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 .owner = THIS_MODULE,
1722 .aperture_sizes = intel_i810_sizes,
1723 .size_type = FIXED_APER_SIZE,
1724 .num_aperture_sizes = 2,
Joe Perchesc7258012008-03-26 14:10:02 -07001725 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001726 .configure = intel_i810_configure,
1727 .fetch_size = intel_i810_fetch_size,
1728 .cleanup = intel_i810_cleanup,
1729 .tlb_flush = intel_i810_tlbflush,
1730 .mask_memory = intel_i810_mask_memory,
1731 .masks = intel_i810_masks,
1732 .agp_enable = intel_i810_agp_enable,
1733 .cache_flush = global_cache_flush,
1734 .create_gatt_table = agp_generic_create_gatt_table,
1735 .free_gatt_table = agp_generic_free_gatt_table,
1736 .insert_memory = intel_i810_insert_entries,
1737 .remove_memory = intel_i810_remove_entries,
1738 .alloc_by_type = intel_i810_alloc_by_type,
1739 .free_by_type = intel_i810_free_by_type,
1740 .agp_alloc_page = agp_generic_alloc_page,
1741 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001742 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743};
1744
Dave Jonese5524f32007-02-22 18:41:28 -05001745static const struct agp_bridge_driver intel_815_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746 .owner = THIS_MODULE,
1747 .aperture_sizes = intel_815_sizes,
1748 .size_type = U8_APER_SIZE,
1749 .num_aperture_sizes = 2,
1750 .configure = intel_815_configure,
1751 .fetch_size = intel_815_fetch_size,
1752 .cleanup = intel_8xx_cleanup,
1753 .tlb_flush = intel_8xx_tlbflush,
1754 .mask_memory = agp_generic_mask_memory,
1755 .masks = intel_generic_masks,
1756 .agp_enable = agp_generic_enable,
1757 .cache_flush = global_cache_flush,
1758 .create_gatt_table = agp_generic_create_gatt_table,
1759 .free_gatt_table = agp_generic_free_gatt_table,
1760 .insert_memory = agp_generic_insert_memory,
1761 .remove_memory = agp_generic_remove_memory,
1762 .alloc_by_type = agp_generic_alloc_by_type,
1763 .free_by_type = agp_generic_free_by_type,
1764 .agp_alloc_page = agp_generic_alloc_page,
1765 .agp_destroy_page = agp_generic_destroy_page,
Dave Airlie62c96b92008-06-19 14:27:53 +10001766 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001767};
1768
Dave Jonese5524f32007-02-22 18:41:28 -05001769static const struct agp_bridge_driver intel_830_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770 .owner = THIS_MODULE,
1771 .aperture_sizes = intel_i830_sizes,
1772 .size_type = FIXED_APER_SIZE,
Dave Jonesc14635e2006-09-06 11:59:35 -04001773 .num_aperture_sizes = 4,
Joe Perchesc7258012008-03-26 14:10:02 -07001774 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775 .configure = intel_i830_configure,
1776 .fetch_size = intel_i830_fetch_size,
1777 .cleanup = intel_i830_cleanup,
1778 .tlb_flush = intel_i810_tlbflush,
1779 .mask_memory = intel_i810_mask_memory,
1780 .masks = intel_i810_masks,
1781 .agp_enable = intel_i810_agp_enable,
1782 .cache_flush = global_cache_flush,
1783 .create_gatt_table = intel_i830_create_gatt_table,
1784 .free_gatt_table = intel_i830_free_gatt_table,
1785 .insert_memory = intel_i830_insert_entries,
1786 .remove_memory = intel_i830_remove_entries,
1787 .alloc_by_type = intel_i830_alloc_by_type,
1788 .free_by_type = intel_i810_free_by_type,
1789 .agp_alloc_page = agp_generic_alloc_page,
1790 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001791 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie2162e6a2007-11-21 16:36:31 +10001792 .chipset_flush = intel_i830_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001793};
1794
Dave Jonese5524f32007-02-22 18:41:28 -05001795static const struct agp_bridge_driver intel_820_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796 .owner = THIS_MODULE,
1797 .aperture_sizes = intel_8xx_sizes,
1798 .size_type = U8_APER_SIZE,
1799 .num_aperture_sizes = 7,
1800 .configure = intel_820_configure,
1801 .fetch_size = intel_8xx_fetch_size,
1802 .cleanup = intel_820_cleanup,
1803 .tlb_flush = intel_820_tlbflush,
1804 .mask_memory = agp_generic_mask_memory,
1805 .masks = intel_generic_masks,
1806 .agp_enable = agp_generic_enable,
1807 .cache_flush = global_cache_flush,
1808 .create_gatt_table = agp_generic_create_gatt_table,
1809 .free_gatt_table = agp_generic_free_gatt_table,
1810 .insert_memory = agp_generic_insert_memory,
1811 .remove_memory = agp_generic_remove_memory,
1812 .alloc_by_type = agp_generic_alloc_by_type,
1813 .free_by_type = agp_generic_free_by_type,
1814 .agp_alloc_page = agp_generic_alloc_page,
1815 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001816 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001817};
1818
Dave Jonese5524f32007-02-22 18:41:28 -05001819static const struct agp_bridge_driver intel_830mp_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820 .owner = THIS_MODULE,
1821 .aperture_sizes = intel_830mp_sizes,
1822 .size_type = U8_APER_SIZE,
1823 .num_aperture_sizes = 4,
1824 .configure = intel_830mp_configure,
1825 .fetch_size = intel_8xx_fetch_size,
1826 .cleanup = intel_8xx_cleanup,
1827 .tlb_flush = intel_8xx_tlbflush,
1828 .mask_memory = agp_generic_mask_memory,
1829 .masks = intel_generic_masks,
1830 .agp_enable = agp_generic_enable,
1831 .cache_flush = global_cache_flush,
1832 .create_gatt_table = agp_generic_create_gatt_table,
1833 .free_gatt_table = agp_generic_free_gatt_table,
1834 .insert_memory = agp_generic_insert_memory,
1835 .remove_memory = agp_generic_remove_memory,
1836 .alloc_by_type = agp_generic_alloc_by_type,
1837 .free_by_type = agp_generic_free_by_type,
1838 .agp_alloc_page = agp_generic_alloc_page,
1839 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001840 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001841};
1842
Dave Jonese5524f32007-02-22 18:41:28 -05001843static const struct agp_bridge_driver intel_840_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001844 .owner = THIS_MODULE,
1845 .aperture_sizes = intel_8xx_sizes,
1846 .size_type = U8_APER_SIZE,
1847 .num_aperture_sizes = 7,
1848 .configure = intel_840_configure,
1849 .fetch_size = intel_8xx_fetch_size,
1850 .cleanup = intel_8xx_cleanup,
1851 .tlb_flush = intel_8xx_tlbflush,
1852 .mask_memory = agp_generic_mask_memory,
1853 .masks = intel_generic_masks,
1854 .agp_enable = agp_generic_enable,
1855 .cache_flush = global_cache_flush,
1856 .create_gatt_table = agp_generic_create_gatt_table,
1857 .free_gatt_table = agp_generic_free_gatt_table,
1858 .insert_memory = agp_generic_insert_memory,
1859 .remove_memory = agp_generic_remove_memory,
1860 .alloc_by_type = agp_generic_alloc_by_type,
1861 .free_by_type = agp_generic_free_by_type,
1862 .agp_alloc_page = agp_generic_alloc_page,
1863 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001864 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001865};
1866
Dave Jonese5524f32007-02-22 18:41:28 -05001867static const struct agp_bridge_driver intel_845_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001868 .owner = THIS_MODULE,
1869 .aperture_sizes = intel_8xx_sizes,
1870 .size_type = U8_APER_SIZE,
1871 .num_aperture_sizes = 7,
1872 .configure = intel_845_configure,
1873 .fetch_size = intel_8xx_fetch_size,
1874 .cleanup = intel_8xx_cleanup,
1875 .tlb_flush = intel_8xx_tlbflush,
1876 .mask_memory = agp_generic_mask_memory,
1877 .masks = intel_generic_masks,
1878 .agp_enable = agp_generic_enable,
1879 .cache_flush = global_cache_flush,
1880 .create_gatt_table = agp_generic_create_gatt_table,
1881 .free_gatt_table = agp_generic_free_gatt_table,
1882 .insert_memory = agp_generic_insert_memory,
1883 .remove_memory = agp_generic_remove_memory,
1884 .alloc_by_type = agp_generic_alloc_by_type,
1885 .free_by_type = agp_generic_free_by_type,
1886 .agp_alloc_page = agp_generic_alloc_page,
1887 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001888 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Dave Airlie2162e6a2007-11-21 16:36:31 +10001889 .chipset_flush = intel_i830_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001890};
1891
Dave Jonese5524f32007-02-22 18:41:28 -05001892static const struct agp_bridge_driver intel_850_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001893 .owner = THIS_MODULE,
1894 .aperture_sizes = intel_8xx_sizes,
1895 .size_type = U8_APER_SIZE,
1896 .num_aperture_sizes = 7,
1897 .configure = intel_850_configure,
1898 .fetch_size = intel_8xx_fetch_size,
1899 .cleanup = intel_8xx_cleanup,
1900 .tlb_flush = intel_8xx_tlbflush,
1901 .mask_memory = agp_generic_mask_memory,
1902 .masks = intel_generic_masks,
1903 .agp_enable = agp_generic_enable,
1904 .cache_flush = global_cache_flush,
1905 .create_gatt_table = agp_generic_create_gatt_table,
1906 .free_gatt_table = agp_generic_free_gatt_table,
1907 .insert_memory = agp_generic_insert_memory,
1908 .remove_memory = agp_generic_remove_memory,
1909 .alloc_by_type = agp_generic_alloc_by_type,
1910 .free_by_type = agp_generic_free_by_type,
1911 .agp_alloc_page = agp_generic_alloc_page,
1912 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001913 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001914};
1915
Dave Jonese5524f32007-02-22 18:41:28 -05001916static const struct agp_bridge_driver intel_860_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001917 .owner = THIS_MODULE,
1918 .aperture_sizes = intel_8xx_sizes,
1919 .size_type = U8_APER_SIZE,
1920 .num_aperture_sizes = 7,
1921 .configure = intel_860_configure,
1922 .fetch_size = intel_8xx_fetch_size,
1923 .cleanup = intel_8xx_cleanup,
1924 .tlb_flush = intel_8xx_tlbflush,
1925 .mask_memory = agp_generic_mask_memory,
1926 .masks = intel_generic_masks,
1927 .agp_enable = agp_generic_enable,
1928 .cache_flush = global_cache_flush,
1929 .create_gatt_table = agp_generic_create_gatt_table,
1930 .free_gatt_table = agp_generic_free_gatt_table,
1931 .insert_memory = agp_generic_insert_memory,
1932 .remove_memory = agp_generic_remove_memory,
1933 .alloc_by_type = agp_generic_alloc_by_type,
1934 .free_by_type = agp_generic_free_by_type,
1935 .agp_alloc_page = agp_generic_alloc_page,
1936 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001937 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001938};
1939
Dave Jonese5524f32007-02-22 18:41:28 -05001940static const struct agp_bridge_driver intel_915_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001941 .owner = THIS_MODULE,
1942 .aperture_sizes = intel_i830_sizes,
1943 .size_type = FIXED_APER_SIZE,
Dave Jonesc14635e2006-09-06 11:59:35 -04001944 .num_aperture_sizes = 4,
Joe Perchesc7258012008-03-26 14:10:02 -07001945 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001946 .configure = intel_i915_configure,
Eric Anholtc41e0de2006-12-19 12:57:24 -08001947 .fetch_size = intel_i9xx_fetch_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001948 .cleanup = intel_i915_cleanup,
1949 .tlb_flush = intel_i810_tlbflush,
1950 .mask_memory = intel_i810_mask_memory,
1951 .masks = intel_i810_masks,
1952 .agp_enable = intel_i810_agp_enable,
1953 .cache_flush = global_cache_flush,
1954 .create_gatt_table = intel_i915_create_gatt_table,
1955 .free_gatt_table = intel_i830_free_gatt_table,
1956 .insert_memory = intel_i915_insert_entries,
1957 .remove_memory = intel_i915_remove_entries,
1958 .alloc_by_type = intel_i830_alloc_by_type,
1959 .free_by_type = intel_i810_free_by_type,
1960 .agp_alloc_page = agp_generic_alloc_page,
1961 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001962 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10001963 .chipset_flush = intel_i915_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964};
1965
Dave Jonese5524f32007-02-22 18:41:28 -05001966static const struct agp_bridge_driver intel_i965_driver = {
Dave Airlie62c96b92008-06-19 14:27:53 +10001967 .owner = THIS_MODULE,
1968 .aperture_sizes = intel_i830_sizes,
1969 .size_type = FIXED_APER_SIZE,
1970 .num_aperture_sizes = 4,
1971 .needs_scratch_page = true,
Dave Airlie0e480e52008-06-19 14:57:31 +10001972 .configure = intel_i915_configure,
1973 .fetch_size = intel_i9xx_fetch_size,
Dave Airlie62c96b92008-06-19 14:27:53 +10001974 .cleanup = intel_i915_cleanup,
1975 .tlb_flush = intel_i810_tlbflush,
1976 .mask_memory = intel_i965_mask_memory,
1977 .masks = intel_i810_masks,
1978 .agp_enable = intel_i810_agp_enable,
1979 .cache_flush = global_cache_flush,
1980 .create_gatt_table = intel_i965_create_gatt_table,
1981 .free_gatt_table = intel_i830_free_gatt_table,
1982 .insert_memory = intel_i915_insert_entries,
1983 .remove_memory = intel_i915_remove_entries,
1984 .alloc_by_type = intel_i830_alloc_by_type,
1985 .free_by_type = intel_i810_free_by_type,
1986 .agp_alloc_page = agp_generic_alloc_page,
1987 .agp_destroy_page = agp_generic_destroy_page,
1988 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10001989 .chipset_flush = intel_i915_chipset_flush,
Eric Anholt65c25aa2006-09-06 11:57:18 -04001990};
Linus Torvalds1da177e2005-04-16 15:20:36 -07001991
Dave Jonese5524f32007-02-22 18:41:28 -05001992static const struct agp_bridge_driver intel_7505_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993 .owner = THIS_MODULE,
1994 .aperture_sizes = intel_8xx_sizes,
1995 .size_type = U8_APER_SIZE,
1996 .num_aperture_sizes = 7,
1997 .configure = intel_7505_configure,
1998 .fetch_size = intel_8xx_fetch_size,
1999 .cleanup = intel_8xx_cleanup,
2000 .tlb_flush = intel_8xx_tlbflush,
2001 .mask_memory = agp_generic_mask_memory,
2002 .masks = intel_generic_masks,
2003 .agp_enable = agp_generic_enable,
2004 .cache_flush = global_cache_flush,
2005 .create_gatt_table = agp_generic_create_gatt_table,
2006 .free_gatt_table = agp_generic_free_gatt_table,
2007 .insert_memory = agp_generic_insert_memory,
2008 .remove_memory = agp_generic_remove_memory,
2009 .alloc_by_type = agp_generic_alloc_by_type,
2010 .free_by_type = agp_generic_free_by_type,
2011 .agp_alloc_page = agp_generic_alloc_page,
2012 .agp_destroy_page = agp_generic_destroy_page,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01002013 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014};
2015
Wang Zhenyu874808c62007-06-06 11:16:25 +08002016static const struct agp_bridge_driver intel_g33_driver = {
Dave Airlie62c96b92008-06-19 14:27:53 +10002017 .owner = THIS_MODULE,
2018 .aperture_sizes = intel_i830_sizes,
2019 .size_type = FIXED_APER_SIZE,
2020 .num_aperture_sizes = 4,
2021 .needs_scratch_page = true,
2022 .configure = intel_i915_configure,
2023 .fetch_size = intel_i9xx_fetch_size,
2024 .cleanup = intel_i915_cleanup,
2025 .tlb_flush = intel_i810_tlbflush,
2026 .mask_memory = intel_i965_mask_memory,
2027 .masks = intel_i810_masks,
2028 .agp_enable = intel_i810_agp_enable,
2029 .cache_flush = global_cache_flush,
2030 .create_gatt_table = intel_i915_create_gatt_table,
2031 .free_gatt_table = intel_i830_free_gatt_table,
2032 .insert_memory = intel_i915_insert_entries,
2033 .remove_memory = intel_i915_remove_entries,
2034 .alloc_by_type = intel_i830_alloc_by_type,
2035 .free_by_type = intel_i810_free_by_type,
2036 .agp_alloc_page = agp_generic_alloc_page,
2037 .agp_destroy_page = agp_generic_destroy_page,
2038 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10002039 .chipset_flush = intel_i915_chipset_flush,
Wang Zhenyu874808c62007-06-06 11:16:25 +08002040};
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002041
2042static int find_gmch(u16 device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002043{
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002044 struct pci_dev *gmch_device;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002045
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002046 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2047 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2048 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
Dave Airlief011ae72008-01-25 11:23:04 +10002049 device, gmch_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002050 }
2051
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002052 if (!gmch_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002053 return 0;
2054
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002055 intel_private.pcidev = gmch_device;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002056 return 1;
2057}
2058
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002059/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2060 * driver and gmch_driver must be non-null, and find_gmch will determine
2061 * which one should be used if a gmch_chip_id is present.
2062 */
2063static const struct intel_driver_description {
2064 unsigned int chip_id;
2065 unsigned int gmch_chip_id;
Wang Zhenyu88889852007-06-14 10:01:04 +08002066 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002067 char *name;
2068 const struct agp_bridge_driver *driver;
2069 const struct agp_bridge_driver *gmch_driver;
2070} intel_agp_chipsets[] = {
Wang Zhenyu88889852007-06-14 10:01:04 +08002071 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2072 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2073 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2074 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002075 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002076 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002077 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002078 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002079 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002080 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2081 &intel_815_driver, &intel_810_driver },
2082 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2083 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2084 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002085 &intel_830mp_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002086 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2087 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2088 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002089 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002090 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2091 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2092 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002093 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002094 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2095 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002096 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002097 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
Carlos Martíne914a362008-01-24 10:34:09 +10002098 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2099 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002100 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002101 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002102 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002103 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002104 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002105 NULL, &intel_915_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002106 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002107 NULL, &intel_915_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002108 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002109 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002110 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002111 NULL, &intel_i965_driver },
Zhenyu Wang9119f852008-01-23 15:49:26 +10002112 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002113 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002114 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002115 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002116 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002117 NULL, &intel_i965_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002118 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002119 NULL, &intel_i965_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002120 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002121 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002122 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2123 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2124 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002125 NULL, &intel_g33_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002126 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002127 NULL, &intel_g33_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002128 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002129 NULL, &intel_g33_driver },
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07002130 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2131 "Mobile Intel? GM45 Express", NULL, &intel_i965_driver },
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10002132 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2133 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2134 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2135 "Q45/Q43", NULL, &intel_i965_driver },
2136 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2137 "G45/G43", NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002138 { 0, 0, 0, NULL, NULL, NULL }
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002139};
2140
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141static int __devinit agp_intel_probe(struct pci_dev *pdev,
2142 const struct pci_device_id *ent)
2143{
2144 struct agp_bridge_data *bridge;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002145 u8 cap_ptr = 0;
2146 struct resource *r;
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002147 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002148
2149 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2150
2151 bridge = agp_alloc_bridge();
2152 if (!bridge)
2153 return -ENOMEM;
2154
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002155 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2156 /* In case that multiple models of gfx chip may
2157 stand on same host bridge type, this can be
2158 sure we detect the right IGD. */
Wang Zhenyu88889852007-06-14 10:01:04 +08002159 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2160 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2161 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2162 bridge->driver =
2163 intel_agp_chipsets[i].gmch_driver;
2164 break;
2165 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2166 continue;
2167 } else {
2168 bridge->driver = intel_agp_chipsets[i].driver;
2169 break;
2170 }
2171 }
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002172 }
2173
2174 if (intel_agp_chipsets[i].name == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175 if (cap_ptr)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002176 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2177 pdev->vendor, pdev->device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002178 agp_put_bridge(bridge);
2179 return -ENODEV;
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002180 }
2181
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002182 if (bridge->driver == NULL) {
Wang Zhenyu47d46372007-06-21 13:43:18 +08002183 /* bridge has no AGP and no IGD detected */
2184 if (cap_ptr)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002185 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2186 intel_agp_chipsets[i].gmch_chip_id);
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002187 agp_put_bridge(bridge);
2188 return -ENODEV;
Dave Airlief011ae72008-01-25 11:23:04 +10002189 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002190
2191 bridge->dev = pdev;
2192 bridge->capndx = cap_ptr;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002193 bridge->dev_private_data = &intel_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002194
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002195 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002196
2197 /*
2198 * The following fixes the case where the BIOS has "forgotten" to
2199 * provide an address range for the GART.
2200 * 20030610 - hamish@zot.org
2201 */
2202 r = &pdev->resource[0];
2203 if (!r->start && r->end) {
Dave Jones6a92a4e2006-02-28 00:54:25 -05002204 if (pci_assign_resource(pdev, 0)) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002205 dev_err(&pdev->dev, "can't assign resource 0\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 agp_put_bridge(bridge);
2207 return -ENODEV;
2208 }
2209 }
2210
2211 /*
2212 * If the device has not been properly setup, the following will catch
2213 * the problem and should stop the system from crashing.
2214 * 20030610 - hamish@zot.org
2215 */
2216 if (pci_enable_device(pdev)) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002217 dev_err(&pdev->dev, "can't enable PCI device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002218 agp_put_bridge(bridge);
2219 return -ENODEV;
2220 }
2221
2222 /* Fill in the mode register */
2223 if (cap_ptr) {
2224 pci_read_config_dword(pdev,
2225 bridge->capndx+PCI_AGP_STATUS,
2226 &bridge->mode);
2227 }
2228
2229 pci_set_drvdata(pdev, bridge);
2230 return agp_add_bridge(bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002231}
2232
2233static void __devexit agp_intel_remove(struct pci_dev *pdev)
2234{
2235 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2236
2237 agp_remove_bridge(bridge);
2238
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002239 if (intel_private.pcidev)
2240 pci_dev_put(intel_private.pcidev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002241
2242 agp_put_bridge(bridge);
2243}
2244
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002245#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246static int agp_intel_resume(struct pci_dev *pdev)
2247{
2248 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
Keith Packarda8c84df2008-07-31 15:48:07 +10002249 int ret_val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002250
2251 pci_restore_state(pdev);
2252
Wang Zhenyu4b953202007-01-17 11:07:54 +08002253 /* We should restore our graphics device's config space,
2254 * as host bridge (00:00) resumes before graphics device (02:00),
2255 * then our access to its pci space can work right.
2256 */
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002257 if (intel_private.pcidev)
2258 pci_restore_state(intel_private.pcidev);
Wang Zhenyu4b953202007-01-17 11:07:54 +08002259
Linus Torvalds1da177e2005-04-16 15:20:36 -07002260 if (bridge->driver == &intel_generic_driver)
2261 intel_configure();
2262 else if (bridge->driver == &intel_850_driver)
2263 intel_850_configure();
2264 else if (bridge->driver == &intel_845_driver)
2265 intel_845_configure();
2266 else if (bridge->driver == &intel_830mp_driver)
2267 intel_830mp_configure();
2268 else if (bridge->driver == &intel_915_driver)
2269 intel_i915_configure();
2270 else if (bridge->driver == &intel_830_driver)
2271 intel_i830_configure();
2272 else if (bridge->driver == &intel_810_driver)
2273 intel_i810_configure();
Dave Jones08da3f42006-09-10 21:09:26 -04002274 else if (bridge->driver == &intel_i965_driver)
2275 intel_i915_configure();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002276
Keith Packarda8c84df2008-07-31 15:48:07 +10002277 ret_val = agp_rebind_memory();
2278 if (ret_val != 0)
2279 return ret_val;
2280
Linus Torvalds1da177e2005-04-16 15:20:36 -07002281 return 0;
2282}
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002283#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284
2285static struct pci_device_id agp_intel_pci_table[] = {
2286#define ID(x) \
2287 { \
2288 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2289 .class_mask = ~0, \
2290 .vendor = PCI_VENDOR_ID_INTEL, \
2291 .device = x, \
2292 .subvendor = PCI_ANY_ID, \
2293 .subdevice = PCI_ANY_ID, \
2294 }
2295 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2296 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2297 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2298 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2299 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2300 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2301 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2302 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2303 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2304 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2305 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2306 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2307 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2308 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2309 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2310 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2311 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2312 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2313 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2314 ID(PCI_DEVICE_ID_INTEL_7505_0),
2315 ID(PCI_DEVICE_ID_INTEL_7205_0),
Carlos Martíne914a362008-01-24 10:34:09 +10002316 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002317 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2318 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
Alan Hourihaned0de98f2005-05-31 19:50:49 +01002319 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
Alan Hourihane3b0e8ea2006-01-19 14:08:40 +00002320 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
Zhenyu Wangdde47872007-07-26 09:18:09 +08002321 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
Eric Anholt65c25aa2006-09-06 11:57:18 -04002322 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
Zhenyu Wang9119f852008-01-23 15:49:26 +10002323 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
Eric Anholt65c25aa2006-09-06 11:57:18 -04002324 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2325 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
Wang Zhenyu4598af32007-04-09 08:51:36 +08002326 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
Zhenyu Wangdde47872007-07-26 09:18:09 +08002327 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
Wang Zhenyu874808c62007-06-06 11:16:25 +08002328 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2329 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2330 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07002331 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10002332 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2333 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2334 ID(PCI_DEVICE_ID_INTEL_G45_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002335 { }
2336};
2337
2338MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2339
2340static struct pci_driver agp_intel_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002341 .name = "agpgart-intel",
2342 .id_table = agp_intel_pci_table,
2343 .probe = agp_intel_probe,
2344 .remove = __devexit_p(agp_intel_remove),
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002345#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002346 .resume = agp_intel_resume,
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002347#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002348};
2349
2350static int __init agp_intel_init(void)
2351{
2352 if (agp_off)
2353 return -EINVAL;
2354 return pci_register_driver(&agp_intel_pci_driver);
2355}
2356
2357static void __exit agp_intel_cleanup(void)
2358{
2359 pci_unregister_driver(&agp_intel_pci_driver);
2360}
2361
2362module_init(agp_intel_init);
2363module_exit(agp_intel_cleanup);
2364
2365MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2366MODULE_LICENSE("GPL and additional rights");